sys/net/i4b/layer1/ifpnp/i4b_ifpnp_avm.c

   1 /*
   2  *   Copyright (c) 1999, 2000 Udo Schweigert. All rights reserved.
   3  *
   4  *   Redistribution and use in source and binary forms, with or without
   5  *   modification, are permitted provided that the following conditions
   6  *   are met:
   7  *
   8  *   1. Redistributions of source code must retain the above copyright
   9  *      notice, this list of conditions and the following disclaimer.
  10  *   2. Redistributions in binary form must reproduce the above copyright
  11  *      notice, this list of conditions and the following disclaimer in the
  12  *      documentation and/or other materials provided with the distribution.
  13  *   3. Neither the name of the author nor the names of any co-contributors
  14  *      may be used to endorse or promote products derived from this software
  15  *      without specific prior written permission.
  16  *   4. Altered versions must be plainly marked as such, and must not be
  17  *      misrepresented as being the original software and/or documentation.
  18  *
  19  *   THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  20  *   ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  21  *   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  22  *   ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  23  *   FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  24  *   DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  25  *   OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  26  *   HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  27  *   LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  28  *   OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  29  *   SUCH DAMAGE.
  30  *
  31  *---------------------------------------------------------------------------
  32  *
  33  *      i4b_ifpnp_avm.c: AVM Fritz!Card PnP hardware driver
  34  *      ---------------------------------------------------
  35  *
  36  * $FreeBSD: src/sys/i4b/layer1/ifpnp/i4b_ifpnp_avm.c,v 1.5.2.1 2001/08/10 14:08:37 obrien Exp $
  37  *
  38  *      last edit-date: [Fri Jan 12 17:05:28 2001]
  39  *
  40  *---------------------------------------------------------------------------*/
  41
  42 #include "ifpnp.h"
  43 #include "opt_i4b.h"
  44
  45 #if (NIFPNP > 0)
  46
  47 #include <sys/param.h>
  48 #include <sys/kernel.h>
  49 #include <sys/systm.h>
  50 #include <sys/mbuf.h>
  51
  52 #include <machine/bus.h>
  53 #include <sys/bus.h>
  54 #include <sys/rman.h>
  55
  56 #include <isa/isavar.h>
  57
  58 #include <sys/socket.h>
  59 #include <net/if.h>
  60
  61 #include <machine/i4b_debug.h>
  62 #include <machine/i4b_ioctl.h>
  63 #include <machine/i4b_trace.h>
  64
  65 #include <i4b/include/i4b_global.h>
  66 #include <i4b/include/i4b_mbuf.h>
  67
  68 #include <i4b/layer1/i4b_l1.h>
  69 #include <i4b/layer1/isic/i4b_isic.h>
  70 #include <i4b/layer1/isic/i4b_isac.h>
  71 #include <i4b/layer1/isic/i4b_hscx.h>
  72
  73 #include <i4b/layer1/ifpnp/i4b_ifpnp_ext.h>
  74
  75 /* prototypes */
  76 static void avm_pnp_intr(void *);
  77 static void hscx_write_reg(int, u_int, struct l1_softc *, u_int);
  78 static void hscx_write_reg_val(int, u_int, u_int8_t, struct l1_softc *);
  79 static u_int hscx_read_reg(int, u_int, struct l1_softc *);
  80 static void hscx_read_fifo(int, void *, size_t, struct l1_softc *);
  81 static void hscx_write_fifo(int, void *, size_t, struct l1_softc *);
  82 static void avm_pnp_hscx_int_handler(struct l1_softc *);
  83 static void avm_pnp_hscx_intr(int, u_int, u_int, struct l1_softc *);
  84 static void avm_pnp_init_linktab(struct l1_softc *);
  85 static void avm_pnp_bchannel_setup(int, int, int, int);
  86 static void avm_pnp_bchannel_start(int, int);
  87 static void avm_pnp_hscx_init(struct l1_softc *, int, int);
  88 static void avm_pnp_bchannel_stat(int, int, bchan_statistics_t *);
  89 static void avm_pnp_set_linktab(int, int, drvr_link_t *);
  90 static isdn_link_t * avm_pnp_ret_linktab(int, int);
  91 static int avm_pnp_probe(device_t);
  92 static int avm_pnp_hscx_fifo(l1_bchan_state_t *, struct l1_softc *);
  93 int avm_pnp_attach(device_t);
  94 static void ifpnp_isac_intr(struct l1_softc *sc);
  95
  96 static device_method_t avm_pnp_methods[] = {
  97         /* Device interface */
  98         DEVMETHOD(device_probe,         avm_pnp_probe),
  99         DEVMETHOD(device_attach,        avm_pnp_attach),
 100         { 0, 0 }
 101 };
 102
 103 static driver_t avm_pnp_driver = {
 104         "ifpnp",
 105         avm_pnp_methods,
 106         sizeof(struct l1_softc)
 107 };
 108
 109 static devclass_t avm_pnp_devclass;
 110
 111 DRIVER_MODULE(avm_pnp, isa, avm_pnp_driver, avm_pnp_devclass, 0, 0);
 112
 113 /* jump table for multiplex routines */
 114
 115 struct i4b_l1mux_func avm_pnp_l1mux_func = {
 116         avm_pnp_ret_linktab,
 117         avm_pnp_set_linktab,
 118         ifpnp_mph_command_req,
 119         ifpnp_ph_data_req,
 120         ifpnp_ph_activate_req,
 121 };
 122
 123 struct l1_softc *ifpnp_scp[IFPNP_MAXUNIT];
 124
 125 /*---------------------------------------------------------------------------*
 126  *      AVM PnP Fritz!Card special registers
 127  *---------------------------------------------------------------------------*/
 128
 129 /*
 130  *      register offsets from i/o base
 131  */
 132 #define CLASS_OFFSET            0x00
 133 #define REVISION_OFFSET         0x01
 134 #define STAT0_OFFSET            0x02
 135 #define STAT1_OFFSET            0x03
 136 #define ADDR_REG_OFFSET         0x04
 137 /*#define MODREG_OFFSET         0x06
 138 #define VERREG_OFFSET           0x07*/
 139
 140 /* these 2 are used to select an ISAC register set */
 141 #define ISAC_LO_REG_OFFSET      0x04
 142 #define ISAC_HI_REG_OFFSET      0x06
 143
 144 /* offset higher than this goes to the HI register set */
 145 #define MAX_LO_REG_OFFSET       0x2f
 146
 147 /* mask for the offset */
 148 #define ISAC_REGSET_MASK        0x0f
 149
 150 /* the offset from the base to the ISAC registers */
 151 #define ISAC_REG_OFFSET         0x10
 152
 153 /* the offset from the base to the ISAC FIFO */
 154 #define ISAC_FIFO               0x02
 155
 156 /* not really the HSCX, but sort of */
 157 #define HSCX_FIFO               0x00
 158 #define HSCX_STAT               0x04
 159
 160 /*
 161  *      AVM PnP Status Latch 0 read only bits
 162  */
 163 #define ASL_IRQ_ISAC            0x01    /* ISAC  interrupt, active low */
 164 #define ASL_IRQ_HSCX            0x02    /* HSX   interrupt, active low */
 165 #define ASL_IRQ_TIMER           0x04    /* Timer interrupt, active low */
 166 #define ASL_IRQ_BCHAN           ASL_IRQ_HSCX
 167 /* actually active LOW */
 168 #define ASL_IRQ_Pending         (ASL_IRQ_ISAC | ASL_IRQ_HSCX | ASL_IRQ_TIMER)
 169
 170 /*
 171  *      AVM Status Latch 0 write only bits
 172  */
 173 #define ASL_RESET_ALL           0x01  /* reset siemens IC's, active 1 */
 174 #define ASL_TIMERDISABLE        0x02  /* active high */
 175 #define ASL_TIMERRESET          0x04  /* active high */
 176 #define ASL_ENABLE_INT          0x08  /* active high */
 177 #define ASL_TESTBIT             0x10  /* active high */
 178
 179 /*
 180  *      AVM Status Latch 1 write only bits
 181  */
 182 #define ASL1_INTSEL              0x0f  /* active high */
 183 #define ASL1_ENABLE_IOM          0x80  /* active high */
 184
 185 /*
 186  * "HSCX" mode bits
 187  */
 188 #define  HSCX_MODE_ITF_FLG      0x01
 189 #define  HSCX_MODE_TRANS        0x02
 190 #define  HSCX_MODE_CCR_7        0x04
 191 #define  HSCX_MODE_CCR_16       0x08
 192 #define  HSCX_MODE_TESTLOOP     0x80
 193
 194 /*
 195  * "HSCX" status bits
 196  */
 197 #define  HSCX_STAT_RME          0x01
 198 #define  HSCX_STAT_RDO          0x10
 199 #define  HSCX_STAT_CRCVFRRAB    0x0E
 200 #define  HSCX_STAT_CRCVFR       0x06
 201 #define  HSCX_STAT_RML_MASK     0x3f00
 202
 203 /*
 204  * "HSCX" interrupt bits
 205  */
 206 #define  HSCX_INT_XPR           0x80
 207 #define  HSCX_INT_XDU           0x40
 208 #define  HSCX_INT_RPR           0x20
 209 #define  HSCX_INT_MASK          0xE0
 210
 211 /*
 212  * "HSCX" command bits
 213  */
 214 #define  HSCX_CMD_XRS           0x80
 215 #define  HSCX_CMD_XME           0x01
 216 #define  HSCX_CMD_RRS           0x20
 217 #define  HSCX_CMD_XML_MASK      0x3f00
 218
 219 /*
 220  * to prevent deactivating the "HSCX" when both channels are active we
 221  * define an HSCX_ACTIVE flag which is or'd into the channel's state
 222  * flag in avm_pnp_bchannel_setup upon active and cleared upon deactivation.
 223  * It is set high to allow room for new flags.
 224  */
 225 #define HSCX_AVMA1PP_ACTIVE     0x1000
 226
 227 /*---------------------------------------------------------------------------*
 228  *      AVM read fifo routines
 229  *---------------------------------------------------------------------------*/
 230
 231 static void
 232 avm_pnp_read_fifo(struct l1_softc *sc, int what, void *buf, size_t size)
 233 {
 234         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 235         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 236
 237         switch (what) {
 238                 case ISIC_WHAT_ISAC:
 239                         bus_space_write_1(btag, bhandle,  ADDR_REG_OFFSET, ISAC_FIFO);
 240                         bus_space_read_multi_1(btag, bhandle,  ISAC_REG_OFFSET, buf, size);
 241                         break;
 242                 case ISIC_WHAT_HSCXA:
 243                         hscx_read_fifo(0, buf, size, sc);
 244                         break;
 245                 case ISIC_WHAT_HSCXB:
 246                         hscx_read_fifo(1, buf, size, sc);
 247                         break;
 248         }
 249 }
 250
 251 static void
 252 hscx_read_fifo(int chan, void *buf, size_t len, struct l1_softc *sc)
 253 {
 254         u_int8_t *ip;
 255         size_t cnt;
 256         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 257         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 258
 259         bus_space_write_1(btag, bhandle, ADDR_REG_OFFSET, chan);
 260         ip = (u_int8_t *)buf;
 261         cnt = 0;
 262         while (cnt++ < len)
 263         {
 264                 *ip++ = bus_space_read_1(btag, bhandle, ISAC_REG_OFFSET);
 265         }
 266 }
 267
 268 /*---------------------------------------------------------------------------*
 269  *      AVM write fifo routines
 270  *---------------------------------------------------------------------------*/
 271 static void
 272 avm_pnp_write_fifo(struct l1_softc *sc, int what, void *buf, size_t size)
 273 {
 274         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 275         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 276
 277         switch (what) {
 278                 case ISIC_WHAT_ISAC:
 279                         bus_space_write_1(btag, bhandle,  ADDR_REG_OFFSET, ISAC_FIFO);
 280                         bus_space_write_multi_1(btag, bhandle,  ISAC_REG_OFFSET, (u_int8_t*)buf, size);
 281                         break;
 282                 case ISIC_WHAT_HSCXA:
 283                         hscx_write_fifo(0, buf, size, sc);
 284                         break;
 285                 case ISIC_WHAT_HSCXB:
 286                         hscx_write_fifo(1, buf, size, sc);
 287                         break;
 288         }
 289 }
 290
 291 static void
 292 hscx_write_fifo(int chan, void *buf, size_t len, struct l1_softc *sc)
 293 {
 294         u_int8_t *ip;
 295         size_t cnt;
 296         l1_bchan_state_t *Bchan = &sc->sc_chan[chan];
 297         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 298         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 299
 300         sc->avma1pp_cmd &= ~HSCX_CMD_XME;
 301         sc->avma1pp_txl = 0;
 302
 303         if (Bchan->out_mbuf_cur == NULL)
 304         {
 305           if (Bchan->bprot != BPROT_NONE)
 306                  sc->avma1pp_cmd |= HSCX_CMD_XME;
 307         }
 308         if (len != sc->sc_bfifolen)
 309                 sc->avma1pp_txl = len;
 310
 311         hscx_write_reg(chan, HSCX_STAT, sc, 3);
 312
 313         ip = (u_int8_t *)buf;
 314         cnt = 0;
 315         while (cnt++ < len)
 316         {
 317                 bus_space_write_1(btag, bhandle, ISAC_REG_OFFSET, *ip++);
 318         }
 319 }
 320
 321 /*---------------------------------------------------------------------------*
 322  *      AVM write register routines
 323  *---------------------------------------------------------------------------*/
 324
 325 static void
 326 avm_pnp_write_reg(struct l1_softc *sc, int what, bus_size_t offs, u_int8_t data)
 327 {
 328         u_char reg_bank;
 329         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 330         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 331
 332         switch (what) {
 333                 case ISIC_WHAT_ISAC:
 334                         reg_bank = (offs > MAX_LO_REG_OFFSET) ? ISAC_HI_REG_OFFSET:ISAC_LO_REG_OFFSET;
 335                         /* set the register bank */
 336                         bus_space_write_1(btag, bhandle, ADDR_REG_OFFSET, reg_bank);
 337                         bus_space_write_1(btag, bhandle, ISAC_REG_OFFSET + (offs & ISAC_REGSET_MASK), data);
 338                         break;
 339                 case ISIC_WHAT_HSCXA:
 340                         hscx_write_reg_val(0, offs, data, sc);
 341                         break;
 342                 case ISIC_WHAT_HSCXB:
 343                         hscx_write_reg_val(1, offs, data, sc);
 344                         break;
 345         }
 346 }
 347
 348 static void
 349 hscx_write_reg(int chan, u_int off, struct l1_softc *sc, u_int which)
 350 {
 351         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 352         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 353
 354         /* point at the correct channel */
 355         bus_space_write_1(btag, bhandle, ADDR_REG_OFFSET, chan);
 356         if (which & 4)
 357                 bus_space_write_1(btag, bhandle, ISAC_REG_OFFSET + off + 2, sc->avma1pp_prot);
 358         if (which & 2)
 359                 bus_space_write_1(btag, bhandle, ISAC_REG_OFFSET + off + 1, sc->avma1pp_txl);
 360         if (which & 1)
 361                 bus_space_write_1(btag, bhandle, ISAC_REG_OFFSET + off, sc->avma1pp_cmd);
 362 }
 363
 364 static void
 365 hscx_write_reg_val(int chan, u_int off, u_int8_t val, struct l1_softc *sc)
 366 {
 367         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 368         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 369
 370         /* point at the correct channel */
 371         bus_space_write_1(btag, bhandle, ADDR_REG_OFFSET, chan);
 372         bus_space_write_1(btag, bhandle, ISAC_REG_OFFSET + off, val);
 373 }
 374
 375 /*---------------------------------------------------------------------------*
 376  *      AVM read register routines
 377  *---------------------------------------------------------------------------*/
 378 static u_int8_t
 379 avm_pnp_read_reg(struct l1_softc *sc, int what, bus_size_t offs)
 380 {
 381         u_char reg_bank;
 382         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 383         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 384
 385         switch (what) {
 386                 case ISIC_WHAT_ISAC:
 387                         reg_bank = (offs > MAX_LO_REG_OFFSET) ? ISAC_HI_REG_OFFSET:ISAC_LO_REG_OFFSET;
 388                         /* set the register bank */
 389                         bus_space_write_1(btag, bhandle, ADDR_REG_OFFSET, reg_bank);
 390                         return(bus_space_read_1(btag, bhandle, ISAC_REG_OFFSET +
 391                                 (offs & ISAC_REGSET_MASK)));
 392                 case ISIC_WHAT_HSCXA:
 393                         return hscx_read_reg(0, offs, sc);
 394                 case ISIC_WHAT_HSCXB:
 395                         return hscx_read_reg(1, offs, sc);
 396         }
 397         return 0;
 398 }
 399
 400 static u_int
 401 hscx_read_reg(int chan, u_int off, struct l1_softc *sc)
 402 {
 403         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 404         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 405
 406         /* point at the correct channel */
 407         bus_space_write_1(btag, bhandle, ADDR_REG_OFFSET, chan);
 408         return(bus_space_read_1(btag, bhandle, ISAC_REG_OFFSET + off));
 409 }
 410
 411
 412 static struct ifpnp_ids {
 413         u_long vend_id;
 414         char *id_str;
 415 } ifpnp_ids[] = {
 416         { 0x0009cd06,           "AVM Fritz!Card PnP"            },
 417         { 0, 0 }
 418 };
 419
 420 /*---------------------------------------------------------------------------*
 421  *      avm_pnp_probe - probe for a card
 422  *---------------------------------------------------------------------------*/
 423 static int
 424 avm_pnp_probe(dev)
 425         device_t                dev;
 426 {
 427         struct ifpnp_ids *ids;                  /* pnp id's */
 428         char *string = NULL;                            /* the name */
 429         u_int32_t vend_id = isa_get_vendorid(dev);      /* vendor id */
 430
 431         /* search table of knowd id's */
 432
 433         for(ids = ifpnp_ids; ids->vend_id != 0; ids++)
 434         {
 435                 if(vend_id == ids->vend_id)
 436                 {
 437                         string = ids->id_str;
 438                         break;
 439                 }
 440         }
 441
 442         if(string)              /* set name if we have one */
 443         {
 444                 device_set_desc(dev, string);   /* set description */
 445                 return 0;
 446         }
 447         else
 448         {
 449                 return ENXIO;
 450         }
 451 }
 452
 453 /*---------------------------------------------------------------------------*
 454  *      avm_pnp_attach - attach Fritz!Card PnP
 455  *---------------------------------------------------------------------------*/
 456 int
 457 avm_pnp_attach(device_t dev)
 458 {
 459         struct l1_softc *sc;
 460         u_int v;
 461         int unit, error = 0;
 462         int s;
 463         u_int16_t vid;
 464         void *ih = 0;
 465         bus_space_handle_t bhandle;
 466         bus_space_tag_t btag;
 467
 468         s = splimp();
 469
 470         vid = isa_get_vendorid(dev);
 471         sc = device_get_softc(dev);
 472         unit = device_get_unit(dev);
 473         bzero(sc, sizeof(struct l1_softc));
 474
 475         /* probably not really required */
 476         if(unit > IFPNP_MAXUNIT) {
 477                 printf("avm_pnp%d: Error, unit > IFPNP_MAXUNIT!\n", unit);
 478                 splx(s);
 479                 return(ENXIO);
 480         }
 481
 482         ifpnp_scp[unit] = sc;
 483
 484
 485         /* get io_base */
 486         if(!(sc->sc_resources.io_base[0] =
 487                         bus_alloc_resource(dev, SYS_RES_IOPORT,
 488                                                 &sc->sc_resources.io_rid[0],
 489                                                 0UL, ~0UL, 1, RF_ACTIVE ) ))
 490         {
 491                 printf("avm_pnp_attach: Couldn't get my io_base.\n");
 492                 return ENXIO;
 493         }
 494         if (sc->sc_resources.io_base[0] == NULL) {
 495                 printf("avm_pnp%d: couldn't map IO port\n", unit);
 496                 error = ENXIO;
 497                 goto fail;
 498         }
 499
 500         bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 501         btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 502
 503         /* will not be used for pnp devices */
 504         sc->sc_port = rman_get_start(sc->sc_resources.io_base[0]);
 505
 506         /* get irq, release io_base if we don't get it */
 507
 508         if(!(sc->sc_resources.irq =
 509                         bus_alloc_resource(dev, SYS_RES_IRQ,
 510                                            &sc->sc_resources.irq_rid,
 511                                            0UL, ~0UL, 1, RF_ACTIVE)))
 512         {
 513                 printf("avm_pnp%d: Could not get irq.\n",unit);
 514                 error = ENXIO;
 515                 goto fail;
 516         }
 517
 518         /* not needed */
 519         sc->sc_irq = rman_get_start(sc->sc_resources.irq);
 520         bus_setup_intr(dev,sc->sc_resources.irq,INTR_TYPE_NET,
 521                                 (void(*)(void*))avm_pnp_intr, sc,&ih);
 522         sc->sc_unit = unit;
 523
 524         /* end of new-bus stuff */
 525
 526         ISAC_BASE = (caddr_t)ISIC_WHAT_ISAC;
 527
 528         HSCX_A_BASE = (caddr_t)ISIC_WHAT_HSCXA;
 529         HSCX_B_BASE = (caddr_t)ISIC_WHAT_HSCXB;
 530
 531         /* setup access routines */
 532
 533         sc->clearirq = NULL;
 534         sc->readreg = avm_pnp_read_reg;
 535         sc->writereg = avm_pnp_write_reg;
 536
 537         sc->readfifo = avm_pnp_read_fifo;
 538         sc->writefifo = avm_pnp_write_fifo;
 539
 540         /* setup card type */
 541
 542         sc->sc_cardtyp = CARD_TYPEP_AVM_PNP;
 543
 544         /* setup IOM bus type */
 545
 546         sc->sc_bustyp = BUS_TYPE_IOM2;
 547
 548         /* set up some other miscellaneous things */
 549         sc->sc_ipac = 0;
 550         sc->sc_bfifolen = HSCX_FIFO_LEN;
 551
 552         /* reset the card */
 553         /* the Linux driver does this to clear any pending ISAC interrupts */
 554         v = 0;
 555         v = ISAC_READ(I_STAR);
 556         v = ISAC_READ(I_MODE);
 557         v = ISAC_READ(I_ADF2);
 558         v = ISAC_READ(I_ISTA);
 559         if (v & ISAC_ISTA_EXI)
 560         {
 561                  v = ISAC_READ(I_EXIR);
 562         }
 563         v = ISAC_READ(I_CIRR);
 564         ISAC_WRITE(I_MASK, 0xff);
 565         /* the Linux driver does this to clear any pending HSCX interrupts */
 566         v = hscx_read_reg(0, HSCX_STAT, sc);
 567         v = hscx_read_reg(1, HSCX_STAT, sc);
 568
 569         bus_space_write_1(btag, bhandle, STAT0_OFFSET, ASL_RESET_ALL|ASL_TIMERDISABLE);
 570         DELAY(SEC_DELAY/100); /* 10 ms */
 571         bus_space_write_1(btag, bhandle, STAT1_OFFSET, ASL1_ENABLE_IOM|sc->sc_irq);
 572         DELAY(SEC_DELAY/100); /* 10 ms */
 573         bus_space_write_1(btag, bhandle, STAT0_OFFSET, ASL_TIMERRESET|ASL_ENABLE_INT|ASL_TIMERDISABLE);
 574         DELAY(SEC_DELAY/100); /* 10 ms */
 575
 576          printf("ifpnp%d: AVM Fritz!Card PnP Class %#x Revision %d \n", unit,
 577                         bus_space_read_1(btag, bhandle, CLASS_OFFSET),
 578                         bus_space_read_1(btag, bhandle, REVISION_OFFSET));
 579
 580          printf("ifpnp%d: ISAC %s (IOM-%c)\n", unit,
 581                 "2085 Version A1/A2 or 2086/2186 Version 1.1",
 582                  sc->sc_bustyp == BUS_TYPE_IOM1 ? '1' : '2');
 583
 584
 585         /* init the ISAC */
 586         ifpnp_isac_init(sc);
 587
 588         /* init the "HSCX" */
 589         avm_pnp_bchannel_setup(sc->sc_unit, HSCX_CH_A, BPROT_NONE, 0);
 590
 591         avm_pnp_bchannel_setup(sc->sc_unit, HSCX_CH_B, BPROT_NONE, 0);
 592
 593         /* can't use the normal B-Channel stuff */
 594         avm_pnp_init_linktab(sc);
 595
 596         /* set trace level */
 597
 598         sc->sc_trace = TRACE_OFF;
 599
 600         sc->sc_state = ISAC_IDLE;
 601
 602         sc->sc_ibuf = NULL;
 603         sc->sc_ib = NULL;
 604         sc->sc_ilen = 0;
 605
 606         sc->sc_obuf = NULL;
 607         sc->sc_op = NULL;
 608         sc->sc_ol = 0;
 609         sc->sc_freeflag = 0;
 610
 611         sc->sc_obuf2 = NULL;
 612         sc->sc_freeflag2 = 0;
 613
 614         callout_handle_init(&sc->sc_T3_callout);
 615         callout_handle_init(&sc->sc_T4_callout);
 616
 617         /* init higher protocol layers */
 618
 619         i4b_l1_mph_status_ind(L0IFPNPUNIT(sc->sc_unit), STI_ATTACH, sc->sc_cardtyp, &avm_pnp_l1mux_func);
 620
 621   fail:
 622         splx(s);
 623         return(error);
 624 }
 625
 626 /*
 627  * this is the real interrupt routine
 628  */
 629 static void
 630 avm_pnp_hscx_intr(int h_chan, u_int stat, u_int cnt, struct l1_softc *sc)
 631 {
 632         register l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
 633         int activity = -1;
 634
 635         NDBGL1(L1_H_IRQ, "%#x", stat);
 636
 637         if((stat & HSCX_INT_XDU) && (chan->bprot != BPROT_NONE))/* xmit data underrun */
 638         {
 639                 chan->stat_XDU++;
 640                 NDBGL1(L1_H_XFRERR, "xmit data underrun");
 641                 /* abort the transmission */
 642                 sc->avma1pp_txl = 0;
 643                 sc->avma1pp_cmd |= HSCX_CMD_XRS;
 644                 hscx_write_reg(h_chan, HSCX_STAT, sc, 1);
 645                 sc->avma1pp_cmd &= ~HSCX_CMD_XRS;
 646                 hscx_write_reg(h_chan, HSCX_STAT, sc, 1);
 647
 648                 if (chan->out_mbuf_head != NULL)  /* don't continue to transmit this buffer */
 649                 {
 650                         i4b_Bfreembuf(chan->out_mbuf_head);
 651                         chan->out_mbuf_cur = chan->out_mbuf_head = NULL;
 652                 }
 653         }
 654
 655         /*
 656          * The following is based on examination of the Linux driver.
 657          *
 658          * The logic here is different than with a "real" HSCX; all kinds
 659          * of information (interrupt/status bits) are in stat.
 660          *              HSCX_INT_RPR indicates a receive interrupt
 661          *                      HSCX_STAT_RDO indicates an overrun condition, abort -
 662          *                      otherwise read the bytes ((stat & HSCX_STZT_RML_MASK) >> 8)
 663          *                      HSCX_STAT_RME indicates end-of-frame and apparently any
 664          *                      CRC/framing errors are only reported in this state.
 665          *                              if ((stat & HSCX_STAT_CRCVFRRAB) != HSCX_STAT_CRCVFR)
 666          *                                      CRC/framing error
 667          */
 668
 669         if(stat & HSCX_INT_RPR)
 670         {
 671                 register int fifo_data_len;
 672                 int error = 0;
 673                 /* always have to read the FIFO, so use a scratch buffer */
 674                 u_char scrbuf[HSCX_FIFO_LEN];
 675
 676                 if(stat & HSCX_STAT_RDO)
 677                 {
 678                         chan->stat_RDO++;
 679                         NDBGL1(L1_H_XFRERR, "receive data overflow");
 680                         error++;
 681                 }
 682
 683                 /*
 684                  * check whether we're receiving data for an inactive B-channel
 685                  * and discard it. This appears to happen for telephony when
 686                  * both B-channels are active and one is deactivated. Since
 687                  * it is not really possible to deactivate the channel in that
 688                  * case (the ASIC seems to deactivate _both_ channels), the
 689                  * "deactivated" channel keeps receiving data which can lead
 690                  * to exhaustion of mbufs and a kernel panic.
 691                  *
 692                  * This is a hack, but it's the only solution I can think of
 693                  * without having the documentation for the ASIC.
 694                  * GJ - 28 Nov 1999
 695                  */
 696                  if (chan->state == HSCX_IDLE)
 697                  {
 698                         NDBGL1(L1_H_XFRERR, "toss data from %d", h_chan);
 699                         error++;
 700                  }
 701
 702                 fifo_data_len = cnt;
 703
 704                 if(fifo_data_len == 0)
 705                         fifo_data_len = sc->sc_bfifolen;
 706
 707                 /* ALWAYS read data from HSCX fifo */
 708
 709                 HSCX_RDFIFO(h_chan, scrbuf, fifo_data_len);
 710                 chan->rxcount += fifo_data_len;
 711
 712                 /* all error conditions checked, now decide and take action */
 713
 714                 if(error == 0)
 715                 {
 716                         if(chan->in_mbuf == NULL)
 717                         {
 718                                 if((chan->in_mbuf = i4b_Bgetmbuf(BCH_MAX_DATALEN)) == NULL)
 719                                         panic("L1 avm_pnp_hscx_intr: RME, cannot allocate mbuf!\n");
 720                                 chan->in_cbptr = chan->in_mbuf->m_data;
 721                                 chan->in_len = 0;
 722                         }
 723
 724                         if((chan->in_len + fifo_data_len) <= BCH_MAX_DATALEN)
 725                         {
 726                                 /* OK to copy the data */
 727                                 bcopy(scrbuf, chan->in_cbptr, fifo_data_len);
 728                                 chan->in_cbptr += fifo_data_len;
 729                                 chan->in_len += fifo_data_len;
 730
 731                                 /* setup mbuf data length */
 732
 733                                 chan->in_mbuf->m_len = chan->in_len;
 734                                 chan->in_mbuf->m_pkthdr.len = chan->in_len;
 735
 736                                 if(sc->sc_trace & TRACE_B_RX)
 737                                 {
 738                                         i4b_trace_hdr_t hdr;
 739                                         hdr.unit = L0IFPNPUNIT(sc->sc_unit);
 740                                         hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
 741                                         hdr.dir = FROM_NT;
 742                                         hdr.count = ++sc->sc_trace_bcount;
 743                                         MICROTIME(hdr.time);
 744                                         i4b_l1_trace_ind(&hdr, chan->in_mbuf->m_len, chan->in_mbuf->m_data);
 745                                 }
 746
 747                                 if (stat & HSCX_STAT_RME)
 748                                 {
 749                                   if((stat & HSCX_STAT_CRCVFRRAB) == HSCX_STAT_CRCVFR)
 750                                   {
 751                                          (*chan->isic_drvr_linktab->bch_rx_data_ready)(chan->isic_drvr_linktab->unit);
 752                                          activity = ACT_RX;
 753
 754                                          /* mark buffer ptr as unused */
 755
 756                                          chan->in_mbuf = NULL;
 757                                          chan->in_cbptr = NULL;
 758                                          chan->in_len = 0;
 759                                   }
 760                                   else
 761                                   {
 762                                                 chan->stat_CRC++;
 763                                                 NDBGL1(L1_H_XFRERR, "CRC/RAB");
 764                                           if (chan->in_mbuf != NULL)
 765                                           {
 766                                                   i4b_Bfreembuf(chan->in_mbuf);
 767                                                   chan->in_mbuf = NULL;
 768                                                   chan->in_cbptr = NULL;
 769                                                   chan->in_len = 0;
 770                                           }
 771                                   }
 772                                 }
 773                         } /* END enough space in mbuf */
 774                         else
 775                         {
 776                                  if(chan->bprot == BPROT_NONE)
 777                                  {
 778                                           /* setup mbuf data length */
 779
 780                                           chan->in_mbuf->m_len = chan->in_len;
 781                                           chan->in_mbuf->m_pkthdr.len = chan->in_len;
 782
 783                                           if(sc->sc_trace & TRACE_B_RX)
 784                                           {
 785                                                         i4b_trace_hdr_t hdr;
 786                                                         hdr.unit = L0IFPNPUNIT(sc->sc_unit);
 787                                                         hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
 788                                                         hdr.dir = FROM_NT;
 789                                                         hdr.count = ++sc->sc_trace_bcount;
 790                                                         MICROTIME(hdr.time);
 791                                                         i4b_l1_trace_ind(&hdr, chan->in_mbuf->m_len, chan->in_mbuf->m_data);
 792                                                 }
 793
 794                                           if(!(i4b_l1_bchan_tel_silence(chan->in_mbuf->m_data, chan->in_mbuf->m_len)))
 795                                                  activity = ACT_RX;
 796
 797                                           /* move rx'd data to rx queue */
 798 #if defined (__FreeBSD__) && __FreeBSD__ > 4
 799                                           (void) IF_HANDOFF(&chan->rx_queue, chan->in_mbuf, NULL);
 800 #else
 801                                           if(!(IF_QFULL(&chan->rx_queue)))
 802                                           {
 803                                                 IF_ENQUEUE(&chan->rx_queue, chan->in_mbuf);
 804                                           }
 805                                           else
 806                                           {
 807                                                 i4b_Bfreembuf(chan->in_mbuf);
 808                                           }
 809 #endif
 810                                           /* signal upper layer that data are available */
 811                                           (*chan->isic_drvr_linktab->bch_rx_data_ready)(chan->isic_drvr_linktab->unit);
 812
 813                                           /* alloc new buffer */
 814
 815                                           if((chan->in_mbuf = i4b_Bgetmbuf(BCH_MAX_DATALEN)) == NULL)
 816                                                  panic("L1 avm_pnp_hscx_intr: RPF, cannot allocate new mbuf!\n");
 817
 818                                           /* setup new data ptr */
 819
 820                                           chan->in_cbptr = chan->in_mbuf->m_data;
 821
 822                                           /* OK to copy the data */
 823                                           bcopy(scrbuf, chan->in_cbptr, fifo_data_len);
 824
 825                                           chan->in_cbptr += fifo_data_len;
 826                                           chan->in_len = fifo_data_len;
 827
 828                                           chan->rxcount += fifo_data_len;
 829                                         }
 830                                  else
 831                                         {
 832                                           NDBGL1(L1_H_XFRERR, "RAWHDLC rx buffer overflow in RPF, in_len=%d", chan->in_len);
 833                                           chan->in_cbptr = chan->in_mbuf->m_data;
 834                                           chan->in_len = 0;
 835                                         }
 836                           }
 837                 } /* if(error == 0) */
 838                 else
 839                 {
 840                         /* land here for RDO */
 841                         if (chan->in_mbuf != NULL)
 842                         {
 843                                 i4b_Bfreembuf(chan->in_mbuf);
 844                                 chan->in_mbuf = NULL;
 845                                 chan->in_cbptr = NULL;
 846                                 chan->in_len = 0;
 847                         }
 848                         sc->avma1pp_txl = 0;
 849                         sc->avma1pp_cmd |= HSCX_CMD_RRS;
 850                         hscx_write_reg(h_chan, HSCX_STAT, sc, 1);
 851                         sc->avma1pp_cmd &= ~HSCX_CMD_RRS;
 852                         hscx_write_reg(h_chan, HSCX_STAT, sc, 1);
 853                 }
 854         }
 855
 856
 857         /* transmit fifo empty, new data can be written to fifo */
 858
 859         if(stat & HSCX_INT_XPR)
 860         {
 861                 /*
 862                  * for a description what is going on here, please have
 863                  * a look at isic_bchannel_start() in i4b_bchan.c !
 864                  */
 865
 866                 NDBGL1(L1_H_IRQ, "unit %d, chan %d - XPR, Tx Fifo Empty!", sc->sc_unit, h_chan);
 867
 868                 if(chan->out_mbuf_cur == NULL)  /* last frame is transmitted */
 869                 {
 870                         IF_DEQUEUE(&chan->tx_queue, chan->out_mbuf_head);
 871
 872                         if(chan->out_mbuf_head == NULL)
 873                         {
 874                                 chan->state &= ~HSCX_TX_ACTIVE;
 875                                 (*chan->isic_drvr_linktab->bch_tx_queue_empty)(chan->isic_drvr_linktab->unit);
 876                         }
 877                         else
 878                         {
 879                                 chan->state |= HSCX_TX_ACTIVE;
 880                                 chan->out_mbuf_cur = chan->out_mbuf_head;
 881                                 chan->out_mbuf_cur_ptr = chan->out_mbuf_cur->m_data;
 882                                 chan->out_mbuf_cur_len = chan->out_mbuf_cur->m_len;
 883
 884                                 if(sc->sc_trace & TRACE_B_TX)
 885                                 {
 886                                         i4b_trace_hdr_t hdr;
 887                                         hdr.unit = L0IFPNPUNIT(sc->sc_unit);
 888                                         hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
 889                                         hdr.dir = FROM_TE;
 890                                         hdr.count = ++sc->sc_trace_bcount;
 891                                         MICROTIME(hdr.time);
 892                                         i4b_l1_trace_ind(&hdr, chan->out_mbuf_cur->m_len, chan->out_mbuf_cur->m_data);
 893                                 }
 894
 895                                 if(chan->bprot == BPROT_NONE)
 896                                 {
 897                                         if(!(i4b_l1_bchan_tel_silence(chan->out_mbuf_cur->m_data, chan->out_mbuf_cur->m_len)))
 898                                                 activity = ACT_TX;
 899                                 }
 900                                 else
 901                                 {
 902                                         activity = ACT_TX;
 903                                 }
 904                         }
 905                 }
 906
 907                 avm_pnp_hscx_fifo(chan, sc);
 908         }
 909
 910         /* call timeout handling routine */
 911
 912         if(activity == ACT_RX || activity == ACT_TX)
 913                 (*chan->isic_drvr_linktab->bch_activity)(chan->isic_drvr_linktab->unit, activity);
 914 }
 915
 916 /*
 917  * this is the main routine which checks each channel and then calls
 918  * the real interrupt routine as appropriate
 919  */
 920 static void
 921 avm_pnp_hscx_int_handler(struct l1_softc *sc)
 922 {
 923         u_char stat = 0;
 924         u_char cnt = 0;
 925
 926         stat = hscx_read_reg(0, HSCX_STAT, sc);
 927         if (stat & HSCX_INT_RPR)
 928           cnt = hscx_read_reg(0, HSCX_STAT+1, sc);
 929         if (stat & HSCX_INT_MASK)
 930           avm_pnp_hscx_intr(0, stat, cnt, sc);
 931
 932         cnt = 0;
 933         stat = hscx_read_reg(1, HSCX_STAT, sc);
 934         if (stat & HSCX_INT_RPR)
 935           cnt = hscx_read_reg(1, HSCX_STAT+1, sc);
 936         if (stat & HSCX_INT_MASK)
 937           avm_pnp_hscx_intr(1, stat, cnt, sc);
 938 }
 939
 940 static void
 941 avm_pnp_intr(void *xsc)
 942 {
 943         u_char stat;
 944         struct l1_softc *sc;
 945         bus_space_handle_t bhandle;
 946         bus_space_tag_t btag;
 947
 948         sc = xsc;
 949         bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 950         btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 951
 952         stat = bus_space_read_1(btag, bhandle, STAT0_OFFSET);
 953         NDBGL1(L1_H_IRQ, "stat %x", stat);
 954         /* was there an interrupt from this card ? */
 955         if ((stat & ASL_IRQ_Pending) == ASL_IRQ_Pending)
 956                 return; /* no */
 957         /* interrupts are low active */
 958         if (!(stat & ASL_IRQ_TIMER))
 959           NDBGL1(L1_H_IRQ, "timer interrupt ???");
 960         if (!(stat & ASL_IRQ_HSCX))
 961         {
 962           NDBGL1(L1_H_IRQ, "HSCX");
 963                 avm_pnp_hscx_int_handler(sc);
 964         }
 965         if (!(stat & ASL_IRQ_ISAC))
 966         {
 967           NDBGL1(L1_H_IRQ, "ISAC");
 968                 ifpnp_isac_intr(sc);
 969         }
 970 }
 971
 972 static void
 973 avm_pnp_hscx_init(struct l1_softc *sc, int h_chan, int activate)
 974 {
 975         l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
 976
 977         NDBGL1(L1_BCHAN, "unit=%d, channel=%d, %s",
 978                 sc->sc_unit, h_chan, activate ? "activate" : "deactivate");
 979
 980         if (activate == 0)
 981         {
 982                 /* only deactivate if both channels are idle */
 983                 if (sc->sc_chan[HSCX_CH_A].state != HSCX_IDLE ||
 984                         sc->sc_chan[HSCX_CH_B].state != HSCX_IDLE)
 985                 {
 986                         return;
 987                 }
 988                 sc->avma1pp_cmd = HSCX_CMD_XRS|HSCX_CMD_RRS;
 989                 sc->avma1pp_prot = HSCX_MODE_TRANS;
 990                 hscx_write_reg(h_chan, HSCX_STAT, sc, 5);
 991                 return;
 992         }
 993         if(chan->bprot == BPROT_RHDLC)
 994         {
 995                   NDBGL1(L1_BCHAN, "BPROT_RHDLC");
 996
 997                 /* HDLC Frames, transparent mode 0 */
 998                 sc->avma1pp_cmd = HSCX_CMD_XRS|HSCX_CMD_RRS;
 999                 sc->avma1pp_prot = HSCX_MODE_ITF_FLG;
1000                 hscx_write_reg(h_chan, HSCX_STAT, sc, 5);
1001                 sc->avma1pp_cmd = HSCX_CMD_XRS;
1002                 hscx_write_reg(h_chan, HSCX_STAT, sc, 1);
1003                 sc->avma1pp_cmd = 0;
1004         }
1005         else
1006         {
1007                   NDBGL1(L1_BCHAN, "BPROT_NONE??");
1008
1009                 /* Raw Telephony, extended transparent mode 1 */
1010                 sc->avma1pp_cmd = HSCX_CMD_XRS|HSCX_CMD_RRS;
1011                 sc->avma1pp_prot = HSCX_MODE_TRANS;
1012                 hscx_write_reg(h_chan, HSCX_STAT, sc, 5);
1013                 sc->avma1pp_cmd = HSCX_CMD_XRS;
1014                 hscx_write_reg(h_chan, HSCX_STAT, sc, 1);
1015                 sc->avma1pp_cmd = 0;
1016         }
1017 }
1018
1019 static void
1020 avm_pnp_bchannel_setup(int unit, int h_chan, int bprot, int activate)
1021 {
1022         struct l1_softc *sc = ifpnp_scp[unit];
1023         l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
1024
1025         int s = SPLI4B();
1026
1027         if(activate == 0)
1028         {
1029                 /* deactivation */
1030                 chan->state = HSCX_IDLE;
1031                 avm_pnp_hscx_init(sc, h_chan, activate);
1032         }
1033
1034         NDBGL1(L1_BCHAN, "unit=%d, channel=%d, %s",
1035                 sc->sc_unit, h_chan, activate ? "activate" : "deactivate");
1036
1037         /* general part */
1038
1039         chan->unit = sc->sc_unit;       /* unit number */
1040         chan->channel = h_chan;         /* B channel */
1041         chan->bprot = bprot;            /* B channel protocol */
1042         chan->state = HSCX_IDLE;        /* B channel state */
1043
1044         /* receiver part */
1045
1046         chan->rx_queue.ifq_maxlen = IFQ_MAXLEN;
1047
1048 #if defined (__FreeBSD__) && __FreeBSD__ > 4
1049         mtx_init(&chan->rx_queue.ifq_mtx, "i4b_avm_pnp_rx", MTX_DEF);
1050 #endif
1051
1052         i4b_Bcleanifq(&chan->rx_queue); /* clean rx queue */
1053
1054         chan->rxcount = 0;              /* reset rx counter */
1055
1056         i4b_Bfreembuf(chan->in_mbuf);   /* clean rx mbuf */
1057
1058         chan->in_mbuf = NULL;           /* reset mbuf ptr */
1059         chan->in_cbptr = NULL;          /* reset mbuf curr ptr */
1060         chan->in_len = 0;               /* reset mbuf data len */
1061
1062         /* transmitter part */
1063
1064         chan->tx_queue.ifq_maxlen = IFQ_MAXLEN;
1065
1066 #if defined (__FreeBSD__) && __FreeBSD__ > 4
1067         mtx_init(&chan->tx_queue.ifq_mtx, "i4b_avm_pnp_tx", MTX_DEF);
1068 #endif
1069         i4b_Bcleanifq(&chan->tx_queue); /* clean tx queue */
1070
1071         chan->txcount = 0;              /* reset tx counter */
1072
1073         i4b_Bfreembuf(chan->out_mbuf_head);     /* clean tx mbuf */
1074
1075         chan->out_mbuf_head = NULL;     /* reset head mbuf ptr */
1076         chan->out_mbuf_cur = NULL;      /* reset current mbuf ptr */
1077         chan->out_mbuf_cur_ptr = NULL;  /* reset current mbuf data ptr */
1078         chan->out_mbuf_cur_len = 0;     /* reset current mbuf data cnt */
1079
1080         if(activate != 0)
1081         {
1082                 /* activation */
1083                 avm_pnp_hscx_init(sc, h_chan, activate);
1084                 chan->state |= HSCX_AVMA1PP_ACTIVE;
1085         }
1086
1087         splx(s);
1088 }
1089
1090 static void
1091 avm_pnp_bchannel_start(int unit, int h_chan)
1092 {
1093         struct l1_softc *sc = ifpnp_scp[unit];
1094         register l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
1095         int s;
1096         int activity = -1;
1097
1098         s = SPLI4B();                           /* enter critical section */
1099         if(chan->state & HSCX_TX_ACTIVE)        /* already running ? */
1100         {
1101                 splx(s);
1102                 return;                         /* yes, leave */
1103         }
1104
1105         /* get next mbuf from queue */
1106
1107         IF_DEQUEUE(&chan->tx_queue, chan->out_mbuf_head);
1108
1109         if(chan->out_mbuf_head == NULL)         /* queue empty ? */
1110         {
1111                 splx(s);                        /* leave critical section */
1112                 return;                         /* yes, exit */
1113         }
1114
1115         /* init current mbuf values */
1116
1117         chan->out_mbuf_cur = chan->out_mbuf_head;
1118         chan->out_mbuf_cur_len = chan->out_mbuf_cur->m_len;
1119         chan->out_mbuf_cur_ptr = chan->out_mbuf_cur->m_data;
1120
1121         /* activity indicator for timeout handling */
1122
1123         if(chan->bprot == BPROT_NONE)
1124         {
1125                 if(!(i4b_l1_bchan_tel_silence(chan->out_mbuf_cur->m_data, chan->out_mbuf_cur->m_len)))
1126                         activity = ACT_TX;
1127         }
1128         else
1129         {
1130                 activity = ACT_TX;
1131         }
1132
1133         chan->state |= HSCX_TX_ACTIVE;          /* we start transmitting */
1134
1135         if(sc->sc_trace & TRACE_B_TX)   /* if trace, send mbuf to trace dev */
1136         {
1137                 i4b_trace_hdr_t hdr;
1138                 hdr.unit = L0IFPNPUNIT(sc->sc_unit);
1139                 hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
1140                 hdr.dir = FROM_TE;
1141                 hdr.count = ++sc->sc_trace_bcount;
1142                 MICROTIME(hdr.time);
1143                 i4b_l1_trace_ind(&hdr, chan->out_mbuf_cur->m_len, chan->out_mbuf_cur->m_data);
1144         }
1145
1146         avm_pnp_hscx_fifo(chan, sc);
1147
1148         /* call timeout handling routine */
1149
1150         if(activity == ACT_RX || activity == ACT_TX)
1151                 (*chan->isic_drvr_linktab->bch_activity)(chan->isic_drvr_linktab->unit, activity);
1152
1153         splx(s);
1154 }
1155
1156 /*---------------------------------------------------------------------------*
1157  *      return the address of isic drivers linktab
1158  *---------------------------------------------------------------------------*/
1159 static isdn_link_t *
1160 avm_pnp_ret_linktab(int unit, int channel)
1161 {
1162         struct l1_softc *sc = ifpnp_scp[unit];
1163         l1_bchan_state_t *chan = &sc->sc_chan[channel];
1164
1165         return(&chan->isic_isdn_linktab);
1166 }
1167
1168 /*---------------------------------------------------------------------------*
1169  *      set the driver linktab in the b channel softc
1170  *---------------------------------------------------------------------------*/
1171 static void
1172 avm_pnp_set_linktab(int unit, int channel, drvr_link_t *dlt)
1173 {
1174         struct l1_softc *sc = ifpnp_scp[unit];
1175         l1_bchan_state_t *chan = &sc->sc_chan[channel];
1176
1177         chan->isic_drvr_linktab = dlt;
1178 }
1179
1180
1181 /*---------------------------------------------------------------------------*
1182  *      initialize our local linktab
1183  *---------------------------------------------------------------------------*/
1184 static void
1185 avm_pnp_init_linktab(struct l1_softc *sc)
1186 {
1187         l1_bchan_state_t *chan = &sc->sc_chan[HSCX_CH_A];
1188         isdn_link_t *lt = &chan->isic_isdn_linktab;
1189
1190         /* make sure the hardware driver is known to layer 4 */
1191         /* avoid overwriting if already set */
1192         if (ctrl_types[CTRL_PASSIVE].set_linktab == NULL)
1193         {
1194                 ctrl_types[CTRL_PASSIVE].set_linktab = avm_pnp_set_linktab;
1195                 ctrl_types[CTRL_PASSIVE].get_linktab = avm_pnp_ret_linktab;
1196         }
1197
1198         /* local setup */
1199         lt->unit = sc->sc_unit;
1200         lt->channel = HSCX_CH_A;
1201         lt->bch_config = avm_pnp_bchannel_setup;
1202         lt->bch_tx_start = avm_pnp_bchannel_start;
1203         lt->bch_stat = avm_pnp_bchannel_stat;
1204         lt->tx_queue = &chan->tx_queue;
1205
1206         /* used by non-HDLC data transfers, i.e. telephony drivers */
1207         lt->rx_queue = &chan->rx_queue;
1208
1209         /* used by HDLC data transfers, i.e. ipr and isp drivers */
1210         lt->rx_mbuf = &chan->in_mbuf;
1211
1212         chan = &sc->sc_chan[HSCX_CH_B];
1213         lt = &chan->isic_isdn_linktab;
1214
1215         lt->unit = sc->sc_unit;
1216         lt->channel = HSCX_CH_B;
1217         lt->bch_config = avm_pnp_bchannel_setup;
1218         lt->bch_tx_start = avm_pnp_bchannel_start;
1219         lt->bch_stat = avm_pnp_bchannel_stat;
1220         lt->tx_queue = &chan->tx_queue;
1221
1222         /* used by non-HDLC data transfers, i.e. telephony drivers */
1223         lt->rx_queue = &chan->rx_queue;
1224
1225         /* used by HDLC data transfers, i.e. ipr and isp drivers */
1226         lt->rx_mbuf = &chan->in_mbuf;
1227 }
1228
1229 /*
1230  * use this instead of isic_bchannel_stat in i4b_bchan.c because it's static
1231  */
1232 static void
1233 avm_pnp_bchannel_stat(int unit, int h_chan, bchan_statistics_t *bsp)
1234 {
1235         struct l1_softc *sc = ifpnp_scp[unit];
1236         l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
1237         int s;
1238
1239         s = SPLI4B();
1240
1241         bsp->outbytes = chan->txcount;
1242         bsp->inbytes = chan->rxcount;
1243
1244         chan->txcount = 0;
1245         chan->rxcount = 0;
1246
1247         splx(s);
1248 }
1249
1250 /*---------------------------------------------------------------------------*
1251  *      fill HSCX fifo with data from the current mbuf
1252  *      Put this here until it can go into i4b_hscx.c
1253  *---------------------------------------------------------------------------*/
1254 static int
1255 avm_pnp_hscx_fifo(l1_bchan_state_t *chan, struct l1_softc *sc)
1256 {
1257         int len;
1258         int nextlen;
1259         int i;
1260         int cmd = 0;
1261         /* using a scratch buffer simplifies writing to the FIFO */
1262         u_char scrbuf[HSCX_FIFO_LEN];
1263
1264         len = 0;
1265
1266         /*
1267          * fill the HSCX tx fifo with data from the current mbuf. if
1268          * current mbuf holds less data than HSCX fifo length, try to
1269          * get the next mbuf from (a possible) mbuf chain. if there is
1270          * not enough data in a single mbuf or in a chain, then this
1271          * is the last mbuf and we tell the HSCX that it has to send
1272          * CRC and closing flag
1273          */
1274
1275         while(chan->out_mbuf_cur && len != sc->sc_bfifolen)
1276         {
1277                 nextlen = min(chan->out_mbuf_cur_len, sc->sc_bfifolen - len);
1278
1279 #ifdef NOTDEF
1280                 printf("i:mh=%p, mc=%p, mcp=%p, mcl=%d l=%d nl=%d # ",
1281                         chan->out_mbuf_head,
1282                         chan->out_mbuf_cur,
1283                         chan->out_mbuf_cur_ptr,
1284                         chan->out_mbuf_cur_len,
1285                         len,
1286                         nextlen);
1287 #endif
1288
1289                 cmd |= HSCX_CMDR_XTF;
1290                 /* collect the data in the scratch buffer */
1291                 for (i = 0; i < nextlen; i++)
1292                         scrbuf[i + len] = chan->out_mbuf_cur_ptr[i];
1293
1294                 len += nextlen;
1295                 chan->txcount += nextlen;
1296
1297                 chan->out_mbuf_cur_ptr += nextlen;
1298                 chan->out_mbuf_cur_len -= nextlen;
1299
1300                 if(chan->out_mbuf_cur_len == 0)
1301                 {
1302                         if((chan->out_mbuf_cur = chan->out_mbuf_cur->m_next) != NULL)
1303                         {
1304                                 chan->out_mbuf_cur_ptr = chan->out_mbuf_cur->m_data;
1305                                 chan->out_mbuf_cur_len = chan->out_mbuf_cur->m_len;
1306
1307                                 if(sc->sc_trace & TRACE_B_TX)
1308                                 {
1309                                         i4b_trace_hdr_t hdr;
1310                                         hdr.unit = L0IFPNPUNIT(sc->sc_unit);
1311                                         hdr.type = (chan->channel == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
1312                                         hdr.dir = FROM_TE;
1313                                         hdr.count = ++sc->sc_trace_bcount;
1314                                         MICROTIME(hdr.time);
1315                                         i4b_l1_trace_ind(&hdr, chan->out_mbuf_cur->m_len, chan->out_mbuf_cur->m_data);
1316                                 }
1317                         }
1318                         else
1319                         {
1320                                 if (chan->bprot != BPROT_NONE)
1321                                         cmd |= HSCX_CMDR_XME;
1322                                 i4b_Bfreembuf(chan->out_mbuf_head);
1323                                 chan->out_mbuf_head = NULL;
1324                         }
1325                 }
1326         }
1327         /* write what we have from the scratch buf to the HSCX fifo */
1328         if (len != 0)
1329                 HSCX_WRFIFO(chan->channel, scrbuf, len);
1330         return(cmd);
1331 }
1332
1333 /*---------------------------------------------------------------------------*
1334  *      ifpnp - ISAC interrupt routine
1335  *---------------------------------------------------------------------------*/
1336 static void
1337 ifpnp_isac_intr(struct l1_softc *sc)
1338 {
1339         register u_char isac_irq_stat;
1340
1341         for(;;)
1342         {
1343                 /* get isac irq status */
1344                 isac_irq_stat = ISAC_READ(I_ISTA);
1345
1346                 if(isac_irq_stat)
1347                         ifpnp_isac_irq(sc, isac_irq_stat); /* isac handler */
1348                 else
1349                         break;
1350         }
1351
1352         ISAC_WRITE(I_MASK, 0xff);
1353
1354         DELAY(100);
1355
1356         ISAC_WRITE(I_MASK, ISAC_IMASK);
1357 }
1358
1359 /*---------------------------------------------------------------------------*
1360  *      ifpnp_recover - try to recover from irq lockup
1361  *---------------------------------------------------------------------------*/
1362 void
1363 ifpnp_recover(struct l1_softc *sc)
1364 {
1365         u_char byte;
1366
1367         /* get isac irq status */
1368
1369         byte = ISAC_READ(I_ISTA);
1370
1371         NDBGL1(L1_ERROR, "  ISAC: ISTA = 0x%x", byte);
1372
1373         if(byte & ISAC_ISTA_EXI)
1374                 NDBGL1(L1_ERROR, "  ISAC: EXIR = 0x%x", (u_char)ISAC_READ(I_EXIR));
1375
1376         if(byte & ISAC_ISTA_CISQ)
1377         {
1378                 byte = ISAC_READ(I_CIRR);
1379
1380                 NDBGL1(L1_ERROR, "  ISAC: CISQ = 0x%x", byte);
1381
1382                 if(byte & ISAC_CIRR_SQC)
1383                         NDBGL1(L1_ERROR, "  ISAC: SQRR = 0x%x", (u_char)ISAC_READ(I_SQRR));
1384         }
1385
1386         NDBGL1(L1_ERROR, "  ISAC: IMASK = 0x%x", ISAC_IMASK);
1387
1388         ISAC_WRITE(I_MASK, 0xff);
1389         DELAY(100);
1390         ISAC_WRITE(I_MASK, ISAC_IMASK);
1391 }
1392
1393 #endif /* NIFPNP > 0 */