sys/dev/netif/igb/if_igb.c

   1 /*
   2  * Copyright (c) 2001-2011, Intel Corporation
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *
   8  *  1. Redistributions of source code must retain the above copyright notice,
   9  *     this list of conditions and the following disclaimer.
  10  *
  11  *  2. Redistributions in binary form must reproduce the above copyright
  12  *     notice, this list of conditions and the following disclaimer in the
  13  *     documentation and/or other materials provided with the distribution.
  14  *
  15  *  3. Neither the name of the Intel Corporation nor the names of its
  16  *     contributors may be used to endorse or promote products derived from
  17  *     this software without specific prior written permission.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  20  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  22  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  23  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  29  * POSSIBILITY OF SUCH DAMAGE.
  30  */
  31
  32 #include "opt_polling.h"
  33 #include "opt_igb.h"
  34
  35 #include <sys/param.h>
  36 #include <sys/bus.h>
  37 #include <sys/endian.h>
  38 #include <sys/interrupt.h>
  39 #include <sys/kernel.h>
  40 #include <sys/malloc.h>
  41 #include <sys/mbuf.h>
  42 #include <sys/proc.h>
  43 #include <sys/rman.h>
  44 #include <sys/serialize.h>
  45 #include <sys/serialize2.h>
  46 #include <sys/socket.h>
  47 #include <sys/sockio.h>
  48 #include <sys/sysctl.h>
  49 #include <sys/systm.h>
  50
  51 #include <net/bpf.h>
  52 #include <net/ethernet.h>
  53 #include <net/if.h>
  54 #include <net/if_arp.h>
  55 #include <net/if_dl.h>
  56 #include <net/if_media.h>
  57 #include <net/ifq_var.h>
  58 #include <net/toeplitz.h>
  59 #include <net/toeplitz2.h>
  60 #include <net/vlan/if_vlan_var.h>
  61 #include <net/vlan/if_vlan_ether.h>
  62 #include <net/if_poll.h>
  63
  64 #include <netinet/in_systm.h>
  65 #include <netinet/in.h>
  66 #include <netinet/ip.h>
  67 #include <netinet/tcp.h>
  68 #include <netinet/udp.h>
  69
  70 #include <bus/pci/pcivar.h>
  71 #include <bus/pci/pcireg.h>
  72
  73 #include <dev/netif/ig_hal/e1000_api.h>
  74 #include <dev/netif/ig_hal/e1000_82575.h>
  75 #include <dev/netif/igb/if_igb.h>
  76
  77 #ifdef IGB_RSS_DEBUG
  78 #define IGB_RSS_DPRINTF(sc, lvl, fmt, ...) \
  79 do { \
  80         if (sc->rss_debug >= lvl) \
  81                 if_printf(&sc->arpcom.ac_if, fmt, __VA_ARGS__); \
  82 } while (0)
  83 #else   /* !IGB_RSS_DEBUG */
  84 #define IGB_RSS_DPRINTF(sc, lvl, fmt, ...)      ((void)0)
  85 #endif  /* IGB_RSS_DEBUG */
  86
  87 #define IGB_NAME        "Intel(R) PRO/1000 "
  88 #define IGB_DEVICE(id)  \
  89         { IGB_VENDOR_ID, E1000_DEV_ID_##id, IGB_NAME #id }
  90 #define IGB_DEVICE_NULL { 0, 0, NULL }
  91
  92 static struct igb_device {
  93         uint16_t        vid;
  94         uint16_t        did;
  95         const char      *desc;
  96 } igb_devices[] = {
  97         IGB_DEVICE(82575EB_COPPER),
  98         IGB_DEVICE(82575EB_FIBER_SERDES),
  99         IGB_DEVICE(82575GB_QUAD_COPPER),
 100         IGB_DEVICE(82576),
 101         IGB_DEVICE(82576_NS),
 102         IGB_DEVICE(82576_NS_SERDES),
 103         IGB_DEVICE(82576_FIBER),
 104         IGB_DEVICE(82576_SERDES),
 105         IGB_DEVICE(82576_SERDES_QUAD),
 106         IGB_DEVICE(82576_QUAD_COPPER),
 107         IGB_DEVICE(82576_QUAD_COPPER_ET2),
 108         IGB_DEVICE(82576_VF),
 109         IGB_DEVICE(82580_COPPER),
 110         IGB_DEVICE(82580_FIBER),
 111         IGB_DEVICE(82580_SERDES),
 112         IGB_DEVICE(82580_SGMII),
 113         IGB_DEVICE(82580_COPPER_DUAL),
 114         IGB_DEVICE(82580_QUAD_FIBER),
 115         IGB_DEVICE(DH89XXCC_SERDES),
 116         IGB_DEVICE(DH89XXCC_SGMII),
 117         IGB_DEVICE(DH89XXCC_SFP),
 118         IGB_DEVICE(DH89XXCC_BACKPLANE),
 119         IGB_DEVICE(I350_COPPER),
 120         IGB_DEVICE(I350_FIBER),
 121         IGB_DEVICE(I350_SERDES),
 122         IGB_DEVICE(I350_SGMII),
 123         IGB_DEVICE(I350_VF),
 124
 125         /* required last entry */
 126         IGB_DEVICE_NULL
 127 };
 128
 129 static int      igb_probe(device_t);
 130 static int      igb_attach(device_t);
 131 static int      igb_detach(device_t);
 132 static int      igb_shutdown(device_t);
 133 static int      igb_suspend(device_t);
 134 static int      igb_resume(device_t);
 135
 136 static boolean_t igb_is_valid_ether_addr(const uint8_t *);
 137 static void     igb_setup_ifp(struct igb_softc *);
 138 static int      igb_txctx_pullup(struct igb_tx_ring *, struct mbuf **);
 139 static boolean_t igb_txctx(struct igb_tx_ring *, struct mbuf *);
 140 static void     igb_add_sysctl(struct igb_softc *);
 141 static int      igb_sysctl_intr_rate(SYSCTL_HANDLER_ARGS);
 142 static int      igb_sysctl_tx_intr_nsegs(SYSCTL_HANDLER_ARGS);
 143
 144 static void     igb_vf_init_stats(struct igb_softc *);
 145 static void     igb_reset(struct igb_softc *);
 146 static void     igb_update_stats_counters(struct igb_softc *);
 147 static void     igb_update_vf_stats_counters(struct igb_softc *);
 148 static void     igb_update_link_status(struct igb_softc *);
 149 static void     igb_init_tx_unit(struct igb_softc *);
 150 static void     igb_init_rx_unit(struct igb_softc *);
 151
 152 static void     igb_set_vlan(struct igb_softc *);
 153 static void     igb_set_multi(struct igb_softc *);
 154 static void     igb_set_promisc(struct igb_softc *);
 155 static void     igb_disable_promisc(struct igb_softc *);
 156
 157 static int      igb_alloc_rings(struct igb_softc *);
 158 static void     igb_free_rings(struct igb_softc *);
 159 static int      igb_create_tx_ring(struct igb_tx_ring *);
 160 static int      igb_create_rx_ring(struct igb_rx_ring *);
 161 static void     igb_free_tx_ring(struct igb_tx_ring *);
 162 static void     igb_free_rx_ring(struct igb_rx_ring *);
 163 static void     igb_destroy_tx_ring(struct igb_tx_ring *, int);
 164 static void     igb_destroy_rx_ring(struct igb_rx_ring *, int);
 165 static void     igb_init_tx_ring(struct igb_tx_ring *);
 166 static int      igb_init_rx_ring(struct igb_rx_ring *);
 167 static int      igb_newbuf(struct igb_rx_ring *, int, boolean_t);
 168 static int      igb_encap(struct igb_tx_ring *, struct mbuf **);
 169
 170 static void     igb_stop(struct igb_softc *);
 171 static void     igb_init(void *);
 172 static int      igb_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
 173 static void     igb_media_status(struct ifnet *, struct ifmediareq *);
 174 static int      igb_media_change(struct ifnet *);
 175 static void     igb_timer(void *);
 176 static void     igb_watchdog(struct ifnet *);
 177 static void     igb_start(struct ifnet *);
 178 #ifdef DEVICE_POLLING
 179 static void     igb_poll(struct ifnet *, enum poll_cmd, int);
 180 #endif
 181 static void     igb_serialize(struct ifnet *, enum ifnet_serialize);
 182 static void     igb_deserialize(struct ifnet *, enum ifnet_serialize);
 183 static int      igb_tryserialize(struct ifnet *, enum ifnet_serialize);
 184 #ifdef INVARIANTS
 185 static void     igb_serialize_assert(struct ifnet *, enum ifnet_serialize,
 186                     boolean_t);
 187 #endif
 188
 189 static void     igb_intr(void *);
 190 static void     igb_shared_intr(void *);
 191 static void     igb_rxeof(struct igb_rx_ring *, int);
 192 static void     igb_txeof(struct igb_tx_ring *);
 193 static void     igb_set_eitr(struct igb_softc *);
 194 static void     igb_enable_intr(struct igb_softc *);
 195 static void     igb_disable_intr(struct igb_softc *);
 196 static void     igb_init_unshared_intr(struct igb_softc *);
 197 static void     igb_init_intr(struct igb_softc *);
 198 static int      igb_setup_intr(struct igb_softc *);
 199 static void     igb_setup_tx_intr(struct igb_tx_ring *, int *, int);
 200 static void     igb_setup_rx_intr(struct igb_rx_ring *, int *, int);
 201 static void     igb_set_intr_mask(struct igb_softc *);
 202
 203 /* Management and WOL Support */
 204 static void     igb_get_mgmt(struct igb_softc *);
 205 static void     igb_rel_mgmt(struct igb_softc *);
 206 static void     igb_get_hw_control(struct igb_softc *);
 207 static void     igb_rel_hw_control(struct igb_softc *);
 208 static void     igb_enable_wol(device_t);
 209
 210 static device_method_t igb_methods[] = {
 211         /* Device interface */
 212         DEVMETHOD(device_probe,         igb_probe),
 213         DEVMETHOD(device_attach,        igb_attach),
 214         DEVMETHOD(device_detach,        igb_detach),
 215         DEVMETHOD(device_shutdown,      igb_shutdown),
 216         DEVMETHOD(device_suspend,       igb_suspend),
 217         DEVMETHOD(device_resume,        igb_resume),
 218         { 0, 0 }
 219 };
 220
 221 static driver_t igb_driver = {
 222         "igb",
 223         igb_methods,
 224         sizeof(struct igb_softc),
 225 };
 226
 227 static devclass_t igb_devclass;
 228
 229 DECLARE_DUMMY_MODULE(if_igb);
 230 MODULE_DEPEND(igb, ig_hal, 1, 1, 1);
 231 DRIVER_MODULE(if_igb, pci, igb_driver, igb_devclass, NULL, NULL);
 232
 233 static int      igb_rxd = IGB_DEFAULT_RXD;
 234 static int      igb_txd = IGB_DEFAULT_TXD;
 235 static int      igb_rxr = 0;
 236 static int      igb_msi_enable = 1;
 237 static int      igb_msix_enable = 1;
 238 static int      igb_eee_disabled = 1;   /* Energy Efficient Ethernet */
 239 static int      igb_fc_setting = e1000_fc_full;
 240
 241 /*
 242  * DMA Coalescing, only for i350 - default to off,
 243  * this feature is for power savings
 244  */
 245 static int      igb_dma_coalesce = 0;
 246
 247 TUNABLE_INT("hw.igb.rxd", &igb_rxd);
 248 TUNABLE_INT("hw.igb.txd", &igb_txd);
 249 TUNABLE_INT("hw.igb.rxr", &igb_rxr);
 250 TUNABLE_INT("hw.igb.msi.enable", &igb_msi_enable);
 251 TUNABLE_INT("hw.igb.msix.enable", &igb_msix_enable);
 252 TUNABLE_INT("hw.igb.fc_setting", &igb_fc_setting);
 253
 254 /* i350 specific */
 255 TUNABLE_INT("hw.igb.eee_disabled", &igb_eee_disabled);
 256 TUNABLE_INT("hw.igb.dma_coalesce", &igb_dma_coalesce);
 257
 258 static __inline void
 259 igb_rxcsum(uint32_t staterr, struct mbuf *mp)
 260 {
 261         /* Ignore Checksum bit is set */
 262         if (staterr & E1000_RXD_STAT_IXSM)
 263                 return;
 264
 265         if ((staterr & (E1000_RXD_STAT_IPCS | E1000_RXDEXT_STATERR_IPE)) ==
 266             E1000_RXD_STAT_IPCS)
 267                 mp->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | CSUM_IP_VALID;
 268
 269         if (staterr & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)) {
 270                 if ((staterr & E1000_RXDEXT_STATERR_TCPE) == 0) {
 271                         mp->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
 272                             CSUM_PSEUDO_HDR | CSUM_FRAG_NOT_CHECKED;
 273                         mp->m_pkthdr.csum_data = htons(0xffff);
 274                 }
 275         }
 276 }
 277
 278 static __inline struct pktinfo *
 279 igb_rssinfo(struct mbuf *m, struct pktinfo *pi,
 280     uint32_t hash, uint32_t hashtype, uint32_t staterr)
 281 {
 282         switch (hashtype) {
 283         case E1000_RXDADV_RSSTYPE_IPV4_TCP:
 284                 pi->pi_netisr = NETISR_IP;
 285                 pi->pi_flags = 0;
 286                 pi->pi_l3proto = IPPROTO_TCP;
 287                 break;
 288
 289         case E1000_RXDADV_RSSTYPE_IPV4:
 290                 if (staterr & E1000_RXD_STAT_IXSM)
 291                         return NULL;
 292
 293                 if ((staterr &
 294                      (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) ==
 295                     E1000_RXD_STAT_TCPCS) {
 296                         pi->pi_netisr = NETISR_IP;
 297                         pi->pi_flags = 0;
 298                         pi->pi_l3proto = IPPROTO_UDP;
 299                         break;
 300                 }
 301                 /* FALL THROUGH */
 302         default:
 303                 return NULL;
 304         }
 305
 306         m->m_flags |= M_HASH;
 307         m->m_pkthdr.hash = toeplitz_hash(hash);
 308         return pi;
 309 }
 310
 311 static int
 312 igb_probe(device_t dev)
 313 {
 314         const struct igb_device *d;
 315         uint16_t vid, did;
 316
 317         vid = pci_get_vendor(dev);
 318         did = pci_get_device(dev);
 319
 320         for (d = igb_devices; d->desc != NULL; ++d) {
 321                 if (vid == d->vid && did == d->did) {
 322                         device_set_desc(dev, d->desc);
 323                         return 0;
 324                 }
 325         }
 326         return ENXIO;
 327 }
 328
 329 static int
 330 igb_attach(device_t dev)
 331 {
 332         struct igb_softc *sc = device_get_softc(dev);
 333         uint16_t eeprom_data;
 334         u_int intr_flags;
 335         int error = 0, i, j, ring_max;
 336
 337 #ifdef notyet
 338         /* SYSCTL stuff */
 339         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 340             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 341             OID_AUTO, "nvm", CTLTYPE_INT|CTLFLAG_RW, adapter, 0,
 342             igb_sysctl_nvm_info, "I", "NVM Information");
 343
 344         SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
 345             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 346             OID_AUTO, "enable_aim", CTLTYPE_INT|CTLFLAG_RW,
 347             &igb_enable_aim, 1, "Interrupt Moderation");
 348
 349         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 350             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 351             OID_AUTO, "flow_control", CTLTYPE_INT|CTLFLAG_RW,
 352             adapter, 0, igb_set_flowcntl, "I", "Flow Control");
 353 #endif
 354
 355         callout_init_mp(&sc->timer);
 356
 357         sc->dev = sc->osdep.dev = dev;
 358
 359         /*
 360          * Determine hardware and mac type
 361          */
 362         sc->hw.vendor_id = pci_get_vendor(dev);
 363         sc->hw.device_id = pci_get_device(dev);
 364         sc->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1);
 365         sc->hw.subsystem_vendor_id = pci_read_config(dev, PCIR_SUBVEND_0, 2);
 366         sc->hw.subsystem_device_id = pci_read_config(dev, PCIR_SUBDEV_0, 2);
 367
 368         if (e1000_set_mac_type(&sc->hw))
 369                 return ENXIO;
 370
 371         /* Are we a VF device? */
 372         if (sc->hw.mac.type == e1000_vfadapt ||
 373             sc->hw.mac.type == e1000_vfadapt_i350)
 374                 sc->vf_ifp = 1;
 375         else
 376                 sc->vf_ifp = 0;
 377
 378         /* Enable bus mastering */
 379         pci_enable_busmaster(dev);
 380
 381         /*
 382          * Allocate IO memory
 383          */
 384         sc->mem_rid = PCIR_BAR(0);
 385         sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid,
 386             RF_ACTIVE);
 387         if (sc->mem_res == NULL) {
 388                 device_printf(dev, "Unable to allocate bus resource: memory\n");
 389                 error = ENXIO;
 390                 goto failed;
 391         }
 392         sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->mem_res);
 393         sc->osdep.mem_bus_space_handle = rman_get_bushandle(sc->mem_res);
 394
 395         sc->hw.hw_addr = (uint8_t *)&sc->osdep.mem_bus_space_handle;
 396
 397         /*
 398          * Allocate interrupt
 399          */
 400         sc->intr_type = pci_alloc_1intr(dev, igb_msi_enable,
 401             &sc->intr_rid, &intr_flags);
 402
 403         sc->intr_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->intr_rid,
 404             intr_flags);
 405         if (sc->intr_res == NULL) {
 406                 device_printf(dev, "Unable to allocate bus resource: "
 407                     "interrupt\n");
 408                 error = ENXIO;
 409                 goto failed;
 410         }
 411
 412         /* Save PCI command register for Shared Code */
 413         sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
 414         sc->hw.back = &sc->osdep;
 415
 416         switch (sc->hw.mac.type) {
 417         case e1000_82575:
 418                 ring_max = IGB_MAX_RING_82575;
 419                 break;
 420         case e1000_82580:
 421                 ring_max = IGB_MAX_RING_82580;
 422                 break;
 423         case e1000_i350:
 424                 ring_max = IGB_MAX_RING_I350;
 425                 break;
 426         case e1000_82576:
 427                 ring_max = IGB_MAX_RING_82576;
 428                 break;
 429         default:
 430                 ring_max = IGB_MIN_RING;
 431                 break;
 432         }
 433         sc->rx_ring_cnt = device_getenv_int(dev, "rxr", igb_rxr);
 434         sc->rx_ring_cnt = if_ring_count2(sc->rx_ring_cnt, ring_max);
 435 #ifdef IGB_RSS_DEBUG
 436         sc->rx_ring_cnt = device_getenv_int(dev, "rxr_debug", sc->rx_ring_cnt);
 437 #endif
 438         sc->rx_ring_inuse = sc->rx_ring_cnt;
 439         sc->tx_ring_cnt = 1; /* XXX */
 440
 441         sc->intr_rate = IGB_INTR_RATE;
 442
 443         /* Do Shared Code initialization */
 444         if (e1000_setup_init_funcs(&sc->hw, TRUE)) {
 445                 device_printf(dev, "Setup of Shared code failed\n");
 446                 error = ENXIO;
 447                 goto failed;
 448         }
 449
 450         e1000_get_bus_info(&sc->hw);
 451
 452         sc->hw.mac.autoneg = DO_AUTO_NEG;
 453         sc->hw.phy.autoneg_wait_to_complete = FALSE;
 454         sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
 455
 456         /* Copper options */
 457         if (sc->hw.phy.media_type == e1000_media_type_copper) {
 458                 sc->hw.phy.mdix = AUTO_ALL_MODES;
 459                 sc->hw.phy.disable_polarity_correction = FALSE;
 460                 sc->hw.phy.ms_type = IGB_MASTER_SLAVE;
 461         }
 462
 463         /* Set the frame limits assuming  standard ethernet sized frames. */
 464         sc->max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN;
 465
 466         /* Allocate RX/TX rings */
 467         error = igb_alloc_rings(sc);
 468         if (error)
 469                 goto failed;
 470
 471         /*
 472          * Setup serializers
 473          */
 474         lwkt_serialize_init(&sc->main_serialize);
 475         i = 0;
 476         sc->serializes[i++] = &sc->main_serialize;
 477
 478         sc->tx_serialize = i;
 479         for (j = 0; j < sc->tx_ring_cnt; ++j)
 480                 sc->serializes[i++] = &sc->tx_rings[j].tx_serialize;
 481
 482         sc->rx_serialize = i;
 483         for (j = 0; j < sc->rx_ring_cnt; ++j)
 484                 sc->serializes[i++] = &sc->rx_rings[j].rx_serialize;
 485
 486         sc->serialize_cnt = i;
 487         KKASSERT(sc->serialize_cnt <= IGB_NSERIALIZE);
 488
 489         /* Allocate the appropriate stats memory */
 490         if (sc->vf_ifp) {
 491                 sc->stats = kmalloc(sizeof(struct e1000_vf_stats), M_DEVBUF,
 492                     M_WAITOK | M_ZERO);
 493                 igb_vf_init_stats(sc);
 494         } else {
 495                 sc->stats = kmalloc(sizeof(struct e1000_hw_stats), M_DEVBUF,
 496                     M_WAITOK | M_ZERO);
 497         }
 498
 499         /* Allocate multicast array memory. */
 500         sc->mta = kmalloc(ETHER_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES,
 501             M_DEVBUF, M_WAITOK);
 502
 503         /* Some adapter-specific advanced features */
 504         if (sc->hw.mac.type >= e1000_i350) {
 505 #ifdef notyet
 506                 igb_set_sysctl_value(adapter, "dma_coalesce",
 507                     "configure dma coalesce",
 508                     &adapter->dma_coalesce, igb_dma_coalesce);
 509                 igb_set_sysctl_value(adapter, "eee_disabled",
 510                     "enable Energy Efficient Ethernet",
 511                     &adapter->hw.dev_spec._82575.eee_disable,
 512                     igb_eee_disabled);
 513 #else
 514                 sc->dma_coalesce = igb_dma_coalesce;
 515                 sc->hw.dev_spec._82575.eee_disable = igb_eee_disabled;
 516 #endif
 517                 e1000_set_eee_i350(&sc->hw);
 518         }
 519
 520         /*
 521          * Start from a known state, this is important in reading the nvm and
 522          * mac from that.
 523          */
 524         e1000_reset_hw(&sc->hw);
 525
 526         /* Make sure we have a good EEPROM before we read from it */
 527         if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
 528                 /*
 529                  * Some PCI-E parts fail the first check due to
 530                  * the link being in sleep state, call it again,
 531                  * if it fails a second time its a real issue.
 532                  */
 533                 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
 534                         device_printf(dev,
 535                             "The EEPROM Checksum Is Not Valid\n");
 536                         error = EIO;
 537                         goto failed;
 538                 }
 539         }
 540
 541         /* Copy the permanent MAC address out of the EEPROM */
 542         if (e1000_read_mac_addr(&sc->hw) < 0) {
 543                 device_printf(dev, "EEPROM read error while reading MAC"
 544                     " address\n");
 545                 error = EIO;
 546                 goto failed;
 547         }
 548         if (!igb_is_valid_ether_addr(sc->hw.mac.addr)) {
 549                 device_printf(dev, "Invalid MAC address\n");
 550                 error = EIO;
 551                 goto failed;
 552         }
 553
 554 #ifdef notyet
 555         /*
 556         ** Configure Interrupts
 557         */
 558         if ((adapter->msix > 1) && (igb_enable_msix))
 559                 error = igb_allocate_msix(adapter);
 560         else /* MSI or Legacy */
 561                 error = igb_allocate_legacy(adapter);
 562         if (error)
 563                 goto err_late;
 564 #endif
 565
 566         /* Setup OS specific network interface */
 567         igb_setup_ifp(sc);
 568
 569         /* Add sysctl tree, must after igb_setup_ifp() */
 570         igb_add_sysctl(sc);
 571
 572         /* Now get a good starting state */
 573         igb_reset(sc);
 574
 575         /* Initialize statistics */
 576         igb_update_stats_counters(sc);
 577
 578         sc->hw.mac.get_link_status = 1;
 579         igb_update_link_status(sc);
 580
 581         /* Indicate SOL/IDER usage */
 582         if (e1000_check_reset_block(&sc->hw)) {
 583                 device_printf(dev,
 584                     "PHY reset is blocked due to SOL/IDER session.\n");
 585         }
 586
 587         /* Determine if we have to control management hardware */
 588         if (e1000_enable_mng_pass_thru(&sc->hw))
 589                 sc->flags |= IGB_FLAG_HAS_MGMT;
 590
 591         /*
 592          * Setup Wake-on-Lan
 593          */
 594         /* APME bit in EEPROM is mapped to WUC.APME */
 595         eeprom_data = E1000_READ_REG(&sc->hw, E1000_WUC) & E1000_WUC_APME;
 596         if (eeprom_data)
 597                 sc->wol = E1000_WUFC_MAG;
 598         /* XXX disable WOL */
 599         sc->wol = 0;
 600
 601 #ifdef notyet
 602         /* Register for VLAN events */
 603         adapter->vlan_attach = EVENTHANDLER_REGISTER(vlan_config,
 604              igb_register_vlan, adapter, EVENTHANDLER_PRI_FIRST);
 605         adapter->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig,
 606              igb_unregister_vlan, adapter, EVENTHANDLER_PRI_FIRST);
 607 #endif
 608
 609 #ifdef notyet
 610         igb_add_hw_stats(adapter);
 611 #endif
 612
 613         error = igb_setup_intr(sc);
 614         if (error) {
 615                 ether_ifdetach(&sc->arpcom.ac_if);
 616                 goto failed;
 617         }
 618         return 0;
 619
 620 failed:
 621         igb_detach(dev);
 622         return error;
 623 }
 624
 625 static int
 626 igb_detach(device_t dev)
 627 {
 628         struct igb_softc *sc = device_get_softc(dev);
 629
 630         if (device_is_attached(dev)) {
 631                 struct ifnet *ifp = &sc->arpcom.ac_if;
 632
 633                 ifnet_serialize_all(ifp);
 634
 635                 igb_stop(sc);
 636
 637                 e1000_phy_hw_reset(&sc->hw);
 638
 639                 /* Give control back to firmware */
 640                 igb_rel_mgmt(sc);
 641                 igb_rel_hw_control(sc);
 642
 643                 if (sc->wol) {
 644                         E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
 645                         E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
 646                         igb_enable_wol(dev);
 647                 }
 648
 649                 bus_teardown_intr(dev, sc->intr_res, sc->intr_tag);
 650
 651                 ifnet_deserialize_all(ifp);
 652
 653                 ether_ifdetach(ifp);
 654         } else if (sc->mem_res != NULL) {
 655                 igb_rel_hw_control(sc);
 656         }
 657         bus_generic_detach(dev);
 658
 659         if (sc->intr_res != NULL) {
 660                 bus_release_resource(dev, SYS_RES_IRQ, sc->intr_rid,
 661                     sc->intr_res);
 662         }
 663         if (sc->intr_type == PCI_INTR_TYPE_MSI)
 664                 pci_release_msi(dev);
 665
 666         if (sc->mem_res != NULL) {
 667                 bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid,
 668                     sc->mem_res);
 669         }
 670
 671         igb_free_rings(sc);
 672
 673         if (sc->mta != NULL)
 674                 kfree(sc->mta, M_DEVBUF);
 675         if (sc->stats != NULL)
 676                 kfree(sc->stats, M_DEVBUF);
 677
 678         if (sc->sysctl_tree != NULL)
 679                 sysctl_ctx_free(&sc->sysctl_ctx);
 680
 681         return 0;
 682 }
 683
 684 static int
 685 igb_shutdown(device_t dev)
 686 {
 687         return igb_suspend(dev);
 688 }
 689
 690 static int
 691 igb_suspend(device_t dev)
 692 {
 693         struct igb_softc *sc = device_get_softc(dev);
 694         struct ifnet *ifp = &sc->arpcom.ac_if;
 695
 696         ifnet_serialize_all(ifp);
 697
 698         igb_stop(sc);
 699
 700         igb_rel_mgmt(sc);
 701         igb_rel_hw_control(sc);
 702
 703         if (sc->wol) {
 704                 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
 705                 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
 706                 igb_enable_wol(dev);
 707         }
 708
 709         ifnet_deserialize_all(ifp);
 710
 711         return bus_generic_suspend(dev);
 712 }
 713
 714 static int
 715 igb_resume(device_t dev)
 716 {
 717         struct igb_softc *sc = device_get_softc(dev);
 718         struct ifnet *ifp = &sc->arpcom.ac_if;
 719
 720         ifnet_serialize_all(ifp);
 721
 722         igb_init(sc);
 723         igb_get_mgmt(sc);
 724
 725         if_devstart(ifp);
 726
 727         ifnet_deserialize_all(ifp);
 728
 729         return bus_generic_resume(dev);
 730 }
 731
 732 static int
 733 igb_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
 734 {
 735         struct igb_softc *sc = ifp->if_softc;
 736         struct ifreq *ifr = (struct ifreq *)data;
 737         int max_frame_size, mask, reinit;
 738         int error = 0;
 739
 740         ASSERT_IFNET_SERIALIZED_ALL(ifp);
 741
 742         switch (command) {
 743         case SIOCSIFMTU:
 744                 max_frame_size = 9234;
 745                 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN -
 746                     ETHER_CRC_LEN) {
 747                         error = EINVAL;
 748                         break;
 749                 }
 750
 751                 ifp->if_mtu = ifr->ifr_mtu;
 752                 sc->max_frame_size = ifp->if_mtu + ETHER_HDR_LEN +
 753                     ETHER_CRC_LEN;
 754
 755                 if (ifp->if_flags & IFF_RUNNING)
 756                         igb_init(sc);
 757                 break;
 758
 759         case SIOCSIFFLAGS:
 760                 if (ifp->if_flags & IFF_UP) {
 761                         if (ifp->if_flags & IFF_RUNNING) {
 762                                 if ((ifp->if_flags ^ sc->if_flags) &
 763                                     (IFF_PROMISC | IFF_ALLMULTI)) {
 764                                         igb_disable_promisc(sc);
 765                                         igb_set_promisc(sc);
 766                                 }
 767                         } else {
 768                                 igb_init(sc);
 769                         }
 770                 } else if (ifp->if_flags & IFF_RUNNING) {
 771                         igb_stop(sc);
 772                 }
 773                 sc->if_flags = ifp->if_flags;
 774                 break;
 775
 776         case SIOCADDMULTI:
 777         case SIOCDELMULTI:
 778                 if (ifp->if_flags & IFF_RUNNING) {
 779                         igb_disable_intr(sc);
 780                         igb_set_multi(sc);
 781 #ifdef DEVICE_POLLING
 782                         if (!(ifp->if_flags & IFF_POLLING))
 783 #endif
 784                                 igb_enable_intr(sc);
 785                 }
 786                 break;
 787
 788         case SIOCSIFMEDIA:
 789                 /*
 790                  * As the speed/duplex settings are being
 791                  * changed, we need toreset the PHY.
 792                  */
 793                 sc->hw.phy.reset_disable = FALSE;
 794
 795                 /* Check SOL/IDER usage */
 796                 if (e1000_check_reset_block(&sc->hw)) {
 797                         if_printf(ifp, "Media change is "
 798                             "blocked due to SOL/IDER session.\n");
 799                         break;
 800                 }
 801                 /* FALL THROUGH */
 802
 803         case SIOCGIFMEDIA:
 804                 error = ifmedia_ioctl(ifp, ifr, &sc->media, command);
 805                 break;
 806
 807         case SIOCSIFCAP:
 808                 reinit = 0;
 809                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
 810                 if (mask & IFCAP_HWCSUM) {
 811                         ifp->if_capenable ^= (mask & IFCAP_HWCSUM);
 812                         reinit = 1;
 813                 }
 814                 if (mask & IFCAP_VLAN_HWTAGGING) {
 815                         ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
 816                         reinit = 1;
 817                 }
 818                 if (mask & IFCAP_RSS)
 819                         ifp->if_capenable ^= IFCAP_RSS;
 820                 if (reinit && (ifp->if_flags & IFF_RUNNING))
 821                         igb_init(sc);
 822                 break;
 823
 824         default:
 825                 error = ether_ioctl(ifp, command, data);
 826                 break;
 827         }
 828         return error;
 829 }
 830
 831 static void
 832 igb_init(void *xsc)
 833 {
 834         struct igb_softc *sc = xsc;
 835         struct ifnet *ifp = &sc->arpcom.ac_if;
 836         int i;
 837
 838         ASSERT_IFNET_SERIALIZED_ALL(ifp);
 839
 840         igb_stop(sc);
 841
 842         /* Get the latest mac address, User can use a LAA */
 843         bcopy(IF_LLADDR(ifp), sc->hw.mac.addr, ETHER_ADDR_LEN);
 844
 845         /* Put the address into the Receive Address Array */
 846         e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0);
 847
 848         igb_reset(sc);
 849         igb_update_link_status(sc);
 850
 851         E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
 852
 853         /* Set hardware offload abilities */
 854         if (ifp->if_capenable & IFCAP_TXCSUM)
 855                 ifp->if_hwassist = IGB_CSUM_FEATURES;
 856         else
 857                 ifp->if_hwassist = 0;
 858
 859         /* Configure for OS presence */
 860         igb_get_mgmt(sc);
 861
 862         if (IGB_ENABLE_HWRSS(sc)) {
 863                 if (sc->intr_type != PCI_INTR_TYPE_MSIX
 864 #ifdef DEVICE_POLLING
 865                     || (ifp->if_flags & IFF_POLLING)
 866 #endif
 867                     ) {
 868                         sc->rx_ring_inuse = IGB_MIN_RING_RSS;
 869                         if (bootverbose) {
 870                                 if_printf(ifp, "RX rings %d/%d\n",
 871                                     sc->rx_ring_inuse, sc->rx_ring_cnt);
 872                         }
 873                 }
 874         }
 875
 876         /* Prepare transmit descriptors and buffers */
 877         for (i = 0; i < sc->tx_ring_cnt; ++i)
 878                 igb_init_tx_ring(&sc->tx_rings[i]);
 879         igb_init_tx_unit(sc);
 880
 881         /* Setup Multicast table */
 882         igb_set_multi(sc);
 883
 884 #if 0
 885         /*
 886          * Figure out the desired mbuf pool
 887          * for doing jumbo/packetsplit
 888          */
 889         if (adapter->max_frame_size <= 2048)
 890                 adapter->rx_mbuf_sz = MCLBYTES;
 891         else if (adapter->max_frame_size <= 4096)
 892                 adapter->rx_mbuf_sz = MJUMPAGESIZE;
 893         else
 894                 adapter->rx_mbuf_sz = MJUM9BYTES;
 895 #endif
 896
 897         /* Initialize interrupt */
 898         igb_init_intr(sc);
 899
 900         /* Prepare receive descriptors and buffers */
 901         for (i = 0; i < sc->rx_ring_inuse; ++i) {
 902                 int error;
 903
 904                 error = igb_init_rx_ring(&sc->rx_rings[i]);
 905                 if (error) {
 906                         if_printf(ifp, "Could not setup receive structures\n");
 907                         igb_stop(sc);
 908                         return;
 909                 }
 910         }
 911         igb_init_rx_unit(sc);
 912
 913         /* Enable VLAN support */
 914         if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
 915                 igb_set_vlan(sc);
 916
 917         /* Don't lose promiscuous settings */
 918         igb_set_promisc(sc);
 919
 920         ifp->if_flags |= IFF_RUNNING;
 921         ifp->if_flags &= ~IFF_OACTIVE;
 922
 923         callout_reset(&sc->timer, hz, igb_timer, sc);
 924         e1000_clear_hw_cntrs_base_generic(&sc->hw);
 925
 926 #if 0
 927         if (adapter->msix > 1) /* Set up queue routing */
 928                 igb_configure_queues(adapter);
 929 #endif
 930
 931         /* this clears any pending interrupts */
 932         E1000_READ_REG(&sc->hw, E1000_ICR);
 933 #ifdef DEVICE_POLLING
 934         /*
 935          * Only enable interrupts if we are not polling, make sure
 936          * they are off otherwise.
 937          */
 938         if (ifp->if_flags & IFF_POLLING)
 939                 igb_disable_intr(sc);
 940         else
 941 #endif /* DEVICE_POLLING */
 942         {
 943                 igb_enable_intr(sc);
 944                 E1000_WRITE_REG(&sc->hw, E1000_ICS, E1000_ICS_LSC);
 945         }
 946
 947         /* Set Energy Efficient Ethernet */
 948         e1000_set_eee_i350(&sc->hw);
 949
 950         /* Don't reset the phy next time init gets called */
 951         sc->hw.phy.reset_disable = TRUE;
 952 }
 953
 954 static void
 955 igb_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
 956 {
 957         struct igb_softc *sc = ifp->if_softc;
 958         u_char fiber_type = IFM_1000_SX;
 959
 960         ASSERT_IFNET_SERIALIZED_ALL(ifp);
 961
 962         igb_update_link_status(sc);
 963
 964         ifmr->ifm_status = IFM_AVALID;
 965         ifmr->ifm_active = IFM_ETHER;
 966
 967         if (!sc->link_active)
 968                 return;
 969
 970         ifmr->ifm_status |= IFM_ACTIVE;
 971
 972         if (sc->hw.phy.media_type == e1000_media_type_fiber ||
 973             sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
 974                 ifmr->ifm_active |= fiber_type | IFM_FDX;
 975         } else {
 976                 switch (sc->link_speed) {
 977                 case 10:
 978                         ifmr->ifm_active |= IFM_10_T;
 979                         break;
 980
 981                 case 100:
 982                         ifmr->ifm_active |= IFM_100_TX;
 983                         break;
 984
 985                 case 1000:
 986                         ifmr->ifm_active |= IFM_1000_T;
 987                         break;
 988                 }
 989                 if (sc->link_duplex == FULL_DUPLEX)
 990                         ifmr->ifm_active |= IFM_FDX;
 991                 else
 992                         ifmr->ifm_active |= IFM_HDX;
 993         }
 994 }
 995
 996 static int
 997 igb_media_change(struct ifnet *ifp)
 998 {
 999         struct igb_softc *sc = ifp->if_softc;
1000         struct ifmedia *ifm = &sc->media;
1001
1002         ASSERT_IFNET_SERIALIZED_ALL(ifp);
1003
1004         if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1005                 return EINVAL;
1006
1007         switch (IFM_SUBTYPE(ifm->ifm_media)) {
1008         case IFM_AUTO:
1009                 sc->hw.mac.autoneg = DO_AUTO_NEG;
1010                 sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
1011                 break;
1012
1013         case IFM_1000_LX:
1014         case IFM_1000_SX:
1015         case IFM_1000_T:
1016                 sc->hw.mac.autoneg = DO_AUTO_NEG;
1017                 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
1018                 break;
1019
1020         case IFM_100_TX:
1021                 sc->hw.mac.autoneg = FALSE;
1022                 sc->hw.phy.autoneg_advertised = 0;
1023                 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1024                         sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL;
1025                 else
1026                         sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF;
1027                 break;
1028
1029         case IFM_10_T:
1030                 sc->hw.mac.autoneg = FALSE;
1031                 sc->hw.phy.autoneg_advertised = 0;
1032                 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1033                         sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL;
1034                 else
1035                         sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF;
1036                 break;
1037
1038         default:
1039                 if_printf(ifp, "Unsupported media type\n");
1040                 break;
1041         }
1042
1043         igb_init(sc);
1044
1045         return 0;
1046 }
1047
1048 static void
1049 igb_set_promisc(struct igb_softc *sc)
1050 {
1051         struct ifnet *ifp = &sc->arpcom.ac_if;
1052         struct e1000_hw *hw = &sc->hw;
1053         uint32_t reg;
1054
1055         if (sc->vf_ifp) {
1056                 e1000_promisc_set_vf(hw, e1000_promisc_enabled);
1057                 return;
1058         }
1059
1060         reg = E1000_READ_REG(hw, E1000_RCTL);
1061         if (ifp->if_flags & IFF_PROMISC) {
1062                 reg |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1063                 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1064         } else if (ifp->if_flags & IFF_ALLMULTI) {
1065                 reg |= E1000_RCTL_MPE;
1066                 reg &= ~E1000_RCTL_UPE;
1067                 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1068         }
1069 }
1070
1071 static void
1072 igb_disable_promisc(struct igb_softc *sc)
1073 {
1074         struct e1000_hw *hw = &sc->hw;
1075         uint32_t reg;
1076
1077         if (sc->vf_ifp) {
1078                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
1079                 return;
1080         }
1081         reg = E1000_READ_REG(hw, E1000_RCTL);
1082         reg &= ~E1000_RCTL_UPE;
1083         reg &= ~E1000_RCTL_MPE;
1084         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1085 }
1086
1087 static void
1088 igb_set_multi(struct igb_softc *sc)
1089 {
1090         struct ifnet *ifp = &sc->arpcom.ac_if;
1091         struct ifmultiaddr *ifma;
1092         uint32_t reg_rctl = 0;
1093         uint8_t *mta;
1094         int mcnt = 0;
1095
1096         mta = sc->mta;
1097         bzero(mta, ETH_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES);
1098
1099         TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1100                 if (ifma->ifma_addr->sa_family != AF_LINK)
1101                         continue;
1102
1103                 if (mcnt == MAX_NUM_MULTICAST_ADDRESSES)
1104                         break;
1105
1106                 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1107                     &mta[mcnt * ETH_ADDR_LEN], ETH_ADDR_LEN);
1108                 mcnt++;
1109         }
1110
1111         if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) {
1112                 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1113                 reg_rctl |= E1000_RCTL_MPE;
1114                 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1115         } else {
1116                 e1000_update_mc_addr_list(&sc->hw, mta, mcnt);
1117         }
1118 }
1119
1120 static void
1121 igb_timer(void *xsc)
1122 {
1123         struct igb_softc *sc = xsc;
1124
1125         lwkt_serialize_enter(&sc->main_serialize);
1126
1127         igb_update_link_status(sc);
1128         igb_update_stats_counters(sc);
1129
1130         callout_reset(&sc->timer, hz, igb_timer, sc);
1131
1132         lwkt_serialize_exit(&sc->main_serialize);
1133 }
1134
1135 static void
1136 igb_update_link_status(struct igb_softc *sc)
1137 {
1138         struct ifnet *ifp = &sc->arpcom.ac_if;
1139         struct e1000_hw *hw = &sc->hw;
1140         uint32_t link_check, thstat, ctrl;
1141
1142         link_check = thstat = ctrl = 0;
1143
1144         /* Get the cached link value or read for real */
1145         switch (hw->phy.media_type) {
1146         case e1000_media_type_copper:
1147                 if (hw->mac.get_link_status) {
1148                         /* Do the work to read phy */
1149                         e1000_check_for_link(hw);
1150                         link_check = !hw->mac.get_link_status;
1151                 } else {
1152                         link_check = TRUE;
1153                 }
1154                 break;
1155
1156         case e1000_media_type_fiber:
1157                 e1000_check_for_link(hw);
1158                 link_check = E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU;
1159                 break;
1160
1161         case e1000_media_type_internal_serdes:
1162                 e1000_check_for_link(hw);
1163                 link_check = hw->mac.serdes_has_link;
1164                 break;
1165
1166         /* VF device is type_unknown */
1167         case e1000_media_type_unknown:
1168                 e1000_check_for_link(hw);
1169                 link_check = !hw->mac.get_link_status;
1170                 /* Fall thru */
1171         default:
1172                 break;
1173         }
1174
1175         /* Check for thermal downshift or shutdown */
1176         if (hw->mac.type == e1000_i350) {
1177                 thstat = E1000_READ_REG(hw, E1000_THSTAT);
1178                 ctrl = E1000_READ_REG(hw, E1000_CTRL_EXT);
1179         }
1180
1181         /* Now we check if a transition has happened */
1182         if (link_check && sc->link_active == 0) {
1183                 e1000_get_speed_and_duplex(hw,
1184                     &sc->link_speed, &sc->link_duplex);
1185                 if (bootverbose) {
1186                         if_printf(ifp, "Link is up %d Mbps %s\n",
1187                             sc->link_speed,
1188                             sc->link_duplex == FULL_DUPLEX ?
1189                             "Full Duplex" : "Half Duplex");
1190                 }
1191                 sc->link_active = 1;
1192
1193                 ifp->if_baudrate = sc->link_speed * 1000000;
1194                 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_GMII) &&
1195                     (thstat & E1000_THSTAT_LINK_THROTTLE))
1196                         if_printf(ifp, "Link: thermal downshift\n");
1197                 /* This can sleep */
1198                 ifp->if_link_state = LINK_STATE_UP;
1199                 if_link_state_change(ifp);
1200         } else if (!link_check && sc->link_active == 1) {
1201                 ifp->if_baudrate = sc->link_speed = 0;
1202                 sc->link_duplex = 0;
1203                 if (bootverbose)
1204                         if_printf(ifp, "Link is Down\n");
1205                 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_GMII) &&
1206                     (thstat & E1000_THSTAT_PWR_DOWN))
1207                         if_printf(ifp, "Link: thermal shutdown\n");
1208                 sc->link_active = 0;
1209                 /* This can sleep */
1210                 ifp->if_link_state = LINK_STATE_DOWN;
1211                 if_link_state_change(ifp);
1212         }
1213 }
1214
1215 static void
1216 igb_stop(struct igb_softc *sc)
1217 {
1218         struct ifnet *ifp = &sc->arpcom.ac_if;
1219         int i;
1220
1221         ASSERT_IFNET_SERIALIZED_ALL(ifp);
1222
1223         igb_disable_intr(sc);
1224
1225         callout_stop(&sc->timer);
1226
1227         ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1228         ifp->if_timer = 0;
1229
1230         e1000_reset_hw(&sc->hw);
1231         E1000_WRITE_REG(&sc->hw, E1000_WUC, 0);
1232
1233         e1000_led_off(&sc->hw);
1234         e1000_cleanup_led(&sc->hw);
1235
1236         for (i = 0; i < sc->tx_ring_cnt; ++i)
1237                 igb_free_tx_ring(&sc->tx_rings[i]);
1238         for (i = 0; i < sc->rx_ring_cnt; ++i)
1239                 igb_free_rx_ring(&sc->rx_rings[i]);
1240 }
1241
1242 static void
1243 igb_reset(struct igb_softc *sc)
1244 {
1245         struct ifnet *ifp = &sc->arpcom.ac_if;
1246         struct e1000_hw *hw = &sc->hw;
1247         struct e1000_fc_info *fc = &hw->fc;
1248         uint32_t pba = 0;
1249         uint16_t hwm;
1250
1251         /* Let the firmware know the OS is in control */
1252         igb_get_hw_control(sc);
1253
1254         /*
1255          * Packet Buffer Allocation (PBA)
1256          * Writing PBA sets the receive portion of the buffer
1257          * the remainder is used for the transmit buffer.
1258          */
1259         switch (hw->mac.type) {
1260         case e1000_82575:
1261                 pba = E1000_PBA_32K;
1262                 break;
1263
1264         case e1000_82576:
1265         case e1000_vfadapt:
1266                 pba = E1000_READ_REG(hw, E1000_RXPBS);
1267                 pba &= E1000_RXPBS_SIZE_MASK_82576;
1268                 break;
1269
1270         case e1000_82580:
1271         case e1000_i350:
1272         case e1000_vfadapt_i350:
1273                 pba = E1000_READ_REG(hw, E1000_RXPBS);
1274                 pba = e1000_rxpbs_adjust_82580(pba);
1275                 break;
1276                 /* XXX pba = E1000_PBA_35K; */
1277
1278         default:
1279                 break;
1280         }
1281
1282         /* Special needs in case of Jumbo frames */
1283         if (hw->mac.type == e1000_82575 && ifp->if_mtu > ETHERMTU) {
1284                 uint32_t tx_space, min_tx, min_rx;
1285
1286                 pba = E1000_READ_REG(hw, E1000_PBA);
1287                 tx_space = pba >> 16;
1288                 pba &= 0xffff;
1289
1290                 min_tx = (sc->max_frame_size +
1291                     sizeof(struct e1000_tx_desc) - ETHER_CRC_LEN) * 2;
1292                 min_tx = roundup2(min_tx, 1024);
1293                 min_tx >>= 10;
1294                 min_rx = sc->max_frame_size;
1295                 min_rx = roundup2(min_rx, 1024);
1296                 min_rx >>= 10;
1297                 if (tx_space < min_tx && (min_tx - tx_space) < pba) {
1298                         pba = pba - (min_tx - tx_space);
1299                         /*
1300                          * if short on rx space, rx wins
1301                          * and must trump tx adjustment
1302                          */
1303                         if (pba < min_rx)
1304                                 pba = min_rx;
1305                 }
1306                 E1000_WRITE_REG(hw, E1000_PBA, pba);
1307         }
1308
1309         /*
1310          * These parameters control the automatic generation (Tx) and
1311          * response (Rx) to Ethernet PAUSE frames.
1312          * - High water mark should allow for at least two frames to be
1313          *   received after sending an XOFF.
1314          * - Low water mark works best when it is very near the high water mark.
1315          *   This allows the receiver to restart by sending XON when it has
1316          *   drained a bit.
1317          */
1318         hwm = min(((pba << 10) * 9 / 10),
1319             ((pba << 10) - 2 * sc->max_frame_size));
1320
1321         if (hw->mac.type < e1000_82576) {
1322                 fc->high_water = hwm & 0xFFF8; /* 8-byte granularity */
1323                 fc->low_water = fc->high_water - 8;
1324         } else {
1325                 fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */
1326                 fc->low_water = fc->high_water - 16;
1327         }
1328         fc->pause_time = IGB_FC_PAUSE_TIME;
1329         fc->send_xon = TRUE;
1330
1331         /* Issue a global reset */
1332         e1000_reset_hw(hw);
1333         E1000_WRITE_REG(hw, E1000_WUC, 0);
1334
1335         if (e1000_init_hw(hw) < 0)
1336                 if_printf(ifp, "Hardware Initialization Failed\n");
1337
1338         /* Setup DMA Coalescing */
1339         if (hw->mac.type == e1000_i350 && sc->dma_coalesce) {
1340                 uint32_t reg;
1341
1342                 hwm = (pba - 4) << 10;
1343                 reg = ((pba - 6) << E1000_DMACR_DMACTHR_SHIFT)
1344                     & E1000_DMACR_DMACTHR_MASK;
1345
1346                 /* transition to L0x or L1 if available..*/
1347                 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
1348
1349                 /* timer = +-1000 usec in 32usec intervals */
1350                 reg |= (1000 >> 5);
1351                 E1000_WRITE_REG(hw, E1000_DMACR, reg);
1352
1353                 /* No lower threshold */
1354                 E1000_WRITE_REG(hw, E1000_DMCRTRH, 0);
1355
1356                 /* set hwm to PBA -  2 * max frame size */
1357                 E1000_WRITE_REG(hw, E1000_FCRTC, hwm);
1358
1359                 /* Set the interval before transition */
1360                 reg = E1000_READ_REG(hw, E1000_DMCTLX);
1361                 reg |= 0x800000FF; /* 255 usec */
1362                 E1000_WRITE_REG(hw, E1000_DMCTLX, reg);
1363
1364                 /* free space in tx packet buffer to wake from DMA coal */
1365                 E1000_WRITE_REG(hw, E1000_DMCTXTH,
1366                     (20480 - (2 * sc->max_frame_size)) >> 6);
1367
1368                 /* make low power state decision controlled by DMA coal */
1369                 reg = E1000_READ_REG(hw, E1000_PCIEMISC);
1370                 E1000_WRITE_REG(hw, E1000_PCIEMISC,
1371                     reg | E1000_PCIEMISC_LX_DECISION);
1372                 if_printf(ifp, "DMA Coalescing enabled\n");
1373         }
1374
1375         E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
1376         e1000_get_phy_info(hw);
1377         e1000_check_for_link(hw);
1378 }
1379
1380 static void
1381 igb_setup_ifp(struct igb_softc *sc)
1382 {
1383         struct ifnet *ifp = &sc->arpcom.ac_if;
1384
1385         if_initname(ifp, device_get_name(sc->dev), device_get_unit(sc->dev));
1386         ifp->if_softc = sc;
1387         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1388         ifp->if_init =  igb_init;
1389         ifp->if_ioctl = igb_ioctl;
1390         ifp->if_start = igb_start;
1391         ifp->if_serialize = igb_serialize;
1392         ifp->if_deserialize = igb_deserialize;
1393         ifp->if_tryserialize = igb_tryserialize;
1394 #ifdef INVARIANTS
1395         ifp->if_serialize_assert = igb_serialize_assert;
1396 #endif
1397 #ifdef DEVICE_POLLING
1398         ifp->if_poll = igb_poll;
1399 #endif
1400         ifp->if_watchdog = igb_watchdog;
1401
1402         ifq_set_maxlen(&ifp->if_snd, sc->tx_rings[0].num_tx_desc - 1);
1403         ifq_set_ready(&ifp->if_snd);
1404
1405         ether_ifattach(ifp, sc->hw.mac.addr, NULL);
1406
1407         ifp->if_capabilities =
1408             IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU;
1409         if (IGB_ENABLE_HWRSS(sc))
1410                 ifp->if_capabilities |= IFCAP_RSS;
1411         ifp->if_capenable = ifp->if_capabilities;
1412         ifp->if_hwassist = IGB_CSUM_FEATURES;
1413
1414         /*
1415          * Tell the upper layer(s) we support long frames
1416          */
1417         ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1418
1419         /*
1420          * Specify the media types supported by this adapter and register
1421          * callbacks to update media and link information
1422          */
1423         ifmedia_init(&sc->media, IFM_IMASK, igb_media_change, igb_media_status);
1424         if (sc->hw.phy.media_type == e1000_media_type_fiber ||
1425             sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
1426                 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX | IFM_FDX,
1427                     0, NULL);
1428                 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX, 0, NULL);
1429         } else {
1430                 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T, 0, NULL);
1431                 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T | IFM_FDX,
1432                     0, NULL);
1433                 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX, 0, NULL);
1434                 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX,
1435                     0, NULL);
1436                 if (sc->hw.phy.type != e1000_phy_ife) {
1437                         ifmedia_add(&sc->media,
1438                             IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
1439                         ifmedia_add(&sc->media,
1440                             IFM_ETHER | IFM_1000_T, 0, NULL);
1441                 }
1442         }
1443         ifmedia_add(&sc->media, IFM_ETHER | IFM_AUTO, 0, NULL);
1444         ifmedia_set(&sc->media, IFM_ETHER | IFM_AUTO);
1445 }
1446
1447 static void
1448 igb_add_sysctl(struct igb_softc *sc)
1449 {
1450 #ifdef IGB_RSS_DEBUG
1451         char rx_pkt[32];
1452         int i;
1453 #endif
1454
1455         sysctl_ctx_init(&sc->sysctl_ctx);
1456         sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx,
1457             SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
1458             device_get_nameunit(sc->dev), CTLFLAG_RD, 0, "");
1459         if (sc->sysctl_tree == NULL) {
1460                 device_printf(sc->dev, "can't add sysctl node\n");
1461                 return;
1462         }
1463
1464         SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1465             OID_AUTO, "rxr", CTLFLAG_RD, &sc->rx_ring_cnt, 0, "# of RX rings");
1466         SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1467             OID_AUTO, "rxr_inuse", CTLFLAG_RD, &sc->rx_ring_inuse, 0,
1468             "# of RX rings used");
1469         SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1470             OID_AUTO, "rxd", CTLFLAG_RD, &sc->rx_rings[0].num_rx_desc, 0,
1471             "# of RX descs");
1472         SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1473             OID_AUTO, "txd", CTLFLAG_RD, &sc->tx_rings[0].num_tx_desc, 0,
1474             "# of TX descs");
1475
1476         SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1477             OID_AUTO, "intr_rate", CTLTYPE_INT | CTLFLAG_RW,
1478             sc, 0, igb_sysctl_intr_rate, "I", "interrupt rate");
1479
1480         SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1481             OID_AUTO, "tx_intr_nsegs", CTLTYPE_INT | CTLFLAG_RW,
1482             sc, 0, igb_sysctl_tx_intr_nsegs, "I",
1483             "# of segments per TX interrupt");
1484
1485 #ifdef IGB_RSS_DEBUG
1486         SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1487             OID_AUTO, "rss_debug", CTLFLAG_RW, &sc->rss_debug, 0,
1488             "RSS debug level");
1489         for (i = 0; i < sc->rx_ring_cnt; ++i) {
1490                 ksnprintf(rx_pkt, sizeof(rx_pkt), "rx%d_pkt", i);
1491                 SYSCTL_ADD_ULONG(&sc->sysctl_ctx,
1492                     SYSCTL_CHILDREN(sc->sysctl_tree), OID_AUTO, rx_pkt,
1493                     CTLFLAG_RW, &sc->rx_rings[i].rx_packets, "RXed packets");
1494         }
1495 #endif
1496 }
1497
1498 static int
1499 igb_alloc_rings(struct igb_softc *sc)
1500 {
1501         int error, i;
1502
1503         /*
1504          * Create top level busdma tag
1505          */
1506         error = bus_dma_tag_create(NULL, 1, 0,
1507             BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
1508             BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0,
1509             &sc->parent_tag);
1510         if (error) {
1511                 device_printf(sc->dev, "could not create top level DMA tag\n");
1512                 return error;
1513         }
1514
1515         /*
1516          * Allocate TX descriptor rings and buffers
1517          */
1518         sc->tx_rings = kmalloc(sizeof(struct igb_tx_ring) * sc->tx_ring_cnt,
1519             M_DEVBUF, M_WAITOK | M_ZERO);
1520         for (i = 0; i < sc->tx_ring_cnt; ++i) {
1521                 struct igb_tx_ring *txr = &sc->tx_rings[i];
1522
1523                 /* Set up some basics */
1524                 txr->sc = sc;
1525                 txr->me = i;
1526                 lwkt_serialize_init(&txr->tx_serialize);
1527
1528                 error = igb_create_tx_ring(txr);
1529                 if (error)
1530                         return error;
1531         }
1532
1533         /*
1534          * Allocate RX descriptor rings and buffers
1535          */
1536         sc->rx_rings = kmalloc(sizeof(struct igb_rx_ring) * sc->rx_ring_cnt,
1537             M_DEVBUF, M_WAITOK | M_ZERO);
1538         for (i = 0; i < sc->rx_ring_cnt; ++i) {
1539                 struct igb_rx_ring *rxr = &sc->rx_rings[i];
1540
1541                 /* Set up some basics */
1542                 rxr->sc = sc;
1543                 rxr->me = i;
1544                 lwkt_serialize_init(&rxr->rx_serialize);
1545
1546                 error = igb_create_rx_ring(rxr);
1547                 if (error)
1548                         return error;
1549         }
1550
1551         return 0;
1552 }
1553
1554 static void
1555 igb_free_rings(struct igb_softc *sc)
1556 {
1557         int i;
1558
1559         if (sc->tx_rings != NULL) {
1560                 for (i = 0; i < sc->tx_ring_cnt; ++i) {
1561                         struct igb_tx_ring *txr = &sc->tx_rings[i];
1562
1563                         igb_destroy_tx_ring(txr, txr->num_tx_desc);
1564                 }
1565                 kfree(sc->tx_rings, M_DEVBUF);
1566         }
1567
1568         if (sc->rx_rings != NULL) {
1569                 for (i = 0; i < sc->rx_ring_cnt; ++i) {
1570                         struct igb_rx_ring *rxr = &sc->rx_rings[i];
1571
1572                         igb_destroy_rx_ring(rxr, rxr->num_rx_desc);
1573                 }
1574                 kfree(sc->rx_rings, M_DEVBUF);
1575         }
1576 }
1577
1578 static int
1579 igb_create_tx_ring(struct igb_tx_ring *txr)
1580 {
1581         int tsize, error, i;
1582
1583         /*
1584          * Validate number of transmit descriptors. It must not exceed
1585          * hardware maximum, and must be multiple of IGB_DBA_ALIGN.
1586          */
1587         if (((igb_txd * sizeof(struct e1000_tx_desc)) % IGB_DBA_ALIGN) != 0 ||
1588             (igb_txd > IGB_MAX_TXD) || (igb_txd < IGB_MIN_TXD)) {
1589                 device_printf(txr->sc->dev,
1590                     "Using %d TX descriptors instead of %d!\n",
1591                     IGB_DEFAULT_TXD, igb_txd);
1592                 txr->num_tx_desc = IGB_DEFAULT_TXD;
1593         } else {
1594                 txr->num_tx_desc = igb_txd;
1595         }
1596
1597         /*
1598          * Allocate TX descriptor ring
1599          */
1600         tsize = roundup2(txr->num_tx_desc * sizeof(union e1000_adv_tx_desc),
1601             IGB_DBA_ALIGN);
1602         txr->txdma.dma_vaddr = bus_dmamem_coherent_any(txr->sc->parent_tag,
1603             IGB_DBA_ALIGN, tsize, BUS_DMA_WAITOK,
1604             &txr->txdma.dma_tag, &txr->txdma.dma_map, &txr->txdma.dma_paddr);
1605         if (txr->txdma.dma_vaddr == NULL) {
1606                 device_printf(txr->sc->dev,
1607                     "Unable to allocate TX Descriptor memory\n");
1608                 return ENOMEM;
1609         }
1610         txr->tx_base = txr->txdma.dma_vaddr;
1611         bzero(txr->tx_base, tsize);
1612
1613         txr->tx_buf = kmalloc(sizeof(struct igb_tx_buf) * txr->num_tx_desc,
1614             M_DEVBUF, M_WAITOK | M_ZERO);
1615
1616         /*
1617          * Allocate TX head write-back buffer
1618          */
1619         txr->tx_hdr = bus_dmamem_coherent_any(txr->sc->parent_tag,
1620             __VM_CACHELINE_SIZE, __VM_CACHELINE_SIZE, BUS_DMA_WAITOK,
1621             &txr->tx_hdr_dtag, &txr->tx_hdr_dmap, &txr->tx_hdr_paddr);
1622         if (txr->tx_hdr == NULL) {
1623                 device_printf(txr->sc->dev,
1624                     "Unable to allocate TX head write-back buffer\n");
1625                 return ENOMEM;
1626         }
1627
1628         /*
1629          * Create DMA tag for TX buffers
1630          */
1631         error = bus_dma_tag_create(txr->sc->parent_tag,
1632             1, 0,               /* alignment, bounds */
1633             BUS_SPACE_MAXADDR,  /* lowaddr */
1634             BUS_SPACE_MAXADDR,  /* highaddr */
1635             NULL, NULL,         /* filter, filterarg */
1636             IGB_TSO_SIZE,       /* maxsize */
1637             IGB_MAX_SCATTER,    /* nsegments */
1638             PAGE_SIZE,          /* maxsegsize */
1639             BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW |
1640             BUS_DMA_ONEBPAGE,   /* flags */
1641             &txr->tx_tag);
1642         if (error) {
1643                 device_printf(txr->sc->dev, "Unable to allocate TX DMA tag\n");
1644                 kfree(txr->tx_buf, M_DEVBUF);
1645                 txr->tx_buf = NULL;
1646                 return error;
1647         }
1648
1649         /*
1650          * Create DMA maps for TX buffers
1651          */
1652         for (i = 0; i < txr->num_tx_desc; ++i) {
1653                 struct igb_tx_buf *txbuf = &txr->tx_buf[i];
1654
1655                 error = bus_dmamap_create(txr->tx_tag,
1656                     BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE, &txbuf->map);
1657                 if (error) {
1658                         device_printf(txr->sc->dev,
1659                             "Unable to create TX DMA map\n");
1660                         igb_destroy_tx_ring(txr, i);
1661                         return error;
1662                 }
1663         }
1664
1665         /*
1666          * Initialize various watermark
1667          */
1668         txr->spare_desc = IGB_TX_SPARE;
1669         txr->intr_nsegs = txr->num_tx_desc / 16;
1670         txr->oact_hi_desc = txr->num_tx_desc / 2;
1671         txr->oact_lo_desc = txr->num_tx_desc / 8;
1672         if (txr->oact_lo_desc > IGB_TX_OACTIVE_MAX)
1673                 txr->oact_lo_desc = IGB_TX_OACTIVE_MAX;
1674         if (txr->oact_lo_desc < txr->spare_desc + IGB_TX_RESERVED)
1675                 txr->oact_lo_desc = txr->spare_desc + IGB_TX_RESERVED;
1676
1677         return 0;
1678 }
1679
1680 static void
1681 igb_free_tx_ring(struct igb_tx_ring *txr)
1682 {
1683         int i;
1684
1685         for (i = 0; i < txr->num_tx_desc; ++i) {
1686                 struct igb_tx_buf *txbuf = &txr->tx_buf[i];
1687
1688                 if (txbuf->m_head != NULL) {
1689                         bus_dmamap_unload(txr->tx_tag, txbuf->map);
1690                         m_freem(txbuf->m_head);
1691                         txbuf->m_head = NULL;
1692                 }
1693         }
1694 }
1695
1696 static void
1697 igb_destroy_tx_ring(struct igb_tx_ring *txr, int ndesc)
1698 {
1699         int i;
1700
1701         if (txr->txdma.dma_vaddr != NULL) {
1702                 bus_dmamap_unload(txr->txdma.dma_tag, txr->txdma.dma_map);
1703                 bus_dmamem_free(txr->txdma.dma_tag, txr->txdma.dma_vaddr,
1704                     txr->txdma.dma_map);
1705                 bus_dma_tag_destroy(txr->txdma.dma_tag);
1706                 txr->txdma.dma_vaddr = NULL;
1707         }
1708
1709         if (txr->tx_hdr != NULL) {
1710                 bus_dmamap_unload(txr->tx_hdr_dtag, txr->tx_hdr_dmap);
1711                 bus_dmamem_free(txr->tx_hdr_dtag, txr->tx_hdr,
1712                     txr->tx_hdr_dmap);
1713                 bus_dma_tag_destroy(txr->tx_hdr_dtag);
1714                 txr->tx_hdr = NULL;
1715         }
1716
1717         if (txr->tx_buf == NULL)
1718                 return;
1719
1720         for (i = 0; i < ndesc; ++i) {
1721                 struct igb_tx_buf *txbuf = &txr->tx_buf[i];
1722
1723                 KKASSERT(txbuf->m_head == NULL);
1724                 bus_dmamap_destroy(txr->tx_tag, txbuf->map);
1725         }
1726         bus_dma_tag_destroy(txr->tx_tag);
1727
1728         kfree(txr->tx_buf, M_DEVBUF);
1729         txr->tx_buf = NULL;
1730 }
1731
1732 static void
1733 igb_init_tx_ring(struct igb_tx_ring *txr)
1734 {
1735         /* Clear the old descriptor contents */
1736         bzero(txr->tx_base,
1737             sizeof(union e1000_adv_tx_desc) * txr->num_tx_desc);
1738
1739         /* Clear TX head write-back buffer */
1740         *(txr->tx_hdr) = 0;
1741
1742         /* Reset indices */
1743         txr->next_avail_desc = 0;
1744         txr->next_to_clean = 0;
1745         txr->tx_nsegs = 0;
1746
1747         /* Set number of descriptors available */
1748         txr->tx_avail = txr->num_tx_desc;
1749 }
1750
1751 static void
1752 igb_init_tx_unit(struct igb_softc *sc)
1753 {
1754         struct e1000_hw *hw = &sc->hw;
1755         uint32_t tctl;
1756         int i;
1757
1758         /* Setup the Tx Descriptor Rings */
1759         for (i = 0; i < sc->tx_ring_cnt; ++i) {
1760                 struct igb_tx_ring *txr = &sc->tx_rings[i];
1761                 uint64_t bus_addr = txr->txdma.dma_paddr;
1762                 uint64_t hdr_paddr = txr->tx_hdr_paddr;
1763                 uint32_t txdctl = 0;
1764                 uint32_t dca_txctrl;
1765
1766                 E1000_WRITE_REG(hw, E1000_TDLEN(i),
1767                     txr->num_tx_desc * sizeof(struct e1000_tx_desc));
1768                 E1000_WRITE_REG(hw, E1000_TDBAH(i),
1769                     (uint32_t)(bus_addr >> 32));
1770                 E1000_WRITE_REG(hw, E1000_TDBAL(i),
1771                     (uint32_t)bus_addr);
1772
1773                 /* Setup the HW Tx Head and Tail descriptor pointers */
1774                 E1000_WRITE_REG(hw, E1000_TDT(i), 0);
1775                 E1000_WRITE_REG(hw, E1000_TDH(i), 0);
1776
1777                 txdctl |= IGB_TX_PTHRESH;
1778                 txdctl |= IGB_TX_HTHRESH << 8;
1779                 txdctl |= IGB_TX_WTHRESH << 16;
1780                 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
1781                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl);
1782
1783                 dca_txctrl = E1000_READ_REG(hw, E1000_DCA_TXCTRL(i));
1784                 dca_txctrl &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN;
1785                 E1000_WRITE_REG(hw, E1000_DCA_TXCTRL(i), dca_txctrl);
1786
1787                 E1000_WRITE_REG(hw, E1000_TDWBAH(i),
1788                     (uint32_t)(hdr_paddr >> 32));
1789                 E1000_WRITE_REG(hw, E1000_TDWBAL(i),
1790                     ((uint32_t)hdr_paddr) | E1000_TX_HEAD_WB_ENABLE);
1791         }
1792
1793         if (sc->vf_ifp)
1794                 return;
1795
1796         e1000_config_collision_dist(hw);
1797
1798         /* Program the Transmit Control Register */
1799         tctl = E1000_READ_REG(hw, E1000_TCTL);
1800         tctl &= ~E1000_TCTL_CT;
1801         tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
1802             (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT));
1803
1804         /* This write will effectively turn on the transmit unit. */
1805         E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1806 }
1807
1808 static boolean_t
1809 igb_txctx(struct igb_tx_ring *txr, struct mbuf *mp)
1810 {
1811         struct e1000_adv_tx_context_desc *TXD;
1812         struct igb_tx_buf *txbuf;
1813         uint32_t vlan_macip_lens, type_tucmd_mlhl, mss_l4len_idx;
1814         struct ether_vlan_header *eh;
1815         struct ip *ip = NULL;
1816         int ehdrlen, ctxd, ip_hlen = 0;
1817         uint16_t etype, vlantag = 0;
1818         boolean_t offload = TRUE;
1819
1820         if ((mp->m_pkthdr.csum_flags & IGB_CSUM_FEATURES) == 0)
1821                 offload = FALSE;
1822
1823         vlan_macip_lens = type_tucmd_mlhl = mss_l4len_idx = 0;
1824         ctxd = txr->next_avail_desc;
1825         txbuf = &txr->tx_buf[ctxd];
1826         TXD = (struct e1000_adv_tx_context_desc *)&txr->tx_base[ctxd];
1827
1828         /*
1829          * In advanced descriptors the vlan tag must
1830          * be placed into the context descriptor, thus
1831          * we need to be here just for that setup.
1832          */
1833         if (mp->m_flags & M_VLANTAG) {
1834                 vlantag = htole16(mp->m_pkthdr.ether_vlantag);
1835                 vlan_macip_lens |= (vlantag << E1000_ADVTXD_VLAN_SHIFT);
1836         } else if (!offload) {
1837                 return FALSE;
1838         }
1839
1840         /*
1841          * Determine where frame payload starts.
1842          * Jump over vlan headers if already present,
1843          * helpful for QinQ too.
1844          */
1845         KASSERT(mp->m_len >= ETHER_HDR_LEN,
1846             ("igb_txctx_pullup is not called (eh)?\n"));
1847         eh = mtod(mp, struct ether_vlan_header *);
1848         if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
1849                 KASSERT(mp->m_len >= ETHER_HDR_LEN + EVL_ENCAPLEN,
1850                     ("igb_txctx_pullup is not called (evh)?\n"));
1851                 etype = ntohs(eh->evl_proto);
1852                 ehdrlen = ETHER_HDR_LEN + EVL_ENCAPLEN;
1853         } else {
1854                 etype = ntohs(eh->evl_encap_proto);
1855                 ehdrlen = ETHER_HDR_LEN;
1856         }
1857
1858         /* Set the ether header length */
1859         vlan_macip_lens |= ehdrlen << E1000_ADVTXD_MACLEN_SHIFT;
1860
1861         switch (etype) {
1862         case ETHERTYPE_IP:
1863                 KASSERT(mp->m_len >= ehdrlen + IGB_IPVHL_SIZE,
1864                     ("igb_txctx_pullup is not called (eh+ip_vhl)?\n"));
1865
1866                 /* NOTE: We could only safely access ip.ip_vhl part */
1867                 ip = (struct ip *)(mp->m_data + ehdrlen);
1868                 ip_hlen = ip->ip_hl << 2;
1869
1870                 if (mp->m_pkthdr.csum_flags & CSUM_IP)
1871                         type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_IPV4;
1872                 break;
1873
1874 #ifdef notyet
1875         case ETHERTYPE_IPV6:
1876                 ip6 = (struct ip6_hdr *)(mp->m_data + ehdrlen);
1877                 ip_hlen = sizeof(struct ip6_hdr);
1878                 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_IPV6;
1879                 break;
1880 #endif
1881
1882         default:
1883                 offload = FALSE;
1884                 break;
1885         }
1886
1887         vlan_macip_lens |= ip_hlen;
1888         type_tucmd_mlhl |= E1000_ADVTXD_DCMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
1889
1890         if (mp->m_pkthdr.csum_flags & CSUM_TCP)
1891                 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_TCP;
1892         else if (mp->m_pkthdr.csum_flags & CSUM_UDP)
1893                 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_UDP;
1894
1895         /* 82575 needs the queue index added */
1896         if (txr->sc->hw.mac.type == e1000_82575)
1897                 mss_l4len_idx = txr->me << 4;
1898
1899         /* Now copy bits into descriptor */
1900         TXD->vlan_macip_lens = htole32(vlan_macip_lens);
1901         TXD->type_tucmd_mlhl = htole32(type_tucmd_mlhl);
1902         TXD->seqnum_seed = htole32(0);
1903         TXD->mss_l4len_idx = htole32(mss_l4len_idx);
1904
1905         txbuf->m_head = NULL;
1906
1907         /* We've consumed the first desc, adjust counters */
1908         if (++ctxd == txr->num_tx_desc)
1909                 ctxd = 0;
1910         txr->next_avail_desc = ctxd;
1911         --txr->tx_avail;
1912
1913         return offload;
1914 }
1915
1916 static void
1917 igb_txeof(struct igb_tx_ring *txr)
1918 {
1919         struct ifnet *ifp = &txr->sc->arpcom.ac_if;
1920         int first, hdr, avail;
1921
1922         if (txr->tx_avail == txr->num_tx_desc)
1923                 return;
1924
1925         first = txr->next_to_clean;
1926         hdr = *(txr->tx_hdr);
1927
1928         if (first == hdr)
1929                 return;
1930
1931         avail = txr->tx_avail;
1932         while (first != hdr) {
1933                 struct igb_tx_buf *txbuf = &txr->tx_buf[first];
1934
1935                 ++avail;
1936                 if (txbuf->m_head) {
1937                         bus_dmamap_unload(txr->tx_tag, txbuf->map);
1938                         m_freem(txbuf->m_head);
1939                         txbuf->m_head = NULL;
1940                         ++ifp->if_opackets;
1941                 }
1942                 if (++first == txr->num_tx_desc)
1943                         first = 0;
1944         }
1945         txr->next_to_clean = first;
1946         txr->tx_avail = avail;
1947
1948         /*
1949          * If we have a minimum free, clear IFF_OACTIVE
1950          * to tell the stack that it is OK to send packets.
1951          */
1952         if (IGB_IS_NOT_OACTIVE(txr)) {
1953                 ifp->if_flags &= ~IFF_OACTIVE;
1954
1955                 /*
1956                  * We have enough TX descriptors, turn off
1957                  * the watchdog.  We allow small amount of
1958                  * packets (roughly intr_nsegs) pending on
1959                  * the transmit ring.
1960                  */
1961                 ifp->if_timer = 0;
1962         }
1963 }
1964
1965 static int
1966 igb_create_rx_ring(struct igb_rx_ring *rxr)
1967 {
1968         int rsize, i, error;
1969
1970         /*
1971          * Validate number of receive descriptors. It must not exceed
1972          * hardware maximum, and must be multiple of IGB_DBA_ALIGN.
1973          */
1974         if (((igb_rxd * sizeof(struct e1000_rx_desc)) % IGB_DBA_ALIGN) != 0 ||
1975             (igb_rxd > IGB_MAX_RXD) || (igb_rxd < IGB_MIN_RXD)) {
1976                 device_printf(rxr->sc->dev,
1977                     "Using %d RX descriptors instead of %d!\n",
1978                     IGB_DEFAULT_RXD, igb_rxd);
1979                 rxr->num_rx_desc = IGB_DEFAULT_RXD;
1980         } else {
1981                 rxr->num_rx_desc = igb_rxd;
1982         }
1983
1984         /*
1985          * Allocate RX descriptor ring
1986          */
1987         rsize = roundup2(rxr->num_rx_desc * sizeof(union e1000_adv_rx_desc),
1988             IGB_DBA_ALIGN);
1989         rxr->rxdma.dma_vaddr = bus_dmamem_coherent_any(rxr->sc->parent_tag,
1990             IGB_DBA_ALIGN, rsize, BUS_DMA_WAITOK,
1991             &rxr->rxdma.dma_tag, &rxr->rxdma.dma_map,
1992             &rxr->rxdma.dma_paddr);
1993         if (rxr->rxdma.dma_vaddr == NULL) {
1994                 device_printf(rxr->sc->dev,
1995                     "Unable to allocate RxDescriptor memory\n");
1996                 return ENOMEM;
1997         }
1998         rxr->rx_base = rxr->rxdma.dma_vaddr;
1999         bzero(rxr->rx_base, rsize);
2000
2001         rxr->rx_buf = kmalloc(sizeof(struct igb_rx_buf) * rxr->num_rx_desc,
2002             M_DEVBUF, M_WAITOK | M_ZERO);
2003
2004         /*
2005          * Create DMA tag for RX buffers
2006          */
2007         error = bus_dma_tag_create(rxr->sc->parent_tag,
2008             1, 0,               /* alignment, bounds */
2009             BUS_SPACE_MAXADDR,  /* lowaddr */
2010             BUS_SPACE_MAXADDR,  /* highaddr */
2011             NULL, NULL,         /* filter, filterarg */
2012             MCLBYTES,           /* maxsize */
2013             1,                  /* nsegments */
2014             MCLBYTES,           /* maxsegsize */
2015             BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, /* flags */
2016             &rxr->rx_tag);
2017         if (error) {
2018                 device_printf(rxr->sc->dev,
2019                     "Unable to create RX payload DMA tag\n");
2020                 kfree(rxr->rx_buf, M_DEVBUF);
2021                 rxr->rx_buf = NULL;
2022                 return error;
2023         }
2024
2025         /*
2026          * Create spare DMA map for RX buffers
2027          */
2028         error = bus_dmamap_create(rxr->rx_tag, BUS_DMA_WAITOK,
2029             &rxr->rx_sparemap);
2030         if (error) {
2031                 device_printf(rxr->sc->dev,
2032                     "Unable to create spare RX DMA maps\n");
2033                 bus_dma_tag_destroy(rxr->rx_tag);
2034                 kfree(rxr->rx_buf, M_DEVBUF);
2035                 rxr->rx_buf = NULL;
2036                 return error;
2037         }
2038
2039         /*
2040          * Create DMA maps for RX buffers
2041          */
2042         for (i = 0; i < rxr->num_rx_desc; i++) {
2043                 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2044
2045                 error = bus_dmamap_create(rxr->rx_tag,
2046                     BUS_DMA_WAITOK, &rxbuf->map);
2047                 if (error) {
2048                         device_printf(rxr->sc->dev,
2049                             "Unable to create RX DMA maps\n");
2050                         igb_destroy_rx_ring(rxr, i);
2051                         return error;
2052                 }
2053         }
2054         return 0;
2055 }
2056
2057 static void
2058 igb_free_rx_ring(struct igb_rx_ring *rxr)
2059 {
2060         int i;
2061
2062         for (i = 0; i < rxr->num_rx_desc; ++i) {
2063                 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2064
2065                 if (rxbuf->m_head != NULL) {
2066                         bus_dmamap_unload(rxr->rx_tag, rxbuf->map);
2067                         m_freem(rxbuf->m_head);
2068                         rxbuf->m_head = NULL;
2069                 }
2070         }
2071
2072         if (rxr->fmp != NULL)
2073                 m_freem(rxr->fmp);
2074         rxr->fmp = NULL;
2075         rxr->lmp = NULL;
2076 }
2077
2078 static void
2079 igb_destroy_rx_ring(struct igb_rx_ring *rxr, int ndesc)
2080 {
2081         int i;
2082
2083         if (rxr->rxdma.dma_vaddr != NULL) {
2084                 bus_dmamap_unload(rxr->rxdma.dma_tag, rxr->rxdma.dma_map);
2085                 bus_dmamem_free(rxr->rxdma.dma_tag, rxr->rxdma.dma_vaddr,
2086                     rxr->rxdma.dma_map);
2087                 bus_dma_tag_destroy(rxr->rxdma.dma_tag);
2088                 rxr->rxdma.dma_vaddr = NULL;
2089         }
2090
2091         if (rxr->rx_buf == NULL)
2092                 return;
2093
2094         for (i = 0; i < ndesc; ++i) {
2095                 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2096
2097                 KKASSERT(rxbuf->m_head == NULL);
2098                 bus_dmamap_destroy(rxr->rx_tag, rxbuf->map);
2099         }
2100         bus_dmamap_destroy(rxr->rx_tag, rxr->rx_sparemap);
2101         bus_dma_tag_destroy(rxr->rx_tag);
2102
2103         kfree(rxr->rx_buf, M_DEVBUF);
2104         rxr->rx_buf = NULL;
2105 }
2106
2107 static void
2108 igb_setup_rxdesc(union e1000_adv_rx_desc *rxd, const struct igb_rx_buf *rxbuf)
2109 {
2110         rxd->read.pkt_addr = htole64(rxbuf->paddr);
2111         rxd->wb.upper.status_error = 0;
2112 }
2113
2114 static int
2115 igb_newbuf(struct igb_rx_ring *rxr, int i, boolean_t wait)
2116 {
2117         struct mbuf *m;
2118         bus_dma_segment_t seg;
2119         bus_dmamap_t map;
2120         struct igb_rx_buf *rxbuf;
2121         int error, nseg;
2122
2123         m = m_getcl(wait ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
2124         if (m == NULL) {
2125                 if (wait) {
2126                         if_printf(&rxr->sc->arpcom.ac_if,
2127                             "Unable to allocate RX mbuf\n");
2128                 }
2129                 return ENOBUFS;
2130         }
2131         m->m_len = m->m_pkthdr.len = MCLBYTES;
2132
2133         if (rxr->sc->max_frame_size <= MCLBYTES - ETHER_ALIGN)
2134                 m_adj(m, ETHER_ALIGN);
2135
2136         error = bus_dmamap_load_mbuf_segment(rxr->rx_tag,
2137             rxr->rx_sparemap, m, &seg, 1, &nseg, BUS_DMA_NOWAIT);
2138         if (error) {
2139                 m_freem(m);
2140                 if (wait) {
2141                         if_printf(&rxr->sc->arpcom.ac_if,
2142                             "Unable to load RX mbuf\n");
2143                 }
2144                 return error;
2145         }
2146
2147         rxbuf = &rxr->rx_buf[i];
2148         if (rxbuf->m_head != NULL)
2149                 bus_dmamap_unload(rxr->rx_tag, rxbuf->map);
2150
2151         map = rxbuf->map;
2152         rxbuf->map = rxr->rx_sparemap;
2153         rxr->rx_sparemap = map;
2154
2155         rxbuf->m_head = m;
2156         rxbuf->paddr = seg.ds_addr;
2157
2158         igb_setup_rxdesc(&rxr->rx_base[i], rxbuf);
2159         return 0;
2160 }
2161
2162 static int
2163 igb_init_rx_ring(struct igb_rx_ring *rxr)
2164 {
2165         int i;
2166
2167         /* Clear the ring contents */
2168         bzero(rxr->rx_base,
2169             rxr->num_rx_desc * sizeof(union e1000_adv_rx_desc));
2170
2171         /* Now replenish the ring mbufs */
2172         for (i = 0; i < rxr->num_rx_desc; ++i) {
2173                 int error;
2174
2175                 error = igb_newbuf(rxr, i, TRUE);
2176                 if (error)
2177                         return error;
2178         }
2179
2180         /* Setup our descriptor indices */
2181         rxr->next_to_check = 0;
2182
2183         rxr->fmp = NULL;
2184         rxr->lmp = NULL;
2185         rxr->discard = FALSE;
2186
2187         return 0;
2188 }
2189
2190 static void
2191 igb_init_rx_unit(struct igb_softc *sc)
2192 {
2193         struct ifnet *ifp = &sc->arpcom.ac_if;
2194         struct e1000_hw *hw = &sc->hw;
2195         uint32_t rctl, rxcsum, srrctl = 0;
2196         int i;
2197
2198         /*
2199          * Make sure receives are disabled while setting
2200          * up the descriptor ring
2201          */
2202         rctl = E1000_READ_REG(hw, E1000_RCTL);
2203         E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
2204
2205 #if 0
2206         /*
2207         ** Set up for header split
2208         */
2209         if (igb_header_split) {
2210                 /* Use a standard mbuf for the header */
2211                 srrctl |= IGB_HDR_BUF << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
2212                 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2213         } else
2214 #endif
2215                 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
2216
2217         /*
2218         ** Set up for jumbo frames
2219         */
2220         if (ifp->if_mtu > ETHERMTU) {
2221                 rctl |= E1000_RCTL_LPE;
2222 #if 0
2223                 if (adapter->rx_mbuf_sz == MJUMPAGESIZE) {
2224                         srrctl |= 4096 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2225                         rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX;
2226                 } else if (adapter->rx_mbuf_sz > MJUMPAGESIZE) {
2227                         srrctl |= 8192 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2228                         rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX;
2229                 }
2230                 /* Set maximum packet len */
2231                 psize = adapter->max_frame_size;
2232                 /* are we on a vlan? */
2233                 if (adapter->ifp->if_vlantrunk != NULL)
2234                         psize += VLAN_TAG_SIZE;
2235                 E1000_WRITE_REG(&adapter->hw, E1000_RLPML, psize);
2236 #else
2237                 srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2238                 rctl |= E1000_RCTL_SZ_2048;
2239 #endif
2240         } else {
2241                 rctl &= ~E1000_RCTL_LPE;
2242                 srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2243                 rctl |= E1000_RCTL_SZ_2048;
2244         }
2245
2246         /* Setup the Base and Length of the Rx Descriptor Rings */
2247         for (i = 0; i < sc->rx_ring_inuse; ++i) {
2248                 struct igb_rx_ring *rxr = &sc->rx_rings[i];
2249                 uint64_t bus_addr = rxr->rxdma.dma_paddr;
2250                 uint32_t rxdctl;
2251
2252                 E1000_WRITE_REG(hw, E1000_RDLEN(i),
2253                     rxr->num_rx_desc * sizeof(struct e1000_rx_desc));
2254                 E1000_WRITE_REG(hw, E1000_RDBAH(i),
2255                     (uint32_t)(bus_addr >> 32));
2256                 E1000_WRITE_REG(hw, E1000_RDBAL(i),
2257                     (uint32_t)bus_addr);
2258                 E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl);
2259                 /* Enable this Queue */
2260                 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));
2261                 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
2262                 rxdctl &= 0xFFF00000;
2263                 rxdctl |= IGB_RX_PTHRESH;
2264                 rxdctl |= IGB_RX_HTHRESH << 8;
2265                 rxdctl |= IGB_RX_WTHRESH << 16;
2266                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
2267         }
2268
2269         rxcsum = E1000_READ_REG(&sc->hw, E1000_RXCSUM);
2270         rxcsum &= ~(E1000_RXCSUM_PCSS_MASK | E1000_RXCSUM_IPPCSE);
2271
2272         /*
2273          * Receive Checksum Offload for TCP and UDP
2274          *
2275          * Checksum offloading is also enabled if multiple receive
2276          * queue is to be supported, since we need it to figure out
2277          * fragments.
2278          */
2279         if ((ifp->if_capenable & IFCAP_RXCSUM) || IGB_ENABLE_HWRSS(sc)) {
2280                 /*
2281                  * NOTE:
2282                  * PCSD must be enabled to enable multiple
2283                  * receive queues.
2284                  */
2285                 rxcsum |= E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL |
2286                     E1000_RXCSUM_PCSD;
2287         } else {
2288                 rxcsum &= ~(E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL |
2289                     E1000_RXCSUM_PCSD);
2290         }
2291         E1000_WRITE_REG(&sc->hw, E1000_RXCSUM, rxcsum);
2292
2293         if (IGB_ENABLE_HWRSS(sc)) {
2294                 uint8_t key[IGB_NRSSRK * IGB_RSSRK_SIZE];
2295                 uint32_t reta_shift;
2296                 int j, r;
2297
2298                 /*
2299                  * NOTE:
2300                  * When we reach here, RSS has already been disabled
2301                  * in igb_stop(), so we could safely configure RSS key
2302                  * and redirect table.
2303                  */
2304
2305                 /*
2306                  * Configure RSS key
2307                  */
2308                 toeplitz_get_key(key, sizeof(key));
2309                 for (i = 0; i < IGB_NRSSRK; ++i) {
2310                         uint32_t rssrk;
2311
2312                         rssrk = IGB_RSSRK_VAL(key, i);
2313                         IGB_RSS_DPRINTF(sc, 1, "rssrk%d 0x%08x\n", i, rssrk);
2314
2315                         E1000_WRITE_REG(hw, E1000_RSSRK(i), rssrk);
2316                 }
2317
2318                 /*
2319                  * Configure RSS redirect table in following fashion:
2320                  * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)]
2321                  */
2322                 reta_shift = IGB_RETA_SHIFT;
2323                 if (hw->mac.type == e1000_82575)
2324                         reta_shift = IGB_RETA_SHIFT_82575;
2325
2326                 r = 0;
2327                 for (j = 0; j < IGB_NRETA; ++j) {
2328                         uint32_t reta = 0;
2329
2330                         for (i = 0; i < IGB_RETA_SIZE; ++i) {
2331                                 uint32_t q;
2332
2333                                 q = (r % sc->rx_ring_inuse) << reta_shift;
2334                                 reta |= q << (8 * i);
2335                                 ++r;
2336                         }
2337                         IGB_RSS_DPRINTF(sc, 1, "reta 0x%08x\n", reta);
2338                         E1000_WRITE_REG(hw, E1000_RETA(j), reta);
2339                 }
2340
2341                 /*
2342                  * Enable multiple receive queues.
2343                  * Enable IPv4 RSS standard hash functions.
2344                  * Disable RSS interrupt on 82575
2345                  */
2346                 E1000_WRITE_REG(&sc->hw, E1000_MRQC,
2347                                 E1000_MRQC_ENABLE_RSS_4Q |
2348                                 E1000_MRQC_RSS_FIELD_IPV4_TCP |
2349                                 E1000_MRQC_RSS_FIELD_IPV4);
2350         }
2351
2352         /* Setup the Receive Control Register */
2353         rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2354         rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO |
2355             E1000_RCTL_RDMTS_HALF |
2356             (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
2357         /* Strip CRC bytes. */
2358         rctl |= E1000_RCTL_SECRC;
2359         /* Make sure VLAN Filters are off */
2360         rctl &= ~E1000_RCTL_VFE;
2361         /* Don't store bad packets */
2362         rctl &= ~E1000_RCTL_SBP;
2363
2364         /* Enable Receives */
2365         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2366
2367         /*
2368          * Setup the HW Rx Head and Tail Descriptor Pointers
2369          *   - needs to be after enable
2370          */
2371         for (i = 0; i < sc->rx_ring_inuse; ++i) {
2372                 struct igb_rx_ring *rxr = &sc->rx_rings[i];
2373
2374                 E1000_WRITE_REG(hw, E1000_RDH(i), rxr->next_to_check);
2375                 E1000_WRITE_REG(hw, E1000_RDT(i), rxr->num_rx_desc - 1);
2376         }
2377 }
2378
2379 static void
2380 igb_rxeof(struct igb_rx_ring *rxr, int count)
2381 {
2382         struct ifnet *ifp = &rxr->sc->arpcom.ac_if;
2383         union e1000_adv_rx_desc *cur;
2384         uint32_t staterr;
2385         int i;
2386
2387         i = rxr->next_to_check;
2388         cur = &rxr->rx_base[i];
2389         staterr = le32toh(cur->wb.upper.status_error);
2390
2391         if ((staterr & E1000_RXD_STAT_DD) == 0)
2392                 return;
2393
2394         while ((staterr & E1000_RXD_STAT_DD) && count != 0) {
2395                 struct pktinfo *pi = NULL, pi0;
2396                 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2397                 struct mbuf *m = NULL;
2398                 boolean_t eop;
2399
2400                 eop = (staterr & E1000_RXD_STAT_EOP) ? TRUE : FALSE;
2401                 if (eop)
2402                         --count;
2403
2404                 if ((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) == 0 &&
2405                     !rxr->discard) {
2406                         struct mbuf *mp = rxbuf->m_head;
2407                         uint32_t hash, hashtype;
2408                         uint16_t vlan;
2409                         int len;
2410
2411                         len = le16toh(cur->wb.upper.length);
2412                         if (rxr->sc->hw.mac.type == e1000_i350 &&
2413                             (staterr & E1000_RXDEXT_STATERR_LB))
2414                                 vlan = be16toh(cur->wb.upper.vlan);
2415                         else
2416                                 vlan = le16toh(cur->wb.upper.vlan);
2417
2418                         hash = le32toh(cur->wb.lower.hi_dword.rss);
2419                         hashtype = le32toh(cur->wb.lower.lo_dword.data) &
2420                             E1000_RXDADV_RSSTYPE_MASK;
2421
2422                         IGB_RSS_DPRINTF(rxr->sc, 10,
2423                             "ring%d, hash 0x%08x, hashtype %u\n",
2424                             rxr->me, hash, hashtype);
2425
2426                         bus_dmamap_sync(rxr->rx_tag, rxbuf->map,
2427                             BUS_DMASYNC_POSTREAD);
2428
2429                         if (igb_newbuf(rxr, i, FALSE) != 0) {
2430                                 ifp->if_iqdrops++;
2431                                 goto discard;
2432                         }
2433
2434                         mp->m_len = len;
2435                         if (rxr->fmp == NULL) {
2436                                 mp->m_pkthdr.len = len;
2437                                 rxr->fmp = mp;
2438                                 rxr->lmp = mp;
2439                         } else {
2440                                 rxr->lmp->m_next = mp;
2441                                 rxr->lmp = rxr->lmp->m_next;
2442                                 rxr->fmp->m_pkthdr.len += len;
2443                         }
2444
2445                         if (eop) {
2446                                 m = rxr->fmp;
2447                                 rxr->fmp = NULL;
2448                                 rxr->lmp = NULL;
2449
2450                                 m->m_pkthdr.rcvif = ifp;
2451                                 ifp->if_ipackets++;
2452
2453                                 if (ifp->if_capenable & IFCAP_RXCSUM)
2454                                         igb_rxcsum(staterr, m);
2455
2456                                 if (staterr & E1000_RXD_STAT_VP) {
2457                                         m->m_pkthdr.ether_vlantag = vlan;
2458                                         m->m_flags |= M_VLANTAG;
2459                                 }
2460
2461                                 if (ifp->if_capenable & IFCAP_RSS) {
2462                                         pi = igb_rssinfo(m, &pi0,
2463                                             hash, hashtype, staterr);
2464                                 }
2465 #ifdef IGB_RSS_DEBUG
2466                                 rxr->rx_packets++;
2467 #endif
2468                         }
2469                 } else {
2470                         ifp->if_ierrors++;
2471 discard:
2472                         igb_setup_rxdesc(cur, rxbuf);
2473                         if (!eop)
2474                                 rxr->discard = TRUE;
2475                         else
2476                                 rxr->discard = FALSE;
2477                         if (rxr->fmp != NULL) {
2478                                 m_freem(rxr->fmp);
2479                                 rxr->fmp = NULL;
2480                                 rxr->lmp = NULL;
2481                         }
2482                         m = NULL;
2483                 }
2484
2485                 if (m != NULL)
2486                         ether_input_pkt(ifp, m, pi);
2487
2488                 /* Advance our pointers to the next descriptor. */
2489                 if (++i == rxr->num_rx_desc)
2490                         i = 0;
2491
2492                 cur = &rxr->rx_base[i];
2493                 staterr = le32toh(cur->wb.upper.status_error);
2494         }
2495         rxr->next_to_check = i;
2496
2497         if (--i < 0)
2498                 i = rxr->num_rx_desc - 1;
2499         E1000_WRITE_REG(&rxr->sc->hw, E1000_RDT(rxr->me), i);
2500 }
2501
2502
2503 static void
2504 igb_set_vlan(struct igb_softc *sc)
2505 {
2506         struct e1000_hw *hw = &sc->hw;
2507         uint32_t reg;
2508 #if 0
2509         struct ifnet *ifp = sc->arpcom.ac_if;
2510 #endif
2511
2512         if (sc->vf_ifp) {
2513                 e1000_rlpml_set_vf(hw, sc->max_frame_size + VLAN_TAG_SIZE);
2514                 return;
2515         }
2516
2517         reg = E1000_READ_REG(hw, E1000_CTRL);
2518         reg |= E1000_CTRL_VME;
2519         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2520
2521 #if 0
2522         /* Enable the Filter Table */
2523         if (ifp->if_capenable & IFCAP_VLAN_HWFILTER) {
2524                 reg = E1000_READ_REG(hw, E1000_RCTL);
2525                 reg &= ~E1000_RCTL_CFIEN;
2526                 reg |= E1000_RCTL_VFE;
2527                 E1000_WRITE_REG(hw, E1000_RCTL, reg);
2528         }
2529 #endif
2530
2531         /* Update the frame size */
2532         E1000_WRITE_REG(&sc->hw, E1000_RLPML,
2533             sc->max_frame_size + VLAN_TAG_SIZE);
2534
2535 #if 0
2536         /* Don't bother with table if no vlans */
2537         if ((adapter->num_vlans == 0) ||
2538             ((ifp->if_capenable & IFCAP_VLAN_HWFILTER) == 0))
2539                 return;
2540         /*
2541         ** A soft reset zero's out the VFTA, so
2542         ** we need to repopulate it now.
2543         */
2544         for (int i = 0; i < IGB_VFTA_SIZE; i++)
2545                 if (adapter->shadow_vfta[i] != 0) {
2546                         if (adapter->vf_ifp)
2547                                 e1000_vfta_set_vf(hw,
2548                                     adapter->shadow_vfta[i], TRUE);
2549                         else
2550                                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA,
2551                                  i, adapter->shadow_vfta[i]);
2552                 }
2553 #endif
2554 }
2555
2556 static void
2557 igb_enable_intr(struct igb_softc *sc)
2558 {
2559         lwkt_serialize_handler_enable(&sc->main_serialize);
2560
2561         if ((sc->flags & IGB_FLAG_SHARED_INTR) == 0) {
2562                 /* XXX MSI-X should use sc->intr_mask */
2563                 E1000_WRITE_REG(&sc->hw, E1000_EIAC, 0);
2564                 E1000_WRITE_REG(&sc->hw, E1000_EIAM, sc->intr_mask);
2565                 E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->intr_mask);
2566                 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC);
2567         } else {
2568                 E1000_WRITE_REG(&sc->hw, E1000_IMS, IMS_ENABLE_MASK);
2569         }
2570         E1000_WRITE_FLUSH(&sc->hw);
2571 }
2572
2573 static void
2574 igb_disable_intr(struct igb_softc *sc)
2575 {
2576         if ((sc->flags & IGB_FLAG_SHARED_INTR) == 0) {
2577                 E1000_WRITE_REG(&sc->hw, E1000_EIMC, 0xffffffff);
2578                 E1000_WRITE_REG(&sc->hw, E1000_EIAC, 0);
2579         }
2580         E1000_WRITE_REG(&sc->hw, E1000_IMC, 0xffffffff);
2581         E1000_WRITE_FLUSH(&sc->hw);
2582
2583         lwkt_serialize_handler_disable(&sc->main_serialize);
2584 }
2585
2586 /*
2587  * Bit of a misnomer, what this really means is
2588  * to enable OS management of the system... aka
2589  * to disable special hardware management features
2590  */
2591 static void
2592 igb_get_mgmt(struct igb_softc *sc)
2593 {
2594         if (sc->flags & IGB_FLAG_HAS_MGMT) {
2595                 int manc2h = E1000_READ_REG(&sc->hw, E1000_MANC2H);
2596                 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
2597
2598                 /* disable hardware interception of ARP */
2599                 manc &= ~E1000_MANC_ARP_EN;
2600
2601                 /* enable receiving management packets to the host */
2602                 manc |= E1000_MANC_EN_MNG2HOST;
2603                 manc2h |= 1 << 5; /* Mng Port 623 */
2604                 manc2h |= 1 << 6; /* Mng Port 664 */
2605                 E1000_WRITE_REG(&sc->hw, E1000_MANC2H, manc2h);
2606                 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
2607         }
2608 }
2609
2610 /*
2611  * Give control back to hardware management controller
2612  * if there is one.
2613  */
2614 static void
2615 igb_rel_mgmt(struct igb_softc *sc)
2616 {
2617         if (sc->flags & IGB_FLAG_HAS_MGMT) {
2618                 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
2619
2620                 /* Re-enable hardware interception of ARP */
2621                 manc |= E1000_MANC_ARP_EN;
2622                 manc &= ~E1000_MANC_EN_MNG2HOST;
2623
2624                 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
2625         }
2626 }
2627
2628 /*
2629  * Sets CTRL_EXT:DRV_LOAD bit.
2630  *
2631  * For ASF and Pass Through versions of f/w this means that
2632  * the driver is loaded.
2633  */
2634 static void
2635 igb_get_hw_control(struct igb_softc *sc)
2636 {
2637         uint32_t ctrl_ext;
2638
2639         if (sc->vf_ifp)
2640                 return;
2641
2642         /* Let firmware know the driver has taken over */
2643         ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
2644         E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
2645             ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2646 }
2647
2648 /*
2649  * Resets CTRL_EXT:DRV_LOAD bit.
2650  *
2651  * For ASF and Pass Through versions of f/w this means that the
2652  * driver is no longer loaded.
2653  */
2654 static void
2655 igb_rel_hw_control(struct igb_softc *sc)
2656 {
2657         uint32_t ctrl_ext;
2658
2659         if (sc->vf_ifp)
2660                 return;
2661
2662         /* Let firmware taken over control of h/w */
2663         ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
2664         E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
2665             ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2666 }
2667
2668 static int
2669 igb_is_valid_ether_addr(const uint8_t *addr)
2670 {
2671         uint8_t zero_addr[ETHER_ADDR_LEN] = { 0, 0, 0, 0, 0, 0 };
2672
2673         if ((addr[0] & 1) || !bcmp(addr, zero_addr, ETHER_ADDR_LEN))
2674                 return FALSE;
2675         return TRUE;
2676 }
2677
2678 /*
2679  * Enable PCI Wake On Lan capability
2680  */
2681 static void
2682 igb_enable_wol(device_t dev)
2683 {
2684         uint16_t cap, status;
2685         uint8_t id;
2686
2687         /* First find the capabilities pointer*/
2688         cap = pci_read_config(dev, PCIR_CAP_PTR, 2);
2689
2690         /* Read the PM Capabilities */
2691         id = pci_read_config(dev, cap, 1);
2692         if (id != PCIY_PMG)     /* Something wrong */
2693                 return;
2694
2695         /*
2696          * OK, we have the power capabilities,
2697          * so now get the status register
2698          */
2699         cap += PCIR_POWER_STATUS;
2700         status = pci_read_config(dev, cap, 2);
2701         status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
2702         pci_write_config(dev, cap, status, 2);
2703 }
2704
2705 static void
2706 igb_update_stats_counters(struct igb_softc *sc)
2707 {
2708         struct e1000_hw *hw = &sc->hw;
2709         struct e1000_hw_stats *stats;
2710         struct ifnet *ifp = &sc->arpcom.ac_if;
2711
2712         /*
2713          * The virtual function adapter has only a
2714          * small controlled set of stats, do only
2715          * those and return.
2716          */
2717         if (sc->vf_ifp) {
2718                 igb_update_vf_stats_counters(sc);
2719                 return;
2720         }
2721         stats = sc->stats;
2722
2723         if (sc->hw.phy.media_type == e1000_media_type_copper ||
2724             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
2725                 stats->symerrs +=
2726                     E1000_READ_REG(hw,E1000_SYMERRS);
2727                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
2728         }
2729
2730         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
2731         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
2732         stats->scc += E1000_READ_REG(hw, E1000_SCC);
2733         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
2734
2735         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
2736         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
2737         stats->colc += E1000_READ_REG(hw, E1000_COLC);
2738         stats->dc += E1000_READ_REG(hw, E1000_DC);
2739         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
2740         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
2741         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
2742
2743         /*
2744          * For watchdog management we need to know if we have been
2745          * paused during the last interval, so capture that here.
2746          */
2747         sc->pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
2748         stats->xoffrxc += sc->pause_frames;
2749         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
2750         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
2751         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
2752         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
2753         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
2754         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
2755         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
2756         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
2757         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
2758         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
2759         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
2760         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
2761
2762         /* For the 64-bit byte counters the low dword must be read first. */
2763         /* Both registers clear on the read of the high dword */
2764
2765         stats->gorc += E1000_READ_REG(hw, E1000_GORCL) +
2766             ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
2767         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL) +
2768             ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
2769
2770         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
2771         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
2772         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
2773         stats->roc += E1000_READ_REG(hw, E1000_ROC);
2774         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
2775
2776         stats->tor += E1000_READ_REG(hw, E1000_TORH);
2777         stats->tot += E1000_READ_REG(hw, E1000_TOTH);
2778
2779         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
2780         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
2781         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
2782         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
2783         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
2784         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
2785         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
2786         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
2787         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
2788         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
2789
2790         /* Interrupt Counts */
2791
2792         stats->iac += E1000_READ_REG(hw, E1000_IAC);
2793         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
2794         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
2795         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
2796         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
2797         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
2798         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
2799         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
2800         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
2801
2802         /* Host to Card Statistics */
2803
2804         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
2805         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
2806         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
2807         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
2808         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
2809         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
2810         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
2811         stats->hgorc += (E1000_READ_REG(hw, E1000_HGORCL) +
2812             ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32));
2813         stats->hgotc += (E1000_READ_REG(hw, E1000_HGOTCL) +
2814             ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32));
2815         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
2816         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
2817         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
2818
2819         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
2820         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
2821         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
2822         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
2823         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
2824         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
2825
2826         ifp->if_collisions = stats->colc;
2827
2828         /* Rx Errors */
2829         ifp->if_ierrors = stats->rxerrc + stats->crcerrs + stats->algnerrc +
2830             stats->ruc + stats->roc + stats->mpc + stats->cexterr;
2831
2832         /* Tx Errors */
2833         ifp->if_oerrors = stats->ecol + stats->latecol + sc->watchdog_events;
2834
2835         /* Driver specific counters */
2836         sc->device_control = E1000_READ_REG(hw, E1000_CTRL);
2837         sc->rx_control = E1000_READ_REG(hw, E1000_RCTL);
2838         sc->int_mask = E1000_READ_REG(hw, E1000_IMS);
2839         sc->eint_mask = E1000_READ_REG(hw, E1000_EIMS);
2840         sc->packet_buf_alloc_tx =
2841             ((E1000_READ_REG(hw, E1000_PBA) & 0xffff0000) >> 16);
2842         sc->packet_buf_alloc_rx =
2843             (E1000_READ_REG(hw, E1000_PBA) & 0xffff);
2844 }
2845
2846 static void
2847 igb_vf_init_stats(struct igb_softc *sc)
2848 {
2849         struct e1000_hw *hw = &sc->hw;
2850         struct e1000_vf_stats *stats;
2851
2852         stats = sc->stats;
2853         stats->last_gprc = E1000_READ_REG(hw, E1000_VFGPRC);
2854         stats->last_gorc = E1000_READ_REG(hw, E1000_VFGORC);
2855         stats->last_gptc = E1000_READ_REG(hw, E1000_VFGPTC);
2856         stats->last_gotc = E1000_READ_REG(hw, E1000_VFGOTC);
2857         stats->last_mprc = E1000_READ_REG(hw, E1000_VFMPRC);
2858 }
2859
2860 static void
2861 igb_update_vf_stats_counters(struct igb_softc *sc)
2862 {
2863         struct e1000_hw *hw = &sc->hw;
2864         struct e1000_vf_stats *stats;
2865
2866         if (sc->link_speed == 0)
2867                 return;
2868
2869         stats = sc->stats;
2870         UPDATE_VF_REG(E1000_VFGPRC, stats->last_gprc, stats->gprc);
2871         UPDATE_VF_REG(E1000_VFGORC, stats->last_gorc, stats->gorc);
2872         UPDATE_VF_REG(E1000_VFGPTC, stats->last_gptc, stats->gptc);
2873         UPDATE_VF_REG(E1000_VFGOTC, stats->last_gotc, stats->gotc);
2874         UPDATE_VF_REG(E1000_VFMPRC, stats->last_mprc, stats->mprc);
2875 }
2876
2877 #ifdef DEVICE_POLLING
2878
2879 static void
2880 igb_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2881 {
2882         struct igb_softc *sc = ifp->if_softc;
2883         uint32_t reg_icr;
2884
2885         ASSERT_SERIALIZED(&sc->main_serialize);
2886
2887         switch (cmd) {
2888         case POLL_REGISTER:
2889                 igb_disable_intr(sc);
2890                 break;
2891
2892         case POLL_DEREGISTER:
2893                 igb_enable_intr(sc);
2894                 break;
2895
2896         case POLL_AND_CHECK_STATUS:
2897                 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
2898                 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
2899                         sc->hw.mac.get_link_status = 1;
2900                         igb_update_link_status(sc);
2901                 }
2902                 /* FALL THROUGH */
2903         case POLL_ONLY:
2904                 if (ifp->if_flags & IFF_RUNNING) {
2905                         struct igb_tx_ring *txr;
2906                         int i;
2907
2908                         for (i = 0; i < sc->rx_ring_inuse; ++i) {
2909                                 struct igb_rx_ring *rxr = &sc->rx_rings[i];
2910
2911                                 lwkt_serialize_enter(&rxr->rx_serialize);
2912                                 igb_rxeof(rxr, count);
2913                                 lwkt_serialize_exit(&rxr->rx_serialize);
2914                         }
2915
2916                         txr = &sc->tx_rings[0];
2917                         lwkt_serialize_enter(&txr->tx_serialize);
2918                         igb_txeof(txr);
2919                         if (!ifq_is_empty(&ifp->if_snd))
2920                                 if_devstart(ifp);
2921                         lwkt_serialize_exit(&txr->tx_serialize);
2922                 }
2923                 break;
2924         }
2925 }
2926
2927 #endif /* DEVICE_POLLING */
2928
2929 static void
2930 igb_intr(void *xsc)
2931 {
2932         struct igb_softc *sc = xsc;
2933         struct ifnet *ifp = &sc->arpcom.ac_if;
2934         uint32_t eicr;
2935
2936         ASSERT_SERIALIZED(&sc->main_serialize);
2937
2938         eicr = E1000_READ_REG(&sc->hw, E1000_EICR);
2939
2940         if (eicr == 0)
2941                 return;
2942
2943         if (ifp->if_flags & IFF_RUNNING) {
2944                 struct igb_tx_ring *txr;
2945                 int i;
2946
2947                 for (i = 0; i < sc->rx_ring_inuse; ++i) {
2948                         struct igb_rx_ring *rxr = &sc->rx_rings[i];
2949
2950                         if (eicr & rxr->rx_intr_mask) {
2951                                 lwkt_serialize_enter(&rxr->rx_serialize);
2952                                 igb_rxeof(rxr, -1);
2953                                 lwkt_serialize_exit(&rxr->rx_serialize);
2954                         }
2955                 }
2956
2957                 txr = &sc->tx_rings[0];
2958                 if (eicr & txr->tx_intr_mask) {
2959                         lwkt_serialize_enter(&txr->tx_serialize);
2960                         igb_txeof(txr);
2961                         if (!ifq_is_empty(&ifp->if_snd))
2962                                 if_devstart(ifp);
2963                         lwkt_serialize_exit(&txr->tx_serialize);
2964                 }
2965         }
2966
2967         if (eicr & E1000_EICR_OTHER) {
2968                 uint32_t icr = E1000_READ_REG(&sc->hw, E1000_ICR);
2969
2970                 /* Link status change */
2971                 if (icr & E1000_ICR_LSC) {
2972                         sc->hw.mac.get_link_status = 1;
2973                         igb_update_link_status(sc);
2974                 }
2975         }
2976
2977         /*
2978          * Reading EICR has the side effect to clear interrupt mask,
2979          * so all interrupts need to be enabled here.
2980          */
2981         E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->intr_mask);
2982 }
2983
2984 static void
2985 igb_shared_intr(void *xsc)
2986 {
2987         struct igb_softc *sc = xsc;
2988         struct ifnet *ifp = &sc->arpcom.ac_if;
2989         uint32_t reg_icr;
2990
2991         ASSERT_SERIALIZED(&sc->main_serialize);
2992
2993         reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
2994
2995         /* Hot eject?  */
2996         if (reg_icr == 0xffffffff)
2997                 return;
2998
2999         /* Definitely not our interrupt.  */
3000         if (reg_icr == 0x0)
3001                 return;
3002
3003         if ((reg_icr & E1000_ICR_INT_ASSERTED) == 0)
3004                 return;
3005
3006         if (ifp->if_flags & IFF_RUNNING) {
3007                 struct igb_tx_ring *txr;
3008                 int i;
3009
3010                 for (i = 0; i < sc->rx_ring_inuse; ++i) {
3011                         struct igb_rx_ring *rxr = &sc->rx_rings[i];
3012
3013                         lwkt_serialize_enter(&rxr->rx_serialize);
3014                         igb_rxeof(rxr, -1);
3015                         lwkt_serialize_exit(&rxr->rx_serialize);
3016                 }
3017
3018                 txr = &sc->tx_rings[0];
3019                 lwkt_serialize_enter(&txr->tx_serialize);
3020                 igb_txeof(txr);
3021                 if (!ifq_is_empty(&ifp->if_snd))
3022                         if_devstart(ifp);
3023                 lwkt_serialize_exit(&txr->tx_serialize);
3024         }
3025
3026         /* Link status change */
3027         if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3028                 sc->hw.mac.get_link_status = 1;
3029                 igb_update_link_status(sc);
3030         }
3031
3032         if (reg_icr & E1000_ICR_RXO)
3033                 sc->rx_overruns++;
3034 }
3035
3036 static int
3037 igb_txctx_pullup(struct igb_tx_ring *txr, struct mbuf **m0)
3038 {
3039         struct mbuf *m = *m0;
3040         struct ether_header *eh;
3041         int len;
3042
3043         txr->ctx_try_pullup++;
3044
3045         len = ETHER_HDR_LEN + IGB_IPVHL_SIZE;
3046
3047         if (__predict_false(!M_WRITABLE(m))) {
3048                 if (__predict_false(m->m_len < ETHER_HDR_LEN)) {
3049                         txr->ctx_drop1++;
3050                         m_freem(m);
3051                         *m0 = NULL;
3052                         return ENOBUFS;
3053                 }
3054                 eh = mtod(m, struct ether_header *);
3055
3056                 if (eh->ether_type == htons(ETHERTYPE_VLAN))
3057                         len += EVL_ENCAPLEN;
3058
3059                 if (m->m_len < len) {
3060                         txr->ctx_drop2++;
3061                         m_freem(m);
3062                         *m0 = NULL;
3063                         return ENOBUFS;
3064                 }
3065                 return 0;
3066         }
3067
3068         if (__predict_false(m->m_len < ETHER_HDR_LEN)) {
3069                 txr->ctx_pullup1++;
3070                 m = m_pullup(m, ETHER_HDR_LEN);
3071                 if (m == NULL) {
3072                         txr->ctx_pullup1_failed++;
3073                         *m0 = NULL;
3074                         return ENOBUFS;
3075                 }
3076                 *m0 = m;
3077         }
3078         eh = mtod(m, struct ether_header *);
3079
3080         if (eh->ether_type == htons(ETHERTYPE_VLAN))
3081                 len += EVL_ENCAPLEN;
3082
3083         if (m->m_len < len) {
3084                 txr->ctx_pullup2++;
3085                 m = m_pullup(m, len);
3086                 if (m == NULL) {
3087                         txr->ctx_pullup2_failed++;
3088                         *m0 = NULL;
3089                         return ENOBUFS;
3090                 }
3091                 *m0 = m;
3092         }
3093         return 0;
3094 }
3095
3096 static int
3097 igb_encap(struct igb_tx_ring *txr, struct mbuf **m_headp)
3098 {
3099         bus_dma_segment_t segs[IGB_MAX_SCATTER];
3100         bus_dmamap_t map;
3101         struct igb_tx_buf *tx_buf, *tx_buf_mapped;
3102         union e1000_adv_tx_desc *txd = NULL;
3103         struct mbuf *m_head = *m_headp;
3104         uint32_t olinfo_status = 0, cmd_type_len = 0, cmd_rs = 0;
3105         int maxsegs, nsegs, i, j, error, last = 0;
3106         uint32_t hdrlen = 0;
3107
3108         if (m_head->m_len < IGB_TXCSUM_MINHL &&
3109             ((m_head->m_pkthdr.csum_flags & IGB_CSUM_FEATURES) ||
3110              (m_head->m_flags & M_VLANTAG))) {
3111                 /*
3112                  * Make sure that ethernet header and ip.ip_hl are in
3113                  * contiguous memory, since if TXCSUM or VLANTAG is
3114                  * enabled, later TX context descriptor's setup need
3115                  * to access ip.ip_hl.
3116                  */
3117                 error = igb_txctx_pullup(txr, m_headp);
3118                 if (error) {
3119                         KKASSERT(*m_headp == NULL);
3120                         return error;
3121                 }
3122                 m_head = *m_headp;
3123         }
3124
3125         /* Set basic descriptor constants */
3126         cmd_type_len |= E1000_ADVTXD_DTYP_DATA;
3127         cmd_type_len |= E1000_ADVTXD_DCMD_IFCS | E1000_ADVTXD_DCMD_DEXT;
3128         if (m_head->m_flags & M_VLANTAG)
3129                 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
3130
3131         /*
3132          * Map the packet for DMA.
3133          */
3134         tx_buf = &txr->tx_buf[txr->next_avail_desc];
3135         tx_buf_mapped = tx_buf;
3136         map = tx_buf->map;
3137
3138         maxsegs = txr->tx_avail - IGB_TX_RESERVED;
3139         KASSERT(maxsegs >= txr->spare_desc, ("not enough spare TX desc\n"));
3140         if (maxsegs > IGB_MAX_SCATTER)
3141                 maxsegs = IGB_MAX_SCATTER;
3142
3143         error = bus_dmamap_load_mbuf_defrag(txr->tx_tag, map, m_headp,
3144             segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
3145         if (error) {
3146                 if (error == ENOBUFS)
3147                         txr->sc->mbuf_defrag_failed++;
3148                 else
3149                         txr->sc->no_tx_dma_setup++;
3150
3151                 m_freem(*m_headp);
3152                 *m_headp = NULL;
3153                 return error;
3154         }
3155         bus_dmamap_sync(txr->tx_tag, map, BUS_DMASYNC_PREWRITE);
3156
3157         m_head = *m_headp;
3158
3159 #if 0
3160         /*
3161          * Set up the context descriptor:
3162          * used when any hardware offload is done.
3163          * This includes CSUM, VLAN, and TSO. It
3164          * will use the first descriptor.
3165          */
3166         if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3167                 if (igb_tso_setup(txr, m_head, &hdrlen)) {
3168                         cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
3169                         olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
3170                         olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3171                 } else
3172                         return (ENXIO);
3173         } else if (igb_tx_ctx_setup(txr, m_head))
3174                 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3175 #else
3176         if (igb_txctx(txr, m_head)) {
3177                 olinfo_status |= (E1000_TXD_POPTS_IXSM << 8);
3178                 if (m_head->m_pkthdr.csum_flags & (CSUM_UDP | CSUM_TCP))
3179                         olinfo_status |= (E1000_TXD_POPTS_TXSM << 8);
3180                 txr->tx_nsegs++;
3181         }
3182 #endif
3183
3184         txr->tx_nsegs += nsegs;
3185         if (txr->tx_nsegs >= txr->intr_nsegs) {
3186                 /*
3187                  * Report Status (RS) is turned on every intr_nsegs
3188                  * descriptors (roughly).
3189                  */
3190                 txr->tx_nsegs = 0;
3191                 cmd_rs = E1000_ADVTXD_DCMD_RS;
3192         }
3193
3194         /* Calculate payload length */
3195         olinfo_status |= ((m_head->m_pkthdr.len - hdrlen)
3196             << E1000_ADVTXD_PAYLEN_SHIFT);
3197
3198         /* 82575 needs the queue index added */
3199         if (txr->sc->hw.mac.type == e1000_82575)
3200                 olinfo_status |= txr->me << 4;
3201
3202         /* Set up our transmit descriptors */
3203         i = txr->next_avail_desc;
3204         for (j = 0; j < nsegs; j++) {
3205                 bus_size_t seg_len;
3206                 bus_addr_t seg_addr;
3207
3208                 tx_buf = &txr->tx_buf[i];
3209                 txd = (union e1000_adv_tx_desc *)&txr->tx_base[i];
3210                 seg_addr = segs[j].ds_addr;
3211                 seg_len = segs[j].ds_len;
3212
3213                 txd->read.buffer_addr = htole64(seg_addr);
3214                 txd->read.cmd_type_len = htole32(cmd_type_len | seg_len);
3215                 txd->read.olinfo_status = htole32(olinfo_status);
3216                 last = i;
3217                 if (++i == txr->num_tx_desc)
3218                         i = 0;
3219                 tx_buf->m_head = NULL;
3220         }
3221
3222         KASSERT(txr->tx_avail > nsegs, ("invalid avail TX desc\n"));
3223         txr->next_avail_desc = i;
3224         txr->tx_avail -= nsegs;
3225
3226         tx_buf->m_head = m_head;
3227         tx_buf_mapped->map = tx_buf->map;
3228         tx_buf->map = map;
3229
3230         /*
3231          * Last Descriptor of Packet needs End Of Packet (EOP)
3232          */
3233         txd->read.cmd_type_len |= htole32(E1000_ADVTXD_DCMD_EOP | cmd_rs);
3234
3235         /*
3236          * Advance the Transmit Descriptor Tail (TDT), this tells the E1000
3237          * that this frame is available to transmit.
3238          */
3239         E1000_WRITE_REG(&txr->sc->hw, E1000_TDT(txr->me), i);
3240         ++txr->tx_packets;
3241
3242         return 0;
3243 }
3244
3245 static void
3246 igb_start(struct ifnet *ifp)
3247 {
3248         struct igb_softc *sc = ifp->if_softc;
3249         struct igb_tx_ring *txr = &sc->tx_rings[0];
3250         struct mbuf *m_head;
3251
3252         ASSERT_SERIALIZED(&txr->tx_serialize);
3253
3254         if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING)
3255                 return;
3256
3257         if (!sc->link_active) {
3258                 ifq_purge(&ifp->if_snd);
3259                 return;
3260         }
3261
3262         if (!IGB_IS_NOT_OACTIVE(txr))
3263                 igb_txeof(txr);
3264
3265         while (!ifq_is_empty(&ifp->if_snd)) {
3266                 if (IGB_IS_OACTIVE(txr)) {
3267                         ifp->if_flags |= IFF_OACTIVE;
3268                         /* Set watchdog on */
3269                         ifp->if_timer = 5;
3270                         break;
3271                 }
3272
3273                 m_head = ifq_dequeue(&ifp->if_snd, NULL);
3274                 if (m_head == NULL)
3275                         break;
3276
3277                 if (igb_encap(txr, &m_head)) {
3278                         ifp->if_oerrors++;
3279                         continue;
3280                 }
3281
3282                 /* Send a copy of the frame to the BPF listener */
3283                 ETHER_BPF_MTAP(ifp, m_head);
3284         }
3285 }
3286
3287 static void
3288 igb_watchdog(struct ifnet *ifp)
3289 {
3290         struct igb_softc *sc = ifp->if_softc;
3291         struct igb_tx_ring *txr = &sc->tx_rings[0];
3292
3293         ASSERT_IFNET_SERIALIZED_ALL(ifp);
3294
3295         /*
3296          * If flow control has paused us since last checking
3297          * it invalidates the watchdog timing, so dont run it.
3298          */
3299         if (sc->pause_frames) {
3300                 sc->pause_frames = 0;
3301                 ifp->if_timer = 5;
3302                 return;
3303         }
3304
3305         if_printf(ifp, "Watchdog timeout -- resetting\n");
3306         if_printf(ifp, "Queue(%d) tdh = %d, hw tdt = %d\n", txr->me,
3307             E1000_READ_REG(&sc->hw, E1000_TDH(txr->me)),
3308             E1000_READ_REG(&sc->hw, E1000_TDT(txr->me)));
3309         if_printf(ifp, "TX(%d) desc avail = %d, "
3310             "Next TX to Clean = %d\n",
3311             txr->me, txr->tx_avail, txr->next_to_clean);
3312
3313         ifp->if_oerrors++;
3314         sc->watchdog_events++;
3315
3316         igb_init(sc);
3317         if (!ifq_is_empty(&ifp->if_snd))
3318                 if_devstart(ifp);
3319 }
3320
3321 static void
3322 igb_set_eitr(struct igb_softc *sc)
3323 {
3324         uint32_t itr = 0;
3325
3326         if (sc->intr_rate > 0) {
3327                 if (sc->hw.mac.type == e1000_82575) {
3328                         itr = 1000000000 / 256 / sc->intr_rate;
3329                         /*
3330                          * NOTE:
3331                          * Document is wrong on the 2 bits left shift
3332                          */
3333                 } else {
3334                         itr = 1000000 / sc->intr_rate;
3335                         itr <<= 2;
3336                 }
3337                 itr &= 0x7FFC;
3338         }
3339         if (sc->hw.mac.type == e1000_82575)
3340                 itr |= itr << 16;
3341         else
3342                 itr |= E1000_EITR_CNT_IGNR;
3343         E1000_WRITE_REG(&sc->hw, E1000_EITR(0), itr);
3344 }
3345
3346 static int
3347 igb_sysctl_intr_rate(SYSCTL_HANDLER_ARGS)
3348 {
3349         struct igb_softc *sc = (void *)arg1;
3350         struct ifnet *ifp = &sc->arpcom.ac_if;
3351         int error, intr_rate;
3352
3353         intr_rate = sc->intr_rate;
3354         error = sysctl_handle_int(oidp, &intr_rate, 0, req);
3355         if (error || req->newptr == NULL)
3356                 return error;
3357         if (intr_rate < 0)
3358                 return EINVAL;
3359
3360         ifnet_serialize_all(ifp);
3361
3362         sc->intr_rate = intr_rate;
3363         if (ifp->if_flags & IFF_RUNNING)
3364                 igb_set_eitr(sc);
3365
3366         ifnet_deserialize_all(ifp);
3367
3368         if (bootverbose)
3369                 if_printf(ifp, "Interrupt rate set to %d/sec\n", sc->intr_rate);
3370         return 0;
3371 }
3372
3373 static int
3374 igb_sysctl_tx_intr_nsegs(SYSCTL_HANDLER_ARGS)
3375 {
3376         struct igb_softc *sc = (void *)arg1;
3377         struct ifnet *ifp = &sc->arpcom.ac_if;
3378         struct igb_tx_ring *txr = &sc->tx_rings[0];
3379         int error, nsegs;
3380
3381         nsegs = txr->intr_nsegs;
3382         error = sysctl_handle_int(oidp, &nsegs, 0, req);
3383         if (error || req->newptr == NULL)
3384                 return error;
3385         if (nsegs <= 0)
3386                 return EINVAL;
3387
3388         ifnet_serialize_all(ifp);
3389
3390         if (nsegs >= txr->num_tx_desc - txr->oact_lo_desc ||
3391             nsegs >= txr->oact_hi_desc - IGB_MAX_SCATTER) {
3392                 error = EINVAL;
3393         } else {
3394                 error = 0;
3395                 txr->intr_nsegs = nsegs;
3396         }
3397
3398         ifnet_deserialize_all(ifp);
3399
3400         return error;
3401 }
3402
3403 static void
3404 igb_init_intr(struct igb_softc *sc)
3405 {
3406         igb_set_intr_mask(sc);
3407         if (sc->flags & IGB_FLAG_SHARED_INTR)
3408                 igb_set_eitr(sc);
3409         else
3410                 igb_init_unshared_intr(sc);
3411 }
3412
3413 static void
3414 igb_init_unshared_intr(struct igb_softc *sc)
3415 {
3416         struct e1000_hw *hw = &sc->hw;
3417         const struct igb_rx_ring *rxr;
3418         const struct igb_tx_ring *txr;
3419         uint32_t ivar, index;
3420         int i;
3421
3422         /*
3423          * Enable extended mode
3424          */
3425         if (sc->hw.mac.type != e1000_82575) {
3426                 E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_NSICR);
3427         } else {
3428                 uint32_t tmp;
3429
3430                 tmp = E1000_READ_REG(hw, E1000_CTRL_EXT);
3431                 tmp |= E1000_CTRL_EXT_IRCA;
3432                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmp);
3433         }
3434
3435         /*
3436          * Map TX/RX interrupts to EICR
3437          */
3438         switch (sc->hw.mac.type) {
3439         case e1000_82580:
3440         case e1000_i350:
3441         case e1000_vfadapt:
3442         case e1000_vfadapt_i350:
3443                 /* RX entries */
3444                 for (i = 0; i < sc->rx_ring_inuse; ++i) {
3445                         rxr = &sc->rx_rings[i];
3446
3447                         index = i >> 1;
3448                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3449
3450                         if (i & 1) {
3451                                 ivar &= 0xff00ffff;
3452                                 ivar |=
3453                                 (rxr->rx_intr_bit | E1000_IVAR_VALID) << 16;
3454                         } else {
3455                                 ivar &= 0xffffff00;
3456                                 ivar |=
3457                                 (rxr->rx_intr_bit | E1000_IVAR_VALID);
3458                         }
3459                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3460                 }
3461                 /* TX entries */
3462                 for (i = 0; i < sc->tx_ring_cnt; ++i) {
3463                         txr = &sc->tx_rings[i];
3464
3465                         index = i >> 1;
3466                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3467
3468                         if (i & 1) {
3469                                 ivar &= 0x00ffffff;
3470                                 ivar |=
3471                                 (txr->tx_intr_bit | E1000_IVAR_VALID) << 24;
3472                         } else {
3473                                 ivar &= 0xffff00ff;
3474                                 ivar |=
3475                                 (txr->tx_intr_bit | E1000_IVAR_VALID) << 8;
3476                         }
3477                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3478                 }
3479                 /* Clear unused IVAR_MISC */
3480                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, 0);
3481                 break;
3482
3483         case e1000_82576:
3484                 /* RX entries */
3485                 for (i = 0; i < sc->rx_ring_inuse; ++i) {
3486                         rxr = &sc->rx_rings[i];
3487
3488                         index = i & 0x7; /* Each IVAR has two entries */
3489                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3490
3491                         if (i < 8) {
3492                                 ivar &= 0xffffff00;
3493                                 ivar |=
3494                                 (rxr->rx_intr_bit | E1000_IVAR_VALID);
3495                         } else {
3496                                 ivar &= 0xff00ffff;
3497                                 ivar |=
3498                                 (rxr->rx_intr_bit | E1000_IVAR_VALID) << 16;
3499                         }
3500                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3501                 }
3502                 /* TX entries */
3503                 for (i = 0; i < sc->tx_ring_cnt; ++i) {
3504                         txr = &sc->tx_rings[i];
3505
3506                         index = i & 0x7; /* Each IVAR has two entries */
3507                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3508
3509                         if (i < 8) {
3510                                 ivar &= 0xffff00ff;
3511                                 ivar |=
3512                                 (txr->tx_intr_bit | E1000_IVAR_VALID) << 8;
3513                         } else {
3514                                 ivar &= 0x00ffffff;
3515                                 ivar |=
3516                                 (txr->tx_intr_bit | E1000_IVAR_VALID) << 24;
3517                         }
3518                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3519                 }
3520                 /* Clear unused IVAR_MISC */
3521                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, 0);
3522                 break;
3523
3524         case e1000_82575:
3525                 /*
3526                  * Enable necessary interrupt bits.
3527                  *
3528                  * The name of the register is confusing; in addition to
3529                  * configuring the first vector of MSI-X, it also configures
3530                  * which bits of EICR could be set by the hardware even when
3531                  * MSI or line interrupt is used; it thus controls interrupt
3532                  * generation.  It MUST be configured explicitly; the default
3533                  * value mentioned in the datasheet is wrong: RX queue0 and
3534                  * TX queue0 are NOT enabled by default.
3535                  */
3536                 E1000_WRITE_REG(&sc->hw, E1000_MSIXBM(0), sc->intr_mask);
3537                 break;
3538
3539         default:
3540                 break;
3541         }
3542
3543         /*
3544          * Configure interrupt moderation
3545          */
3546         igb_set_eitr(sc);
3547 }
3548
3549 static int
3550 igb_setup_intr(struct igb_softc *sc)
3551 {
3552         struct ifnet *ifp = &sc->arpcom.ac_if;
3553         int error, i, intr_bit, intr_bitmax;
3554
3555         /*
3556          * Setup interrupt mask
3557          */
3558         switch (sc->hw.mac.type) {
3559         case e1000_82575:
3560                 intr_bitmax = IGB_MAX_TXRXINT_82575;
3561                 break;
3562         case e1000_82580:
3563                 intr_bitmax = IGB_MAX_TXRXINT_82580;
3564                 break;
3565         case e1000_i350:
3566                 intr_bitmax = IGB_MAX_TXRXINT_I350;
3567                 break;
3568         case e1000_82576:
3569                 intr_bitmax = IGB_MAX_TXRXINT_82576;
3570                 break;
3571         default:
3572                 intr_bitmax = IGB_MIN_TXRXINT;
3573                 break;
3574         }
3575         intr_bit = 0;
3576         for (i = 0; i < sc->tx_ring_cnt; ++i)
3577                 igb_setup_tx_intr(&sc->tx_rings[i], &intr_bit, intr_bitmax);
3578         for (i = 0; i < sc->rx_ring_cnt; ++i)
3579                 igb_setup_rx_intr(&sc->rx_rings[i], &intr_bit, intr_bitmax);
3580
3581         igb_set_intr_mask(sc);
3582
3583         if (sc->intr_type == PCI_INTR_TYPE_LEGACY) {
3584                 int unshared;
3585
3586                 unshared = device_getenv_int(sc->dev, "irq.unshared", 0);
3587                 if (!unshared) {
3588                         sc->flags |= IGB_FLAG_SHARED_INTR;
3589                         if (bootverbose)
3590                                 device_printf(sc->dev, "IRQ shared\n");
3591                 } else if (bootverbose) {
3592                         device_printf(sc->dev, "IRQ unshared\n");
3593                 }
3594         }
3595
3596         error = bus_setup_intr(sc->dev, sc->intr_res, INTR_MPSAFE,
3597             (sc->flags & IGB_FLAG_SHARED_INTR) ? igb_shared_intr : igb_intr,
3598             sc, &sc->intr_tag, &sc->main_serialize);
3599         if (error) {
3600                 device_printf(sc->dev, "Failed to register interrupt handler");
3601                 return error;
3602         }
3603
3604         ifp->if_cpuid = rman_get_cpuid(sc->intr_res);
3605         KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
3606
3607         return 0;
3608 }
3609
3610 static void
3611 igb_setup_tx_intr(struct igb_tx_ring *txr, int *intr_bit0, int intr_bitmax)
3612 {
3613         if (txr->sc->hw.mac.type == e1000_82575) {
3614                 txr->tx_intr_bit = 0;   /* unused */
3615                 switch (txr->me) {
3616                 case 0:
3617                         txr->tx_intr_mask = E1000_EICR_TX_QUEUE0;
3618                         break;
3619                 case 1:
3620                         txr->tx_intr_mask = E1000_EICR_TX_QUEUE1;
3621                         break;
3622                 case 2:
3623                         txr->tx_intr_mask = E1000_EICR_TX_QUEUE2;
3624                         break;
3625                 case 3:
3626                         txr->tx_intr_mask = E1000_EICR_TX_QUEUE3;
3627                         break;
3628                 default:
3629                         panic("unsupported # of TX ring, %d\n", txr->me);
3630                 }
3631         } else {
3632                 int intr_bit = *intr_bit0;
3633
3634                 txr->tx_intr_bit = intr_bit % intr_bitmax;
3635                 txr->tx_intr_mask = 1 << txr->tx_intr_bit;
3636
3637                 *intr_bit0 = intr_bit + 1;
3638         }
3639 }
3640
3641 static void
3642 igb_setup_rx_intr(struct igb_rx_ring *rxr, int *intr_bit0, int intr_bitmax)
3643 {
3644         if (rxr->sc->hw.mac.type == e1000_82575) {
3645                 rxr->rx_intr_bit = 0;   /* unused */
3646                 switch (rxr->me) {
3647                 case 0:
3648                         rxr->rx_intr_mask = E1000_EICR_RX_QUEUE0;
3649                         break;
3650                 case 1:
3651                         rxr->rx_intr_mask = E1000_EICR_RX_QUEUE1;
3652                         break;
3653                 case 2:
3654                         rxr->rx_intr_mask = E1000_EICR_RX_QUEUE2;
3655                         break;
3656                 case 3:
3657                         rxr->rx_intr_mask = E1000_EICR_RX_QUEUE3;
3658                         break;
3659                 default:
3660                         panic("unsupported # of RX ring, %d\n", rxr->me);
3661                 }
3662         } else {
3663                 int intr_bit = *intr_bit0;
3664
3665                 rxr->rx_intr_bit = intr_bit % intr_bitmax;
3666                 rxr->rx_intr_mask = 1 << rxr->rx_intr_bit;
3667
3668                 *intr_bit0 = intr_bit + 1;
3669         }
3670 }
3671
3672 static void
3673 igb_serialize(struct ifnet *ifp, enum ifnet_serialize slz)
3674 {
3675         struct igb_softc *sc = ifp->if_softc;
3676
3677         ifnet_serialize_array_enter(sc->serializes, sc->serialize_cnt,
3678             sc->tx_serialize, sc->rx_serialize, slz);
3679 }
3680
3681 static void
3682 igb_deserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3683 {
3684         struct igb_softc *sc = ifp->if_softc;
3685
3686         ifnet_serialize_array_exit(sc->serializes, sc->serialize_cnt,
3687             sc->tx_serialize, sc->rx_serialize, slz);
3688 }
3689
3690 static int
3691 igb_tryserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3692 {
3693         struct igb_softc *sc = ifp->if_softc;
3694
3695         return ifnet_serialize_array_try(sc->serializes, sc->serialize_cnt,
3696             sc->tx_serialize, sc->rx_serialize, slz);
3697 }
3698
3699 #ifdef INVARIANTS
3700
3701 static void
3702 igb_serialize_assert(struct ifnet *ifp, enum ifnet_serialize slz,
3703     boolean_t serialized)
3704 {
3705         struct igb_softc *sc = ifp->if_softc;
3706
3707         ifnet_serialize_array_assert(sc->serializes, sc->serialize_cnt,
3708             sc->tx_serialize, sc->rx_serialize, slz, serialized);
3709 }
3710
3711 #endif  /* INVARIANTS */
3712
3713 static void
3714 igb_set_intr_mask(struct igb_softc *sc)
3715 {
3716         int i;
3717
3718         sc->intr_mask = E1000_EICR_OTHER;
3719         for (i = 0; i < sc->rx_ring_inuse; ++i)
3720                 sc->intr_mask |= sc->rx_rings[i].rx_intr_mask;
3721         for (i = 0; i < sc->tx_ring_cnt; ++i)
3722                 sc->intr_mask |= sc->tx_rings[i].tx_intr_mask;
3723         if (bootverbose) {
3724                 if_printf(&sc->arpcom.ac_if, "intr mask 0x%08x\n",
3725                     sc->intr_mask);
3726         }
3727 }