2 * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca>
3 * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * $FreeBSD: src/sys/dev/sound/pci/hda/hdac.c,v 1.36.2.3 2007/06/21 20:58:44 ariff Exp $
28 * $DragonFly: src/sys/dev/sound/pci/hda/hdac.c,v 1.9 2007/07/22 18:53:19 dillon Exp $
32 * Intel High Definition Audio (Controller) driver for FreeBSD. Be advised
33 * that this driver still in its early stage, and possible of rewrite are
34 * pretty much guaranteed. There are supposedly several distinct parent/child
35 * busses to make this "perfect", but as for now and for the sake of
36 * simplicity, everything is gobble up within single source.
39 * 1) HDA Controller support
40 * 2) HDA Codecs support, which may include
44 * 3) Widget parser - the real magic of why this driver works on so
45 * many hardwares with minimal vendor specific quirk. The original
46 * parser was written using Ruby and can be found at
47 * http://people.freebsd.org/~ariff/HDA/parser.rb . This crude
48 * ruby parser take the verbose dmesg dump as its input. Refer to
49 * http://www.microsoft.com/whdc/device/audio/default.mspx for various
50 * interesting documents, especially UAA (Universal Audio Architecture).
51 * 4) Possible vendor specific support.
52 * (snd_hda_intel, snd_hda_ati, etc..)
54 * Thanks to Ahmad Ubaidah Omar @ Defenxis Sdn. Bhd. for the
55 * Compaq V3000 with Conexant HDA.
57 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
59 * * This driver is a collaborative effort made by: *
61 * * Stephane E. Potvin <sepotvin@videotron.ca> *
62 * * Andrea Bittau <a.bittau@cs.ucl.ac.uk> *
63 * * Wesley Morgan <morganw@chemikals.org> *
64 * * Daniel Eischen <deischen@FreeBSD.org> *
65 * * Maxime Guillaud <bsd-ports@mguillaud.net> *
66 * * Ariff Abdullah <ariff@FreeBSD.org> *
68 * * ....and various people from freebsd-multimedia@FreeBSD.org *
70 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
73 #include <sys/ctype.h>
75 #include <dev/sound/pcm/sound.h>
76 #include <bus/pci/pcireg.h>
77 #include <bus/pci/pcivar.h>
79 #include <dev/sound/pci/hda/hdac_private.h>
80 #include <dev/sound/pci/hda/hdac_reg.h>
81 #include <dev/sound/pci/hda/hda_reg.h>
82 #include <dev/sound/pci/hda/hdac.h>
86 #define HDA_DRV_TEST_REV "20070619_0045"
87 #define HDA_WIDGET_PARSER_REV 1
89 SND_DECLARE_FILE("$DragonFly: src/sys/dev/sound/pci/hda/hdac.c,v 1.9 2007/07/22 18:53:19 dillon Exp $");
91 #define HDA_BOOTVERBOSE(stmt) do { \
92 if (bootverbose != 0) { \
98 #undef HDAC_INTR_EXTRA
99 #define HDAC_INTR_EXTRA 1
102 #define hdac_lock(sc) snd_mtxlock((sc)->lock)
103 #define hdac_unlock(sc) snd_mtxunlock((sc)->lock)
104 #define hdac_lockassert(sc) snd_mtxassert((sc)->lock)
105 #define hdac_lockowned(sc) (1)/* mtx_owned((sc)->lock) */
107 #if 0 /* TODO: No uncacheable DMA support in DragonFly. */
108 #include <machine/specialreg.h>
109 #define HDAC_DMA_ATTR(sc, v, s, attr) do { \
110 vm_offset_t va = (vm_offset_t)(v); \
111 vm_size_t sz = (vm_size_t)(s); \
112 if ((sc) != NULL && (sc)->nocache != 0 && va != 0 && sz != 0) \
113 (void)pmap_change_attr(va, sz, (attr)); \
116 #define HDAC_DMA_ATTR(...)
119 #define HDA_FLAG_MATCH(fl, v) (((fl) & (v)) == (v))
120 #define HDA_DEV_MATCH(fl, v) ((fl) == (v) || \
121 (fl) == 0xffffffff || \
122 (((fl) & 0xffff0000) == 0xffff0000 && \
123 ((fl) & 0x0000ffff) == ((v) & 0x0000ffff)) || \
124 (((fl) & 0x0000ffff) == 0x0000ffff && \
125 ((fl) & 0xffff0000) == ((v) & 0xffff0000)))
126 #define HDA_MATCH_ALL 0xffffffff
127 #define HDAC_INVALID 0xffffffff
129 /* Default controller / jack sense poll: 250ms */
130 #define HDAC_POLL_INTERVAL max(hz >> 2, 1)
132 #define HDA_MODEL_CONSTRUCT(vendor, model) \
133 (((uint32_t)(model) << 16) | ((vendor##_VENDORID) & 0xffff))
135 /* Controller models */
138 #define INTEL_VENDORID 0x8086
139 #define HDA_INTEL_82801F HDA_MODEL_CONSTRUCT(INTEL, 0x2668)
140 #define HDA_INTEL_82801G HDA_MODEL_CONSTRUCT(INTEL, 0x27d8)
141 #define HDA_INTEL_82801H HDA_MODEL_CONSTRUCT(INTEL, 0x284b)
142 #define HDA_INTEL_63XXESB HDA_MODEL_CONSTRUCT(INTEL, 0x269a)
143 #define HDA_INTEL_ALL HDA_MODEL_CONSTRUCT(INTEL, 0xffff)
146 #define NVIDIA_VENDORID 0x10de
147 #define HDA_NVIDIA_MCP51 HDA_MODEL_CONSTRUCT(NVIDIA, 0x026c)
148 #define HDA_NVIDIA_MCP55 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0371)
149 #define HDA_NVIDIA_MCP61A HDA_MODEL_CONSTRUCT(NVIDIA, 0x03e4)
150 #define HDA_NVIDIA_MCP61B HDA_MODEL_CONSTRUCT(NVIDIA, 0x03f0)
151 #define HDA_NVIDIA_MCP65A HDA_MODEL_CONSTRUCT(NVIDIA, 0x044a)
152 #define HDA_NVIDIA_MCP65B HDA_MODEL_CONSTRUCT(NVIDIA, 0x044b)
153 #define HDA_NVIDIA_ALL HDA_MODEL_CONSTRUCT(NVIDIA, 0xffff)
156 #define ATI_VENDORID 0x1002
157 #define HDA_ATI_SB450 HDA_MODEL_CONSTRUCT(ATI, 0x437b)
158 #define HDA_ATI_SB600 HDA_MODEL_CONSTRUCT(ATI, 0x4383)
159 #define HDA_ATI_ALL HDA_MODEL_CONSTRUCT(ATI, 0xffff)
162 #define VIA_VENDORID 0x1106
163 #define HDA_VIA_VT82XX HDA_MODEL_CONSTRUCT(VIA, 0x3288)
164 #define HDA_VIA_ALL HDA_MODEL_CONSTRUCT(VIA, 0xffff)
167 #define SIS_VENDORID 0x1039
168 #define HDA_SIS_966 HDA_MODEL_CONSTRUCT(SIS, 0x7502)
169 #define HDA_SIS_ALL HDA_MODEL_CONSTRUCT(SIS, 0xffff)
174 #define INTEL_D101GGC_SUBVENDOR HDA_MODEL_CONSTRUCT(INTEL, 0xd600)
177 #define HP_VENDORID 0x103c
178 #define HP_V3000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b5)
179 #define HP_NX7400_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a2)
180 #define HP_NX6310_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30aa)
181 #define HP_NX6325_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b0)
182 #define HP_XW4300_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3013)
183 #define HP_3010_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3010)
184 #define HP_DV5000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a5)
185 #define HP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0xffff)
186 /* What is wrong with XN 2563 anyway? (Got the picture ?) */
187 #define HP_NX6325_SUBVENDORX 0x103c30b0
190 #define DELL_VENDORID 0x1028
191 #define DELL_D820_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01cc)
192 #define DELL_I1300_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01c9)
193 #define DELL_XPSM1210_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01d7)
194 #define DELL_OPLX745_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01da)
195 #define DELL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0xffff)
198 #define CLEVO_VENDORID 0x1558
199 #define CLEVO_D900T_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0x0900)
200 #define CLEVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0xffff)
203 #define ACER_VENDORID 0x1025
204 #define ACER_A5050_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x010f)
205 #define ACER_3681WXM_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0110)
206 #define ACER_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0xffff)
209 #define ASUS_VENDORID 0x1043
210 #define ASUS_M5200_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1993)
211 #define ASUS_U5F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263)
212 #define ASUS_A8JC_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1153)
213 #define ASUS_P1AH2_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb)
214 #define ASUS_A7M_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1323)
215 #define ASUS_A7T_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x13c2)
216 #define ASUS_W6F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263)
217 #define ASUS_W2J_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1971)
218 #define ASUS_F3JC_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1338)
219 #define ASUS_M2V_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81e7)
220 #define ASUS_M2N_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x8234)
221 #define ASUS_M2NPVMX_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb)
222 #define ASUS_P5BWD_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81ec)
223 #define ASUS_VMCSM_SUBVENDOR HDA_MODEL_CONSTRUCT(NVIDIA, 0xcb84)
224 #define ASUS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0xffff)
227 #define IBM_VENDORID 0x1014
228 #define IBM_M52_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0x02f6)
229 #define IBM_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0xffff)
232 #define LENOVO_VENDORID 0x17aa
233 #define LENOVO_3KN100_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x2066)
234 #define LENOVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0xffff)
237 #define SAMSUNG_VENDORID 0x144d
238 #define SAMSUNG_Q1_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xc027)
239 #define SAMSUNG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xffff)
242 #define MEDION_VENDORID 0x161f
243 #define MEDION_MD95257_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0x203d)
244 #define MEDION_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0xffff)
247 * Apple Intel MacXXXX seems using Sigmatel codec/vendor id
248 * instead of their own, which is beyond my comprehension
249 * (see HDA_CODEC_STAC9221 below).
251 #define APPLE_INTEL_MAC 0x76808384
254 #define LG_VENDORID 0x1854
255 #define LG_LW20_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0x0018)
256 #define LG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0xffff)
258 /* Fujitsu Siemens */
259 #define FS_VENDORID 0x1734
260 #define FS_PA1510_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10b8)
261 #define FS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0xffff)
264 #define TOSHIBA_VENDORID 0x1179
265 #define TOSHIBA_U200_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0x0001)
266 #define TOSHIBA_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xffff)
268 /* Micro-Star International (MSI) */
269 #define MSI_VENDORID 0x1462
270 #define MSI_MS1034_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x0349)
271 #define MSI_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0xffff)
274 #define UNIWILL_VENDORID 0x1584
275 #define UNIWILL_9075_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9075)
276 #define UNIWILL_9080_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9080)
279 /* Misc constants.. */
280 #define HDA_AMP_MUTE_DEFAULT (0xffffffff)
281 #define HDA_AMP_MUTE_NONE (0)
282 #define HDA_AMP_MUTE_LEFT (1 << 0)
283 #define HDA_AMP_MUTE_RIGHT (1 << 1)
284 #define HDA_AMP_MUTE_ALL (HDA_AMP_MUTE_LEFT | HDA_AMP_MUTE_RIGHT)
286 #define HDA_AMP_LEFT_MUTED(v) ((v) & (HDA_AMP_MUTE_LEFT))
287 #define HDA_AMP_RIGHT_MUTED(v) (((v) & HDA_AMP_MUTE_RIGHT) >> 1)
289 #define HDA_DAC_PATH (1 << 0)
290 #define HDA_ADC_PATH (1 << 1)
291 #define HDA_ADC_RECSEL (1 << 2)
293 #define HDA_DAC_LOCKED (1 << 3)
294 #define HDA_ADC_LOCKED (1 << 4)
296 #define HDA_CTL_OUT (1 << 0)
297 #define HDA_CTL_IN (1 << 1)
298 #define HDA_CTL_BOTH (HDA_CTL_IN | HDA_CTL_OUT)
300 #define HDA_GPIO_MAX 8
301 /* 0 - 7 = GPIO , 8 = Flush */
302 #define HDA_QUIRK_GPIO0 (1 << 0)
303 #define HDA_QUIRK_GPIO1 (1 << 1)
304 #define HDA_QUIRK_GPIO2 (1 << 2)
305 #define HDA_QUIRK_GPIO3 (1 << 3)
306 #define HDA_QUIRK_GPIO4 (1 << 4)
307 #define HDA_QUIRK_GPIO5 (1 << 5)
308 #define HDA_QUIRK_GPIO6 (1 << 6)
309 #define HDA_QUIRK_GPIO7 (1 << 7)
310 #define HDA_QUIRK_GPIOFLUSH (1 << 8)
312 /* 9 - 25 = anything else */
313 #define HDA_QUIRK_SOFTPCMVOL (1 << 9)
314 #define HDA_QUIRK_FIXEDRATE (1 << 10)
315 #define HDA_QUIRK_FORCESTEREO (1 << 11)
316 #define HDA_QUIRK_EAPDINV (1 << 12)
317 #define HDA_QUIRK_DMAPOS (1 << 13)
319 /* 26 - 31 = vrefs */
320 #define HDA_QUIRK_IVREF50 (1 << 26)
321 #define HDA_QUIRK_IVREF80 (1 << 27)
322 #define HDA_QUIRK_IVREF100 (1 << 28)
323 #define HDA_QUIRK_OVREF50 (1 << 29)
324 #define HDA_QUIRK_OVREF80 (1 << 30)
325 #define HDA_QUIRK_OVREF100 (1 << 31)
327 #define HDA_QUIRK_IVREF (HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF80 | \
329 #define HDA_QUIRK_OVREF (HDA_QUIRK_OVREF50 | HDA_QUIRK_OVREF80 | \
331 #define HDA_QUIRK_VREF (HDA_QUIRK_IVREF | HDA_QUIRK_OVREF)
333 #define SOUND_MASK_SKIP (1 << 30)
334 #define SOUND_MASK_DISABLE (1 << 31)
336 static const struct {
339 } hdac_quirks_tab[] = {
340 { "gpio0", HDA_QUIRK_GPIO0 },
341 { "gpio1", HDA_QUIRK_GPIO1 },
342 { "gpio2", HDA_QUIRK_GPIO2 },
343 { "gpio3", HDA_QUIRK_GPIO3 },
344 { "gpio4", HDA_QUIRK_GPIO4 },
345 { "gpio5", HDA_QUIRK_GPIO5 },
346 { "gpio6", HDA_QUIRK_GPIO6 },
347 { "gpio7", HDA_QUIRK_GPIO7 },
348 { "gpioflush", HDA_QUIRK_GPIOFLUSH },
349 { "softpcmvol", HDA_QUIRK_SOFTPCMVOL },
350 { "fixedrate", HDA_QUIRK_FIXEDRATE },
351 { "forcestereo", HDA_QUIRK_FORCESTEREO },
352 { "eapdinv", HDA_QUIRK_EAPDINV },
353 { "dmapos", HDA_QUIRK_DMAPOS },
354 { "ivref50", HDA_QUIRK_IVREF50 },
355 { "ivref80", HDA_QUIRK_IVREF80 },
356 { "ivref100", HDA_QUIRK_IVREF100 },
357 { "ovref50", HDA_QUIRK_OVREF50 },
358 { "ovref80", HDA_QUIRK_OVREF80 },
359 { "ovref100", HDA_QUIRK_OVREF100 },
360 { "ivref", HDA_QUIRK_IVREF },
361 { "ovref", HDA_QUIRK_OVREF },
362 { "vref", HDA_QUIRK_VREF },
364 #define HDAC_QUIRKS_TAB_LEN \
365 (sizeof(hdac_quirks_tab) / sizeof(hdac_quirks_tab[0]))
367 #define HDA_BDL_MIN 2
368 #define HDA_BDL_MAX 256
369 #define HDA_BDL_DEFAULT HDA_BDL_MIN
371 #define HDA_BLK_MIN HDAC_DMA_ALIGNMENT
372 #define HDA_BLK_ALIGN (~(HDA_BLK_MIN - 1))
374 #define HDA_BUFSZ_MIN 4096
375 #define HDA_BUFSZ_MAX 65536
376 #define HDA_BUFSZ_DEFAULT 16384
378 #define HDA_PARSE_MAXDEPTH 10
380 #define HDAC_UNSOLTAG_EVENT_HP 0x00
381 #define HDAC_UNSOLTAG_EVENT_TEST 0x01
383 MALLOC_DEFINE(M_HDAC, "hdac", "High Definition Audio Controller");
391 static uint32_t hdac_fmt[] = {
392 AFMT_STEREO | AFMT_S16_LE,
396 static struct pcmchan_caps hdac_caps = {48000, 48000, hdac_fmt, 0};
398 static const struct {
402 { HDA_INTEL_82801F, "Intel 82801F" },
403 { HDA_INTEL_82801G, "Intel 82801G" },
404 { HDA_INTEL_82801H, "Intel 82801H" },
405 { HDA_INTEL_63XXESB, "Intel 631x/632xESB" },
406 { HDA_NVIDIA_MCP51, "NVidia MCP51" },
407 { HDA_NVIDIA_MCP55, "NVidia MCP55" },
408 { HDA_NVIDIA_MCP61A, "NVidia MCP61A" },
409 { HDA_NVIDIA_MCP61B, "NVidia MCP61B" },
410 { HDA_NVIDIA_MCP65A, "NVidia MCP65A" },
411 { HDA_NVIDIA_MCP65B, "NVidia MCP65B" },
412 { HDA_ATI_SB450, "ATI SB450" },
413 { HDA_ATI_SB600, "ATI SB600" },
414 { HDA_VIA_VT82XX, "VIA VT8251/8237A" },
415 { HDA_SIS_966, "SiS 966" },
417 { HDA_INTEL_ALL, "Intel (Unknown)" },
418 { HDA_NVIDIA_ALL, "NVidia (Unknown)" },
419 { HDA_ATI_ALL, "ATI (Unknown)" },
420 { HDA_VIA_ALL, "VIA (Unknown)" },
421 { HDA_SIS_ALL, "SiS (Unknown)" },
423 #define HDAC_DEVICES_LEN (sizeof(hdac_devices) / sizeof(hdac_devices[0]))
425 static const struct {
430 } hdac_pcie_snoop[] = {
431 { INTEL_VENDORID, 0x00, 0x00, 0x00 },
432 { ATI_VENDORID, 0x42, 0xf8, 0x02 },
433 { NVIDIA_VENDORID, 0x4e, 0xf0, 0x0f },
435 #define HDAC_PCIESNOOP_LEN \
436 (sizeof(hdac_pcie_snoop) / sizeof(hdac_pcie_snoop[0]))
438 static const struct {
445 { 8000, 1, 0x0000, 0x0000, 0x0500 }, /* (48000 * 1) / 6 */
446 { 9600, 0, 0x0000, 0x0000, 0x0400 }, /* (48000 * 1) / 5 */
447 { 12000, 0, 0x0000, 0x0000, 0x0300 }, /* (48000 * 1) / 4 */
448 { 16000, 1, 0x0000, 0x0000, 0x0200 }, /* (48000 * 1) / 3 */
449 { 18000, 0, 0x0000, 0x1000, 0x0700 }, /* (48000 * 3) / 8 */
450 { 19200, 0, 0x0000, 0x0800, 0x0400 }, /* (48000 * 2) / 5 */
451 { 24000, 0, 0x0000, 0x0000, 0x0100 }, /* (48000 * 1) / 2 */
452 { 28800, 0, 0x0000, 0x1000, 0x0400 }, /* (48000 * 3) / 5 */
453 { 32000, 1, 0x0000, 0x0800, 0x0200 }, /* (48000 * 2) / 3 */
454 { 36000, 0, 0x0000, 0x1000, 0x0300 }, /* (48000 * 3) / 4 */
455 { 38400, 0, 0x0000, 0x1800, 0x0400 }, /* (48000 * 4) / 5 */
456 { 48000, 1, 0x0000, 0x0000, 0x0000 }, /* (48000 * 1) / 1 */
457 { 64000, 0, 0x0000, 0x1800, 0x0200 }, /* (48000 * 4) / 3 */
458 { 72000, 0, 0x0000, 0x1000, 0x0100 }, /* (48000 * 3) / 2 */
459 { 96000, 1, 0x0000, 0x0800, 0x0000 }, /* (48000 * 2) / 1 */
460 { 144000, 0, 0x0000, 0x1000, 0x0000 }, /* (48000 * 3) / 1 */
461 { 192000, 1, 0x0000, 0x1800, 0x0000 }, /* (48000 * 4) / 1 */
462 { 8820, 0, 0x4000, 0x0000, 0x0400 }, /* (44100 * 1) / 5 */
463 { 11025, 1, 0x4000, 0x0000, 0x0300 }, /* (44100 * 1) / 4 */
464 { 12600, 0, 0x4000, 0x0800, 0x0600 }, /* (44100 * 2) / 7 */
465 { 14700, 0, 0x4000, 0x0000, 0x0200 }, /* (44100 * 1) / 3 */
466 { 17640, 0, 0x4000, 0x0800, 0x0400 }, /* (44100 * 2) / 5 */
467 { 18900, 0, 0x4000, 0x1000, 0x0600 }, /* (44100 * 3) / 7 */
468 { 22050, 1, 0x4000, 0x0000, 0x0100 }, /* (44100 * 1) / 2 */
469 { 25200, 0, 0x4000, 0x1800, 0x0600 }, /* (44100 * 4) / 7 */
470 { 26460, 0, 0x4000, 0x1000, 0x0400 }, /* (44100 * 3) / 5 */
471 { 29400, 0, 0x4000, 0x0800, 0x0200 }, /* (44100 * 2) / 3 */
472 { 33075, 0, 0x4000, 0x1000, 0x0300 }, /* (44100 * 3) / 4 */
473 { 35280, 0, 0x4000, 0x1800, 0x0400 }, /* (44100 * 4) / 5 */
474 { 44100, 1, 0x4000, 0x0000, 0x0000 }, /* (44100 * 1) / 1 */
475 { 58800, 0, 0x4000, 0x1800, 0x0200 }, /* (44100 * 4) / 3 */
476 { 66150, 0, 0x4000, 0x1000, 0x0100 }, /* (44100 * 3) / 2 */
477 { 88200, 1, 0x4000, 0x0800, 0x0000 }, /* (44100 * 2) / 1 */
478 { 132300, 0, 0x4000, 0x1000, 0x0000 }, /* (44100 * 3) / 1 */
479 { 176400, 1, 0x4000, 0x1800, 0x0000 }, /* (44100 * 4) / 1 */
481 #define HDA_RATE_TAB_LEN (sizeof(hda_rate_tab) / sizeof(hda_rate_tab[0]))
483 /* All codecs you can eat... */
484 #define HDA_CODEC_CONSTRUCT(vendor, id) \
485 (((uint32_t)(vendor##_VENDORID) << 16) | ((id) & 0xffff))
488 #define REALTEK_VENDORID 0x10ec
489 #define HDA_CODEC_ALC260 HDA_CODEC_CONSTRUCT(REALTEK, 0x0260)
490 #define HDA_CODEC_ALC262 HDA_CODEC_CONSTRUCT(REALTEK, 0x0262)
491 #define HDA_CODEC_ALC660 HDA_CODEC_CONSTRUCT(REALTEK, 0x0660)
492 #define HDA_CODEC_ALC861 HDA_CODEC_CONSTRUCT(REALTEK, 0x0861)
493 #define HDA_CODEC_ALC861VD HDA_CODEC_CONSTRUCT(REALTEK, 0x0862)
494 #define HDA_CODEC_ALC880 HDA_CODEC_CONSTRUCT(REALTEK, 0x0880)
495 #define HDA_CODEC_ALC882 HDA_CODEC_CONSTRUCT(REALTEK, 0x0882)
496 #define HDA_CODEC_ALC883 HDA_CODEC_CONSTRUCT(REALTEK, 0x0883)
497 #define HDA_CODEC_ALC885 HDA_CODEC_CONSTRUCT(REALTEK, 0x0885)
498 #define HDA_CODEC_ALC888 HDA_CODEC_CONSTRUCT(REALTEK, 0x0888)
499 #define HDA_CODEC_ALCXXXX HDA_CODEC_CONSTRUCT(REALTEK, 0xffff)
502 #define ANALOGDEVICES_VENDORID 0x11d4
503 #define HDA_CODEC_AD1981HD HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1981)
504 #define HDA_CODEC_AD1983 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1983)
505 #define HDA_CODEC_AD1986A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1986)
506 #define HDA_CODEC_AD1988 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1988)
507 #define HDA_CODEC_AD1988B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x198b)
508 #define HDA_CODEC_ADXXXX HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0xffff)
511 #define CMEDIA_VENDORID 0x434d
512 #define HDA_CODEC_CMI9880 HDA_CODEC_CONSTRUCT(CMEDIA, 0x4980)
513 #define HDA_CODEC_CMIXXXX HDA_CODEC_CONSTRUCT(CMEDIA, 0xffff)
516 #define SIGMATEL_VENDORID 0x8384
517 #define HDA_CODEC_STAC9221 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7680)
518 #define HDA_CODEC_STAC9221D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7683)
519 #define HDA_CODEC_STAC9220 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7690)
520 #define HDA_CODEC_STAC922XD HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7681)
521 #define HDA_CODEC_STAC9227 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7618)
522 #define HDA_CODEC_STAC9271D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7627)
523 #define HDA_CODEC_STACXXXX HDA_CODEC_CONSTRUCT(SIGMATEL, 0xffff)
528 * Ok, the truth is, I don't have any idea at all whether
529 * it is "Venice" or "Waikiki" or other unnamed CXyadayada. The only
530 * place that tell me it is "Venice" is from its Windows driver INF.
533 * Waikiki - CX20551-22
535 #define CONEXANT_VENDORID 0x14f1
536 #define HDA_CODEC_CXVENICE HDA_CODEC_CONSTRUCT(CONEXANT, 0x5045)
537 #define HDA_CODEC_CXWAIKIKI HDA_CODEC_CONSTRUCT(CONEXANT, 0x5047)
538 #define HDA_CODEC_CXXXXX HDA_CODEC_CONSTRUCT(CONEXANT, 0xffff)
541 #define HDA_CODEC_VT1708_8 HDA_CODEC_CONSTRUCT(VIA, 0x1708)
542 #define HDA_CODEC_VT1708_9 HDA_CODEC_CONSTRUCT(VIA, 0x1709)
543 #define HDA_CODEC_VT1708_A HDA_CODEC_CONSTRUCT(VIA, 0x170a)
544 #define HDA_CODEC_VT1708_B HDA_CODEC_CONSTRUCT(VIA, 0x170b)
545 #define HDA_CODEC_VT1709_0 HDA_CODEC_CONSTRUCT(VIA, 0xe710)
546 #define HDA_CODEC_VT1709_1 HDA_CODEC_CONSTRUCT(VIA, 0xe711)
547 #define HDA_CODEC_VT1709_2 HDA_CODEC_CONSTRUCT(VIA, 0xe712)
548 #define HDA_CODEC_VT1709_3 HDA_CODEC_CONSTRUCT(VIA, 0xe713)
549 #define HDA_CODEC_VT1709_4 HDA_CODEC_CONSTRUCT(VIA, 0xe714)
550 #define HDA_CODEC_VT1709_5 HDA_CODEC_CONSTRUCT(VIA, 0xe715)
551 #define HDA_CODEC_VT1709_6 HDA_CODEC_CONSTRUCT(VIA, 0xe716)
552 #define HDA_CODEC_VT1709_7 HDA_CODEC_CONSTRUCT(VIA, 0xe717)
553 #define HDA_CODEC_VTXXXX HDA_CODEC_CONSTRUCT(VIA, 0xffff)
557 static const struct {
561 { HDA_CODEC_ALC260, "Realtek ALC260" },
562 { HDA_CODEC_ALC262, "Realtek ALC262" },
563 { HDA_CODEC_ALC660, "Realtek ALC660" },
564 { HDA_CODEC_ALC861, "Realtek ALC861" },
565 { HDA_CODEC_ALC861VD, "Realtek ALC861-VD" },
566 { HDA_CODEC_ALC880, "Realtek ALC880" },
567 { HDA_CODEC_ALC882, "Realtek ALC882" },
568 { HDA_CODEC_ALC883, "Realtek ALC883" },
569 { HDA_CODEC_ALC885, "Realtek ALC885" },
570 { HDA_CODEC_ALC888, "Realtek ALC888" },
571 { HDA_CODEC_AD1981HD, "Analog Devices AD1981HD" },
572 { HDA_CODEC_AD1983, "Analog Devices AD1983" },
573 { HDA_CODEC_AD1986A, "Analog Devices AD1986A" },
574 { HDA_CODEC_AD1988, "Analog Devices AD1988" },
575 { HDA_CODEC_AD1988B, "Analog Devices AD1988B" },
576 { HDA_CODEC_CMI9880, "CMedia CMI9880" },
577 { HDA_CODEC_STAC9221, "Sigmatel STAC9221" },
578 { HDA_CODEC_STAC9221D, "Sigmatel STAC9221D" },
579 { HDA_CODEC_STAC9220, "Sigmatel STAC9220" },
580 { HDA_CODEC_STAC922XD, "Sigmatel STAC9220D/9223D" },
581 { HDA_CODEC_STAC9227, "Sigmatel STAC9227" },
582 { HDA_CODEC_STAC9271D, "Sigmatel STAC9271D" },
583 { HDA_CODEC_CXVENICE, "Conexant Venice" },
584 { HDA_CODEC_CXWAIKIKI, "Conexant Waikiki" },
585 { HDA_CODEC_VT1708_8, "VIA VT1708_8" },
586 { HDA_CODEC_VT1708_9, "VIA VT1708_9" },
587 { HDA_CODEC_VT1708_A, "VIA VT1708_A" },
588 { HDA_CODEC_VT1708_B, "VIA VT1708_B" },
589 { HDA_CODEC_VT1709_0, "VIA VT1709_0" },
590 { HDA_CODEC_VT1709_1, "VIA VT1709_1" },
591 { HDA_CODEC_VT1709_2, "VIA VT1709_2" },
592 { HDA_CODEC_VT1709_3, "VIA VT1709_3" },
593 { HDA_CODEC_VT1709_4, "VIA VT1709_4" },
594 { HDA_CODEC_VT1709_5, "VIA VT1709_5" },
595 { HDA_CODEC_VT1709_6, "VIA VT1709_6" },
596 { HDA_CODEC_VT1709_7, "VIA VT1709_7" },
598 { HDA_CODEC_ALCXXXX, "Realtek (Unknown)" },
599 { HDA_CODEC_ADXXXX, "Analog Devices (Unknown)" },
600 { HDA_CODEC_CMIXXXX, "CMedia (Unknown)" },
601 { HDA_CODEC_STACXXXX, "Sigmatel (Unknown)" },
602 { HDA_CODEC_CXXXXX, "Conexant (Unknown)" },
603 { HDA_CODEC_VTXXXX, "VIA (Unknown)" },
605 #define HDAC_CODECS_LEN (sizeof(hdac_codecs) / sizeof(hdac_codecs[0]))
613 static const struct {
623 } hdac_hp_switch[] = {
624 /* Specific OEM models */
625 { HP_V3000_SUBVENDOR, HDA_CODEC_CXVENICE, HDAC_HP_SWITCH_CTL,
626 0, 0, -1, 17, { 16, -1 }, 16 },
627 /* { HP_XW4300_SUBVENDOR, HDA_CODEC_ALC260, HDAC_HP_SWITCH_CTL,
628 0, 0, -1, 21, { 16, 17, -1 }, -1 } */
629 /*{ HP_3010_SUBVENDOR, HDA_CODEC_ALC260, HDAC_HP_SWITCH_DEBUG,
630 0, 1, 0, 16, { 15, 18, 19, 20, 21, -1 }, -1 },*/
631 { HP_NX7400_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL,
632 0, 0, -1, 6, { 5, -1 }, 5 },
633 { HP_NX6310_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL,
634 0, 0, -1, 6, { 5, -1 }, 5 },
635 { HP_NX6325_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL,
636 0, 0, -1, 6, { 5, -1 }, 5 },
637 { TOSHIBA_U200_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL,
638 0, 0, -1, 6, { 5, -1 }, -1 },
639 { DELL_D820_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL,
640 0, 0, -1, 13, { 14, -1 }, -1 },
641 { DELL_I1300_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL,
642 0, 0, -1, 13, { 14, -1 }, -1 },
643 { DELL_OPLX745_SUBVENDOR, HDA_CODEC_AD1983, HDAC_HP_SWITCH_CTL,
644 0, 0, -1, 6, { 5, 7, -1 }, -1 },
645 { APPLE_INTEL_MAC, HDA_CODEC_STAC9221, HDAC_HP_SWITCH_CTRL,
646 0, 0, -1, 10, { 13, -1 }, -1 },
647 { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A, HDAC_HP_SWITCH_CTL,
648 1, 0, -1, 26, { 27, -1 }, -1 },
649 { LG_LW20_SUBVENDOR, HDA_CODEC_ALC880, HDAC_HP_SWITCH_CTL,
650 0, 0, -1, 27, { 20, -1 }, -1 },
651 { ACER_A5050_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL,
652 0, 0, -1, 20, { 21, -1 }, -1 },
653 { ACER_3681WXM_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL,
654 0, 0, -1, 20, { 21, -1 }, -1 },
655 { UNIWILL_9080_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL,
656 0, 0, -1, 20, { 21, -1 }, -1 },
657 { MSI_MS1034_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL,
658 0, 0, -1, 20, { 27, -1 }, -1 },
660 * All models that at least come from the same vendor with
663 { HP_ALL_SUBVENDOR, HDA_CODEC_CXVENICE, HDAC_HP_SWITCH_CTL,
664 0, 0, -1, 17, { 16, -1 }, 16 },
665 { HP_ALL_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL,
666 0, 0, -1, 6, { 5, -1 }, 5 },
667 { TOSHIBA_ALL_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL,
668 0, 0, -1, 6, { 5, -1 }, -1 },
669 { DELL_ALL_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL,
670 0, 0, -1, 13, { 14, -1 }, -1 },
671 { LENOVO_ALL_SUBVENDOR, HDA_CODEC_AD1986A, HDAC_HP_SWITCH_CTL,
672 1, 0, -1, 26, { 27, -1 }, -1 },
674 { ACER_ALL_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL,
675 0, 0, -1, 20, { 21, -1 }, -1 },
678 #define HDAC_HP_SWITCH_LEN \
679 (sizeof(hdac_hp_switch) / sizeof(hdac_hp_switch[0]))
681 static const struct {
686 } hdac_eapd_switch[] = {
687 { HP_V3000_SUBVENDOR, HDA_CODEC_CXVENICE, 16, 1 },
688 { HP_NX7400_SUBVENDOR, HDA_CODEC_AD1981HD, 5, 1 },
689 { HP_NX6310_SUBVENDOR, HDA_CODEC_AD1981HD, 5, 1 },
691 #define HDAC_EAPD_SWITCH_LEN \
692 (sizeof(hdac_eapd_switch) / sizeof(hdac_eapd_switch[0]))
694 /****************************************************************************
695 * Function prototypes
696 ****************************************************************************/
697 static void hdac_intr_handler(void *);
698 static int hdac_reset(struct hdac_softc *);
699 static int hdac_get_capabilities(struct hdac_softc *);
700 static void hdac_dma_cb(void *, bus_dma_segment_t *, int, int);
701 static int hdac_dma_alloc(struct hdac_softc *,
702 struct hdac_dma *, bus_size_t);
703 static void hdac_dma_free(struct hdac_softc *, struct hdac_dma *);
704 static int hdac_mem_alloc(struct hdac_softc *);
705 static void hdac_mem_free(struct hdac_softc *);
706 static int hdac_irq_alloc(struct hdac_softc *);
707 static void hdac_irq_free(struct hdac_softc *);
708 static void hdac_corb_init(struct hdac_softc *);
709 static void hdac_rirb_init(struct hdac_softc *);
710 static void hdac_corb_start(struct hdac_softc *);
711 static void hdac_rirb_start(struct hdac_softc *);
712 static void hdac_scan_codecs(struct hdac_softc *);
713 static int hdac_probe_codec(struct hdac_codec *);
714 static struct hdac_devinfo *hdac_probe_function(struct hdac_codec *, nid_t);
715 static void hdac_add_child(struct hdac_softc *, struct hdac_devinfo *);
717 static void hdac_attach2(void *);
719 static uint32_t hdac_command_sendone_internal(struct hdac_softc *,
721 static void hdac_command_send_internal(struct hdac_softc *,
722 struct hdac_command_list *, int);
724 static int hdac_probe(device_t);
725 static int hdac_attach(device_t);
726 static int hdac_detach(device_t);
727 static void hdac_widget_connection_select(struct hdac_widget *, uint8_t);
728 static void hdac_audio_ctl_amp_set(struct hdac_audio_ctl *,
730 static struct hdac_audio_ctl *hdac_audio_ctl_amp_get(struct hdac_devinfo *,
732 static void hdac_audio_ctl_amp_set_internal(struct hdac_softc *,
733 nid_t, nid_t, int, int, int, int, int, int);
734 static int hdac_audio_ctl_ossmixer_getnextdev(struct hdac_devinfo *);
735 static struct hdac_widget *hdac_widget_get(struct hdac_devinfo *, nid_t);
737 static int hdac_rirb_flush(struct hdac_softc *sc);
738 static int hdac_unsolq_flush(struct hdac_softc *sc);
740 #define hdac_command(a1, a2, a3) \
741 hdac_command_sendone_internal(a1, a2, a3)
743 #define hdac_codec_id(d) \
744 ((uint32_t)((d == NULL) ? 0x00000000 : \
745 ((((uint32_t)(d)->vendor_id & 0x0000ffff) << 16) | \
746 ((uint32_t)(d)->device_id & 0x0000ffff))))
749 hdac_codec_name(struct hdac_devinfo *devinfo)
754 id = hdac_codec_id(devinfo);
756 for (i = 0; i < HDAC_CODECS_LEN; i++) {
757 if (HDA_DEV_MATCH(hdac_codecs[i].id, id))
758 return (hdac_codecs[i].name);
761 return ((id == 0x00000000) ? "NULL Codec" : "Unknown Codec");
765 hdac_audio_ctl_ossmixer_mask2name(uint32_t devmask)
767 static char *ossname[] = SOUND_DEVICE_NAMES;
768 static char *unknown = "???";
771 for (i = SOUND_MIXER_NRDEVICES - 1; i >= 0; i--) {
772 if (devmask & (1 << i))
779 hdac_audio_ctl_ossmixer_mask2allname(uint32_t mask, char *buf, size_t len)
781 static char *ossname[] = SOUND_DEVICE_NAMES;
785 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) {
786 if (mask & (1 << i)) {
788 strlcat(buf, ", ", len);
789 strlcat(buf, ossname[i], len);
795 static struct hdac_audio_ctl *
796 hdac_audio_ctl_each(struct hdac_devinfo *devinfo, int *index)
798 if (devinfo == NULL ||
799 devinfo->node_type != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO ||
800 index == NULL || devinfo->function.audio.ctl == NULL ||
801 devinfo->function.audio.ctlcnt < 1 ||
802 *index < 0 || *index >= devinfo->function.audio.ctlcnt)
804 return (&devinfo->function.audio.ctl[(*index)++]);
807 static struct hdac_audio_ctl *
808 hdac_audio_ctl_amp_get(struct hdac_devinfo *devinfo, nid_t nid,
811 struct hdac_audio_ctl *ctl, *retctl = NULL;
812 int i, at, atindex, found = 0;
814 if (devinfo == NULL || devinfo->function.audio.ctl == NULL)
827 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
828 if (ctl->enable == 0 || ctl->widget == NULL)
830 if (!(ctl->widget->nid == nid && (atindex == -1 ||
831 ctl->index == atindex)))
839 return ((at == -1) ? retctl : NULL);
843 hdac_hp_switch_handler(struct hdac_devinfo *devinfo)
845 struct hdac_softc *sc;
846 struct hdac_widget *w;
847 struct hdac_audio_ctl *ctl;
848 uint32_t val, id, res;
849 int i = 0, j, forcemute;
852 if (devinfo == NULL || devinfo->codec == NULL ||
853 devinfo->codec->sc == NULL)
856 sc = devinfo->codec->sc;
857 cad = devinfo->codec->cad;
858 id = hdac_codec_id(devinfo);
859 for (i = 0; i < HDAC_HP_SWITCH_LEN; i++) {
860 if (HDA_DEV_MATCH(hdac_hp_switch[i].model,
861 sc->pci_subvendor) &&
862 hdac_hp_switch[i].id == id)
866 if (i >= HDAC_HP_SWITCH_LEN)
870 if (hdac_hp_switch[i].eapdnid != -1) {
871 w = hdac_widget_get(devinfo, hdac_hp_switch[i].eapdnid);
872 if (w != NULL && w->param.eapdbtl != HDAC_INVALID)
873 forcemute = (w->param.eapdbtl &
874 HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD) ? 0 : 1;
877 if (hdac_hp_switch[i].execsense != -1)
879 HDA_CMD_SET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid,
880 hdac_hp_switch[i].execsense), cad);
881 res = hdac_command(sc,
882 HDA_CMD_GET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid), cad);
884 device_printf(sc->dev,
885 "HDA_DEBUG: Pin sense: nid=%d res=0x%08x\n",
886 hdac_hp_switch[i].hpnid, res);
888 res = HDA_CMD_GET_PIN_SENSE_PRESENCE_DETECT(res);
889 res ^= hdac_hp_switch[i].inverted;
891 switch (hdac_hp_switch[i].type) {
892 case HDAC_HP_SWITCH_CTL:
893 ctl = hdac_audio_ctl_amp_get(devinfo,
894 hdac_hp_switch[i].hpnid, 0, 1);
896 val = (res != 0 && forcemute == 0) ?
897 HDA_AMP_MUTE_NONE : HDA_AMP_MUTE_ALL;
898 if (val != ctl->muted) {
900 hdac_audio_ctl_amp_set(ctl,
901 HDA_AMP_MUTE_DEFAULT, ctl->left,
905 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) {
906 ctl = hdac_audio_ctl_amp_get(devinfo,
907 hdac_hp_switch[i].spkrnid[j], 0, 1);
910 val = (res != 0 || forcemute == 1) ?
911 HDA_AMP_MUTE_ALL : HDA_AMP_MUTE_NONE;
912 if (val == ctl->muted)
915 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_DEFAULT,
916 ctl->left, ctl->right);
919 case HDAC_HP_SWITCH_CTRL:
922 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid);
923 if (w != NULL && w->type ==
924 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) {
926 val = w->wclass.pin.ctrl |
927 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE;
929 val = w->wclass.pin.ctrl &
930 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE;
931 if (val != w->wclass.pin.ctrl) {
932 w->wclass.pin.ctrl = val;
934 HDA_CMD_SET_PIN_WIDGET_CTRL(cad,
935 w->nid, w->wclass.pin.ctrl), cad);
938 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) {
939 w = hdac_widget_get(devinfo,
940 hdac_hp_switch[i].spkrnid[j]);
941 if (w == NULL || w->type !=
942 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
944 val = w->wclass.pin.ctrl &
945 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE;
946 if (val == w->wclass.pin.ctrl)
948 w->wclass.pin.ctrl = val;
949 hdac_command(sc, HDA_CMD_SET_PIN_WIDGET_CTRL(
950 cad, w->nid, w->wclass.pin.ctrl), cad);
954 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid);
955 if (w != NULL && w->type ==
956 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) {
957 val = w->wclass.pin.ctrl &
958 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE;
959 if (val != w->wclass.pin.ctrl) {
960 w->wclass.pin.ctrl = val;
962 HDA_CMD_SET_PIN_WIDGET_CTRL(cad,
963 w->nid, w->wclass.pin.ctrl), cad);
966 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) {
967 w = hdac_widget_get(devinfo,
968 hdac_hp_switch[i].spkrnid[j]);
969 if (w == NULL || w->type !=
970 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
973 val = w->wclass.pin.ctrl |
974 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE;
976 val = w->wclass.pin.ctrl &
977 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE;
978 if (val == w->wclass.pin.ctrl)
980 w->wclass.pin.ctrl = val;
981 hdac_command(sc, HDA_CMD_SET_PIN_WIDGET_CTRL(
982 cad, w->nid, w->wclass.pin.ctrl), cad);
986 case HDAC_HP_SWITCH_DEBUG:
987 if (hdac_hp_switch[i].execsense != -1)
989 HDA_CMD_SET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid,
990 hdac_hp_switch[i].execsense), cad);
991 res = hdac_command(sc,
992 HDA_CMD_GET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid), cad);
993 device_printf(sc->dev,
994 "[ 0] HDA_DEBUG: Pin sense: nid=%d res=0x%08x\n",
995 hdac_hp_switch[i].hpnid, res);
996 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) {
997 w = hdac_widget_get(devinfo,
998 hdac_hp_switch[i].spkrnid[j]);
999 if (w == NULL || w->type !=
1000 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
1002 if (hdac_hp_switch[i].execsense != -1)
1004 HDA_CMD_SET_PIN_SENSE(cad, w->nid,
1005 hdac_hp_switch[i].execsense), cad);
1006 res = hdac_command(sc,
1007 HDA_CMD_GET_PIN_SENSE(cad, w->nid), cad);
1008 device_printf(sc->dev,
1009 "[%2d] HDA_DEBUG: Pin sense: nid=%d res=0x%08x\n",
1010 j + 1, w->nid, res);
1019 hdac_unsolicited_handler(struct hdac_codec *codec, uint32_t tag)
1021 struct hdac_softc *sc;
1022 struct hdac_devinfo *devinfo = NULL;
1023 device_t *devlist = NULL;
1026 if (codec == NULL || codec->sc == NULL)
1032 device_printf(sc->dev, "HDA_DEBUG: Unsol Tag: 0x%08x\n", tag);
1035 device_get_children(sc->dev, &devlist, &devcount);
1036 for (i = 0; devlist != NULL && i < devcount; i++) {
1037 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]);
1038 if (devinfo != NULL && devinfo->node_type ==
1039 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO &&
1040 devinfo->codec != NULL &&
1041 devinfo->codec->cad == codec->cad) {
1046 if (devlist != NULL)
1047 kfree(devlist, M_TEMP);
1049 if (devinfo == NULL)
1053 case HDAC_UNSOLTAG_EVENT_HP:
1054 hdac_hp_switch_handler(devinfo);
1056 case HDAC_UNSOLTAG_EVENT_TEST:
1057 device_printf(sc->dev, "Unsol Test!\n");
1065 hdac_stream_intr(struct hdac_softc *sc, struct hdac_chan *ch)
1067 /* XXX to be removed */
1068 #ifdef HDAC_INTR_EXTRA
1072 if (ch->blkcnt == 0)
1075 /* XXX to be removed */
1076 #ifdef HDAC_INTR_EXTRA
1077 res = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDSTS);
1080 /* XXX to be removed */
1081 #ifdef HDAC_INTR_EXTRA
1083 if (res & (HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE))
1084 device_printf(sc->dev,
1085 "PCMDIR_%s intr triggered beyond stream boundary:"
1087 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", res);
1091 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDSTS,
1092 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS );
1094 /* XXX to be removed */
1095 #ifdef HDAC_INTR_EXTRA
1096 if (res & HDAC_SDSTS_BCIS) {
1099 /* XXX to be removed */
1100 #ifdef HDAC_INTR_EXTRA
1107 /****************************************************************************
1108 * void hdac_intr_handler(void *)
1110 * Interrupt handler. Processes interrupts received from the hdac.
1111 ****************************************************************************/
1113 hdac_intr_handler(void *context)
1115 struct hdac_softc *sc;
1118 struct hdac_rirb *rirb_base;
1119 uint32_t trigger = 0;
1121 sc = (struct hdac_softc *)context;
1124 if (sc->polling != 0) {
1128 /* Do we have anything to do? */
1129 intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS);
1130 if (!HDA_FLAG_MATCH(intsts, HDAC_INTSTS_GIS)) {
1135 /* Was this a controller interrupt? */
1136 if (HDA_FLAG_MATCH(intsts, HDAC_INTSTS_CIS)) {
1137 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr;
1138 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS);
1139 /* Get as many responses that we can */
1140 while (HDA_FLAG_MATCH(rirbsts, HDAC_RIRBSTS_RINTFL)) {
1141 HDAC_WRITE_1(&sc->mem,
1142 HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL);
1143 hdac_rirb_flush(sc);
1144 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS);
1146 /* XXX to be removed */
1147 /* Clear interrupt and exit */
1148 #ifdef HDAC_INTR_EXTRA
1149 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, HDAC_INTSTS_CIS);
1153 hdac_unsolq_flush(sc);
1155 if (intsts & HDAC_INTSTS_SIS_MASK) {
1156 if ((intsts & (1 << sc->num_iss)) &&
1157 hdac_stream_intr(sc, &sc->play) != 0)
1159 if ((intsts & (1 << 0)) &&
1160 hdac_stream_intr(sc, &sc->rec) != 0)
1162 /* XXX to be removed */
1163 #ifdef HDAC_INTR_EXTRA
1164 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, intsts &
1165 HDAC_INTSTS_SIS_MASK);
1172 chn_intr(sc->play.c);
1174 chn_intr(sc->rec.c);
1177 /****************************************************************************
1178 * int hdac_reset(hdac_softc *)
1180 * Reset the hdac to a quiescent and known state.
1181 ****************************************************************************/
1183 hdac_reset(struct hdac_softc *sc)
1189 * Stop all Streams DMA engine
1191 for (i = 0; i < sc->num_iss; i++)
1192 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0);
1193 for (i = 0; i < sc->num_oss; i++)
1194 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0);
1195 for (i = 0; i < sc->num_bss; i++)
1196 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0);
1199 * Stop Control DMA engines.
1201 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0);
1202 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0);
1205 * Reset DMA position buffer.
1207 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 0x0);
1208 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, 0x0);
1211 * Reset the controller. The reset must remain asserted for
1212 * a minimum of 100us.
1214 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL);
1215 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST);
1218 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL);
1219 if (!(gctl & HDAC_GCTL_CRST))
1223 if (gctl & HDAC_GCTL_CRST) {
1224 device_printf(sc->dev, "Unable to put hdac in reset\n");
1228 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL);
1229 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST);
1232 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL);
1233 if (gctl & HDAC_GCTL_CRST)
1237 if (!(gctl & HDAC_GCTL_CRST)) {
1238 device_printf(sc->dev, "Device stuck in reset\n");
1243 * Wait for codecs to finish their own reset sequence. The delay here
1244 * should be of 250us but for some reasons, on it's not enough on my
1245 * computer. Let's use twice as much as necessary to make sure that
1246 * it's reset properly.
1254 /****************************************************************************
1255 * int hdac_get_capabilities(struct hdac_softc *);
1257 * Retreive the general capabilities of the hdac;
1258 * Number of Input Streams
1259 * Number of Output Streams
1260 * Number of bidirectional Streams
1262 * CORB and RIRB sizes
1263 ****************************************************************************/
1265 hdac_get_capabilities(struct hdac_softc *sc)
1268 uint8_t corbsize, rirbsize;
1270 gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP);
1271 sc->num_iss = HDAC_GCAP_ISS(gcap);
1272 sc->num_oss = HDAC_GCAP_OSS(gcap);
1273 sc->num_bss = HDAC_GCAP_BSS(gcap);
1275 sc->support_64bit = HDA_FLAG_MATCH(gcap, HDAC_GCAP_64OK);
1277 corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE);
1278 if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_256) ==
1279 HDAC_CORBSIZE_CORBSZCAP_256)
1280 sc->corb_size = 256;
1281 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_16) ==
1282 HDAC_CORBSIZE_CORBSZCAP_16)
1284 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_2) ==
1285 HDAC_CORBSIZE_CORBSZCAP_2)
1288 device_printf(sc->dev, "%s: Invalid corb size (%x)\n",
1289 __func__, corbsize);
1293 rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE);
1294 if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_256) ==
1295 HDAC_RIRBSIZE_RIRBSZCAP_256)
1296 sc->rirb_size = 256;
1297 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_16) ==
1298 HDAC_RIRBSIZE_RIRBSZCAP_16)
1300 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_2) ==
1301 HDAC_RIRBSIZE_RIRBSZCAP_2)
1304 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n",
1305 __func__, rirbsize);
1313 /****************************************************************************
1316 * This function is called by bus_dmamap_load when the mapping has been
1317 * established. We just record the physical address of the mapping into
1318 * the struct hdac_dma passed in.
1319 ****************************************************************************/
1321 hdac_dma_cb(void *callback_arg, bus_dma_segment_t *segs, int nseg, int error)
1323 struct hdac_dma *dma;
1326 dma = (struct hdac_dma *)callback_arg;
1327 dma->dma_paddr = segs[0].ds_addr;
1332 /****************************************************************************
1333 * int hdac_dma_alloc
1335 * This function allocate and setup a dma region (struct hdac_dma).
1336 * It must be freed by a corresponding hdac_dma_free.
1337 ****************************************************************************/
1339 hdac_dma_alloc(struct hdac_softc *sc, struct hdac_dma *dma, bus_size_t size)
1345 roundsz = roundup2(size, HDAC_DMA_ALIGNMENT);
1346 lowaddr = (sc->support_64bit) ? BUS_SPACE_MAXADDR :
1347 BUS_SPACE_MAXADDR_32BIT;
1348 bzero(dma, sizeof(*dma));
1353 result = bus_dma_tag_create(NULL, /* parent */
1354 HDAC_DMA_ALIGNMENT, /* alignment */
1356 lowaddr, /* lowaddr */
1357 BUS_SPACE_MAXADDR, /* highaddr */
1358 NULL, /* filtfunc */
1359 NULL, /* fistfuncarg */
1360 roundsz, /* maxsize */
1362 roundsz, /* maxsegsz */
1364 &dma->dma_tag); /* dmat */
1366 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n",
1368 goto hdac_dma_alloc_fail;
1372 * Allocate DMA memory
1374 #if 0 /* TODO: No uncacheable DMA support in DragonFly. */
1375 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr,
1376 BUS_DMA_NOWAIT | BUS_DMA_ZERO |
1377 ((sc->nocache != 0) ? BUS_DMA_NOCACHE : 0), &dma->dma_map);
1379 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr,
1380 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &dma->dma_map);
1383 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%x)\n",
1385 goto hdac_dma_alloc_fail;
1388 dma->dma_size = roundsz;
1393 result = bus_dmamap_load(dma->dma_tag, dma->dma_map,
1394 (void *)dma->dma_vaddr, roundsz, hdac_dma_cb, (void *)dma, 0);
1395 if (result != 0 || dma->dma_paddr == 0) {
1398 device_printf(sc->dev, "%s: bus_dmamem_load failed (%x)\n",
1400 goto hdac_dma_alloc_fail;
1404 device_printf(sc->dev, "%s: size=%ju -> roundsz=%ju\n",
1405 __func__, (uintmax_t)size, (uintmax_t)roundsz);
1410 hdac_dma_alloc_fail:
1411 hdac_dma_free(sc, dma);
1417 /****************************************************************************
1418 * void hdac_dma_free(struct hdac_softc *, struct hdac_dma *)
1420 * Free a struct dhac_dma that has been previously allocated via the
1421 * hdac_dma_alloc function.
1422 ****************************************************************************/
1424 hdac_dma_free(struct hdac_softc *sc, struct hdac_dma *dma)
1426 if (dma->dma_map != NULL) {
1429 bus_dmamap_sync(dma->dma_tag, dma->dma_map,
1430 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1432 bus_dmamap_unload(dma->dma_tag, dma->dma_map);
1434 if (dma->dma_vaddr != NULL) {
1435 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map);
1436 dma->dma_vaddr = NULL;
1438 dma->dma_map = NULL;
1439 if (dma->dma_tag != NULL) {
1440 bus_dma_tag_destroy(dma->dma_tag);
1441 dma->dma_tag = NULL;
1446 /****************************************************************************
1447 * int hdac_mem_alloc(struct hdac_softc *)
1449 * Allocate all the bus resources necessary to speak with the physical
1451 ****************************************************************************/
1453 hdac_mem_alloc(struct hdac_softc *sc)
1455 struct hdac_mem *mem;
1458 mem->mem_rid = PCIR_BAR(0);
1459 mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
1460 &mem->mem_rid, RF_ACTIVE);
1461 if (mem->mem_res == NULL) {
1462 device_printf(sc->dev,
1463 "%s: Unable to allocate memory resource\n", __func__);
1466 mem->mem_tag = rman_get_bustag(mem->mem_res);
1467 mem->mem_handle = rman_get_bushandle(mem->mem_res);
1472 /****************************************************************************
1473 * void hdac_mem_free(struct hdac_softc *)
1475 * Free up resources previously allocated by hdac_mem_alloc.
1476 ****************************************************************************/
1478 hdac_mem_free(struct hdac_softc *sc)
1480 struct hdac_mem *mem;
1483 if (mem->mem_res != NULL)
1484 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid,
1486 mem->mem_res = NULL;
1489 /****************************************************************************
1490 * int hdac_irq_alloc(struct hdac_softc *)
1492 * Allocate and setup the resources necessary for interrupt handling.
1493 ****************************************************************************/
1495 hdac_irq_alloc(struct hdac_softc *sc)
1497 struct hdac_irq *irq;
1502 irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ,
1503 &irq->irq_rid, RF_SHAREABLE | RF_ACTIVE);
1504 if (irq->irq_res == NULL) {
1505 device_printf(sc->dev, "%s: Unable to allocate irq\n",
1507 goto hdac_irq_alloc_fail;
1509 result = snd_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE,
1510 hdac_intr_handler, sc, &irq->irq_handle);
1512 device_printf(sc->dev,
1513 "%s: Unable to setup interrupt handler (%x)\n",
1515 goto hdac_irq_alloc_fail;
1520 hdac_irq_alloc_fail:
1526 /****************************************************************************
1527 * void hdac_irq_free(struct hdac_softc *)
1529 * Free up resources previously allocated by hdac_irq_alloc.
1530 ****************************************************************************/
1532 hdac_irq_free(struct hdac_softc *sc)
1534 struct hdac_irq *irq;
1537 if (irq->irq_res != NULL && irq->irq_handle != NULL)
1538 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle);
1539 if (irq->irq_res != NULL)
1540 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid,
1542 irq->irq_handle = NULL;
1543 irq->irq_res = NULL;
1546 /****************************************************************************
1547 * void hdac_corb_init(struct hdac_softc *)
1549 * Initialize the corb registers for operations but do not start it up yet.
1550 * The CORB engine must not be running when this function is called.
1551 ****************************************************************************/
1553 hdac_corb_init(struct hdac_softc *sc)
1558 /* Setup the CORB size. */
1559 switch (sc->corb_size) {
1561 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256);
1564 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_16);
1567 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_2);
1570 panic("%s: Invalid CORB size (%x)\n", __func__, sc->corb_size);
1572 HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize);
1574 /* Setup the CORB Address in the hdac */
1575 corbpaddr = (uint64_t)sc->corb_dma.dma_paddr;
1576 HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr);
1577 HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32));
1579 /* Set the WP and RP */
1581 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp);
1582 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST);
1584 * The HDA specification indicates that the CORBRPRST bit will always
1585 * read as zero. Unfortunately, it seems that at least the 82801G
1586 * doesn't reset the bit to zero, which stalls the corb engine.
1587 * manually reset the bit to zero before continuing.
1589 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0);
1591 /* Enable CORB error reporting */
1593 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE);
1597 /****************************************************************************
1598 * void hdac_rirb_init(struct hdac_softc *)
1600 * Initialize the rirb registers for operations but do not start it up yet.
1601 * The RIRB engine must not be running when this function is called.
1602 ****************************************************************************/
1604 hdac_rirb_init(struct hdac_softc *sc)
1609 /* Setup the RIRB size. */
1610 switch (sc->rirb_size) {
1612 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256);
1615 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_16);
1618 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_2);
1621 panic("%s: Invalid RIRB size (%x)\n", __func__, sc->rirb_size);
1623 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize);
1625 /* Setup the RIRB Address in the hdac */
1626 rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr;
1627 HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr);
1628 HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32));
1630 /* Setup the WP and RP */
1632 HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST);
1634 if (sc->polling == 0) {
1635 /* Setup the interrupt threshold */
1636 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2);
1638 /* Enable Overrun and response received reporting */
1640 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL,
1641 HDAC_RIRBCTL_RIRBOIC | HDAC_RIRBCTL_RINTCTL);
1643 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL);
1649 * Make sure that the Host CPU cache doesn't contain any dirty
1650 * cache lines that falls in the rirb. If I understood correctly, it
1651 * should be sufficient to do this only once as the rirb is purely
1652 * read-only from now on.
1654 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map,
1655 BUS_DMASYNC_PREREAD);
1659 /****************************************************************************
1660 * void hdac_corb_start(hdac_softc *)
1662 * Startup the corb DMA engine
1663 ****************************************************************************/
1665 hdac_corb_start(struct hdac_softc *sc)
1669 corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL);
1670 corbctl |= HDAC_CORBCTL_CORBRUN;
1671 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl);
1674 /****************************************************************************
1675 * void hdac_rirb_start(hdac_softc *)
1677 * Startup the rirb DMA engine
1678 ****************************************************************************/
1680 hdac_rirb_start(struct hdac_softc *sc)
1684 rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL);
1685 rirbctl |= HDAC_RIRBCTL_RIRBDMAEN;
1686 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl);
1690 /****************************************************************************
1691 * void hdac_scan_codecs(struct hdac_softc *)
1693 * Scan the bus for available codecs.
1694 ****************************************************************************/
1696 hdac_scan_codecs(struct hdac_softc *sc)
1698 struct hdac_codec *codec;
1702 statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS);
1703 for (i = 0; i < HDAC_CODEC_MAX; i++) {
1704 if (HDAC_STATESTS_SDIWAKE(statests, i)) {
1705 /* We have found a codec. */
1706 codec = (struct hdac_codec *)kmalloc(sizeof(*codec),
1707 M_HDAC, M_ZERO | M_NOWAIT);
1708 if (codec == NULL) {
1709 device_printf(sc->dev,
1710 "Unable to allocate memory for codec\n");
1713 codec->commands = NULL;
1714 codec->responses_received = 0;
1715 codec->verbs_sent = 0;
1718 sc->codecs[i] = codec;
1719 if (hdac_probe_codec(codec) != 0)
1723 /* All codecs have been probed, now try to attach drivers to them */
1724 /* bus_generic_attach(sc->dev); */
1727 /****************************************************************************
1728 * void hdac_probe_codec(struct hdac_softc *, int)
1730 * Probe a the given codec_id for available function groups.
1731 ****************************************************************************/
1733 hdac_probe_codec(struct hdac_codec *codec)
1735 struct hdac_softc *sc = codec->sc;
1736 struct hdac_devinfo *devinfo;
1737 uint32_t vendorid, revisionid, subnode;
1741 nid_t cad = codec->cad;
1744 device_printf(sc->dev, "HDA_DEBUG: Probing codec: %d\n", cad);
1746 vendorid = hdac_command(sc,
1747 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_VENDOR_ID),
1749 revisionid = hdac_command(sc,
1750 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_REVISION_ID),
1752 subnode = hdac_command(sc,
1753 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_SUB_NODE_COUNT),
1755 startnode = HDA_PARAM_SUB_NODE_COUNT_START(subnode);
1756 endnode = startnode + HDA_PARAM_SUB_NODE_COUNT_TOTAL(subnode);
1759 device_printf(sc->dev, "HDA_DEBUG: \tstartnode=%d endnode=%d\n",
1760 startnode, endnode);
1762 for (i = startnode; i < endnode; i++) {
1763 devinfo = hdac_probe_function(codec, i);
1764 if (devinfo != NULL) {
1765 /* XXX Ignore other FG. */
1766 devinfo->vendor_id =
1767 HDA_PARAM_VENDOR_ID_VENDOR_ID(vendorid);
1768 devinfo->device_id =
1769 HDA_PARAM_VENDOR_ID_DEVICE_ID(vendorid);
1770 devinfo->revision_id =
1771 HDA_PARAM_REVISION_ID_REVISION_ID(revisionid);
1772 devinfo->stepping_id =
1773 HDA_PARAM_REVISION_ID_STEPPING_ID(revisionid);
1775 device_printf(sc->dev,
1776 "HDA_DEBUG: \tFound AFG nid=%d "
1777 "[startnode=%d endnode=%d]\n",
1778 devinfo->nid, startnode, endnode);
1785 device_printf(sc->dev, "HDA_DEBUG: \tAFG not found\n");
1790 static struct hdac_devinfo *
1791 hdac_probe_function(struct hdac_codec *codec, nid_t nid)
1793 struct hdac_softc *sc = codec->sc;
1794 struct hdac_devinfo *devinfo;
1795 uint32_t fctgrptype;
1796 nid_t cad = codec->cad;
1798 fctgrptype = HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE(hdac_command(sc,
1799 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_FCT_GRP_TYPE), cad));
1801 /* XXX For now, ignore other FG. */
1802 if (fctgrptype != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO)
1805 devinfo = (struct hdac_devinfo *)kmalloc(sizeof(*devinfo), M_HDAC,
1807 if (devinfo == NULL) {
1808 device_printf(sc->dev, "%s: Unable to allocate ivar\n",
1814 devinfo->node_type = fctgrptype;
1815 devinfo->codec = codec;
1817 hdac_add_child(sc, devinfo);
1823 hdac_add_child(struct hdac_softc *sc, struct hdac_devinfo *devinfo)
1825 devinfo->dev = device_add_child(sc->dev, NULL, -1);
1826 device_set_ivars(devinfo->dev, (void *)devinfo);
1827 /* XXX - Print more information when booting verbose??? */
1831 hdac_widget_connection_parse(struct hdac_widget *w)
1833 struct hdac_softc *sc = w->devinfo->codec->sc;
1835 int i, j, max, ents, entnum;
1836 nid_t cad = w->devinfo->codec->cad;
1838 nid_t cnid, addcnid, prevcnid;
1842 res = hdac_command(sc,
1843 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_CONN_LIST_LENGTH), cad);
1845 ents = HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH(res);
1850 entnum = HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM(res) ? 2 : 4;
1851 max = (sizeof(w->conns) / sizeof(w->conns[0])) - 1;
1854 #define CONN_RMASK(e) (1 << ((32 / (e)) - 1))
1855 #define CONN_NMASK(e) (CONN_RMASK(e) - 1)
1856 #define CONN_RESVAL(r, e, n) ((r) >> ((32 / (e)) * (n)))
1857 #define CONN_RANGE(r, e, n) (CONN_RESVAL(r, e, n) & CONN_RMASK(e))
1858 #define CONN_CNID(r, e, n) (CONN_RESVAL(r, e, n) & CONN_NMASK(e))
1860 for (i = 0; i < ents; i += entnum) {
1861 res = hdac_command(sc,
1862 HDA_CMD_GET_CONN_LIST_ENTRY(cad, nid, i), cad);
1863 for (j = 0; j < entnum; j++) {
1864 cnid = CONN_CNID(res, entnum, j);
1866 if (w->nconns < ents)
1867 device_printf(sc->dev,
1868 "%s: nid=%d WARNING: zero cnid "
1869 "entnum=%d j=%d index=%d "
1870 "entries=%d found=%d res=0x%08x\n",
1871 __func__, nid, entnum, j, i,
1872 ents, w->nconns, res);
1876 if (cnid < w->devinfo->startnode ||
1877 cnid >= w->devinfo->endnode) {
1879 device_printf(sc->dev,
1880 "%s: GHOST: nid=%d j=%d "
1881 "entnum=%d index=%d res=0x%08x\n",
1882 __func__, nid, j, entnum, i, res);
1885 if (CONN_RANGE(res, entnum, j) == 0)
1887 else if (prevcnid == 0 || prevcnid >= cnid) {
1888 device_printf(sc->dev,
1889 "%s: WARNING: Invalid child range "
1890 "nid=%d index=%d j=%d entnum=%d "
1891 "prevcnid=%d cnid=%d res=0x%08x\n",
1892 __func__, nid, i, j, entnum, prevcnid,
1896 addcnid = prevcnid + 1;
1897 while (addcnid <= cnid) {
1898 if (w->nconns > max) {
1899 device_printf(sc->dev,
1900 "%s: nid=%d: Adding %d: "
1901 "Max connection reached! max=%d\n",
1902 __func__, nid, addcnid, max + 1);
1905 w->conns[w->nconns++] = addcnid++;
1913 device_printf(sc->dev,
1914 "HDA_DEBUG: %s: nid=%d entries=%d found=%d\n",
1915 __func__, nid, ents, w->nconns);
1921 hdac_widget_pin_getconfig(struct hdac_widget *w)
1923 struct hdac_softc *sc;
1924 uint32_t config, orig, id;
1927 sc = w->devinfo->codec->sc;
1928 cad = w->devinfo->codec->cad;
1930 id = hdac_codec_id(w->devinfo);
1932 config = hdac_command(sc,
1933 HDA_CMD_GET_CONFIGURATION_DEFAULT(cad, nid),
1938 * XXX REWRITE!!!! Don't argue!
1940 if (id == HDA_CODEC_ALC880 && sc->pci_subvendor == LG_LW20_SUBVENDOR) {
1943 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
1944 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN;
1947 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
1948 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT;
1953 } else if (id == HDA_CODEC_ALC880 &&
1954 (sc->pci_subvendor == CLEVO_D900T_SUBVENDOR ||
1955 sc->pci_subvendor == ASUS_M5200_SUBVENDOR)) {
1969 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
1970 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN;
1972 case 25: /* XXX MIC2 */
1973 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
1974 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN;
1976 case 26: /* LINE1 */
1977 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
1978 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN;
1980 case 27: /* XXX LINE2 */
1981 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
1982 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN;
1985 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
1986 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_CD;
1995 } else if (id == HDA_CODEC_ALC883 &&
1996 HDA_DEV_MATCH(ACER_ALL_SUBVENDOR, sc->pci_subvendor)) {
1999 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK |
2000 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK);
2001 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN |
2002 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED);
2005 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK |
2006 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK);
2007 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD |
2008 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED);
2013 } else if (id == HDA_CODEC_CXVENICE && sc->pci_subvendor ==
2014 HP_V3000_SUBVENDOR) {
2017 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK;
2018 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE;
2021 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK |
2022 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK);
2023 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN |
2024 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED);
2027 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK |
2028 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK);
2029 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD |
2030 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED);
2035 } else if (id == HDA_CODEC_CXWAIKIKI && sc->pci_subvendor ==
2036 HP_DV5000_SUBVENDOR) {
2040 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK;
2041 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE;
2046 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor ==
2047 ASUS_W6F_SUBVENDOR) {
2050 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK |
2051 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK);
2052 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT |
2053 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED);
2056 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK |
2057 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK);
2058 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT |
2059 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK);
2064 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor ==
2065 UNIWILL_9075_SUBVENDOR) {
2068 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK |
2069 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK);
2070 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT |
2071 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK);
2076 } else if (id == HDA_CODEC_AD1986A &&
2077 (sc->pci_subvendor == ASUS_M2NPVMX_SUBVENDOR ||
2078 sc->pci_subvendor == ASUS_VMCSM_SUBVENDOR)) {
2081 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
2082 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN;
2085 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
2086 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN;
2095 device_printf(sc->dev,
2096 "HDA_DEBUG: Pin config nid=%u 0x%08x -> 0x%08x\n",
2104 hdac_widget_pin_getcaps(struct hdac_widget *w)
2106 struct hdac_softc *sc;
2107 uint32_t caps, orig, id;
2110 sc = w->devinfo->codec->sc;
2111 cad = w->devinfo->codec->cad;
2113 id = hdac_codec_id(w->devinfo);
2115 caps = hdac_command(sc,
2116 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_PIN_CAP), cad);
2121 device_printf(sc->dev,
2122 "HDA_DEBUG: Pin caps nid=%u 0x%08x -> 0x%08x\n",
2130 hdac_widget_pin_parse(struct hdac_widget *w)
2132 struct hdac_softc *sc = w->devinfo->codec->sc;
2133 uint32_t config, pincap;
2134 char *devstr, *connstr;
2135 nid_t cad = w->devinfo->codec->cad;
2138 config = hdac_widget_pin_getconfig(w);
2139 w->wclass.pin.config = config;
2141 pincap = hdac_widget_pin_getcaps(w);
2142 w->wclass.pin.cap = pincap;
2144 w->wclass.pin.ctrl = hdac_command(sc,
2145 HDA_CMD_GET_PIN_WIDGET_CTRL(cad, nid), cad) &
2146 ~(HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE |
2147 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE |
2148 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE |
2149 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK);
2151 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap))
2152 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE;
2153 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap))
2154 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE;
2155 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap))
2156 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE;
2157 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) {
2158 w->param.eapdbtl = hdac_command(sc,
2159 HDA_CMD_GET_EAPD_BTL_ENABLE(cad, nid), cad);
2160 w->param.eapdbtl &= 0x7;
2161 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD;
2163 w->param.eapdbtl = HDAC_INVALID;
2165 switch (config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) {
2166 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT:
2167 devstr = "line out";
2169 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER:
2172 case HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT:
2173 devstr = "headphones out";
2175 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD:
2178 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT:
2179 devstr = "SPDIF out";
2181 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT:
2182 devstr = "digital (other) out";
2184 case HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_LINE:
2185 devstr = "modem, line side";
2187 case HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_HANDSET:
2188 devstr = "modem, handset side";
2190 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN:
2193 case HDA_CONFIG_DEFAULTCONF_DEVICE_AUX:
2196 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN:
2199 case HDA_CONFIG_DEFAULTCONF_DEVICE_TELEPHONY:
2200 devstr = "telephony";
2202 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_IN:
2203 devstr = "SPDIF in";
2205 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_IN:
2206 devstr = "digital (other) in";
2208 case HDA_CONFIG_DEFAULTCONF_DEVICE_OTHER:
2216 switch (config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) {
2217 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK:
2220 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE:
2223 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED:
2226 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_BOTH:
2227 connstr = "jack / fixed";
2230 connstr = "unknown";
2234 strlcat(w->name, ": ", sizeof(w->name));
2235 strlcat(w->name, devstr, sizeof(w->name));
2236 strlcat(w->name, " (", sizeof(w->name));
2237 strlcat(w->name, connstr, sizeof(w->name));
2238 strlcat(w->name, ")", sizeof(w->name));
2242 hdac_widget_parse(struct hdac_widget *w)
2244 struct hdac_softc *sc = w->devinfo->codec->sc;
2247 nid_t cad = w->devinfo->codec->cad;
2250 wcap = hdac_command(sc,
2251 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_AUDIO_WIDGET_CAP),
2253 w->param.widget_cap = wcap;
2254 w->type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE(wcap);
2257 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT:
2258 typestr = "audio output";
2260 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT:
2261 typestr = "audio input";
2263 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER:
2264 typestr = "audio mixer";
2266 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR:
2267 typestr = "audio selector";
2269 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX:
2272 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET:
2273 typestr = "power widget";
2275 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET:
2276 typestr = "volume widget";
2278 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET:
2279 typestr = "beep widget";
2281 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VENDOR_WIDGET:
2282 typestr = "vendor widget";
2285 typestr = "unknown type";
2289 strlcpy(w->name, typestr, sizeof(w->name));
2291 if (HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL(wcap)) {
2293 HDA_CMD_SET_POWER_STATE(cad, nid, HDA_CMD_POWER_STATE_D0),
2298 hdac_widget_connection_parse(w);
2300 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(wcap)) {
2301 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap))
2302 w->param.outamp_cap =
2304 HDA_CMD_GET_PARAMETER(cad, nid,
2305 HDA_PARAM_OUTPUT_AMP_CAP), cad);
2307 w->param.outamp_cap =
2308 w->devinfo->function.audio.outamp_cap;
2310 w->param.outamp_cap = 0;
2312 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(wcap)) {
2313 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap))
2314 w->param.inamp_cap =
2316 HDA_CMD_GET_PARAMETER(cad, nid,
2317 HDA_PARAM_INPUT_AMP_CAP), cad);
2319 w->param.inamp_cap =
2320 w->devinfo->function.audio.inamp_cap;
2322 w->param.inamp_cap = 0;
2324 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT ||
2325 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) {
2326 if (HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR(wcap)) {
2327 cap = hdac_command(sc,
2328 HDA_CMD_GET_PARAMETER(cad, nid,
2329 HDA_PARAM_SUPP_STREAM_FORMATS), cad);
2330 w->param.supp_stream_formats = (cap != 0) ? cap :
2331 w->devinfo->function.audio.supp_stream_formats;
2332 cap = hdac_command(sc,
2333 HDA_CMD_GET_PARAMETER(cad, nid,
2334 HDA_PARAM_SUPP_PCM_SIZE_RATE), cad);
2335 w->param.supp_pcm_size_rate = (cap != 0) ? cap :
2336 w->devinfo->function.audio.supp_pcm_size_rate;
2338 w->param.supp_stream_formats =
2339 w->devinfo->function.audio.supp_stream_formats;
2340 w->param.supp_pcm_size_rate =
2341 w->devinfo->function.audio.supp_pcm_size_rate;
2344 w->param.supp_stream_formats = 0;
2345 w->param.supp_pcm_size_rate = 0;
2348 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
2349 hdac_widget_pin_parse(w);
2352 static struct hdac_widget *
2353 hdac_widget_get(struct hdac_devinfo *devinfo, nid_t nid)
2355 if (devinfo == NULL || devinfo->widget == NULL ||
2356 nid < devinfo->startnode || nid >= devinfo->endnode)
2358 return (&devinfo->widget[nid - devinfo->startnode]);
2362 hda_poll_channel(struct hdac_chan *ch)
2365 volatile uint32_t ptr;
2367 if (ch->active == 0)
2370 sz = ch->blksz * ch->blkcnt;
2371 if (ch->dmapos != NULL)
2372 ptr = *(ch->dmapos);
2374 ptr = HDAC_READ_4(&ch->devinfo->codec->sc->mem,
2375 ch->off + HDAC_SDLPIB);
2378 ptr &= ~(ch->blksz - 1);
2379 delta = (sz + ptr - ch->prevptr) % sz;
2381 if (delta < ch->blksz)
2389 #define hda_chan_active(sc) ((sc)->play.active + (sc)->rec.active)
2392 hda_poll_callback(void *arg)
2394 struct hdac_softc *sc = arg;
2395 uint32_t trigger = 0;
2401 if (sc->polling == 0 || hda_chan_active(sc) == 0) {
2406 trigger |= (hda_poll_channel(&sc->play) != 0) ? 1 : 0;
2407 trigger |= (hda_poll_channel(&sc->rec) != 0) ? 2 : 0;
2410 callout_reset(&sc->poll_hda, 1/*sc->poll_ticks*/,
2411 hda_poll_callback, sc);
2416 chn_intr(sc->play.c);
2418 chn_intr(sc->rec.c);
2422 hdac_rirb_flush(struct hdac_softc *sc)
2424 struct hdac_rirb *rirb_base, *rirb;
2425 struct hdac_codec *codec;
2426 struct hdac_command_list *commands;
2432 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr;
2433 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP);
2435 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map,
2436 BUS_DMASYNC_POSTREAD);
2439 while (sc->rirb_rp != rirbwp) {
2441 sc->rirb_rp %= sc->rirb_size;
2442 rirb = &rirb_base[sc->rirb_rp];
2443 cad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex);
2444 if (cad < 0 || cad >= HDAC_CODEC_MAX ||
2445 sc->codecs[cad] == NULL)
2447 resp = rirb->response;
2448 codec = sc->codecs[cad];
2449 commands = codec->commands;
2450 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) {
2451 sc->unsolq[sc->unsolq_wp++] = (cad << 16) |
2452 ((resp >> 26) & 0xffff);
2453 sc->unsolq_wp %= HDAC_UNSOLQ_MAX;
2454 } else if (commands != NULL && commands->num_commands > 0 &&
2455 codec->responses_received < commands->num_commands)
2456 commands->responses[codec->responses_received++] =
2465 hdac_unsolq_flush(struct hdac_softc *sc)
2471 if (sc->unsolq_st == HDAC_UNSOLQ_READY) {
2472 sc->unsolq_st = HDAC_UNSOLQ_BUSY;
2473 while (sc->unsolq_rp != sc->unsolq_wp) {
2474 cad = sc->unsolq[sc->unsolq_rp] >> 16;
2475 tag = sc->unsolq[sc->unsolq_rp++] & 0xffff;
2476 sc->unsolq_rp %= HDAC_UNSOLQ_MAX;
2477 hdac_unsolicited_handler(sc->codecs[cad], tag);
2480 sc->unsolq_st = HDAC_UNSOLQ_READY;
2487 hdac_poll_callback(void *arg)
2489 struct hdac_softc *sc = arg;
2494 if (sc->polling == 0 || sc->poll_ival == 0) {
2498 hdac_rirb_flush(sc);
2499 hdac_unsolq_flush(sc);
2500 callout_reset(&sc->poll_hdac, sc->poll_ival, hdac_poll_callback, sc);
2505 hdac_stream_stop(struct hdac_chan *ch)
2507 struct hdac_softc *sc = ch->devinfo->codec->sc;
2510 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0);
2511 ctl &= ~(HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE |
2513 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl);
2517 if (sc->polling != 0) {
2520 if (hda_chan_active(sc) == 0) {
2521 callout_stop(&sc->poll_hda);
2524 if (sc->play.active != 0)
2528 pollticks = ((uint64_t)hz * ch->blksz) /
2529 ((uint64_t)sndbuf_getbps(ch->b) *
2530 sndbuf_getspd(ch->b));
2534 if (pollticks < 1) {
2536 device_printf(sc->dev,
2537 "%s: pollticks=%d < 1 !\n",
2538 __func__, pollticks);
2542 if (pollticks > sc->poll_ticks) {
2544 device_printf(sc->dev,
2545 "%s: pollticks %d -> %d\n",
2546 __func__, sc->poll_ticks,
2549 sc->poll_ticks = pollticks;
2550 callout_reset(&sc->poll_hda, 1,
2551 hda_poll_callback, sc);
2555 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL);
2556 ctl &= ~(1 << (ch->off >> 5));
2557 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl);
2562 hdac_stream_start(struct hdac_chan *ch)
2564 struct hdac_softc *sc = ch->devinfo->codec->sc;
2567 if (sc->polling != 0) {
2570 pollticks = ((uint64_t)hz * ch->blksz) /
2571 ((uint64_t)sndbuf_getbps(ch->b) * sndbuf_getspd(ch->b));
2575 if (pollticks < 1) {
2577 device_printf(sc->dev,
2578 "%s: pollticks=%d < 1 !\n",
2579 __func__, pollticks);
2583 if (hda_chan_active(sc) == 0 || pollticks < sc->poll_ticks) {
2585 if (hda_chan_active(sc) == 0) {
2586 device_printf(sc->dev,
2587 "%s: pollticks=%d\n",
2588 __func__, pollticks);
2590 device_printf(sc->dev,
2591 "%s: pollticks %d -> %d\n",
2592 __func__, sc->poll_ticks,
2596 sc->poll_ticks = pollticks;
2597 callout_reset(&sc->poll_hda, 1, hda_poll_callback,
2600 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0);
2601 ctl |= HDAC_SDCTL_RUN;
2603 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL);
2604 ctl |= 1 << (ch->off >> 5);
2605 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl);
2606 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0);
2607 ctl |= HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE |
2610 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl);
2616 hdac_stream_reset(struct hdac_chan *ch)
2618 struct hdac_softc *sc = ch->devinfo->codec->sc;
2623 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0);
2624 ctl |= HDAC_SDCTL_SRST;
2625 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl);
2627 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0);
2628 if (ctl & HDAC_SDCTL_SRST)
2632 if (!(ctl & HDAC_SDCTL_SRST)) {
2633 device_printf(sc->dev, "timeout in reset\n");
2635 ctl &= ~HDAC_SDCTL_SRST;
2636 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl);
2639 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0);
2640 if (!(ctl & HDAC_SDCTL_SRST))
2644 if (ctl & HDAC_SDCTL_SRST)
2645 device_printf(sc->dev, "can't reset!\n");
2649 hdac_stream_setid(struct hdac_chan *ch)
2651 struct hdac_softc *sc = ch->devinfo->codec->sc;
2654 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL2);
2655 ctl &= ~HDAC_SDCTL2_STRM_MASK;
2656 ctl |= ch->sid << HDAC_SDCTL2_STRM_SHIFT;
2657 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL2, ctl);
2661 hdac_bdl_setup(struct hdac_chan *ch)
2663 struct hdac_softc *sc = ch->devinfo->codec->sc;
2664 struct hdac_bdle *bdle;
2666 uint32_t blksz, blkcnt;
2669 addr = (uint64_t)sndbuf_getbufaddr(ch->b);
2670 bdle = (struct hdac_bdle *)ch->bdl_dma.dma_vaddr;
2672 if (sc->polling != 0) {
2673 blksz = ch->blksz * ch->blkcnt;
2677 blkcnt = ch->blkcnt;
2680 for (i = 0; i < blkcnt; i++, bdle++) {
2681 bdle->addrl = (uint32_t)addr;
2682 bdle->addrh = (uint32_t)(addr >> 32);
2684 bdle->ioc = 1 ^ sc->polling;
2688 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDCBL, blksz * blkcnt);
2689 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDLVI, blkcnt - 1);
2690 addr = ch->bdl_dma.dma_paddr;
2691 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPL, (uint32_t)addr);
2692 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPU, (uint32_t)(addr >> 32));
2693 if (ch->dmapos != NULL &&
2694 !(HDAC_READ_4(&sc->mem, HDAC_DPIBLBASE) & 0x00000001)) {
2695 addr = sc->pos_dma.dma_paddr;
2696 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE,
2697 ((uint32_t)addr & HDAC_DPLBASE_DPLBASE_MASK) | 0x00000001);
2698 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, (uint32_t)(addr >> 32));
2703 hdac_bdl_alloc(struct hdac_chan *ch)
2705 struct hdac_softc *sc = ch->devinfo->codec->sc;
2708 rc = hdac_dma_alloc(sc, &ch->bdl_dma,
2709 sizeof(struct hdac_bdle) * HDA_BDL_MAX);
2711 device_printf(sc->dev, "can't alloc bdl\n");
2719 hdac_audio_ctl_amp_set_internal(struct hdac_softc *sc, nid_t cad, nid_t nid,
2720 int index, int lmute, int rmute,
2721 int left, int right, int dir)
2728 if (left != right || lmute != rmute) {
2729 v = (1 << (15 - dir)) | (1 << 13) | (index << 8) |
2730 (lmute << 7) | left;
2732 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad);
2733 v = (1 << (15 - dir)) | (1 << 12) | (index << 8) |
2734 (rmute << 7) | right;
2736 v = (1 << (15 - dir)) | (3 << 12) | (index << 8) |
2737 (lmute << 7) | left;
2740 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad);
2744 hdac_audio_ctl_amp_set(struct hdac_audio_ctl *ctl, uint32_t mute,
2745 int left, int right)
2747 struct hdac_softc *sc;
2751 if (ctl == NULL || ctl->widget == NULL ||
2752 ctl->widget->devinfo == NULL ||
2753 ctl->widget->devinfo->codec == NULL ||
2754 ctl->widget->devinfo->codec->sc == NULL)
2757 sc = ctl->widget->devinfo->codec->sc;
2758 cad = ctl->widget->devinfo->codec->cad;
2759 nid = ctl->widget->nid;
2761 if (mute == HDA_AMP_MUTE_DEFAULT) {
2762 lmute = HDA_AMP_LEFT_MUTED(ctl->muted);
2763 rmute = HDA_AMP_RIGHT_MUTED(ctl->muted);
2765 lmute = HDA_AMP_LEFT_MUTED(mute);
2766 rmute = HDA_AMP_RIGHT_MUTED(mute);
2769 if (ctl->dir & HDA_CTL_OUT)
2770 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index,
2771 lmute, rmute, left, right, 0);
2772 if (ctl->dir & HDA_CTL_IN)
2773 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index,
2774 lmute, rmute, left, right, 1);
2780 hdac_widget_connection_select(struct hdac_widget *w, uint8_t index)
2782 if (w == NULL || w->nconns < 1 || index > (w->nconns - 1))
2784 hdac_command(w->devinfo->codec->sc,
2785 HDA_CMD_SET_CONNECTION_SELECT_CONTROL(w->devinfo->codec->cad,
2786 w->nid, index), w->devinfo->codec->cad);
2791 /****************************************************************************
2792 * uint32_t hdac_command_sendone_internal
2794 * Wrapper function that sends only one command to a given codec
2795 ****************************************************************************/
2797 hdac_command_sendone_internal(struct hdac_softc *sc, uint32_t verb, nid_t cad)
2799 struct hdac_command_list cl;
2800 uint32_t response = HDAC_INVALID;
2802 if (!hdac_lockowned(sc))
2803 device_printf(sc->dev, "WARNING!!!! mtx not owned!!!!\n");
2804 cl.num_commands = 1;
2806 cl.responses = &response;
2808 hdac_command_send_internal(sc, &cl, cad);
2813 /****************************************************************************
2814 * hdac_command_send_internal
2816 * Send a command list to the codec via the corb. We queue as much verbs as
2817 * we can and msleep on the codec. When the interrupt get the responses
2818 * back from the rirb, it will wake us up so we can queue the remaining verbs
2820 ****************************************************************************/
2822 hdac_command_send_internal(struct hdac_softc *sc,
2823 struct hdac_command_list *commands, nid_t cad)
2825 struct hdac_codec *codec;
2830 struct hdac_rirb *rirb_base;
2832 if (sc == NULL || sc->codecs[cad] == NULL || commands == NULL ||
2833 commands->num_commands < 1)
2836 codec = sc->codecs[cad];
2837 codec->commands = commands;
2838 codec->responses_received = 0;
2839 codec->verbs_sent = 0;
2840 corb = (uint32_t *)sc->corb_dma.dma_vaddr;
2841 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr;
2844 if (codec->verbs_sent != commands->num_commands) {
2845 /* Queue as many verbs as possible */
2846 corbrp = HDAC_READ_2(&sc->mem, HDAC_CORBRP);
2848 bus_dmamap_sync(sc->corb_dma.dma_tag,
2849 sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE);
2851 while (codec->verbs_sent != commands->num_commands &&
2852 ((sc->corb_wp + 1) % sc->corb_size) != corbrp) {
2854 sc->corb_wp %= sc->corb_size;
2856 commands->verbs[codec->verbs_sent++];
2859 /* Send the verbs to the codecs */
2861 bus_dmamap_sync(sc->corb_dma.dma_tag,
2862 sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE);
2864 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp);
2868 while (hdac_rirb_flush(sc) == 0 && --timeout)
2870 } while ((codec->verbs_sent != commands->num_commands ||
2871 codec->responses_received != commands->num_commands) && --retry);
2874 device_printf(sc->dev,
2875 "%s: TIMEOUT numcmd=%d, sent=%d, received=%d\n",
2876 __func__, commands->num_commands, codec->verbs_sent,
2877 codec->responses_received);
2879 codec->commands = NULL;
2880 codec->responses_received = 0;
2881 codec->verbs_sent = 0;
2883 hdac_unsolq_flush(sc);
2887 /****************************************************************************
2889 ****************************************************************************/
2891 /****************************************************************************
2892 * int hdac_probe(device_t)
2894 * Probe for the presence of an hdac. If none is found, check for a generic
2895 * match using the subclass of the device.
2896 ****************************************************************************/
2898 hdac_probe(device_t dev)
2902 uint16_t class, subclass;
2905 model = (uint32_t)pci_get_device(dev) << 16;
2906 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff;
2907 class = pci_get_class(dev);
2908 subclass = pci_get_subclass(dev);
2910 bzero(desc, sizeof(desc));
2912 for (i = 0; i < HDAC_DEVICES_LEN; i++) {
2913 if (hdac_devices[i].model == model) {
2914 strlcpy(desc, hdac_devices[i].desc, sizeof(desc));
2915 result = BUS_PROBE_DEFAULT;
2918 if (HDA_DEV_MATCH(hdac_devices[i].model, model) &&
2919 class == PCIC_MULTIMEDIA &&
2920 subclass == PCIS_MULTIMEDIA_HDA) {
2921 strlcpy(desc, hdac_devices[i].desc, sizeof(desc));
2922 result = BUS_PROBE_GENERIC;
2926 if (result == ENXIO && class == PCIC_MULTIMEDIA &&
2927 subclass == PCIS_MULTIMEDIA_HDA) {
2928 strlcpy(desc, "Generic", sizeof(desc));
2929 result = BUS_PROBE_GENERIC;
2931 if (result != ENXIO) {
2932 strlcat(desc, " High Definition Audio Controller",
2934 device_set_desc_copy(dev, desc);
2941 hdac_channel_init(kobj_t obj, void *data, struct snd_dbuf *b,
2942 struct pcm_channel *c, int dir)
2944 struct hdac_devinfo *devinfo = data;
2945 struct hdac_softc *sc = devinfo->codec->sc;
2946 struct hdac_chan *ch;
2949 if (dir == PCMDIR_PLAY) {
2951 ch->off = (sc->num_iss + devinfo->function.audio.playcnt) << 5;
2952 devinfo->function.audio.playcnt++;
2955 ch->off = devinfo->function.audio.reccnt << 5;
2956 devinfo->function.audio.reccnt++;
2958 if (devinfo->function.audio.quirks & HDA_QUIRK_FIXEDRATE) {
2959 ch->caps.minspeed = ch->caps.maxspeed = 48000;
2960 ch->pcmrates[0] = 48000;
2961 ch->pcmrates[1] = 0;
2963 if (sc->pos_dma.dma_vaddr != NULL)
2964 ch->dmapos = (uint32_t *)(sc->pos_dma.dma_vaddr +
2965 (sc->streamcnt * 8));
2968 ch->sid = ++sc->streamcnt;
2972 ch->devinfo = devinfo;
2973 ch->blksz = sc->chan_size / sc->chan_blkcnt;
2974 ch->blkcnt = sc->chan_blkcnt;
2977 if (hdac_bdl_alloc(ch) != 0) {
2982 if (sndbuf_alloc(ch->b, sc->chan_dmat, sc->chan_size) != 0)
2985 HDAC_DMA_ATTR(sc, sndbuf_getbuf(ch->b), sndbuf_getmaxsize(ch->b),
2992 hdac_channel_free(kobj_t obj, void *data)
2994 struct hdac_softc *sc;
2995 struct hdac_chan *ch;
2997 ch = (struct hdac_chan *)data;
2998 sc = (ch != NULL && ch->devinfo != NULL && ch->devinfo->codec != NULL) ?
2999 ch->devinfo->codec->sc : NULL;
3000 if (ch != NULL && sc != NULL) {
3001 HDAC_DMA_ATTR(sc, sndbuf_getbuf(ch->b),
3002 sndbuf_getmaxsize(ch->b), PAT_WRITE_BACK);
3009 hdac_channel_setformat(kobj_t obj, void *data, uint32_t format)
3011 struct hdac_chan *ch = data;
3014 for (i = 0; ch->caps.fmtlist[i] != 0; i++) {
3015 if (format == ch->caps.fmtlist[i]) {
3025 hdac_channel_setspeed(kobj_t obj, void *data, uint32_t speed)
3027 struct hdac_chan *ch = data;
3028 uint32_t spd = 0, threshold;
3031 for (i = 0; ch->pcmrates[i] != 0; i++) {
3032 spd = ch->pcmrates[i];
3033 threshold = spd + ((ch->pcmrates[i + 1] != 0) ?
3034 ((ch->pcmrates[i + 1] - spd) >> 1) : 0);
3035 if (speed < threshold)
3039 if (spd == 0) /* impossible */
3048 hdac_stream_setup(struct hdac_chan *ch)
3050 struct hdac_softc *sc = ch->devinfo->codec->sc;
3052 nid_t cad = ch->devinfo->codec->cad;
3056 if (ch->fmt & AFMT_S16_LE)
3057 fmt |= ch->bit16 << 4;
3058 else if (ch->fmt & AFMT_S32_LE)
3059 fmt |= ch->bit32 << 4;
3063 for (i = 0; i < HDA_RATE_TAB_LEN; i++) {
3064 if (hda_rate_tab[i].valid && ch->spd == hda_rate_tab[i].rate) {
3065 fmt |= hda_rate_tab[i].base;
3066 fmt |= hda_rate_tab[i].mul;
3067 fmt |= hda_rate_tab[i].div;
3072 if (ch->fmt & AFMT_STEREO)
3075 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDFMT, fmt);
3077 for (i = 0; ch->io[i] != -1; i++) {
3079 device_printf(sc->dev,
3080 "HDA_DEBUG: PCMDIR_%s: Stream setup nid=%d "
3082 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC",
3086 HDA_CMD_SET_CONV_FMT(cad, ch->io[i], fmt), cad);
3088 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i],
3089 ch->sid << 4), cad);
3094 hdac_channel_setfragments(kobj_t obj, void *data,
3095 uint32_t blksz, uint32_t blkcnt)
3097 struct hdac_chan *ch = data;
3098 struct hdac_softc *sc = ch->devinfo->codec->sc;
3100 blksz &= HDA_BLK_ALIGN;
3102 if (blksz > (sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN))
3103 blksz = sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN;
3104 if (blksz < HDA_BLK_MIN)
3105 blksz = HDA_BLK_MIN;
3106 if (blkcnt > HDA_BDL_MAX)
3107 blkcnt = HDA_BDL_MAX;
3108 if (blkcnt < HDA_BDL_MIN)
3109 blkcnt = HDA_BDL_MIN;
3111 while ((blksz * blkcnt) > sndbuf_getmaxsize(ch->b)) {
3112 if ((blkcnt >> 1) >= HDA_BDL_MIN)
3114 else if ((blksz >> 1) >= HDA_BLK_MIN)
3120 if ((sndbuf_getblksz(ch->b) != blksz ||
3121 sndbuf_getblkcnt(ch->b) != blkcnt) &&
3122 sndbuf_resize(ch->b, blkcnt, blksz) != 0)
3123 device_printf(sc->dev, "%s: failed blksz=%u blkcnt=%u\n",
3124 __func__, blksz, blkcnt);
3126 ch->blksz = sndbuf_getblksz(ch->b);
3127 ch->blkcnt = sndbuf_getblkcnt(ch->b);
3133 hdac_channel_setblocksize(kobj_t obj, void *data, uint32_t blksz)
3135 struct hdac_chan *ch = data;
3136 struct hdac_softc *sc = ch->devinfo->codec->sc;
3138 hdac_channel_setfragments(obj, data, blksz, sc->chan_blkcnt);
3144 hdac_channel_stop(struct hdac_softc *sc, struct hdac_chan *ch)
3146 struct hdac_devinfo *devinfo = ch->devinfo;
3147 nid_t cad = devinfo->codec->cad;
3150 hdac_stream_stop(ch);
3152 for (i = 0; ch->io[i] != -1; i++) {
3154 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i],
3160 hdac_channel_start(struct hdac_softc *sc, struct hdac_chan *ch)
3164 hdac_stream_stop(ch);
3165 hdac_stream_reset(ch);
3167 hdac_stream_setid(ch);
3168 hdac_stream_setup(ch);
3169 hdac_stream_start(ch);
3173 hdac_channel_trigger(kobj_t obj, void *data, int go)
3175 struct hdac_chan *ch = data;
3176 struct hdac_softc *sc = ch->devinfo->codec->sc;
3178 if (!(go == PCMTRIG_START || go == PCMTRIG_STOP || go == PCMTRIG_ABORT))
3184 hdac_channel_start(sc, ch);
3188 hdac_channel_stop(sc, ch);
3199 hdac_channel_getptr(kobj_t obj, void *data)
3201 struct hdac_chan *ch = data;
3202 struct hdac_softc *sc = ch->devinfo->codec->sc;
3206 if (sc->polling != 0)
3208 else if (ch->dmapos != NULL)
3209 ptr = *(ch->dmapos);
3211 ptr = HDAC_READ_4(&sc->mem, ch->off + HDAC_SDLPIB);
3215 * Round to available space and force 128 bytes aligment.
3217 ptr %= ch->blksz * ch->blkcnt;
3218 ptr &= HDA_BLK_ALIGN;
3223 static struct pcmchan_caps *
3224 hdac_channel_getcaps(kobj_t obj, void *data)
3226 return (&((struct hdac_chan *)data)->caps);
3229 static kobj_method_t hdac_channel_methods[] = {
3230 KOBJMETHOD(channel_init, hdac_channel_init),
3231 KOBJMETHOD(channel_free, hdac_channel_free),
3232 KOBJMETHOD(channel_setformat, hdac_channel_setformat),
3233 KOBJMETHOD(channel_setspeed, hdac_channel_setspeed),
3234 KOBJMETHOD(channel_setblocksize, hdac_channel_setblocksize),
3235 KOBJMETHOD(channel_trigger, hdac_channel_trigger),
3236 KOBJMETHOD(channel_getptr, hdac_channel_getptr),
3237 KOBJMETHOD(channel_getcaps, hdac_channel_getcaps),
3240 CHANNEL_DECLARE(hdac_channel);
3243 hdac_jack_poll_callback(void *arg)
3245 struct hdac_devinfo *devinfo = arg;
3246 struct hdac_softc *sc;
3248 if (devinfo == NULL || devinfo->codec == NULL ||
3249 devinfo->codec->sc == NULL)
3251 sc = devinfo->codec->sc;
3253 if (sc->poll_ival == 0) {
3257 hdac_hp_switch_handler(devinfo);
3258 callout_reset(&sc->poll_jack, sc->poll_ival,
3259 hdac_jack_poll_callback, devinfo);
3264 hdac_audio_ctl_ossmixer_init(struct snd_mixer *m)
3266 struct hdac_devinfo *devinfo = mix_getdevinfo(m);
3267 struct hdac_softc *sc = devinfo->codec->sc;
3268 struct hdac_widget *w, *cw;
3269 struct hdac_audio_ctl *ctl;
3270 uint32_t mask, recmask, id;
3271 int i, j, softpcmvol;
3279 id = hdac_codec_id(devinfo);
3280 cad = devinfo->codec->cad;
3281 for (i = 0; i < HDAC_HP_SWITCH_LEN; i++) {
3282 if (!(HDA_DEV_MATCH(hdac_hp_switch[i].model,
3283 sc->pci_subvendor) && hdac_hp_switch[i].id == id))
3285 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid);
3286 if (w == NULL || w->enable == 0 || w->type !=
3287 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
3289 if (hdac_hp_switch[i].polling != 0)
3290 callout_reset(&sc->poll_jack, 1,
3291 hdac_jack_poll_callback, devinfo);
3292 else if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap))
3294 HDA_CMD_SET_UNSOLICITED_RESPONSE(cad, w->nid,
3295 HDA_CMD_SET_UNSOLICITED_RESPONSE_ENABLE |
3296 HDAC_UNSOLTAG_EVENT_HP), cad);
3299 hdac_hp_switch_handler(devinfo);
3301 device_printf(sc->dev,
3302 "HDA_DEBUG: Enabling headphone/speaker "
3303 "audio routing switching:\n");
3304 device_printf(sc->dev,
3305 "HDA_DEBUG: \tindex=%d nid=%d "
3306 "pci_subvendor=0x%08x "
3307 "codec=0x%08x [%s]\n",
3308 i, w->nid, sc->pci_subvendor, id,
3309 (hdac_hp_switch[i].polling != 0) ? "POLL" :
3314 for (i = 0; i < HDAC_EAPD_SWITCH_LEN; i++) {
3315 if (!(HDA_DEV_MATCH(hdac_eapd_switch[i].model,
3316 sc->pci_subvendor) &&
3317 hdac_eapd_switch[i].id == id))
3319 w = hdac_widget_get(devinfo, hdac_eapd_switch[i].eapdnid);
3320 if (w == NULL || w->enable == 0)
3322 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX ||
3323 w->param.eapdbtl == HDAC_INVALID)
3325 mask |= SOUND_MASK_OGAIN;
3329 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
3330 w = hdac_widget_get(devinfo, i);
3331 if (w == NULL || w->enable == 0)
3333 mask |= w->ctlflags;
3334 if (!(w->pflags & HDA_ADC_RECSEL))
3336 for (j = 0; j < w->nconns; j++) {
3337 cw = hdac_widget_get(devinfo, w->conns[j]);
3338 if (cw == NULL || cw->enable == 0)
3340 recmask |= cw->ctlflags;
3344 if (!(mask & SOUND_MASK_PCM)) {
3346 mask |= SOUND_MASK_PCM;
3348 softpcmvol = (devinfo->function.audio.quirks &
3349 HDA_QUIRK_SOFTPCMVOL) ? 1 : 0;
3353 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
3354 if (ctl->widget == NULL || ctl->enable == 0)
3356 if (!(ctl->ossmask & SOUND_MASK_PCM))
3362 if (softpcmvol == 1 || ctl == NULL) {
3363 pcm_setflags(sc->dev, pcm_getflags(sc->dev) | SD_F_SOFTPCMVOL);
3365 device_printf(sc->dev,
3366 "HDA_DEBUG: %s Soft PCM volume\n",
3368 "Forcing" : "Enabling");
3372 * XXX Temporary quirk for STAC9220, until the parser
3375 if (id == HDA_CODEC_STAC9220) {
3376 mask |= SOUND_MASK_VOLUME;
3377 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) !=
3379 if (ctl->widget == NULL || ctl->enable == 0)
3381 if (ctl->widget->nid == 11 && ctl->index == 0) {
3382 ctl->ossmask = SOUND_MASK_VOLUME;
3383 ctl->ossval = 100 | (100 << 8);
3385 ctl->ossmask &= ~SOUND_MASK_VOLUME;
3387 } else if (id == HDA_CODEC_STAC9221) {
3388 mask |= SOUND_MASK_VOLUME;
3389 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) !=
3391 if (ctl->widget == NULL)
3393 if (ctl->widget->type ==
3394 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT &&
3395 ctl->index == 0 && (ctl->widget->nid == 2 ||
3396 ctl->widget->enable != 0)) {
3398 ctl->ossmask = SOUND_MASK_VOLUME;
3399 ctl->ossval = 100 | (100 << 8);
3400 } else if (ctl->enable == 0)
3403 ctl->ossmask &= ~SOUND_MASK_VOLUME;
3406 mix_setparentchild(m, SOUND_MIXER_VOLUME,
3408 if (!(mask & SOUND_MASK_VOLUME))
3409 mix_setrealdev(m, SOUND_MIXER_VOLUME,
3411 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) !=
3413 if (ctl->widget == NULL || ctl->enable == 0)
3415 if (!HDA_FLAG_MATCH(ctl->ossmask,
3416 SOUND_MASK_VOLUME | SOUND_MASK_PCM))
3418 if (!(ctl->mute == 1 && ctl->step == 0))
3424 recmask &= ~(SOUND_MASK_PCM | SOUND_MASK_RECLEV | SOUND_MASK_SPEAKER |
3425 SOUND_MASK_BASS | SOUND_MASK_TREBLE | SOUND_MASK_IGAIN |
3427 recmask &= (1 << SOUND_MIXER_NRDEVICES) - 1;
3428 mask &= (1 << SOUND_MIXER_NRDEVICES) - 1;
3430 mix_setrecdevs(m, recmask);
3431 mix_setdevs(m, mask);
3439 hdac_audio_ctl_ossmixer_set(struct snd_mixer *m, unsigned dev,
3440 unsigned left, unsigned right)
3442 struct hdac_devinfo *devinfo = mix_getdevinfo(m);
3443 struct hdac_softc *sc = devinfo->codec->sc;
3444 struct hdac_widget *w;
3445 struct hdac_audio_ctl *ctl;
3447 int lvol, rvol, mlvol, mrvol;
3451 if (dev == SOUND_MIXER_OGAIN) {
3453 /*if (left != right || !(left == 0 || left == 1)) {
3457 id = hdac_codec_id(devinfo);
3458 for (i = 0; i < HDAC_EAPD_SWITCH_LEN; i++) {
3459 if (HDA_DEV_MATCH(hdac_eapd_switch[i].model,
3460 sc->pci_subvendor) &&
3461 hdac_eapd_switch[i].id == id)
3464 if (i >= HDAC_EAPD_SWITCH_LEN) {
3468 w = hdac_widget_get(devinfo, hdac_eapd_switch[i].eapdnid);
3470 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX ||
3471 w->param.eapdbtl == HDAC_INVALID) {
3475 orig = w->param.eapdbtl;
3477 w->param.eapdbtl &= ~HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD;
3479 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD;
3480 if (orig != w->param.eapdbtl) {
3483 if (hdac_eapd_switch[i].hp_switch != 0)
3484 hdac_hp_switch_handler(devinfo);
3485 val = w->param.eapdbtl;
3486 if (devinfo->function.audio.quirks & HDA_QUIRK_EAPDINV)
3487 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD;
3489 HDA_CMD_SET_EAPD_BTL_ENABLE(devinfo->codec->cad,
3490 w->nid, val), devinfo->codec->cad);
3493 return (left | (left << 8));
3495 if (dev == SOUND_MIXER_VOLUME)
3496 devinfo->function.audio.mvol = left | (right << 8);
3498 mlvol = devinfo->function.audio.mvol & 0x7f;
3499 mrvol = (devinfo->function.audio.mvol >> 8) & 0x7f;
3504 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
3505 if (ctl->widget == NULL || ctl->enable == 0 ||
3506 !(ctl->ossmask & (1 << dev)))
3509 case SOUND_MIXER_VOLUME:
3510 lvol = ((ctl->ossval & 0x7f) * left) / 100;
3511 lvol = (lvol * ctl->step) / 100;
3512 rvol = (((ctl->ossval >> 8) & 0x7f) * right) / 100;
3513 rvol = (rvol * ctl->step) / 100;
3516 if (ctl->ossmask & SOUND_MASK_VOLUME) {
3517 lvol = (left * mlvol) / 100;
3518 lvol = (lvol * ctl->step) / 100;
3519 rvol = (right * mrvol) / 100;
3520 rvol = (rvol * ctl->step) / 100;
3522 lvol = (left * ctl->step) / 100;
3523 rvol = (right * ctl->step) / 100;
3525 ctl->ossval = left | (right << 8);
3529 if (ctl->step < 1) {
3530 mute |= (left == 0) ? HDA_AMP_MUTE_LEFT :
3531 (ctl->muted & HDA_AMP_MUTE_LEFT);
3532 mute |= (right == 0) ? HDA_AMP_MUTE_RIGHT :
3533 (ctl->muted & HDA_AMP_MUTE_RIGHT);
3535 mute |= (lvol == 0) ? HDA_AMP_MUTE_LEFT :
3536 (ctl->muted & HDA_AMP_MUTE_LEFT);
3537 mute |= (rvol == 0) ? HDA_AMP_MUTE_RIGHT :
3538 (ctl->muted & HDA_AMP_MUTE_RIGHT);
3540 hdac_audio_ctl_amp_set(ctl, mute, lvol, rvol);
3544 return (left | (right << 8));
3548 hdac_audio_ctl_ossmixer_setrecsrc(struct snd_mixer *m, uint32_t src)
3550 struct hdac_devinfo *devinfo = mix_getdevinfo(m);
3551 struct hdac_widget *w, *cw;
3552 struct hdac_softc *sc = devinfo->codec->sc;
3553 uint32_t ret = src, target;
3557 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) {
3558 if (src & (1 << i)) {
3566 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
3567 w = hdac_widget_get(devinfo, i);
3568 if (w == NULL || w->enable == 0)
3570 if (!(w->pflags & HDA_ADC_RECSEL))
3572 for (j = 0; j < w->nconns; j++) {
3573 cw = hdac_widget_get(devinfo, w->conns[j]);
3574 if (cw == NULL || cw->enable == 0)
3576 if ((target == SOUND_MASK_VOLUME &&
3578 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) ||
3579 (target != SOUND_MASK_VOLUME &&
3581 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER))
3583 if (cw->ctlflags & target) {
3584 if (!(w->pflags & HDA_ADC_LOCKED))
3585 hdac_widget_connection_select(w, j);
3597 static kobj_method_t hdac_audio_ctl_ossmixer_methods[] = {
3598 KOBJMETHOD(mixer_init, hdac_audio_ctl_ossmixer_init),
3599 KOBJMETHOD(mixer_set, hdac_audio_ctl_ossmixer_set),
3600 KOBJMETHOD(mixer_setrecsrc, hdac_audio_ctl_ossmixer_setrecsrc),
3603 MIXER_DECLARE(hdac_audio_ctl_ossmixer);
3605 /****************************************************************************
3606 * int hdac_attach(device_t)
3608 * Attach the device into the kernel. Interrupts usually won't be enabled
3609 * when this function is called. Setup everything that doesn't require
3610 * interrupts and defer probing of codecs until interrupts are enabled.
3611 ****************************************************************************/
3613 hdac_attach(device_t dev)
3615 struct hdac_softc *sc;
3621 sc = kmalloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO);
3622 sc->lock = snd_mtxcreate(device_get_nameunit(dev), HDAC_MTX_NAME);
3624 sc->pci_subvendor = (uint32_t)pci_get_subdevice(sc->dev) << 16;
3625 sc->pci_subvendor |= (uint32_t)pci_get_subvendor(sc->dev) & 0x0000ffff;
3626 vendor = pci_get_vendor(dev);
3628 if (sc->pci_subvendor == HP_NX6325_SUBVENDORX) {
3629 /* Screw nx6325 - subdevice/subvendor swapped */
3630 sc->pci_subvendor = HP_NX6325_SUBVENDOR;
3633 callout_init(&sc->poll_hda);
3634 callout_init(&sc->poll_hdac);
3635 callout_init(&sc->poll_jack);
3638 sc->poll_ival = HDAC_POLL_INTERVAL;
3639 if (resource_int_value(device_get_name(dev),
3640 device_get_unit(dev), "polling", &i) == 0 && i != 0)
3645 sc->chan_size = pcm_getbuffersize(dev,
3646 HDA_BUFSZ_MIN, HDA_BUFSZ_DEFAULT, HDA_BUFSZ_MAX);
3648 if (resource_int_value(device_get_name(dev),
3649 device_get_unit(dev), "blocksize", &i) == 0 && i > 0) {
3651 if (i < HDA_BLK_MIN)
3653 sc->chan_blkcnt = sc->chan_size / i;
3655 while (sc->chan_blkcnt >> i)
3657 sc->chan_blkcnt = 1 << (i - 1);
3658 if (sc->chan_blkcnt < HDA_BDL_MIN)
3659 sc->chan_blkcnt = HDA_BDL_MIN;
3660 else if (sc->chan_blkcnt > HDA_BDL_MAX)
3661 sc->chan_blkcnt = HDA_BDL_MAX;
3663 sc->chan_blkcnt = HDA_BDL_DEFAULT;
3665 result = bus_dma_tag_create(NULL, /* parent */
3666 HDAC_DMA_ALIGNMENT, /* alignment */
3668 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
3669 BUS_SPACE_MAXADDR, /* highaddr */
3670 NULL, /* filtfunc */
3671 NULL, /* fistfuncarg */
3672 sc->chan_size, /* maxsize */
3674 sc->chan_size, /* maxsegsz */
3676 &sc->chan_dmat); /* dmat */
3678 device_printf(dev, "%s: bus_dma_tag_create failed (%x)\n",
3680 snd_mtxfree(sc->lock);
3681 kfree(sc, M_DEVBUF);
3687 for (i = 0; i < HDAC_CODEC_MAX; i++)
3688 sc->codecs[i] = NULL;
3690 pci_enable_busmaster(dev);
3692 if (vendor == INTEL_VENDORID) {
3694 v = pci_read_config(dev, 0x44, 1);
3695 pci_write_config(dev, 0x44, v & 0xf8, 1);
3697 device_printf(dev, "TCSEL: 0x%02d -> 0x%02d\n", v,
3698 pci_read_config(dev, 0x44, 1));
3702 #if 0 /* TODO: No uncacheable DMA support in DragonFly. */
3705 if (resource_int_value(device_get_name(dev),
3706 device_get_unit(dev), "snoop", &i) == 0 && i != 0) {
3711 * Try to enable PCIe snoop to avoid messing around with
3712 * uncacheable DMA attribute. Since PCIe snoop register
3713 * config is pretty much vendor specific, there are no
3714 * general solutions on how to enable it, forcing us (even
3715 * Microsoft) to enable uncacheable or write combined DMA
3718 * http://msdn2.microsoft.com/en-us/library/ms790324.aspx
3720 for (i = 0; i < HDAC_PCIESNOOP_LEN; i++) {
3721 if (hdac_pcie_snoop[i].vendor != vendor)
3724 if (hdac_pcie_snoop[i].reg == 0x00)
3726 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1);
3727 if ((v & hdac_pcie_snoop[i].enable) ==
3728 hdac_pcie_snoop[i].enable)
3730 v &= hdac_pcie_snoop[i].mask;
3731 v |= hdac_pcie_snoop[i].enable;
3732 pci_write_config(dev, hdac_pcie_snoop[i].reg, v, 1);
3733 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1);
3734 if ((v & hdac_pcie_snoop[i].enable) !=
3735 hdac_pcie_snoop[i].enable) {
3738 "WARNING: Failed to enable PCIe "
3741 #if 0 /* TODO: No uncacheable DMA support in DragonFly. */
3747 #if 0 /* TODO: No uncacheable DMA support in DragonFly. */
3752 device_printf(dev, "DMA Coherency: %s / vendor=0x%04x\n",
3753 (sc->nocache == 0) ? "PCIe snoop" : "Uncacheable", vendor);
3756 /* Allocate resources */
3757 result = hdac_mem_alloc(sc);
3759 goto hdac_attach_fail;
3760 result = hdac_irq_alloc(sc);
3762 goto hdac_attach_fail;
3764 /* Get Capabilities */
3765 result = hdac_get_capabilities(sc);
3767 goto hdac_attach_fail;
3769 /* Allocate CORB and RIRB dma memory */
3770 result = hdac_dma_alloc(sc, &sc->corb_dma,
3771 sc->corb_size * sizeof(uint32_t));
3773 goto hdac_attach_fail;
3774 result = hdac_dma_alloc(sc, &sc->rirb_dma,
3775 sc->rirb_size * sizeof(struct hdac_rirb));
3777 goto hdac_attach_fail;
3779 /* Quiesce everything */
3782 /* Initialize the CORB and RIRB */
3786 /* Defer remaining of initialization until interrupts are enabled */
3787 sc->intrhook.ich_func = hdac_attach2;
3788 sc->intrhook.ich_arg = (void *)sc;
3789 if (cold == 0 || config_intrhook_establish(&sc->intrhook) != 0) {
3790 sc->intrhook.ich_func = NULL;
3791 hdac_attach2((void *)sc);
3798 hdac_dma_free(sc, &sc->rirb_dma);
3799 hdac_dma_free(sc, &sc->corb_dma);
3801 snd_mtxfree(sc->lock);
3802 kfree(sc, M_DEVBUF);
3808 hdac_audio_parse(struct hdac_devinfo *devinfo)
3810 struct hdac_softc *sc = devinfo->codec->sc;
3811 struct hdac_widget *w;
3816 cad = devinfo->codec->cad;
3820 HDA_CMD_SET_POWER_STATE(cad, nid, HDA_CMD_POWER_STATE_D0), cad);
3824 res = hdac_command(sc,
3825 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_SUB_NODE_COUNT), cad);
3827 devinfo->nodecnt = HDA_PARAM_SUB_NODE_COUNT_TOTAL(res);
3828 devinfo->startnode = HDA_PARAM_SUB_NODE_COUNT_START(res);
3829 devinfo->endnode = devinfo->startnode + devinfo->nodecnt;
3831 res = hdac_command(sc,
3832 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_GPIO_COUNT), cad);
3833 devinfo->function.audio.gpio = res;
3836 device_printf(sc->dev, " Vendor: 0x%08x\n",
3837 devinfo->vendor_id);
3838 device_printf(sc->dev, " Device: 0x%08x\n",
3839 devinfo->device_id);
3840 device_printf(sc->dev, " Revision: 0x%08x\n",
3841 devinfo->revision_id);
3842 device_printf(sc->dev, " Stepping: 0x%08x\n",
3843 devinfo->stepping_id);
3844 device_printf(sc->dev, "PCI Subvendor: 0x%08x\n",
3846 device_printf(sc->dev, " Nodes: start=%d "
3847 "endnode=%d total=%d\n",
3848 devinfo->startnode, devinfo->endnode, devinfo->nodecnt);
3849 device_printf(sc->dev, " CORB size: %d\n", sc->corb_size);
3850 device_printf(sc->dev, " RIRB size: %d\n", sc->rirb_size);
3851 device_printf(sc->dev, " Streams: ISS=%d OSS=%d BSS=%d\n",
3852 sc->num_iss, sc->num_oss, sc->num_bss);
3853 device_printf(sc->dev, " GPIO: 0x%08x\n",
3854 devinfo->function.audio.gpio);
3855 device_printf(sc->dev, " NumGPIO=%d NumGPO=%d "
3856 "NumGPI=%d GPIWake=%d GPIUnsol=%d\n",
3857 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio),
3858 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio),
3859 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio),
3860 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio),
3861 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio));
3864 res = hdac_command(sc,
3865 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_STREAM_FORMATS),
3867 devinfo->function.audio.supp_stream_formats = res;
3869 res = hdac_command(sc,
3870 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_PCM_SIZE_RATE),
3872 devinfo->function.audio.supp_pcm_size_rate = res;
3874 res = hdac_command(sc,
3875 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_OUTPUT_AMP_CAP),
3877 devinfo->function.audio.outamp_cap = res;
3879 res = hdac_command(sc,
3880 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_INPUT_AMP_CAP),
3882 devinfo->function.audio.inamp_cap = res;
3884 if (devinfo->nodecnt > 0)
3885 devinfo->widget = (struct hdac_widget *)kmalloc(
3886 sizeof(*(devinfo->widget)) * devinfo->nodecnt, M_HDAC,
3889 devinfo->widget = NULL;
3891 if (devinfo->widget == NULL) {
3892 device_printf(sc->dev, "unable to allocate widgets!\n");
3893 devinfo->endnode = devinfo->startnode;
3894 devinfo->nodecnt = 0;
3898 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
3899 w = hdac_widget_get(devinfo, i);
3901 device_printf(sc->dev, "Ghost widget! nid=%d!\n", i);
3903 w->devinfo = devinfo;
3909 w->param.eapdbtl = HDAC_INVALID;
3910 hdac_widget_parse(w);
3916 hdac_audio_ctl_parse(struct hdac_devinfo *devinfo)
3918 struct hdac_softc *sc = devinfo->codec->sc;
3919 struct hdac_audio_ctl *ctls;
3920 struct hdac_widget *w, *cw;
3921 int i, j, cnt, max, ocap, icap;
3922 int mute, offset, step, size;
3924 /* XXX This is redundant */
3926 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
3927 w = hdac_widget_get(devinfo, i);
3928 if (w == NULL || w->enable == 0)
3930 if (w->param.outamp_cap != 0)
3932 if (w->param.inamp_cap != 0) {
3934 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR:
3935 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER:
3936 for (j = 0; j < w->nconns; j++) {
3937 cw = hdac_widget_get(devinfo,
3939 if (cw == NULL || cw->enable == 0)
3951 devinfo->function.audio.ctlcnt = max;
3956 ctls = (struct hdac_audio_ctl *)kmalloc(
3957 sizeof(*ctls) * max, M_HDAC, M_ZERO | M_NOWAIT);
3961 device_printf(sc->dev, "unable to allocate ctls!\n");
3962 devinfo->function.audio.ctlcnt = 0;
3967 for (i = devinfo->startnode; cnt < max && i < devinfo->endnode; i++) {
3969 device_printf(sc->dev, "%s: Ctl overflow!\n",
3973 w = hdac_widget_get(devinfo, i);
3974 if (w == NULL || w->enable == 0)
3976 ocap = w->param.outamp_cap;
3977 icap = w->param.inamp_cap;
3979 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(ocap);
3980 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(ocap);
3981 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(ocap);
3982 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(ocap);
3983 /*if (offset > step) {
3985 device_printf(sc->dev,
3986 "HDA_DEBUG: BUGGY outamp: nid=%d "
3987 "[offset=%d > step=%d]\n",
3988 w->nid, offset, step);
3992 ctls[cnt].enable = 1;
3993 ctls[cnt].widget = w;
3994 ctls[cnt].mute = mute;
3995 ctls[cnt].step = step;
3996 ctls[cnt].size = size;
3997 ctls[cnt].offset = offset;
3998 ctls[cnt].left = offset;
3999 ctls[cnt].right = offset;
4000 ctls[cnt++].dir = HDA_CTL_OUT;
4004 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(icap);
4005 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(icap);
4006 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(icap);
4007 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(icap);
4008 /*if (offset > step) {
4010 device_printf(sc->dev,
4011 "HDA_DEBUG: BUGGY inamp: nid=%d "
4012 "[offset=%d > step=%d]\n",
4013 w->nid, offset, step);
4018 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR:
4019 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER:
4020 for (j = 0; j < w->nconns; j++) {
4022 device_printf(sc->dev,
4023 "%s: Ctl overflow!\n",
4027 cw = hdac_widget_get(devinfo,
4029 if (cw == NULL || cw->enable == 0)
4031 ctls[cnt].enable = 1;
4032 ctls[cnt].widget = w;
4033 ctls[cnt].childwidget = cw;
4034 ctls[cnt].index = j;
4035 ctls[cnt].mute = mute;
4036 ctls[cnt].step = step;
4037 ctls[cnt].size = size;
4038 ctls[cnt].offset = offset;
4039 ctls[cnt].left = offset;
4040 ctls[cnt].right = offset;
4041 ctls[cnt++].dir = HDA_CTL_IN;
4046 device_printf(sc->dev,
4047 "%s: Ctl overflow!\n",
4051 ctls[cnt].enable = 1;
4052 ctls[cnt].widget = w;
4053 ctls[cnt].mute = mute;
4054 ctls[cnt].step = step;
4055 ctls[cnt].size = size;
4056 ctls[cnt].offset = offset;
4057 ctls[cnt].left = offset;
4058 ctls[cnt].right = offset;
4059 ctls[cnt++].dir = HDA_CTL_IN;
4065 devinfo->function.audio.ctl = ctls;
4068 static const struct {
4071 uint32_t set, unset;
4074 * XXX Force stereo quirk. Monoural recording / playback
4075 * on few codecs (especially ALC880) seems broken or
4076 * perhaps unsupported.
4078 { HDA_MATCH_ALL, HDA_MATCH_ALL,
4079 HDA_QUIRK_FORCESTEREO | HDA_QUIRK_IVREF, 0 },
4080 { ACER_ALL_SUBVENDOR, HDA_MATCH_ALL,
4081 HDA_QUIRK_GPIO0, 0 },
4082 { ASUS_M5200_SUBVENDOR, HDA_CODEC_ALC880,
4083 HDA_QUIRK_GPIO0, 0 },
4084 { ASUS_A7M_SUBVENDOR, HDA_CODEC_ALC880,
4085 HDA_QUIRK_GPIO0, 0 },
4086 { ASUS_A7T_SUBVENDOR, HDA_CODEC_ALC882,
4087 HDA_QUIRK_GPIO0, 0 },
4088 { ASUS_W2J_SUBVENDOR, HDA_CODEC_ALC882,
4089 HDA_QUIRK_GPIO0, 0 },
4090 { ASUS_U5F_SUBVENDOR, HDA_CODEC_AD1986A,
4091 HDA_QUIRK_EAPDINV, 0 },
4092 { ASUS_A8JC_SUBVENDOR, HDA_CODEC_AD1986A,
4093 HDA_QUIRK_EAPDINV, 0 },
4094 { ASUS_F3JC_SUBVENDOR, HDA_CODEC_ALC861,
4095 HDA_QUIRK_OVREF, 0 },
4096 { ASUS_W6F_SUBVENDOR, HDA_CODEC_ALC861,
4097 HDA_QUIRK_OVREF, 0 },
4098 { UNIWILL_9075_SUBVENDOR, HDA_CODEC_ALC861,
4099 HDA_QUIRK_OVREF, 0 },
4100 /*{ ASUS_M2N_SUBVENDOR, HDA_CODEC_AD1988,
4101 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 },*/
4102 { MEDION_MD95257_SUBVENDOR, HDA_CODEC_ALC880,
4103 HDA_QUIRK_GPIO1, 0 },
4104 { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A,
4105 HDA_QUIRK_EAPDINV, 0 },
4106 { SAMSUNG_Q1_SUBVENDOR, HDA_CODEC_AD1986A,
4107 HDA_QUIRK_EAPDINV, 0 },
4108 { APPLE_INTEL_MAC, HDA_CODEC_STAC9221,
4109 HDA_QUIRK_GPIO0 | HDA_QUIRK_GPIO1, 0 },
4110 { HDA_MATCH_ALL, HDA_CODEC_AD1988,
4111 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 },
4112 { HDA_MATCH_ALL, HDA_CODEC_AD1988B,
4113 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 },
4114 { HDA_MATCH_ALL, HDA_CODEC_CXVENICE,
4115 0, HDA_QUIRK_FORCESTEREO },
4116 { HDA_MATCH_ALL, HDA_CODEC_STACXXXX,
4117 HDA_QUIRK_SOFTPCMVOL, 0 }
4119 #define HDAC_QUIRKS_LEN (sizeof(hdac_quirks) / sizeof(hdac_quirks[0]))
4122 hdac_vendor_patch_parse(struct hdac_devinfo *devinfo)
4124 struct hdac_widget *w;
4125 struct hdac_audio_ctl *ctl;
4126 uint32_t id, subvendor;
4129 id = hdac_codec_id(devinfo);
4130 subvendor = devinfo->codec->sc->pci_subvendor;
4135 for (i = 0; i < HDAC_QUIRKS_LEN; i++) {
4136 if (!(HDA_DEV_MATCH(hdac_quirks[i].model, subvendor) &&
4137 HDA_DEV_MATCH(hdac_quirks[i].id, id)))
4139 if (hdac_quirks[i].set != 0)
4140 devinfo->function.audio.quirks |=
4142 if (hdac_quirks[i].unset != 0)
4143 devinfo->function.audio.quirks &=
4144 ~(hdac_quirks[i].unset);
4148 case HDA_CODEC_ALC260:
4149 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
4150 w = hdac_widget_get(devinfo, i);
4151 if (w == NULL || w->enable == 0)
4154 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT)
4159 if (subvendor == HP_XW4300_SUBVENDOR) {
4160 ctl = hdac_audio_ctl_amp_get(devinfo, 16, 0, 1);
4161 if (ctl != NULL && ctl->widget != NULL) {
4162 ctl->ossmask = SOUND_MASK_SPEAKER;
4163 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER;
4165 ctl = hdac_audio_ctl_amp_get(devinfo, 17, 0, 1);
4166 if (ctl != NULL && ctl->widget != NULL) {
4167 ctl->ossmask = SOUND_MASK_SPEAKER;
4168 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER;
4170 } else if (subvendor == HP_3010_SUBVENDOR) {
4171 ctl = hdac_audio_ctl_amp_get(devinfo, 17, 0, 1);
4172 if (ctl != NULL && ctl->widget != NULL) {
4173 ctl->ossmask = SOUND_MASK_SPEAKER;
4174 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER;
4176 ctl = hdac_audio_ctl_amp_get(devinfo, 21, 0, 1);
4177 if (ctl != NULL && ctl->widget != NULL) {
4178 ctl->ossmask = SOUND_MASK_SPEAKER;
4179 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER;
4183 case HDA_CODEC_ALC861:
4184 ctl = hdac_audio_ctl_amp_get(devinfo, 21, 2, 1);
4186 ctl->muted = HDA_AMP_MUTE_ALL;
4188 case HDA_CODEC_ALC880:
4189 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
4190 w = hdac_widget_get(devinfo, i);
4191 if (w == NULL || w->enable == 0)
4194 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT &&
4195 w->nid != 9 && w->nid != 29) {
4197 } else if (w->type !=
4198 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET &&
4201 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET;
4202 w->param.widget_cap &=
4203 ~HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_MASK;
4204 w->param.widget_cap |=
4205 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET <<
4206 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_SHIFT;
4207 strlcpy(w->name, "beep widget", sizeof(w->name));
4211 case HDA_CODEC_ALC883:
4213 * nid: 24/25 = External (jack) or Internal (fixed) Mic.
4214 * Clear vref cap for jack connectivity.
4216 w = hdac_widget_get(devinfo, 24);
4217 if (w != NULL && w->enable != 0 && w->type ==
4218 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX &&
4219 (w->wclass.pin.config &
4220 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) ==
4221 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK)
4222 w->wclass.pin.cap &= ~(
4223 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK |
4224 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK |
4225 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK);
4226 w = hdac_widget_get(devinfo, 25);
4227 if (w != NULL && w->enable != 0 && w->type ==
4228 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX &&
4229 (w->wclass.pin.config &
4230 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) ==
4231 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK)
4232 w->wclass.pin.cap &= ~(
4233 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK |
4234 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK |
4235 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK);
4237 * nid: 26 = Line-in, leave it alone.
4240 case HDA_CODEC_AD1981HD:
4241 w = hdac_widget_get(devinfo, 11);
4242 if (w != NULL && w->enable != 0 && w->nconns > 3)
4244 if (subvendor == IBM_M52_SUBVENDOR) {
4245 ctl = hdac_audio_ctl_amp_get(devinfo, 7, 0, 1);
4247 ctl->ossmask = SOUND_MASK_SPEAKER;
4250 case HDA_CODEC_AD1986A:
4251 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
4252 w = hdac_widget_get(devinfo, i);
4253 if (w == NULL || w->enable == 0)
4256 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT)
4261 if (subvendor == ASUS_M2NPVMX_SUBVENDOR ||
4262 subvendor == ASUS_VMCSM_SUBVENDOR) {
4263 /* nid 28 is mic, nid 29 is line-in */
4264 w = hdac_widget_get(devinfo, 15);
4267 w = hdac_widget_get(devinfo, 16);
4272 case HDA_CODEC_AD1988:
4273 case HDA_CODEC_AD1988B:
4274 /*w = hdac_widget_get(devinfo, 12);
4277 w->pflags |= HDA_ADC_LOCKED;
4279 w = hdac_widget_get(devinfo, 13);
4282 w->pflags |= HDA_ADC_LOCKED;
4284 w = hdac_widget_get(devinfo, 14);
4287 w->pflags |= HDA_ADC_LOCKED;
4289 ctl = hdac_audio_ctl_amp_get(devinfo, 57, 0, 1);
4291 ctl->ossmask = SOUND_MASK_IGAIN;
4292 ctl->widget->ctlflags |= SOUND_MASK_IGAIN;
4294 ctl = hdac_audio_ctl_amp_get(devinfo, 58, 0, 1);
4296 ctl->ossmask = SOUND_MASK_IGAIN;
4297 ctl->widget->ctlflags |= SOUND_MASK_IGAIN;
4299 ctl = hdac_audio_ctl_amp_get(devinfo, 60, 0, 1);
4301 ctl->ossmask = SOUND_MASK_IGAIN;
4302 ctl->widget->ctlflags |= SOUND_MASK_IGAIN;
4304 ctl = hdac_audio_ctl_amp_get(devinfo, 32, 0, 1);
4306 ctl->ossmask = SOUND_MASK_MIC | SOUND_MASK_VOLUME;
4307 ctl->widget->ctlflags |= SOUND_MASK_MIC;
4309 ctl = hdac_audio_ctl_amp_get(devinfo, 32, 4, 1);
4311 ctl->ossmask = SOUND_MASK_MIC | SOUND_MASK_VOLUME;
4312 ctl->widget->ctlflags |= SOUND_MASK_MIC;
4314 ctl = hdac_audio_ctl_amp_get(devinfo, 32, 1, 1);
4316 ctl->ossmask = SOUND_MASK_LINE | SOUND_MASK_VOLUME;
4317 ctl->widget->ctlflags |= SOUND_MASK_LINE;
4319 ctl = hdac_audio_ctl_amp_get(devinfo, 32, 7, 1);
4321 ctl->ossmask = SOUND_MASK_SPEAKER | SOUND_MASK_VOLUME;
4322 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER;
4325 case HDA_CODEC_STAC9221:
4327 * Dell XPS M1210 need all DACs for each output jacks
4329 if (subvendor == DELL_XPSM1210_SUBVENDOR)
4331 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
4332 w = hdac_widget_get(devinfo, i);
4333 if (w == NULL || w->enable == 0)
4336 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT)
4342 case HDA_CODEC_STAC9221D:
4343 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
4344 w = hdac_widget_get(devinfo, i);
4345 if (w == NULL || w->enable == 0)
4348 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT &&
4354 case HDA_CODEC_STAC9227:
4355 w = hdac_widget_get(devinfo, 8);
4358 w = hdac_widget_get(devinfo, 9);
4362 case HDA_CODEC_CXWAIKIKI:
4363 if (subvendor == HP_DV5000_SUBVENDOR) {
4364 w = hdac_widget_get(devinfo, 27);
4368 ctl = hdac_audio_ctl_amp_get(devinfo, 16, 0, 1);
4370 ctl->ossmask = SOUND_MASK_SKIP;
4371 ctl = hdac_audio_ctl_amp_get(devinfo, 25, 0, 1);
4372 if (ctl != NULL && ctl->childwidget != NULL &&
4373 ctl->childwidget->enable != 0) {
4374 ctl->ossmask = SOUND_MASK_PCM | SOUND_MASK_VOLUME;
4375 ctl->childwidget->ctlflags |= SOUND_MASK_PCM;
4377 ctl = hdac_audio_ctl_amp_get(devinfo, 25, 1, 1);
4378 if (ctl != NULL && ctl->childwidget != NULL &&
4379 ctl->childwidget->enable != 0) {
4380 ctl->ossmask = SOUND_MASK_LINE | SOUND_MASK_VOLUME;
4381 ctl->childwidget->ctlflags |= SOUND_MASK_LINE;
4383 ctl = hdac_audio_ctl_amp_get(devinfo, 25, 2, 1);
4384 if (ctl != NULL && ctl->childwidget != NULL &&
4385 ctl->childwidget->enable != 0) {
4386 ctl->ossmask = SOUND_MASK_MIC | SOUND_MASK_VOLUME;
4387 ctl->childwidget->ctlflags |= SOUND_MASK_MIC;
4389 ctl = hdac_audio_ctl_amp_get(devinfo, 26, 0, 1);
4391 ctl->ossmask = SOUND_MASK_SKIP;
4392 /* XXX mixer \=rec mic broken.. why?!? */
4393 /* ctl->widget->ctlflags |= SOUND_MASK_MIC; */
4402 hdac_audio_ctl_ossmixer_getnextdev(struct hdac_devinfo *devinfo)
4404 int *dev = &devinfo->function.audio.ossidx;
4406 while (*dev < SOUND_MIXER_NRDEVICES) {
4408 case SOUND_MIXER_VOLUME:
4409 case SOUND_MIXER_BASS:
4410 case SOUND_MIXER_TREBLE:
4411 case SOUND_MIXER_PCM:
4412 case SOUND_MIXER_SPEAKER:
4413 case SOUND_MIXER_LINE:
4414 case SOUND_MIXER_MIC:
4415 case SOUND_MIXER_CD:
4416 case SOUND_MIXER_RECLEV:
4417 case SOUND_MIXER_IGAIN:
4418 case SOUND_MIXER_OGAIN: /* reserved for EAPD switch */
4431 hdac_widget_find_dac_path(struct hdac_devinfo *devinfo, nid_t nid, int depth)
4433 struct hdac_widget *w;
4436 if (depth > HDA_PARSE_MAXDEPTH)
4438 w = hdac_widget_get(devinfo, nid);
4439 if (w == NULL || w->enable == 0)
4442 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT:
4443 w->pflags |= HDA_DAC_PATH;
4446 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER:
4447 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR:
4448 for (i = 0; i < w->nconns; i++) {
4449 if (hdac_widget_find_dac_path(devinfo,
4450 w->conns[i], depth + 1) != 0) {
4451 if (w->selconn == -1)
4454 w->pflags |= HDA_DAC_PATH;
4465 hdac_widget_find_adc_path(struct hdac_devinfo *devinfo, nid_t nid, int depth)
4467 struct hdac_widget *w;
4468 int i, conndev, ret = 0;
4470 if (depth > HDA_PARSE_MAXDEPTH)
4472 w = hdac_widget_get(devinfo, nid);
4473 if (w == NULL || w->enable == 0)
4476 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT:
4477 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR:
4478 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER:
4479 for (i = 0; i < w->nconns; i++) {
4480 if (hdac_widget_find_adc_path(devinfo, w->conns[i],
4482 if (w->selconn == -1)
4484 w->pflags |= HDA_ADC_PATH;
4489 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX:
4490 conndev = w->wclass.pin.config &
4491 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
4492 if (HDA_PARAM_PIN_CAP_INPUT_CAP(w->wclass.pin.cap) &&
4493 (conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_CD ||
4494 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN ||
4495 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN)) {
4496 w->pflags |= HDA_ADC_PATH;
4500 /*case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER:
4501 if (w->pflags & HDA_DAC_PATH) {
4502 w->pflags |= HDA_ADC_PATH;
4513 hdac_audio_ctl_outamp_build(struct hdac_devinfo *devinfo,
4514 nid_t nid, nid_t pnid, int index, int depth)
4516 struct hdac_widget *w, *pw;
4517 struct hdac_audio_ctl *ctl;
4519 int i, ossdev, conndev, strategy;
4521 if (depth > HDA_PARSE_MAXDEPTH)
4524 w = hdac_widget_get(devinfo, nid);
4525 if (w == NULL || w->enable == 0)
4528 pw = hdac_widget_get(devinfo, pnid);
4529 strategy = devinfo->function.audio.parsing_strategy;
4531 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER
4532 || w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) {
4533 for (i = 0; i < w->nconns; i++) {
4534 fl |= hdac_audio_ctl_outamp_build(devinfo, w->conns[i],
4535 w->nid, i, depth + 1);
4539 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT &&
4540 (w->pflags & HDA_DAC_PATH)) {
4542 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
4543 if (ctl->enable == 0 || ctl->widget == NULL)
4545 /* XXX This should be compressed! */
4546 if (((ctl->widget->nid == w->nid) ||
4547 (ctl->widget->nid == pnid && ctl->index == index &&
4548 (ctl->dir & HDA_CTL_IN)) ||
4549 (ctl->widget->nid == pnid && pw != NULL &&
4551 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR &&
4552 (pw->nconns < 2 || pw->selconn == index ||
4553 pw->selconn == -1) &&
4554 (ctl->dir & HDA_CTL_OUT)) ||
4555 (strategy == HDA_PARSE_DIRECT &&
4556 ctl->widget->nid == w->nid)) &&
4557 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) {
4558 /*if (pw != NULL && pw->selconn == -1)
4559 pw->selconn = index;
4560 fl |= SOUND_MASK_VOLUME;
4561 fl |= SOUND_MASK_PCM;
4562 ctl->ossmask |= SOUND_MASK_VOLUME;
4563 ctl->ossmask |= SOUND_MASK_PCM;
4564 ctl->ossdev = SOUND_MIXER_PCM;*/
4565 if (!(w->ctlflags & SOUND_MASK_PCM) ||
4567 !(pw->ctlflags & SOUND_MASK_PCM))) {
4568 fl |= SOUND_MASK_VOLUME;
4569 fl |= SOUND_MASK_PCM;
4570 ctl->ossmask |= SOUND_MASK_VOLUME;
4571 ctl->ossmask |= SOUND_MASK_PCM;
4572 ctl->ossdev = SOUND_MIXER_PCM;
4573 w->ctlflags |= SOUND_MASK_VOLUME;
4574 w->ctlflags |= SOUND_MASK_PCM;
4576 if (pw->selconn == -1)
4577 pw->selconn = index;
4588 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX &&
4589 HDA_PARAM_PIN_CAP_INPUT_CAP(w->wclass.pin.cap) &&
4590 (w->pflags & HDA_ADC_PATH)) {
4591 conndev = w->wclass.pin.config &
4592 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
4594 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
4595 if (ctl->enable == 0 || ctl->widget == NULL)
4597 /* XXX This should be compressed! */
4598 if (((ctl->widget->nid == pnid && ctl->index == index &&
4599 (ctl->dir & HDA_CTL_IN)) ||
4600 (ctl->widget->nid == pnid && pw != NULL &&
4602 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR &&
4603 (pw->nconns < 2 || pw->selconn == index ||
4604 pw->selconn == -1) &&
4605 (ctl->dir & HDA_CTL_OUT)) ||
4606 (strategy == HDA_PARSE_DIRECT &&
4607 ctl->widget->nid == w->nid)) &&
4608 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) {
4609 if (pw != NULL && pw->selconn == -1)
4610 pw->selconn = index;
4613 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN:
4614 ossdev = SOUND_MIXER_MIC;
4616 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN:
4617 ossdev = SOUND_MIXER_LINE;
4619 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD:
4620 ossdev = SOUND_MIXER_CD;
4624 hdac_audio_ctl_ossmixer_getnextdev(
4630 if (strategy == HDA_PARSE_MIXER) {
4631 fl |= SOUND_MASK_VOLUME;
4632 ctl->ossmask |= SOUND_MASK_VOLUME;
4635 ctl->ossmask |= 1 << ossdev;
4636 ctl->ossdev = ossdev;
4641 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) {
4643 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
4644 if (ctl->enable == 0 || ctl->widget == NULL)
4646 /* XXX This should be compressed! */
4647 if (((ctl->widget->nid == pnid && ctl->index == index &&
4648 (ctl->dir & HDA_CTL_IN)) ||
4649 (ctl->widget->nid == pnid && pw != NULL &&
4651 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR &&
4652 (pw->nconns < 2 || pw->selconn == index ||
4653 pw->selconn == -1) &&
4654 (ctl->dir & HDA_CTL_OUT)) ||
4655 (strategy == HDA_PARSE_DIRECT &&
4656 ctl->widget->nid == w->nid)) &&
4657 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) {
4658 if (pw != NULL && pw->selconn == -1)
4659 pw->selconn = index;
4660 fl |= SOUND_MASK_VOLUME;
4661 fl |= SOUND_MASK_SPEAKER;
4662 ctl->ossmask |= SOUND_MASK_VOLUME;
4663 ctl->ossmask |= SOUND_MASK_SPEAKER;
4664 ctl->ossdev = SOUND_MIXER_SPEAKER;
4674 hdac_audio_ctl_inamp_build(struct hdac_devinfo *devinfo, nid_t nid, int depth)
4676 struct hdac_widget *w, *cw;
4677 struct hdac_audio_ctl *ctl;
4681 if (depth > HDA_PARSE_MAXDEPTH)
4684 w = hdac_widget_get(devinfo, nid);
4685 if (w == NULL || w->enable == 0)
4687 /*if (!(w->pflags & HDA_ADC_PATH))
4689 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT ||
4690 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR))
4693 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
4694 if (ctl->enable == 0 || ctl->widget == NULL)
4696 if (ctl->widget->nid == nid) {
4697 ctl->ossmask |= SOUND_MASK_RECLEV;
4698 w->ctlflags |= SOUND_MASK_RECLEV;
4699 return (SOUND_MASK_RECLEV);
4702 for (i = 0; i < w->nconns; i++) {
4703 cw = hdac_widget_get(devinfo, w->conns[i]);
4704 if (cw == NULL || cw->enable == 0)
4706 if (cw->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)
4708 fl = hdac_audio_ctl_inamp_build(devinfo, cw->nid, depth + 1);
4719 hdac_audio_ctl_recsel_build(struct hdac_devinfo *devinfo, nid_t nid, int depth)
4721 struct hdac_widget *w, *cw;
4724 if (depth > HDA_PARSE_MAXDEPTH)
4727 w = hdac_widget_get(devinfo, nid);
4728 if (w == NULL || w->enable == 0)
4730 /*if (!(w->pflags & HDA_ADC_PATH))
4732 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT ||
4733 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR))
4736 for (i = 0; i < w->nconns; i++) {
4737 cw = hdac_widget_get(devinfo, w->conns[i]);
4741 w->pflags |= HDA_ADC_RECSEL;
4745 for (i = 0; i < w->nconns; i++) {
4746 if (hdac_audio_ctl_recsel_build(devinfo,
4747 w->conns[i], depth + 1) != 0)
4754 hdac_audio_build_tree_strategy(struct hdac_devinfo *devinfo)
4756 struct hdac_widget *w, *cw;
4757 int i, j, conndev, found_dac = 0;
4760 strategy = devinfo->function.audio.parsing_strategy;
4762 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
4763 w = hdac_widget_get(devinfo, i);
4764 if (w == NULL || w->enable == 0)
4766 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
4768 if (!HDA_PARAM_PIN_CAP_OUTPUT_CAP(w->wclass.pin.cap))
4770 conndev = w->wclass.pin.config &
4771 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
4772 if (!(conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT ||
4773 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER ||
4774 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT))
4776 for (j = 0; j < w->nconns; j++) {
4777 cw = hdac_widget_get(devinfo, w->conns[j]);
4778 if (cw == NULL || cw->enable == 0)
4780 if (strategy == HDA_PARSE_MIXER && !(cw->type ==
4781 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER ||
4783 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR))
4785 if (hdac_widget_find_dac_path(devinfo, cw->nid, 0)
4787 if (w->selconn == -1)
4789 w->pflags |= HDA_DAC_PATH;
4799 hdac_audio_build_tree(struct hdac_devinfo *devinfo)
4801 struct hdac_widget *w;
4802 struct hdac_audio_ctl *ctl;
4803 int i, j, dacs, strategy;
4805 /* Construct DAC path */
4806 strategy = HDA_PARSE_MIXER;
4807 devinfo->function.audio.parsing_strategy = strategy;
4809 device_printf(devinfo->codec->sc->dev,
4810 "HDA_DEBUG: HWiP: HDA Widget Parser - Revision %d\n",
4811 HDA_WIDGET_PARSER_REV);
4813 dacs = hdac_audio_build_tree_strategy(devinfo);
4816 device_printf(devinfo->codec->sc->dev,
4817 "HDA_DEBUG: HWiP: 0 DAC path found! "
4819 "using HDA_PARSE_DIRECT strategy.\n");
4821 strategy = HDA_PARSE_DIRECT;
4822 devinfo->function.audio.parsing_strategy = strategy;
4823 dacs = hdac_audio_build_tree_strategy(devinfo);
4827 device_printf(devinfo->codec->sc->dev,
4828 "HDA_DEBUG: HWiP: Found %d DAC path using HDA_PARSE_%s "
4830 dacs, (strategy == HDA_PARSE_MIXER) ? "MIXER" : "DIRECT");
4833 /* Construct ADC path */
4834 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
4835 w = hdac_widget_get(devinfo, i);
4836 if (w == NULL || w->enable == 0)
4838 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT)
4840 (void)hdac_widget_find_adc_path(devinfo, w->nid, 0);
4844 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
4845 w = hdac_widget_get(devinfo, i);
4846 if (w == NULL || w->enable == 0)
4848 if ((strategy == HDA_PARSE_MIXER &&
4849 (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER ||
4850 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)
4851 && (w->pflags & HDA_DAC_PATH)) ||
4852 (strategy == HDA_PARSE_DIRECT && (w->pflags &
4853 (HDA_DAC_PATH | HDA_ADC_PATH)))) {
4854 w->ctlflags |= hdac_audio_ctl_outamp_build(devinfo,
4855 w->nid, devinfo->startnode - 1, 0, 0);
4856 } else if (w->type ==
4857 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) {
4859 while ((ctl = hdac_audio_ctl_each(devinfo, &j)) !=
4861 if (ctl->enable == 0 || ctl->widget == NULL)
4863 if (ctl->widget->nid != w->nid)
4865 ctl->ossmask |= SOUND_MASK_VOLUME;
4866 ctl->ossmask |= SOUND_MASK_SPEAKER;
4867 ctl->ossdev = SOUND_MIXER_SPEAKER;
4868 w->ctlflags |= SOUND_MASK_VOLUME;
4869 w->ctlflags |= SOUND_MASK_SPEAKER;
4874 /* Input mixers (rec) */
4875 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
4876 w = hdac_widget_get(devinfo, i);
4877 if (w == NULL || w->enable == 0)
4879 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT &&
4880 w->pflags & HDA_ADC_PATH))
4882 hdac_audio_ctl_inamp_build(devinfo, w->nid, 0);
4883 hdac_audio_ctl_recsel_build(devinfo, w->nid, 0);
4887 #define HDA_COMMIT_CONN (1 << 0)
4888 #define HDA_COMMIT_CTRL (1 << 1)
4889 #define HDA_COMMIT_EAPD (1 << 2)
4890 #define HDA_COMMIT_GPIO (1 << 3)
4891 #define HDA_COMMIT_MISC (1 << 4)
4892 #define HDA_COMMIT_ALL (HDA_COMMIT_CONN | HDA_COMMIT_CTRL | \
4893 HDA_COMMIT_EAPD | HDA_COMMIT_GPIO | HDA_COMMIT_MISC)
4896 hdac_audio_commit(struct hdac_devinfo *devinfo, uint32_t cfl)
4898 struct hdac_softc *sc = devinfo->codec->sc;
4899 struct hdac_widget *w;
4903 if (!(cfl & HDA_COMMIT_ALL))
4906 cad = devinfo->codec->cad;
4908 if ((cfl & HDA_COMMIT_MISC)) {
4909 if (sc->pci_subvendor == APPLE_INTEL_MAC)
4910 hdac_command(sc, HDA_CMD_12BIT(cad, devinfo->nid,
4914 if (cfl & HDA_COMMIT_GPIO) {
4915 uint32_t gdata, gmask, gdir;
4916 int commitgpio, numgpio;
4923 numgpio = HDA_PARAM_GPIO_COUNT_NUM_GPIO(
4924 devinfo->function.audio.gpio);
4926 if (devinfo->function.audio.quirks & HDA_QUIRK_GPIOFLUSH)
4927 commitgpio = (numgpio > 0) ? 1 : 0;
4929 for (i = 0; i < numgpio && i < HDA_GPIO_MAX; i++) {
4930 if (!(devinfo->function.audio.quirks &
4933 if (commitgpio == 0) {
4936 gdata = hdac_command(sc,
4937 HDA_CMD_GET_GPIO_DATA(cad,
4938 devinfo->nid), cad);
4939 gmask = hdac_command(sc,
4940 HDA_CMD_GET_GPIO_ENABLE_MASK(cad,
4941 devinfo->nid), cad);
4942 gdir = hdac_command(sc,
4943 HDA_CMD_GET_GPIO_DIRECTION(cad,
4944 devinfo->nid), cad);
4945 device_printf(sc->dev,
4946 "GPIO init: data=0x%08x "
4947 "mask=0x%08x dir=0x%08x\n",
4948 gdata, gmask, gdir);
4960 if (commitgpio != 0) {
4962 device_printf(sc->dev,
4963 "GPIO commit: data=0x%08x mask=0x%08x "
4965 gdata, gmask, gdir);
4968 HDA_CMD_SET_GPIO_ENABLE_MASK(cad, devinfo->nid,
4971 HDA_CMD_SET_GPIO_DIRECTION(cad, devinfo->nid,
4974 HDA_CMD_SET_GPIO_DATA(cad, devinfo->nid,
4979 for (i = 0; i < devinfo->nodecnt; i++) {
4980 w = &devinfo->widget[i];
4981 if (w == NULL || w->enable == 0)
4983 if (cfl & HDA_COMMIT_CONN) {
4984 if (w->selconn == -1)
4987 hdac_widget_connection_select(w, w->selconn);
4989 if ((cfl & HDA_COMMIT_CTRL) &&
4990 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) {
4993 pincap = w->wclass.pin.cap;
4995 if ((w->pflags & (HDA_DAC_PATH | HDA_ADC_PATH)) ==
4996 (HDA_DAC_PATH | HDA_ADC_PATH))
4997 device_printf(sc->dev, "WARNING: node %d "
4998 "participate both for DAC/ADC!\n", w->nid);
4999 if (w->pflags & HDA_DAC_PATH) {
5000 w->wclass.pin.ctrl &=
5001 ~HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE;
5002 if ((w->wclass.pin.config &
5003 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) !=
5004 HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT)
5005 w->wclass.pin.ctrl &=
5006 ~HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE;
5007 if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF100) &&
5008 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap))
5009 w->wclass.pin.ctrl |=
5010 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE(
5011 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100);
5012 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF80) &&
5013 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap))
5014 w->wclass.pin.ctrl |=
5015 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE(
5016 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80);
5017 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF50) &&
5018 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap))
5019 w->wclass.pin.ctrl |=
5020 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE(
5021 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50);
5022 } else if (w->pflags & HDA_ADC_PATH) {
5023 w->wclass.pin.ctrl &=
5024 ~(HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE |
5025 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE);
5026 if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF100) &&
5027 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap))
5028 w->wclass.pin.ctrl |=
5029 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE(
5030 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100);
5031 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF80) &&
5032 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap))
5033 w->wclass.pin.ctrl |=
5034 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE(
5035 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80);
5036 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF50) &&
5037 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap))
5038 w->wclass.pin.ctrl |=
5039 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE(
5040 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50);
5042 w->wclass.pin.ctrl &= ~(
5043 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE |
5044 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE |
5045 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE |
5046 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK);
5048 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid,
5049 w->wclass.pin.ctrl), cad);
5051 if ((cfl & HDA_COMMIT_EAPD) &&
5052 w->param.eapdbtl != HDAC_INVALID) {
5055 val = w->param.eapdbtl;
5056 if (devinfo->function.audio.quirks &
5058 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD;
5060 HDA_CMD_SET_EAPD_BTL_ENABLE(cad, w->nid,
5069 hdac_audio_ctl_commit(struct hdac_devinfo *devinfo)
5071 struct hdac_softc *sc = devinfo->codec->sc;
5072 struct hdac_audio_ctl *ctl;
5075 devinfo->function.audio.mvol = 100 | (100 << 8);
5077 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
5078 if (ctl->enable == 0 || ctl->widget == NULL) {
5080 device_printf(sc->dev, "[%2d] Ctl nid=%d",
5081 i, (ctl->widget != NULL) ?
5082 ctl->widget->nid : -1);
5083 if (ctl->childwidget != NULL)
5084 kprintf(" childnid=%d",
5085 ctl->childwidget->nid);
5086 if (ctl->widget == NULL)
5087 kprintf(" NULL WIDGET!");
5088 kprintf(" DISABLED\n");
5093 if (ctl->ossmask == 0) {
5094 device_printf(sc->dev, "[%2d] Ctl nid=%d",
5095 i, ctl->widget->nid);
5096 if (ctl->childwidget != NULL)
5097 kprintf(" childnid=%d",
5098 ctl->childwidget->nid);
5099 kprintf(" Bind to NONE\n");
5102 if (ctl->step > 0) {
5103 ctl->ossval = (ctl->left * 100) / ctl->step;
5104 ctl->ossval |= ((ctl->right * 100) / ctl->step) << 8;
5107 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_DEFAULT,
5108 ctl->left, ctl->right);
5113 hdac_pcmchannel_setup(struct hdac_devinfo *devinfo, int dir)
5115 struct hdac_chan *ch;
5116 struct hdac_widget *w;
5117 uint32_t cap, fmtcap, pcmcap, path;
5118 int i, type, ret, max;
5120 if (dir == PCMDIR_PLAY) {
5121 type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT;
5122 ch = &devinfo->codec->sc->play;
5123 path = HDA_DAC_PATH;
5125 type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT;
5126 ch = &devinfo->codec->sc->rec;
5127 path = HDA_ADC_PATH;
5130 ch->caps = hdac_caps;
5131 ch->caps.fmtlist = ch->fmtlist;
5134 ch->pcmrates[0] = 48000;
5135 ch->pcmrates[1] = 0;
5138 fmtcap = devinfo->function.audio.supp_stream_formats;
5139 pcmcap = devinfo->function.audio.supp_pcm_size_rate;
5140 max = (sizeof(ch->io) / sizeof(ch->io[0])) - 1;
5142 for (i = devinfo->startnode; i < devinfo->endnode && ret < max; i++) {
5143 w = hdac_widget_get(devinfo, i);
5144 if (w == NULL || w->enable == 0 || w->type != type ||
5145 !(w->pflags & path))
5147 cap = w->param.widget_cap;
5148 /*if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(cap))
5150 if (!HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(cap))
5152 cap = w->param.supp_stream_formats;
5153 /*if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) {
5155 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) {
5157 if (!HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap))
5160 fmtcap = w->param.supp_stream_formats;
5161 pcmcap = w->param.supp_pcm_size_rate;
5163 fmtcap &= w->param.supp_stream_formats;
5164 pcmcap &= w->param.supp_pcm_size_rate;
5170 ch->supp_stream_formats = fmtcap;
5171 ch->supp_pcm_size_rate = pcmcap;
5182 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap))
5184 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap))
5186 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap))
5188 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap))
5190 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap))
5193 if (!(devinfo->function.audio.quirks & HDA_QUIRK_FORCESTEREO))
5194 ch->fmtlist[i++] = AFMT_S16_LE;
5195 ch->fmtlist[i++] = AFMT_S16_LE | AFMT_STEREO;
5196 if (ch->bit32 > 0) {
5197 if (!(devinfo->function.audio.quirks &
5198 HDA_QUIRK_FORCESTEREO))
5199 ch->fmtlist[i++] = AFMT_S32_LE;
5200 ch->fmtlist[i++] = AFMT_S32_LE | AFMT_STEREO;
5204 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap))
5205 ch->pcmrates[i++] = 8000;
5206 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap))
5207 ch->pcmrates[i++] = 11025;
5208 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap))
5209 ch->pcmrates[i++] = 16000;
5210 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap))
5211 ch->pcmrates[i++] = 22050;
5212 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap))
5213 ch->pcmrates[i++] = 32000;
5214 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap))
5215 ch->pcmrates[i++] = 44100;
5216 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ(cap)) */
5217 ch->pcmrates[i++] = 48000;
5218 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap))
5219 ch->pcmrates[i++] = 88200;
5220 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap))
5221 ch->pcmrates[i++] = 96000;
5222 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap))
5223 ch->pcmrates[i++] = 176400;
5224 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap))
5225 ch->pcmrates[i++] = 192000;
5226 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ(cap)) */
5227 ch->pcmrates[i] = 0;
5229 ch->caps.minspeed = ch->pcmrates[0];
5230 ch->caps.maxspeed = ch->pcmrates[i - 1];
5238 hdac_dump_ctls(struct hdac_devinfo *devinfo, const char *banner, uint32_t flag)
5240 struct hdac_audio_ctl *ctl;
5241 struct hdac_softc *sc = devinfo->codec->sc;
5247 fl = SOUND_MASK_VOLUME | SOUND_MASK_PCM |
5248 SOUND_MASK_CD | SOUND_MASK_LINE | SOUND_MASK_RECLEV |
5249 SOUND_MASK_MIC | SOUND_MASK_SPEAKER | SOUND_MASK_OGAIN;
5253 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
5254 if (ctl->enable == 0 || ctl->widget == NULL ||
5255 ctl->widget->enable == 0 || (ctl->ossmask &
5256 (SOUND_MASK_SKIP | SOUND_MASK_DISABLE)))
5258 if ((flag == 0 && (ctl->ossmask & ~fl)) ||
5259 (flag != 0 && (ctl->ossmask & flag))) {
5260 if (banner != NULL) {
5261 device_printf(sc->dev, "\n");
5262 device_printf(sc->dev, "%s\n", banner);
5264 goto hdac_ctl_dump_it_all;
5270 hdac_ctl_dump_it_all:
5272 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
5273 if (ctl->enable == 0 || ctl->widget == NULL ||
5274 ctl->widget->enable == 0)
5276 if (!((flag == 0 && (ctl->ossmask & ~fl)) ||
5277 (flag != 0 && (ctl->ossmask & flag))))
5280 device_printf(sc->dev, "\n");
5281 device_printf(sc->dev, "Unknown Ctl (OSS: %s)\n",
5282 hdac_audio_ctl_ossmixer_mask2name(ctl->ossmask));
5284 device_printf(sc->dev, " |\n");
5285 device_printf(sc->dev, " +- nid: %2d index: %2d ",
5286 ctl->widget->nid, ctl->index);
5287 if (ctl->childwidget != NULL)
5288 kprintf("(nid: %2d) ", ctl->childwidget->nid);
5291 kprintf("mute: %d step: %3d size: %3d off: %3d dir=0x%x ossmask=0x%08x\n",
5292 ctl->mute, ctl->step, ctl->size, ctl->offset, ctl->dir,
5298 hdac_dump_audio_formats(struct hdac_softc *sc, uint32_t fcap, uint32_t pcmcap)
5304 device_printf(sc->dev, " Stream cap: 0x%08x\n", cap);
5305 device_printf(sc->dev, " Format:");
5306 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap))
5308 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap))
5309 kprintf(" FLOAT32");
5310 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap))
5316 device_printf(sc->dev, " PCM cap: 0x%08x\n", cap);
5317 device_printf(sc->dev, " PCM size:");
5318 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap))
5320 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap))
5322 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap))
5324 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap))
5326 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap))
5329 device_printf(sc->dev, " PCM rate:");
5330 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap))
5332 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap))
5334 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap))
5336 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap))
5338 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap))
5340 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap))
5343 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap))
5345 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap))
5347 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap))
5349 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap))
5356 hdac_dump_pin(struct hdac_softc *sc, struct hdac_widget *w)
5358 uint32_t pincap, wcap;
5360 pincap = w->wclass.pin.cap;
5361 wcap = w->param.widget_cap;
5363 device_printf(sc->dev, " Pin cap: 0x%08x\n", pincap);
5364 device_printf(sc->dev, " ");
5365 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap))
5367 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap))
5369 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap))
5371 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap))
5373 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap))
5375 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap))
5377 if (HDA_PARAM_PIN_CAP_BALANCED_IO_PINS(pincap))
5379 if (HDA_PARAM_PIN_CAP_VREF_CTRL(pincap)) {
5381 if (HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap))
5383 if (HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap))
5385 if (HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap))
5387 if (HDA_PARAM_PIN_CAP_VREF_CTRL_GROUND(pincap))
5389 if (HDA_PARAM_PIN_CAP_VREF_CTRL_HIZ(pincap))
5393 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap))
5395 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(wcap))
5396 kprintf(" : UNSOL");
5398 device_printf(sc->dev, " Pin config: 0x%08x\n",
5399 w->wclass.pin.config);
5400 device_printf(sc->dev, " Pin control: 0x%08x", w->wclass.pin.ctrl);
5401 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE)
5403 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE)
5405 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE)
5411 hdac_dump_amp(struct hdac_softc *sc, uint32_t cap, char *banner)
5413 device_printf(sc->dev, " %s amp: 0x%08x\n", banner, cap);
5414 device_printf(sc->dev, " "
5415 "mute=%d step=%d size=%d offset=%d\n",
5416 HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(cap),
5417 HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(cap),
5418 HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(cap),
5419 HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(cap));
5423 hdac_dump_nodes(struct hdac_devinfo *devinfo)
5425 struct hdac_softc *sc = devinfo->codec->sc;
5426 struct hdac_widget *w, *cw;
5429 device_printf(sc->dev, "\n");
5430 device_printf(sc->dev, "Default Parameter\n");
5431 device_printf(sc->dev, "-----------------\n");
5432 hdac_dump_audio_formats(sc,
5433 devinfo->function.audio.supp_stream_formats,
5434 devinfo->function.audio.supp_pcm_size_rate);
5435 device_printf(sc->dev, " IN amp: 0x%08x\n",
5436 devinfo->function.audio.inamp_cap);
5437 device_printf(sc->dev, " OUT amp: 0x%08x\n",
5438 devinfo->function.audio.outamp_cap);
5439 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
5440 w = hdac_widget_get(devinfo, i);
5442 device_printf(sc->dev, "Ghost widget nid=%d\n", i);
5445 device_printf(sc->dev, "\n");
5446 device_printf(sc->dev, " nid: %d [%s]%s\n", w->nid,
5447 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap) ?
5448 "DIGITAL" : "ANALOG",
5449 (w->enable == 0) ? " [DISABLED]" : "");
5450 device_printf(sc->dev, " name: %s\n", w->name);
5451 device_printf(sc->dev, " widget_cap: 0x%08x\n",
5452 w->param.widget_cap);
5453 device_printf(sc->dev, " Parse flags: 0x%08x\n",
5455 device_printf(sc->dev, " Ctl flags: 0x%08x\n",
5457 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT ||
5458 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) {
5459 hdac_dump_audio_formats(sc,
5460 w->param.supp_stream_formats,
5461 w->param.supp_pcm_size_rate);
5462 } else if (w->type ==
5463 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
5464 hdac_dump_pin(sc, w);
5465 if (w->param.eapdbtl != HDAC_INVALID)
5466 device_printf(sc->dev, " EAPD: 0x%08x\n",
5468 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(w->param.widget_cap) &&
5469 w->param.outamp_cap != 0)
5470 hdac_dump_amp(sc, w->param.outamp_cap, "Output");
5471 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(w->param.widget_cap) &&
5472 w->param.inamp_cap != 0)
5473 hdac_dump_amp(sc, w->param.inamp_cap, " Input");
5474 device_printf(sc->dev, " connections: %d\n", w->nconns);
5475 for (j = 0; j < w->nconns; j++) {
5476 cw = hdac_widget_get(devinfo, w->conns[j]);
5477 device_printf(sc->dev, " |\n");
5478 device_printf(sc->dev, " + <- nid=%d [%s]",
5479 w->conns[j], (cw == NULL) ? "GHOST!" : cw->name);
5481 kprintf(" [UNKNOWN]");
5482 else if (cw->enable == 0)
5483 kprintf(" [DISABLED]");
5484 if (w->nconns > 1 && w->selconn == j && w->type !=
5485 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER)
5486 kprintf(" (selected)");
5494 hdac_dump_dac_internal(struct hdac_devinfo *devinfo, nid_t nid, int depth)
5496 struct hdac_widget *w, *cw;
5497 struct hdac_softc *sc = devinfo->codec->sc;
5500 if (depth > HDA_PARSE_MAXDEPTH)
5503 w = hdac_widget_get(devinfo, nid);
5504 if (w == NULL || w->enable == 0 || !(w->pflags & HDA_DAC_PATH))
5507 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) {
5508 device_printf(sc->dev, "\n");
5509 device_printf(sc->dev, " nid=%d [%s]\n", w->nid, w->name);
5510 device_printf(sc->dev, " ^\n");
5511 device_printf(sc->dev, " |\n");
5512 device_printf(sc->dev, " +-----<------+\n");
5514 device_printf(sc->dev, " ^\n");
5515 device_printf(sc->dev, " |\n");
5516 device_printf(sc->dev, " ");
5517 kprintf(" nid=%d [%s]\n", w->nid, w->name);
5520 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) {
5522 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) {
5523 for (i = 0; i < w->nconns; i++) {
5524 cw = hdac_widget_get(devinfo, w->conns[i]);
5525 if (cw == NULL || cw->enable == 0 || cw->type ==
5526 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
5528 if (hdac_dump_dac_internal(devinfo, cw->nid,
5532 } else if ((w->type ==
5533 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR ||
5534 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) &&
5535 w->selconn > -1 && w->selconn < w->nconns) {
5536 if (hdac_dump_dac_internal(devinfo, w->conns[w->selconn],
5545 hdac_dump_dac(struct hdac_devinfo *devinfo)
5547 struct hdac_widget *w;
5548 struct hdac_softc *sc = devinfo->codec->sc;
5551 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
5552 w = hdac_widget_get(devinfo, i);
5553 if (w == NULL || w->enable == 0)
5555 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX ||
5556 !(w->pflags & HDA_DAC_PATH))
5560 device_printf(sc->dev, "\n");
5561 device_printf(sc->dev, "Playback path:\n");
5563 hdac_dump_dac_internal(devinfo, w->nid, 0);
5568 hdac_dump_adc(struct hdac_devinfo *devinfo)
5570 struct hdac_widget *w, *cw;
5571 struct hdac_softc *sc = devinfo->codec->sc;
5576 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
5577 w = hdac_widget_get(devinfo, i);
5578 if (w == NULL || w->enable == 0)
5580 if (!(w->pflags & HDA_ADC_RECSEL))
5584 device_printf(sc->dev, "\n");
5585 device_printf(sc->dev, "Recording sources:\n");
5587 device_printf(sc->dev, "\n");
5588 device_printf(sc->dev, " nid=%d [%s]\n", w->nid, w->name);
5589 for (j = 0; j < w->nconns; j++) {
5590 cw = hdac_widget_get(devinfo, w->conns[j]);
5591 if (cw == NULL || cw->enable == 0)
5593 hdac_audio_ctl_ossmixer_mask2allname(cw->ctlflags,
5594 ossdevs, sizeof(ossdevs));
5595 device_printf(sc->dev, " |\n");
5596 device_printf(sc->dev, " + <- nid=%d [%s]",
5598 if (strlen(ossdevs) > 0) {
5599 kprintf(" [recsrc: %s]", ossdevs);
5607 hdac_dump_pcmchannels(struct hdac_softc *sc, int pcnt, int rcnt)
5612 device_printf(sc->dev, "\n");
5613 device_printf(sc->dev, " PCM Playback: %d\n", pcnt);
5614 hdac_dump_audio_formats(sc, sc->play.supp_stream_formats,
5615 sc->play.supp_pcm_size_rate);
5616 device_printf(sc->dev, " DAC:");
5617 for (nids = sc->play.io; *nids != -1; nids++)
5618 kprintf(" %d", *nids);
5623 device_printf(sc->dev, "\n");
5624 device_printf(sc->dev, " PCM Record: %d\n", rcnt);
5625 hdac_dump_audio_formats(sc, sc->play.supp_stream_formats,
5626 sc->rec.supp_pcm_size_rate);
5627 device_printf(sc->dev, " ADC:");
5628 for (nids = sc->rec.io; *nids != -1; nids++)
5629 kprintf(" %d", *nids);
5635 hdac_release_resources(struct hdac_softc *sc)
5637 struct hdac_devinfo *devinfo = NULL;
5638 device_t *devlist = NULL;
5647 callout_stop(&sc->poll_hda);
5648 callout_stop(&sc->poll_hdac);
5649 callout_stop(&sc->poll_jack);
5655 /* give pending interrupts stuck on the lock a chance to clear */
5657 tsleep(&sc->irq, 0, "hdaslp", hz / 10);
5659 device_get_children(sc->dev, &devlist, &devcount);
5660 for (i = 0; devlist != NULL && i < devcount; i++) {
5661 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]);
5662 if (devinfo == NULL)
5664 if (devinfo->widget != NULL)
5665 kfree(devinfo->widget, M_HDAC);
5666 if (devinfo->node_type ==
5667 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO &&
5668 devinfo->function.audio.ctl != NULL)
5669 kfree(devinfo->function.audio.ctl, M_HDAC);
5670 kfree(devinfo, M_HDAC);
5671 device_delete_child(sc->dev, devlist[i]);
5673 if (devlist != NULL)
5674 kfree(devlist, M_TEMP);
5676 for (i = 0; i < HDAC_CODEC_MAX; i++) {
5677 if (sc->codecs[i] != NULL)
5678 kfree(sc->codecs[i], M_HDAC);
5679 sc->codecs[i] = NULL;
5682 hdac_dma_free(sc, &sc->pos_dma);
5683 hdac_dma_free(sc, &sc->rirb_dma);
5684 hdac_dma_free(sc, &sc->corb_dma);
5685 if (sc->play.blkcnt > 0)
5686 hdac_dma_free(sc, &sc->play.bdl_dma);
5687 if (sc->rec.blkcnt > 0)
5688 hdac_dma_free(sc, &sc->rec.bdl_dma);
5689 if (sc->chan_dmat != NULL) {
5690 bus_dma_tag_destroy(sc->chan_dmat);
5691 sc->chan_dmat = NULL;
5694 snd_mtxfree(sc->lock);
5695 kfree(sc, M_DEVBUF);
5698 /* This function surely going to make its way into upper level someday. */
5700 hdac_config_fetch(struct hdac_softc *sc, uint32_t *on, uint32_t *off)
5703 int i = 0, j, k, len, inv;
5711 if (resource_string_value(device_get_name(sc->dev),
5712 device_get_unit(sc->dev), "config", &res) != 0)
5714 if (!(res != NULL && strlen(res) > 0))
5717 device_printf(sc->dev, "HDA_DEBUG: HDA Config:");
5720 while (res[i] != '\0' &&
5721 (res[i] == ',' || isspace(res[i]) != 0))
5723 if (res[i] == '\0') {
5730 while (res[j] != '\0' &&
5731 !(res[j] == ',' || isspace(res[j]) != 0))
5734 if (len > 2 && strncmp(res + i, "no", 2) == 0)
5738 for (k = 0; len > inv && k < HDAC_QUIRKS_TAB_LEN; k++) {
5739 if (strncmp(res + i + inv,
5740 hdac_quirks_tab[k].key, len - inv) != 0)
5742 if (len - inv != strlen(hdac_quirks_tab[k].key))
5745 kprintf(" %s%s", (inv != 0) ? "no" : "",
5746 hdac_quirks_tab[k].key);
5748 if (inv == 0 && on != NULL)
5749 *on |= hdac_quirks_tab[k].value;
5750 else if (inv != 0 && off != NULL)
5751 *off |= hdac_quirks_tab[k].value;
5758 #ifdef SND_DYNSYSCTL
5760 sysctl_hdac_polling(SYSCTL_HANDLER_ARGS)
5762 struct hdac_softc *sc;
5763 struct hdac_devinfo *devinfo;
5768 dev = oidp->oid_arg1;
5769 devinfo = pcm_getdevinfo(dev);
5770 if (devinfo == NULL || devinfo->codec == NULL ||
5771 devinfo->codec->sc == NULL)
5773 sc = devinfo->codec->sc;
5777 err = sysctl_handle_int(oidp, &val, 0, req);
5779 if (err != 0 || req->newptr == NULL)
5781 if (val < 0 || val > 1)
5785 if (val != sc->polling) {
5786 if (hda_chan_active(sc) != 0)
5788 else if (val == 0) {
5789 callout_stop(&sc->poll_hdac);
5792 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT,
5794 ctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL);
5795 ctl |= HDAC_RIRBCTL_RINTCTL;
5796 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, ctl);
5797 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL,
5798 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE);
5802 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 0);
5803 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, 0);
5804 ctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL);
5805 ctl &= ~HDAC_RIRBCTL_RINTCTL;
5806 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, ctl);
5807 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback,
5819 sysctl_hdac_polling_interval(SYSCTL_HANDLER_ARGS)
5821 struct hdac_softc *sc;
5822 struct hdac_devinfo *devinfo;
5826 dev = oidp->oid_arg1;
5827 devinfo = pcm_getdevinfo(dev);
5828 if (devinfo == NULL || devinfo->codec == NULL ||
5829 devinfo->codec->sc == NULL)
5831 sc = devinfo->codec->sc;
5833 val = ((uint64_t)sc->poll_ival * 1000) / hz;
5835 err = sysctl_handle_int(oidp, &val, 0, req);
5837 if (err != 0 || req->newptr == NULL)
5844 val = ((uint64_t)val * hz) / 1000;
5851 sc->poll_ival = val;
5859 sysctl_hdac_dump(SYSCTL_HANDLER_ARGS)
5861 struct hdac_softc *sc;
5862 struct hdac_devinfo *devinfo;
5863 struct hdac_widget *w;
5865 uint32_t res, execres;
5869 dev = oidp->oid_arg1;
5870 devinfo = pcm_getdevinfo(dev);
5871 if (devinfo == NULL || devinfo->codec == NULL ||
5872 devinfo->codec->sc == NULL)
5875 err = sysctl_handle_int(oidp, &val, 0, req);
5876 if (err != 0 || req->newptr == NULL || val == 0)
5878 sc = devinfo->codec->sc;
5879 cad = devinfo->codec->cad;
5881 device_printf(dev, "HDAC Dump AFG [nid=%d]:\n", devinfo->nid);
5882 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
5883 w = hdac_widget_get(devinfo, i);
5884 if (w == NULL || w->type !=
5885 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
5887 execres = hdac_command(sc, HDA_CMD_SET_PIN_SENSE(cad, w->nid, 0),
5889 res = hdac_command(sc, HDA_CMD_GET_PIN_SENSE(cad, w->nid), cad);
5890 device_printf(dev, "nid=%-3d exec=0x%08x sense=0x%08x [%s]\n",
5891 w->nid, execres, res,
5892 (w->enable == 0) ? "DISABLED" : "ENABLED");
5895 "NumGPIO=%d NumGPO=%d NumGPI=%d GPIWake=%d GPIUnsol=%d\n",
5896 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio),
5897 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio),
5898 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio),
5899 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio),
5900 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio));
5901 if (1 || HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio) > 0) {
5902 device_printf(dev, " GPI:");
5903 res = hdac_command(sc,
5904 HDA_CMD_GET_GPI_DATA(cad, devinfo->nid), cad);
5905 kprintf(" data=0x%08x", res);
5906 res = hdac_command(sc,
5907 HDA_CMD_GET_GPI_WAKE_ENABLE_MASK(cad, devinfo->nid),
5909 kprintf(" wake=0x%08x", res);
5910 res = hdac_command(sc,
5911 HDA_CMD_GET_GPI_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid),
5913 kprintf(" unsol=0x%08x", res);
5914 res = hdac_command(sc,
5915 HDA_CMD_GET_GPI_STICKY_MASK(cad, devinfo->nid), cad);
5916 kprintf(" sticky=0x%08x\n", res);
5918 if (1 || HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio) > 0) {
5919 device_printf(dev, " GPO:");
5920 res = hdac_command(sc,
5921 HDA_CMD_GET_GPO_DATA(cad, devinfo->nid), cad);
5922 kprintf(" data=0x%08x\n", res);
5924 if (1 || HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio) > 0) {
5925 device_printf(dev, "GPI0:");
5926 res = hdac_command(sc,
5927 HDA_CMD_GET_GPIO_DATA(cad, devinfo->nid), cad);
5928 kprintf(" data=0x%08x", res);
5929 res = hdac_command(sc,
5930 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, devinfo->nid), cad);
5931 kprintf(" enable=0x%08x", res);
5932 res = hdac_command(sc,
5933 HDA_CMD_GET_GPIO_DIRECTION(cad, devinfo->nid), cad);
5934 kprintf(" direction=0x%08x\n", res);
5935 res = hdac_command(sc,
5936 HDA_CMD_GET_GPIO_WAKE_ENABLE_MASK(cad, devinfo->nid), cad);
5937 device_printf(dev, " wake=0x%08x", res);
5938 res = hdac_command(sc,
5939 HDA_CMD_GET_GPIO_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid),
5941 kprintf(" unsol=0x%08x", res);
5942 res = hdac_command(sc,
5943 HDA_CMD_GET_GPIO_STICKY_MASK(cad, devinfo->nid), cad);
5944 kprintf(" sticky=0x%08x\n", res);
5953 hdac_attach2(void *arg)
5955 struct hdac_softc *sc;
5956 struct hdac_widget *w;
5957 struct hdac_audio_ctl *ctl;
5958 uint32_t quirks_on, quirks_off;
5961 char status[SND_STATUSLEN];
5962 device_t *devlist = NULL;
5964 struct hdac_devinfo *devinfo = NULL;
5966 sc = (struct hdac_softc *)arg;
5968 hdac_config_fetch(sc, &quirks_on, &quirks_off);
5971 device_printf(sc->dev, "HDA_DEBUG: HDA Config: on=0x%08x off=0x%08x\n",
5972 quirks_on, quirks_off);
5977 /* Remove ourselves from the config hooks */
5978 if (sc->intrhook.ich_func != NULL) {
5979 config_intrhook_disestablish(&sc->intrhook);
5980 sc->intrhook.ich_func = NULL;
5983 /* Start the corb and rirb engines */
5985 device_printf(sc->dev, "HDA_DEBUG: Starting CORB Engine...\n");
5987 hdac_corb_start(sc);
5989 device_printf(sc->dev, "HDA_DEBUG: Starting RIRB Engine...\n");
5991 hdac_rirb_start(sc);
5994 device_printf(sc->dev,
5995 "HDA_DEBUG: Enabling controller interrupt...\n");
5997 if (sc->polling == 0)
5998 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL,
5999 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE);
6000 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) |
6006 device_printf(sc->dev, "HDA_DEBUG: Scanning HDA codecs...\n");
6008 hdac_scan_codecs(sc);
6010 device_get_children(sc->dev, &devlist, &devcount);
6011 for (i = 0; devlist != NULL && i < devcount; i++) {
6012 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]);
6013 if (devinfo != NULL && devinfo->node_type ==
6014 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) {
6019 if (devlist != NULL)
6020 kfree(devlist, M_TEMP);
6022 if (devinfo == NULL) {
6024 device_printf(sc->dev, "Audio Function Group not found!\n");
6025 hdac_release_resources(sc);
6030 device_printf(sc->dev,
6031 "HDA_DEBUG: Parsing AFG nid=%d cad=%d\n",
6032 devinfo->nid, devinfo->codec->cad);
6034 hdac_audio_parse(devinfo);
6036 device_printf(sc->dev, "HDA_DEBUG: Parsing Ctls...\n");
6038 hdac_audio_ctl_parse(devinfo);
6040 device_printf(sc->dev, "HDA_DEBUG: Parsing vendor patch...\n");
6042 hdac_vendor_patch_parse(devinfo);
6044 devinfo->function.audio.quirks |= quirks_on;
6045 if (quirks_off != 0)
6046 devinfo->function.audio.quirks &= ~quirks_off;
6048 /* XXX Disable all DIGITAL path. */
6049 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
6050 w = hdac_widget_get(devinfo, i);
6053 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) {
6057 /* XXX Disable useless pin ? */
6058 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX &&
6059 (w->wclass.pin.config &
6060 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) ==
6061 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE)
6065 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
6066 if (ctl->widget == NULL)
6068 if (ctl->ossmask & SOUND_MASK_DISABLE)
6071 if (w->enable == 0 ||
6072 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap))
6074 w = ctl->childwidget;
6077 if (w->enable == 0 ||
6078 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap))
6083 device_printf(sc->dev, "HDA_DEBUG: Building AFG tree...\n");
6085 hdac_audio_build_tree(devinfo);
6088 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
6089 if (ctl->ossmask & (SOUND_MASK_SKIP | SOUND_MASK_DISABLE))
6093 device_printf(sc->dev, "HDA_DEBUG: AFG commit...\n");
6095 hdac_audio_commit(devinfo, HDA_COMMIT_ALL);
6097 device_printf(sc->dev, "HDA_DEBUG: Ctls commit...\n");
6099 hdac_audio_ctl_commit(devinfo);
6102 device_printf(sc->dev, "HDA_DEBUG: PCMDIR_PLAY setup...\n");
6104 pcnt = hdac_pcmchannel_setup(devinfo, PCMDIR_PLAY);
6106 device_printf(sc->dev, "HDA_DEBUG: PCMDIR_REC setup...\n");
6108 rcnt = hdac_pcmchannel_setup(devinfo, PCMDIR_REC);
6112 device_printf(sc->dev,
6113 "HDA_DEBUG: OSS mixer initialization...\n");
6117 * There is no point of return after this. If the driver failed,
6118 * so be it. Let the detach procedure do all the cleanup.
6120 if (mixer_init(sc->dev, &hdac_audio_ctl_ossmixer_class, devinfo) != 0)
6121 device_printf(sc->dev, "Can't register mixer\n");
6129 device_printf(sc->dev,
6130 "HDA_DEBUG: Registering PCM channels...\n");
6132 if (pcm_register(sc->dev, devinfo, pcnt, rcnt) != 0)
6133 device_printf(sc->dev, "Can't register PCM\n");
6137 if ((devinfo->function.audio.quirks & HDA_QUIRK_DMAPOS) &&
6138 hdac_dma_alloc(sc, &sc->pos_dma,
6139 (sc->num_iss + sc->num_oss + sc->num_bss) * 8) != 0) {
6141 device_printf(sc->dev,
6142 "Failed to allocate DMA pos buffer (non-fatal)\n");
6146 for (i = 0; i < pcnt; i++)
6147 pcm_addchan(sc->dev, PCMDIR_PLAY, &hdac_channel_class, devinfo);
6148 for (i = 0; i < rcnt; i++)
6149 pcm_addchan(sc->dev, PCMDIR_REC, &hdac_channel_class, devinfo);
6151 #ifdef SND_DYNSYSCTL
6152 SYSCTL_ADD_PROC(snd_sysctl_tree(sc->dev),
6153 SYSCTL_CHILDREN(snd_sysctl_tree_top(sc->dev)), OID_AUTO,
6154 "polling", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev),
6155 sysctl_hdac_polling, "I", "Enable polling mode");
6156 SYSCTL_ADD_PROC(snd_sysctl_tree(sc->dev),
6157 SYSCTL_CHILDREN(snd_sysctl_tree_top(sc->dev)), OID_AUTO,
6158 "polling_interval", CTLTYPE_INT | CTLFLAG_RW, sc->dev,
6159 sizeof(sc->dev), sysctl_hdac_polling_interval, "I",
6160 "Controller/Jack Sense polling interval (1-1000 ms)");
6162 SYSCTL_ADD_PROC(snd_sysctl_tree(sc->dev),
6163 SYSCTL_CHILDREN(snd_sysctl_tree_top(sc->dev)), OID_AUTO,
6164 "dump", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev),
6165 sysctl_hdac_dump, "I", "Dump states");
6169 ksnprintf(status, SND_STATUSLEN, "at memory 0x%lx irq %ld %s [%s]",
6170 rman_get_start(sc->mem.mem_res), rman_get_start(sc->irq.irq_res),
6171 PCM_KLDSTRING(snd_hda), HDA_DRV_TEST_REV);
6172 pcm_setstatus(sc->dev, status);
6173 device_printf(sc->dev, "<HDA Codec: %s>\n", hdac_codec_name(devinfo));
6175 device_printf(sc->dev, "<HDA Codec ID: 0x%08x>\n",
6176 hdac_codec_id(devinfo));
6178 device_printf(sc->dev, "<HDA Driver Revision: %s>\n",
6182 if (devinfo->function.audio.quirks != 0) {
6183 device_printf(sc->dev, "\n");
6184 device_printf(sc->dev, "HDA config/quirks:");
6185 for (i = 0; i < HDAC_QUIRKS_TAB_LEN; i++) {
6186 if ((devinfo->function.audio.quirks &
6187 hdac_quirks_tab[i].value) ==
6188 hdac_quirks_tab[i].value)
6189 kprintf(" %s", hdac_quirks_tab[i].key);
6193 device_printf(sc->dev, "\n");
6194 device_printf(sc->dev, "+-------------------+\n");
6195 device_printf(sc->dev, "| DUMPING HDA NODES |\n");
6196 device_printf(sc->dev, "+-------------------+\n");
6197 hdac_dump_nodes(devinfo);
6198 device_printf(sc->dev, "\n");
6199 device_printf(sc->dev, "+------------------------+\n");
6200 device_printf(sc->dev, "| DUMPING HDA AMPLIFIERS |\n");
6201 device_printf(sc->dev, "+------------------------+\n");
6202 device_printf(sc->dev, "\n");
6204 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
6205 device_printf(sc->dev, "%3d: nid=%d", i,
6206 (ctl->widget != NULL) ? ctl->widget->nid : -1);
6207 if (ctl->childwidget != NULL)
6208 kprintf(" cnid=%d", ctl->childwidget->nid);
6209 kprintf(" dir=0x%x index=%d "
6210 "ossmask=0x%08x ossdev=%d%s\n",
6211 ctl->dir, ctl->index,
6212 ctl->ossmask, ctl->ossdev,
6213 (ctl->enable == 0) ? " [DISABLED]" : "");
6215 device_printf(sc->dev, "\n");
6216 device_printf(sc->dev, "+-----------------------------------+\n");
6217 device_printf(sc->dev, "| DUMPING HDA AUDIO/VOLUME CONTROLS |\n");
6218 device_printf(sc->dev, "+-----------------------------------+\n");
6219 hdac_dump_ctls(devinfo, "Master Volume (OSS: vol)", SOUND_MASK_VOLUME);
6220 hdac_dump_ctls(devinfo, "PCM Volume (OSS: pcm)", SOUND_MASK_PCM);
6221 hdac_dump_ctls(devinfo, "CD Volume (OSS: cd)", SOUND_MASK_CD);
6222 hdac_dump_ctls(devinfo, "Microphone Volume (OSS: mic)", SOUND_MASK_MIC);
6223 hdac_dump_ctls(devinfo, "Line-in Volume (OSS: line)", SOUND_MASK_LINE);
6224 hdac_dump_ctls(devinfo, "Recording Level (OSS: rec)", SOUND_MASK_RECLEV);
6225 hdac_dump_ctls(devinfo, "Speaker/Beep (OSS: speaker)", SOUND_MASK_SPEAKER);
6226 hdac_dump_ctls(devinfo, NULL, 0);
6227 hdac_dump_dac(devinfo);
6228 hdac_dump_adc(devinfo);
6229 device_printf(sc->dev, "\n");
6230 device_printf(sc->dev, "+--------------------------------------+\n");
6231 device_printf(sc->dev, "| DUMPING PCM Playback/Record Channels |\n");
6232 device_printf(sc->dev, "+--------------------------------------+\n");
6233 hdac_dump_pcmchannels(sc, pcnt, rcnt);
6236 if (sc->polling != 0) {
6238 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc);
6243 /****************************************************************************
6244 * int hdac_detach(device_t)
6246 * Detach and free up resources utilized by the hdac device.
6247 ****************************************************************************/
6249 hdac_detach(device_t dev)
6251 struct hdac_softc *sc = NULL;
6252 struct hdac_devinfo *devinfo = NULL;
6255 devinfo = (struct hdac_devinfo *)pcm_getdevinfo(dev);
6256 if (devinfo != NULL && devinfo->codec != NULL)
6257 sc = devinfo->codec->sc;
6261 if (sc->registered > 0) {
6262 err = pcm_unregister(dev);
6267 hdac_release_resources(sc);
6272 static device_method_t hdac_methods[] = {
6273 /* device interface */
6274 DEVMETHOD(device_probe, hdac_probe),
6275 DEVMETHOD(device_attach, hdac_attach),
6276 DEVMETHOD(device_detach, hdac_detach),
6280 static driver_t hdac_driver = {
6286 DRIVER_MODULE(snd_hda, pci, hdac_driver, pcm_devclass, 0, 0);
6287 MODULE_DEPEND(snd_hda, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
6288 MODULE_VERSION(snd_hda, 1);