2 * Copyright © 2016 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include <linux/console.h>
26 #include <linux/vgaarb.h>
27 #include <linux/vga_switcheroo.h>
31 #define GEN_DEFAULT_PIPEOFFSETS \
32 .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
33 PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \
34 .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
35 TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \
36 .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET }
38 #define GEN_CHV_PIPEOFFSETS \
39 .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
40 CHV_PIPE_C_OFFSET }, \
41 .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
42 CHV_TRANSCODER_C_OFFSET, }, \
43 .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \
44 CHV_PALETTE_C_OFFSET }
46 #define CURSOR_OFFSETS \
47 .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }
49 #define IVB_CURSOR_OFFSETS \
50 .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET }
53 .color = { .degamma_lut_size = 512, .gamma_lut_size = 512 }
55 .color = { .degamma_lut_size = 65, .gamma_lut_size = 257 }
57 #define GEN2_FEATURES \
58 .gen = 2, .num_pipes = 1, \
59 .has_overlay = 1, .overlay_needs_physical = 1, \
60 .has_gmch_display = 1, \
61 .hws_needs_physical = 1, \
62 .ring_mask = RENDER_RING, \
63 GEN_DEFAULT_PIPEOFFSETS, \
66 static const struct intel_device_info intel_i830_info = {
68 .is_mobile = 1, .cursor_needs_physical = 1,
69 .num_pipes = 2, /* legal, last one wins */
72 static const struct intel_device_info intel_845g_info = {
76 static const struct intel_device_info intel_i85x_info = {
78 .is_i85x = 1, .is_mobile = 1,
79 .num_pipes = 2, /* legal, last one wins */
80 .cursor_needs_physical = 1,
84 static const struct intel_device_info intel_i865g_info = {
88 #define GEN3_FEATURES \
89 .gen = 3, .num_pipes = 2, \
90 .has_gmch_display = 1, \
91 .ring_mask = RENDER_RING, \
92 GEN_DEFAULT_PIPEOFFSETS, \
95 static const struct intel_device_info intel_i915g_info = {
97 .is_i915g = 1, .cursor_needs_physical = 1,
98 .has_overlay = 1, .overlay_needs_physical = 1,
99 .hws_needs_physical = 1,
101 static const struct intel_device_info intel_i915gm_info = {
104 .cursor_needs_physical = 1,
105 .has_overlay = 1, .overlay_needs_physical = 1,
108 .hws_needs_physical = 1,
110 static const struct intel_device_info intel_i945g_info = {
112 .has_hotplug = 1, .cursor_needs_physical = 1,
113 .has_overlay = 1, .overlay_needs_physical = 1,
114 .hws_needs_physical = 1,
116 static const struct intel_device_info intel_i945gm_info = {
118 .is_i945gm = 1, .is_mobile = 1,
119 .has_hotplug = 1, .cursor_needs_physical = 1,
120 .has_overlay = 1, .overlay_needs_physical = 1,
123 .hws_needs_physical = 1,
126 #define GEN4_FEATURES \
127 .gen = 4, .num_pipes = 2, \
129 .has_gmch_display = 1, \
130 .ring_mask = RENDER_RING, \
131 GEN_DEFAULT_PIPEOFFSETS, \
134 static const struct intel_device_info intel_i965g_info = {
138 .hws_needs_physical = 1,
141 static const struct intel_device_info intel_i965gm_info = {
144 .is_mobile = 1, .has_fbc = 1,
147 .hws_needs_physical = 1,
150 static const struct intel_device_info intel_g33_info = {
157 static const struct intel_device_info intel_g45_info = {
161 .ring_mask = RENDER_RING | BSD_RING,
164 static const struct intel_device_info intel_gm45_info = {
167 .is_mobile = 1, .has_fbc = 1,
170 .ring_mask = RENDER_RING | BSD_RING,
173 static const struct intel_device_info intel_pineview_info = {
175 .is_g33 = 1, .is_pineview = 1, .is_mobile = 1,
180 #define GEN5_FEATURES \
181 .gen = 5, .num_pipes = 2, \
183 .has_gmbus_irq = 1, \
184 .ring_mask = RENDER_RING | BSD_RING, \
185 GEN_DEFAULT_PIPEOFFSETS, \
188 static const struct intel_device_info intel_ironlake_d_info = {
192 static const struct intel_device_info intel_ironlake_m_info = {
197 #define GEN6_FEATURES \
198 .gen = 6, .num_pipes = 2, \
201 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
205 .has_gmbus_irq = 1, \
206 .has_hw_contexts = 1, \
207 GEN_DEFAULT_PIPEOFFSETS, \
210 static const struct intel_device_info intel_sandybridge_d_info = {
214 static const struct intel_device_info intel_sandybridge_m_info = {
219 #define GEN7_FEATURES \
220 .gen = 7, .num_pipes = 3, \
223 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
227 .has_gmbus_irq = 1, \
228 .has_hw_contexts = 1, \
229 GEN_DEFAULT_PIPEOFFSETS, \
232 static const struct intel_device_info intel_ivybridge_d_info = {
238 static const struct intel_device_info intel_ivybridge_m_info = {
245 static const struct intel_device_info intel_ivybridge_q_info = {
248 .num_pipes = 0, /* legal, last one wins */
252 #define VLV_FEATURES \
253 .gen = 7, .num_pipes = 2, \
255 .has_runtime_pm = 1, \
257 .has_gmbus_irq = 1, \
258 .has_hw_contexts = 1, \
259 .has_gmch_display = 1, \
261 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
262 .display_mmio_offset = VLV_DISPLAY_BASE, \
263 GEN_DEFAULT_PIPEOFFSETS, \
266 static const struct intel_device_info intel_valleyview_info = {
271 #define HSW_FEATURES \
273 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
277 .has_resource_streamer = 1, \
279 .has_rc6p = 0 /* RC6p removed-by HSW */, \
282 static const struct intel_device_info intel_haswell_info = {
288 #define BDW_FEATURES \
291 .has_logical_ring_contexts = 1
293 static const struct intel_device_info intel_broadwell_info = {
299 static const struct intel_device_info intel_broadwell_gt3_info = {
303 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
306 static const struct intel_device_info intel_cherryview_info = {
307 .gen = 8, .num_pipes = 3,
309 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
313 .has_resource_streamer = 1,
316 .has_hw_contexts = 1,
317 .has_logical_ring_contexts = 1,
318 .has_gmch_display = 1,
319 .display_mmio_offset = VLV_DISPLAY_BASE,
325 #define GEN9_FEATURES \
330 static const struct intel_device_info intel_skylake_info = {
339 static const struct intel_device_info intel_skylake_gt3_info = {
346 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
349 static const struct intel_device_info intel_broxton_info = {
353 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
361 .has_resource_streamer = 1,
365 .has_hw_contexts = 1,
366 .has_logical_ring_contexts = 1,
369 GEN_DEFAULT_PIPEOFFSETS,
374 #define KBL_PLATFORM \
378 static const struct intel_device_info intel_kabylake_gt1_info = {
382 static const struct intel_device_info intel_kabylake_gt2_info = {
391 static const struct intel_device_info intel_kabylake_gt3_info = {
398 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
401 #define CFL_PLATFORM \
405 static const struct intel_device_info intel_coffeelake_gt1_info = {
409 static const struct intel_device_info intel_coffeelake_gt2_info = {
413 static const struct intel_device_info intel_coffeelake_gt3_info = {
415 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
419 * Make sure any device matches here are from most specific to most
420 * general. For example, since the Quanta match is based on the subsystem
421 * and subvendor IDs, we need it to come before the more general IVB
422 * PCI ID matches, otherwise we'll use the wrong info struct above.
424 static const struct pci_device_id pciidlist[] = {
425 INTEL_I830_IDS(&intel_i830_info),
426 INTEL_I845G_IDS(&intel_845g_info),
427 INTEL_I85X_IDS(&intel_i85x_info),
428 INTEL_I865G_IDS(&intel_i865g_info),
429 INTEL_I915G_IDS(&intel_i915g_info),
430 INTEL_I915GM_IDS(&intel_i915gm_info),
431 INTEL_I945G_IDS(&intel_i945g_info),
432 INTEL_I945GM_IDS(&intel_i945gm_info),
433 INTEL_I965G_IDS(&intel_i965g_info),
434 INTEL_G33_IDS(&intel_g33_info),
435 INTEL_I965GM_IDS(&intel_i965gm_info),
436 INTEL_GM45_IDS(&intel_gm45_info),
437 INTEL_G45_IDS(&intel_g45_info),
438 INTEL_PINEVIEW_IDS(&intel_pineview_info),
439 INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),
440 INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),
441 INTEL_SNB_D_IDS(&intel_sandybridge_d_info),
442 INTEL_SNB_M_IDS(&intel_sandybridge_m_info),
443 INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */
444 INTEL_IVB_M_IDS(&intel_ivybridge_m_info),
445 INTEL_IVB_D_IDS(&intel_ivybridge_d_info),
446 INTEL_HSW_IDS(&intel_haswell_info),
447 INTEL_VLV_IDS(&intel_valleyview_info),
448 INTEL_BDW_GT12_IDS(&intel_broadwell_info),
449 INTEL_BDW_GT3_IDS(&intel_broadwell_gt3_info),
450 INTEL_CHV_IDS(&intel_cherryview_info),
451 INTEL_SKL_GT1_IDS(&intel_skylake_info),
452 INTEL_SKL_GT2_IDS(&intel_skylake_info),
453 INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info),
454 INTEL_SKL_GT4_IDS(&intel_skylake_gt3_info),
455 INTEL_BXT_IDS(&intel_broxton_info),
456 INTEL_KBL_GT1_IDS(&intel_kabylake_gt1_info),
457 INTEL_KBL_GT2_IDS(&intel_kabylake_gt2_info),
458 INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info),
459 INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info),
460 INTEL_AML_KBL_GT2_IDS(&intel_kabylake_gt2_info),
461 INTEL_CFL_S_GT1_IDS(&intel_coffeelake_gt1_info),
462 INTEL_CFL_S_GT2_IDS(&intel_coffeelake_gt2_info),
463 INTEL_CFL_H_GT1_IDS(&intel_coffeelake_gt1_info),
464 INTEL_CFL_H_GT2_IDS(&intel_coffeelake_gt2_info),
465 INTEL_CFL_U_GT2_IDS(&intel_coffeelake_gt2_info),
466 INTEL_CFL_U_GT3_IDS(&intel_coffeelake_gt3_info),
467 INTEL_WHL_U_GT1_IDS(&intel_coffeelake_gt1_info),
468 INTEL_WHL_U_GT2_IDS(&intel_coffeelake_gt2_info),
469 INTEL_AML_CFL_GT2_IDS(&intel_coffeelake_gt2_info),
470 INTEL_WHL_U_GT3_IDS(&intel_coffeelake_gt3_info),
471 INTEL_CML_GT1_IDS(&intel_coffeelake_gt1_info),
472 INTEL_CML_GT2_IDS(&intel_coffeelake_gt2_info),
475 MODULE_DEVICE_TABLE(pci, pciidlist);
477 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
479 struct intel_device_info *intel_info =
480 (struct intel_device_info *) ent->driver_data;
482 if (IS_PRELIMINARY_HW(intel_info) && !i915.preliminary_hw_support) {
483 DRM_INFO("This hardware requires preliminary hardware support.\n"
484 "See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or modparam preliminary_hw_support\n");
488 /* Only bind to function 0 of the device. Early generations
489 * used function 1 as a placeholder for multi-head. This causes
490 * us confusion instead, especially on the systems where both
491 * functions have the same PCI-ID!
493 if (PCI_FUNC(pdev->devfn))
497 * apple-gmux is needed on dual GPU MacBook Pro
498 * to probe the panel if we're the inactive GPU.
500 if (vga_switcheroo_client_probe_defer(pdev))
501 return -EPROBE_DEFER;
503 return i915_driver_load(pdev, ent);
506 static void i915_pci_remove(struct pci_dev *pdev)
508 struct drm_device *dev = pci_get_drvdata(pdev);
510 i915_driver_unload(dev);
514 static struct pci_driver i915_pci_driver = {
516 .id_table = pciidlist,
517 .probe = i915_pci_probe,
518 .remove = i915_pci_remove,
520 .driver.pm = &i915_pm_ops,
524 static int __init i915_init(void)
529 * Enable KMS by default, unless explicitly overriden by
530 * either the i915.modeset prarameter or by the
531 * vga_text_mode_force boot option.
534 if (i915.modeset == 0)
537 if (vgacon_text_force() && i915.modeset == -1)
541 /* Silently fail loading to not upset userspace. */
542 DRM_DEBUG_DRIVER("KMS disabled.\n");
546 return pci_register_driver(&i915_pci_driver);
549 static void __exit i915_exit(void)
552 if (!i915_pci_driver.driver.owner)
556 pci_unregister_driver(&i915_pci_driver);
559 module_init(i915_init);
560 module_exit(i915_exit);
562 MODULE_AUTHOR("Tungsten Graphics, Inc.");
563 MODULE_AUTHOR("Intel Corporation");
566 i915_pci_probe_dfly(device_t kdev)
569 const struct pci_device_id *ent;
570 static struct pci_dev *pdev = NULL;
571 static device_t bsddev;
573 if (pci_get_class(kdev) != PCIC_DISPLAY)
576 if (pci_get_vendor(kdev) != PCI_VENDOR_ID_INTEL)
579 device = pci_get_device(kdev);
581 for (i = 0; pciidlist[i].device != 0; i++) {
582 if (pciidlist[i].device == device) {
590 if (!strcmp(device_get_name(kdev), "drmsub"))
591 bsddev = device_get_parent(kdev);
595 drm_init_pdev(bsddev, &pdev);
597 /* Print the contents of pdev struct. */
598 drm_print_pdev(pdev);
600 return i915_pci_probe(pdev, ent);
603 static int i915_driver_attach(device_t kdev)
608 static device_method_t i915_methods[] = {
609 /* Device interface */
610 DEVMETHOD(device_probe, i915_pci_probe_dfly),
611 DEVMETHOD(device_attach, i915_driver_attach),
612 DEVMETHOD(device_suspend, i915_suspend_switcheroo),
613 DEVMETHOD(device_resume, i915_resume_switcheroo),
614 DEVMETHOD(device_detach, drm_release),
618 static driver_t i915_driver = {
621 sizeof(struct drm_softc)
624 extern devclass_t drm_devclass;
626 DRIVER_MODULE_ORDERED(i915, vgapci, i915_driver, drm_devclass, NULL, NULL, SI_ORDER_ANY);
627 MODULE_DEPEND(i915, drm, 1, 1, 1);
629 MODULE_DEPEND(i915, acpi, 1, 1, 1);