2 * Aic79xx register and scratch ram definitions.
4 * Copyright (c) 1994-2001 Justin T. Gibbs.
5 * Copyright (c) 2000-2002 Adaptec Inc.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions, and the following disclaimer,
13 * without modification.
14 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
15 * substantially similar to the "NO WARRANTY" disclaimer below
16 * ("Disclaimer") and any redistribution must be conditioned upon
17 * including a substantially similar Disclaimer requirement for further
18 * binary redistribution.
19 * 3. Neither the names of the above-listed copyright holders nor the names
20 * of any contributors may be used to endorse or promote products derived
21 * from this software without specific prior written permission.
23 * Alternatively, this software may be distributed under the terms of the
24 * GNU General Public License ("GPL") version 2 as published by the Free
25 * Software Foundation.
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
37 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38 * POSSIBILITY OF SUCH DAMAGES.
40 * $FreeBSD: src/sys/dev/aic7xxx/aic79xx.reg,v 1.2.2.6 2003/06/10 03:26:07 gibbs Exp $
41 * $DragonFly: src/sys/dev/disk/aic7xxx/aic79xx.reg,v 1.2 2003/06/17 04:28:21 dillon Exp $
43 VERSION = "$Id: //depot/aic7xxx/aic7xxx/aic79xx.reg#70 $"
46 * This file is processed by the aic7xxx_asm utility for use in assembling
47 * firmware for the aic79xx family of SCSI host adapters as well as to generate
48 * a C header file for use in the kernel portion of the Aic79xx driver.
51 /* Register window Modes */
59 #define MK_MODE(src, dst) ((src) | ((dst) << M_DST_SHIFT))
60 #define SET_MODE(src, dst) \
63 if ((ahd->bugs & AHD_SET_MODE_BUG) != 0) { \
64 mvi MK_MODE(src, dst) call set_mode_work_around; \
66 mvi MODE_PTR, MK_MODE(src, dst); \
69 #define TOGGLE_DFF_MODE \
70 if ((ahd->bugs & AHD_SET_MODE_BUG) != 0) { \
71 call toggle_dff_mode_work_around; \
73 xor MODE_PTR, MK_MODE(M_DFF1, M_DFF1); \
76 #define RESTORE_MODE(mode) \
77 if ((ahd->bugs & AHD_SET_MODE_BUG) != 0) { \
78 mov mode call set_mode_work_around; \
83 #define SET_SEQINTCODE(code) \
84 if ((ahd->bugs & AHD_INTCOLLISION_BUG) != 0) { \
85 mvi code call set_seqint_work_around; \
87 mvi SEQINTCODE, code; \
92 * Controls which of the 5, 512byte, address spaces should be used
93 * as the source and destination of any register accesses in our
104 const SRC_MODE_SHIFT 0
105 const DST_MODE_SHIFT 4
108 * Host Interrupt Status
125 * Sequencer Interrupt Code
127 register SEQINTCODE {
131 NO_SEQINT, /* No seqint pending. */
132 BAD_PHASE, /* unknown scsi bus phase */
133 SEND_REJECT, /* sending a message reject */
134 PROTO_VIOLATION, /* Protocol Violation */
135 NO_MATCH, /* no cmd match for reconnect */
136 IGN_WIDE_RES, /* Complex IGN Wide Res Msg */
138 * Returned to data phase
140 * transfer pointers to be
141 * recalculated from the
145 * The bus is ready for the
146 * host to perform another
147 * message transaction. This
148 * mechanism is used for things
149 * like sync/wide negotiation
150 * that require a kernel based
151 * message state engine.
153 BAD_STATUS, /* Bad status from target */
155 * Target attempted to write
156 * beyond the bounds of its
160 * Target completed command
161 * without honoring our ATN
162 * request to issue a message.
165 * The sequencer never saw
166 * the bus go free after
167 * either a command complete
168 * or disconnect message.
177 TASKMGMT_FUNC_COMPLETE, /*
178 * Task management function
179 * request completed with
180 * an expected busfree.
182 TASKMGMT_CMD_CMPLT_OKAY, /*
183 * A command with a non-zero
184 * task management function
185 * has completed via the normal
186 * command completion method
187 * for commands with a zero
188 * task management function.
189 * This happens when an attempt
190 * to abort a command loses
191 * the race for the command to
204 * Clear Host Interrupt
209 field CLRHWERRINT 0x80 /* Rev B or greater */
210 field CLRBRKADRINT 0x40
211 field CLRSWTMINT 0x20
213 field CLRSCSIINT 0x08
216 field CLRSPLTINT 0x01
226 field CIOACCESFAIL 0x40 /* Rev B or greater */
240 field CLRCIOPARERR 0x80
241 field CLRCIOACCESFAIL 0x40 /* Rev B or greater */
242 field CLRMPARERR 0x20
243 field CLRDPARERR 0x10
244 field CLRSQPARERR 0x08
245 field CLRILLOPCODE 0x04
246 field CLRDSCTMOUT 0x02
250 * Host Control Register
251 * Overall host control of the device.
256 field SEQ_RESET 0x80 /* Rev B or greater */
259 field SWTIMER_START_B 0x08 /* Rev B or greater */
263 field CHIPRSTACK 0x01
267 * Host New SCB Queue Offset
269 register HNSCB_QOFF {
276 * Host Empty SCB Queue Offset
278 register HESCB_QOFF {
286 register HS_MAILBOX {
289 mask HOST_TQINPOS 0x80 /* Boundary at either 0 or 128 */
290 mask ENINT_COALESCE 0x40 /* Perform interrupt coalescing */
294 * Sequencer Interupt Status
296 register SEQINTSTAT {
299 field SEQ_SWTMRTO 0x10
300 field SEQ_SEQINT 0x08
301 field SEQ_SCSIINT 0x04
302 field SEQ_PCIINT 0x02
303 field SEQ_SPLTINT 0x01
307 * Clear SEQ Interrupt
309 register CLRSEQINTSTAT {
312 field CLRSEQ_SWTMRTO 0x10
313 field CLRSEQ_SEQINT 0x08
314 field CLRSEQ_SCSIINT 0x04
315 field CLRSEQ_PCIINT 0x02
316 field CLRSEQ_SPLTINT 0x01
329 * SEQ New SCB Queue Offset
331 register SNSCB_QOFF {
339 * SEQ Empty SCB Queue Offset
341 register SESCB_QOFF {
348 * SEQ Done SCB Queue Offset
350 register SDSCB_QOFF {
358 * Queue Offset Control & Status
360 register QOFF_CTLSTA {
364 field EMPTY_SCB_AVAIL 0x80
365 field NEW_SCB_AVAIL 0x40
366 field SDSCB_ROLLOVR 0x20
367 field HS_MAILBOX_ACT 0x10
368 field SCB_QSIZE 0x0F {
391 field SWTMINTMASK 0x80
393 field SWTIMER_START 0x20
394 field AUTOCLRCMDINT 0x10
409 field SCSIENWRDIS 0x40 /* Rev B only. */
415 field DIRECTIONACK 0x04
417 field FIFOFLUSHACK 0x02
418 field DIRECTIONEN 0x01
422 * Device Space Command 0
424 register DSCOMMAND0 {
428 field CACHETHEN 0x80 /* Cache Threshold enable */
429 field DPARCKEN 0x40 /* Data Parity Check Enable */
430 field MPARCKEN 0x20 /* Memory Parity Check Enable */
431 field EXTREQLCK 0x10 /* External Request Lock */
432 field DISABLE_TWATE 0x02 /* Rev B or greater */
433 field CIOPARCKEN 0x01 /* Internal bus parity error enable */
443 field PRELOAD_AVAIL 0x80
444 field PKT_PRELOAD_AVAIL 0x40
455 register SG_CACHE_PRE {
459 field SG_ADDR_MASK 0xf8
464 register SG_CACHE_SHADOW {
468 field SG_ADDR_MASK 0xf8
471 field LAST_SEG_DONE 0x01
481 field RESET_HARB 0x80
482 field RETRY_SWEN 0x08
487 * Data Channel Host Address
497 * Host Overlay DMA Address
514 field SPLIT_DROP_REQ 0x80
518 * Data Channel Host Count
528 * Host Overlay DMA Count
538 * Host Overlay DMA Enable
547 * Scatter/Gather Host Address
567 * Scatter/Gather Host Count
585 * Data FIFO Threshold
591 field WR_DFTHRSH 0x70 {
601 field RD_DFTHRSH 0x07 {
643 * Data Channel Receive Message 0
654 * CMC Recieve Message 0
665 * Overlay Recieve Message 0
667 register OVLYRXMSG0 {
676 * Relaxed Order Enable
691 * Data Channel Receive Message 1
701 * CMC Recieve Message 1
711 * Overlay Recieve Message 1
713 register OVLYRXMSG1 {
736 * Data Channel Receive Message 2
746 * CMC Recieve Message 2
756 * Overlay Recieve Message 2
758 register OVLYRXMSG2 {
766 * Outstanding Split Transactions
775 * Data Channel Receive Message 3
785 * CMC Recieve Message 3
795 * Overlay Recieve Message 3
797 register OVLYRXMSG3 {
812 field UNEXPSCIEN 0x20
813 field SPLTSMADIS 0x10
814 field SPLTSTADIS 0x08
821 * CMC Sequencer Byte Count
823 register CMCSEQBCNT {
830 * Overlay Sequencer Byte Count
832 register OVLYSEQBCNT {
839 * Data Channel Sequencer Byte Count
841 register DCHSEQBCNT {
849 * Data Channel Split Status 0
851 register DCHSPLTSTAT0 {
858 field SCDATBUCKET 0x10
859 field CNTNOTCMPLT 0x08
868 register CMCSPLTSTAT0 {
875 field SCDATBUCKET 0x10
876 field CNTNOTCMPLT 0x08
883 * Overlay Split Status 0
885 register OVLYSPLTSTAT0 {
892 field SCDATBUCKET 0x10
893 field CNTNOTCMPLT 0x08
900 * Data Channel Split Status 1
902 register DCHSPLTSTAT1 {
906 field RXDATABUCKET 0x01
912 register CMCSPLTSTAT1 {
916 field RXDATABUCKET 0x01
920 * Overlay Split Status 1
922 register OVLYSPLTSTAT1 {
926 field RXDATABUCKET 0x01
930 * S/G Receive Message 0
941 * S/G Receive Message 1
951 * S/G Receive Message 2
961 * S/G Receive Message 3
971 * Slave Split Out Address 0
973 register SLVSPLTOUTADR0 {
977 field LOWER_ADDR 0x7F
981 * Slave Split Out Address 1
983 register SLVSPLTOUTADR1 {
992 * Slave Split Out Address 2
994 register SLVSPLTOUTADR2 {
1002 * Slave Split Out Address 3
1004 register SLVSPLTOUTADR3 {
1013 * SG Sequencer Byte Count
1015 register SGSEQBCNT {
1018 modes M_DFF0, M_DFF1
1022 * Slave Split Out Attribute 0
1024 register SLVSPLTOUTATTR0 {
1028 field LOWER_BCNT 0xFF
1032 * Slave Split Out Attribute 1
1034 register SLVSPLTOUTATTR1 {
1038 field CMPLT_DNUM 0xF8
1039 field CMPLT_FNUM 0x07
1043 * Slave Split Out Attribute 2
1045 register SLVSPLTOUTATTR2 {
1050 field CMPLT_BNUM 0xFF
1053 * S/G Split Status 0
1055 register SGSPLTSTAT0 {
1058 modes M_DFF0, M_DFF1
1062 field SCDATBUCKET 0x10
1063 field CNTNOTCMPLT 0x08
1066 field RXSPLTRSP 0x01
1070 * S/G Split Status 1
1072 register SGSPLTSTAT1 {
1075 modes M_DFF0, M_DFF1
1076 field RXDATABUCKET 0x01
1086 field TEST_GROUP 0xF0
1091 * Data FIFO 0 PCI Status
1093 register DF0PCISTAT {
1108 * Data FIFO 1 PCI Status
1110 register DF1PCISTAT {
1127 register SGPCISTAT {
1143 register CMCPCISTAT {
1158 * Overlay PCI Status
1160 register OVLYPCISTAT {
1174 * PCI Status for MSI Master DMA Transfer
1176 register MSIPCISTAT {
1183 field CLRPENDMSI 0x08
1189 * PCI Status for Target
1191 register TARGPCISTAT {
1203 * The last LQ Packet recieved
1209 modes M_DFF0, M_DFF1, M_SCSI
1214 * SCB offset for Target Mode SCB type information
1224 * SCB offset to the Two Byte tag identifier used for target mode.
1233 * Logical Unit Number Pointer
1234 * SCB offset to the LSB (little endian) of the lun field.
1243 * Data Length Pointer
1244 * SCB offset for the 4 byte data length field in target mode.
1246 register DATALENPTR {
1253 * Status Length Pointer
1254 * SCB offset to the two byte status field in target SCBs.
1256 register STATLENPTR {
1263 * Command Length Pointer
1264 * Scb offset for the CDB length field in initiator SCBs.
1266 register CMDLENPTR {
1273 * Task Attribute Pointer
1274 * Scb offset for the byte field specifying the attribute byte
1275 * to be used in command packets.
1284 * Task Management Flags Pointer
1285 * Scb offset for the byte field specifying the attribute flags
1286 * byte to be used in command packets.
1296 * Scb offset for the first byte in the CDB for initiator SCBs.
1305 * Queue Next Pointer
1306 * Scb offset for the 2 byte "next scb link".
1316 * Scb offset to the value to place in the SCSIID register
1317 * during target mode connections.
1326 * Command Aborted Byte Pointer
1327 * Offset to the SCB flags field that includes the
1328 * "SCB aborted" status bit.
1330 register ABRTBYTEPTR {
1337 * Command Aborted Bit Pointer
1338 * Bit offset in the SCB flags field for "SCB aborted" status.
1340 register ABRTBITPTR {
1349 register MAXCMDBYTES {
1358 register MAXCMD2RCV {
1367 register SHORTTHRESH {
1374 * Logical Unit Number Length
1375 * The length, in bytes, of the SCB lun field.
1384 const LUNLEN_SINGLE_LEVEL_LUN 0xF
1388 * The size, in bytes, of the embedded CDB field in initator SCBs.
1398 * The maximum number of commands to issue during a
1399 * single packetized connection.
1408 * Maximum Command Counter
1409 * The number of commands already sent during this connection
1411 register MAXCMDCNT {
1418 * LQ Packet Reserved Bytes
1419 * The bytes to be sent in the currently reserved fileds
1420 * of all LQ packets.
1439 * Command Reserved 0
1440 * The byte to be sent for the reserved byte 0 of
1441 * outgoing command packets.
1450 * LQ Manager Control 0
1456 field LQITARGCLT 0xC0
1457 field LQIINITGCLT 0x30
1458 field LQ0TARGCLT 0x0C
1459 field LQ0INITGCLT 0x03
1463 * LQ Manager Control 1
1468 modes M_DFF0, M_DFF1, M_SCSI
1470 field SINGLECMD 0x02
1471 field ABORTPENDING 0x01
1475 * LQ Manager Control 2
1480 modes M_DFF0, M_DFF1, M_SCSI
1482 field LQICONTINUE 0x40
1483 field LQITOIDLE 0x20
1486 field LQOCONTINUE 0x04
1487 field LQOTOIDLE 0x02
1498 field GSBISTERR 0x40
1499 field GSBISTDONE 0x20
1500 field GSBISTRUN 0x10
1501 field OSBISTERR 0x04
1502 field OSBISTDONE 0x02
1503 field OSBISTRUN 0x01
1507 * SCSI Sequence Control0
1512 modes M_DFF0, M_DFF1, M_SCSI
1516 field FORCEBUSFREE 0x10
1527 field NTBISTERR 0x04
1528 field NTBISTDONE 0x02
1529 field NTBISTRUN 0x01
1533 * SCSI Sequence Control 1
1538 modes M_DFF0, M_DFF1, M_SCSI
1539 field MANUALCTL 0x40
1543 field ENAUTOATNP 0x02
1548 * SCSI Transfer Control 0
1556 field BIOSCANCELEN 0x10
1561 * SCSI Transfer Control 1
1567 field BITBUCKET 0x80
1577 * SCSI Transfer Control 2
1583 field AUTORSTDIS 0x10
1589 * SCSI Bus Initiator IDs
1590 * Bitmask of observed initiators on the bus.
1592 register BUSINITID {
1600 * Data Length Counters
1601 * Packet byte counter.
1606 modes M_DFF0, M_DFF1
1617 field FIFO1FREE 0x20
1618 field FIFO0FREE 0x10
1620 * On the B, this enum only works
1621 * in the read direction. For writes,
1622 * you must use the B version of the
1623 * CURRFIFO_0 definition which is defined
1624 * as a constant outside of this register
1625 * definition to avoid confusing the
1626 * register pretty printing code.
1628 enum CURRFIFO 0x03 {
1635 const B_CURRFIFO_0 0x2
1638 * SCSI Bus Target IDs
1639 * Bitmask of observed targets on the bus.
1641 register BUSTARGID {
1649 * SCSI Control Signal Out
1654 modes M_DFF0, M_DFF1, M_SCSI
1664 * Possible phases to write into SCSISIG0
1666 enum PHASE_MASK CDO|IOO|MSGO {
1669 P_DATAOUT_DT P_DATAOUT|MSGO,
1670 P_DATAIN_DT P_DATAIN|MSGO,
1674 P_MESGIN CDO|IOO|MSGO
1681 modes M_DFF0, M_DFF1, M_SCSI
1691 * Possible phases in SCSISIGI
1693 enum PHASE_MASK CDO|IOO|MSGO {
1696 P_DATAOUT_DT P_DATAOUT|MSGO,
1697 P_DATAIN_DT P_DATAIN|MSGO,
1701 P_MESGIN CDO|IOO|MSGO
1706 * Multiple Target IDs
1707 * Bitmask of ids to respond as a target.
1709 register MULTARGID {
1719 register SCSIPHASE {
1722 modes M_DFF0, M_DFF1, M_SCSI
1723 field STATUS_PHASE 0x20
1724 field COMMAND_PHASE 0x10
1725 field MSG_IN_PHASE 0x08
1726 field MSG_OUT_PHASE 0x04
1727 field DATA_PHASE_MASK 0x03 {
1728 DATA_OUT_PHASE 0x01,
1736 register SCSIDAT0_IMG {
1739 modes M_DFF0, M_DFF1, M_SCSI
1748 modes M_DFF0, M_DFF1, M_SCSI
1758 modes M_DFF0, M_DFF1, M_SCSI
1768 modes M_DFF0, M_DFF1, M_SCSI
1774 * Selection/Reselection ID
1775 * Upper four bits are the device id. The ONEBIT is set when the re/selecting
1776 * device did not set its own ID.
1781 modes M_DFF0, M_DFF1, M_SCSI
1782 field SELID_MASK 0xf0
1787 * SCSI Block Control
1788 * Controls Bus type and channel selection. SELWIDE allows for the
1789 * coexistence of 8bit and 16bit devices on a wide bus.
1794 modes M_DFF0, M_DFF1, M_SCSI
1795 field DIAGLEDEN 0x80
1796 field DIAGLEDON 0x40
1797 field ENAB40 0x08 /* LVD transceiver active */
1798 field ENAB20 0x04 /* SE/HVD transceiver active */
1805 register OPTIONMODE {
1809 field BIOSCANCTL 0x80
1810 field AUTOACKEN 0x40
1811 field BIASCANCTL 0x20
1812 field BUSFREEREV 0x10
1813 field ENDGFORMCHK 0x04
1814 field AUTO_MSGOUT_DE 0x02
1815 mask OPTIONMODE_DEFAULTS AUTO_MSGOUT_DE
1824 modes M_DFF0, M_DFF1, M_SCSI
1825 field TARGET 0x80 /* Board acting as target */
1826 field SELDO 0x40 /* Selection Done */
1827 field SELDI 0x20 /* Board has been selected */
1828 field SELINGO 0x10 /* Selection In Progress */
1829 field IOERR 0x08 /* LVD Tranceiver mode changed */
1830 field OVERRUN 0x04 /* SCSI Offset overrun detected */
1831 field SPIORDY 0x02 /* SCSI PIO Ready */
1832 field ARBDO 0x01 /* Arbitration Done Out */
1836 * Clear SCSI Interrupt 0
1837 * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT0.
1842 modes M_DFF0, M_DFF1, M_SCSI
1845 field CLRSELINGO 0x10
1847 field CLROVERRUN 0x04
1848 field CLRSPIORDY 0x02
1853 * SCSI Interrupt Mode 0
1854 * Setting any bit will enable the corresponding function
1855 * in SIMODE0 to interrupt via the IRQ pin.
1863 field ENSELINGO 0x10
1865 field ENOVERRUN 0x04
1866 field ENSPIORDY 0x02
1876 modes M_DFF0, M_DFF1, M_SCSI
1883 field STRB2FAST 0x02
1888 * Clear SCSI Interrupt 1
1889 * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT1.
1894 modes M_DFF0, M_DFF1, M_SCSI
1895 field CLRSELTIMEO 0x80
1897 field CLRSCSIRSTI 0x20
1898 field CLRBUSFREE 0x08
1899 field CLRSCSIPERR 0x04
1900 field CLRSTRB2FAST 0x02
1901 field CLRREQINIT 0x01
1910 modes M_DFF0, M_DFF1, M_SCSI
1911 field BUSFREETIME 0xc0 {
1916 field NONPACKREQ 0x20
1917 field EXP_ACTIVE 0x10 /* SCSI Expander Active */
1918 field BSYX 0x08 /* Busy Expander */
1919 field WIDE_RES 0x04 /* Modes 0 and 1 only */
1920 field SDONE 0x02 /* Modes 0 and 1 only */
1921 field DMADONE 0x01 /* Modes 0 and 1 only */
1925 * Clear SCSI Interrupt 2
1930 modes M_DFF0, M_DFF1, M_SCSI
1931 field CLRNONPACKREQ 0x20
1932 field CLRWIDE_RES 0x04 /* Modes 0 and 1 only */
1933 field CLRSDONE 0x02 /* Modes 0 and 1 only */
1934 field CLRDMADONE 0x01 /* Modes 0 and 1 only */
1938 * SCSI Interrupt Mode 2
1944 field ENWIDE_RES 0x04
1946 field ENDMADONE 0x01
1950 * Physical Error Diagnosis
1955 modes M_DFF0, M_DFF1, M_SCSI
1958 field PREVPHASE 0x20
1959 field PARITYERR 0x10
1962 field DGFORMERR 0x02
1967 * LQI Manager Current State
1981 modes M_DFF0, M_DFF1, M_SCSI
1985 * LQO Manager Current State
1994 * LQI Manager Status
1999 modes M_DFF0, M_DFF1, M_SCSI
2000 field LQIATNQAS 0x20
2003 field LQIBADLQT 0x04
2005 field LQIATNCMD 0x01
2009 * Clear LQI Interrupts 0
2011 register CLRLQIINT0 {
2014 modes M_DFF0, M_DFF1, M_SCSI
2015 field CLRLQIATNQAS 0x20
2016 field CLRLQICRCT1 0x10
2017 field CLRLQICRCT2 0x08
2018 field CLRLQIBADLQT 0x04
2019 field CLRLQIATNLQ 0x02
2020 field CLRLQIATNCMD 0x01
2024 * LQI Manager Interrupt Mode 0
2030 field ENLQIATNQASK 0x20
2031 field ENLQICRCT1 0x10
2032 field ENLQICRCT2 0x08
2033 field ENLQIBADLQT 0x04
2034 field ENLQIATNLQ 0x02
2035 field ENLQIATNCMD 0x01
2039 * LQI Manager Status 1
2044 modes M_DFF0, M_DFF1, M_SCSI
2045 field LQIPHASE_LQ 0x80
2046 field LQIPHASE_NLQ 0x40
2048 field LQICRCI_LQ 0x10
2049 field LQICRCI_NLQ 0x08
2050 field LQIBADLQI 0x04
2051 field LQIOVERI_LQ 0x02
2052 field LQIOVERI_NLQ 0x01
2056 * Clear LQI Manager Interrupts1
2058 register CLRLQIINT1 {
2061 modes M_DFF0, M_DFF1, M_SCSI
2062 field CLRLQIPHASE_LQ 0x80
2063 field CLRLQIPHASE_NLQ 0x40
2064 field CLRLIQABORT 0x20
2065 field CLRLQICRCI_LQ 0x10
2066 field CLRLQICRCI_NLQ 0x08
2067 field CLRLQIBADLQI 0x04
2068 field CLRLQIOVERI_LQ 0x02
2069 field CLRLQIOVERI_NLQ 0x01
2073 * LQI Manager Interrupt Mode 1
2079 field ENLQIPHASE_LQ 0x80 /* LQIPHASE1 */
2080 field ENLQIPHASE_NLQ 0x40 /* LQIPHASE2 */
2081 field ENLIQABORT 0x20
2082 field ENLQICRCI_LQ 0x10 /* LQICRCI1 */
2083 field ENLQICRCI_NLQ 0x08 /* LQICRCI2 */
2084 field ENLQIBADLQI 0x04
2085 field ENLQIOVERI_LQ 0x02 /* LQIOVERI1 */
2086 field ENLQIOVERI_NLQ 0x01 /* LQIOVERI2 */
2090 * LQI Manager Status 2
2095 modes M_DFF0, M_DFF1, M_SCSI
2096 field PACKETIZED 0x80
2097 field LQIPHASE_OUTPKT 0x40
2098 field LQIWORKONLQ 0x20
2099 field LQIWAITFIFO 0x10
2100 field LQISTOPPKT 0x08
2101 field LQISTOPLQ 0x04
2102 field LQISTOPCMD 0x02
2103 field LQIGSAVAIL 0x01
2112 modes M_DFF0, M_DFF1, M_SCSI
2113 field NTRAMPERR 0x02
2114 field OSRAMPERR 0x01
2118 * Clear SCSI Status 3
2123 modes M_DFF0, M_DFF1, M_SCSI
2124 field CLRNTRAMPERR 0x02
2125 field CLROSRAMPERR 0x01
2129 * SCSI Interrupt Mode 3
2135 field ENNTRAMPERR 0x02
2136 field ENOSRAMPERR 0x01
2140 * LQO Manager Status 0
2145 modes M_DFF0, M_DFF1, M_SCSI
2146 field LQOTARGSCBPERR 0x10
2147 field LQOSTOPT2 0x08
2149 field LQOATNPKT 0x02
2154 * Clear LQO Manager interrupt 0
2156 register CLRLQOINT0 {
2159 modes M_DFF0, M_DFF1, M_SCSI
2160 field CLRLQOTARGSCBPERR 0x10
2161 field CLRLQOSTOPT2 0x08
2162 field CLRLQOATNLQ 0x04
2163 field CLRLQOATNPKT 0x02
2164 field CLRLQOTCRC 0x01
2168 * LQO Manager Interrupt Mode 0
2174 field ENLQOTARGSCBPERR 0x10
2175 field ENLQOSTOPT2 0x08
2176 field ENLQOATNLQ 0x04
2177 field ENLQOATNPKT 0x02
2178 field ENLQOTCRC 0x01
2182 * LQO Manager Status 1
2187 modes M_DFF0, M_DFF1, M_SCSI
2188 field LQOINITSCBPERR 0x10
2189 field LQOSTOPI2 0x08
2190 field LQOBADQAS 0x04
2191 field LQOBUSFREE 0x02
2192 field LQOPHACHGINPKT 0x01
2196 * Clear LOQ Interrupt 1
2198 register CLRLQOINT1 {
2201 modes M_DFF0, M_DFF1, M_SCSI
2202 field CLRLQOINITSCBPERR 0x10
2203 field CLRLQOSTOPI2 0x08
2204 field CLRLQOBADQAS 0x04
2205 field CLRLQOBUSFREE 0x02
2206 field CLRLQOPHACHGINPKT 0x01
2210 * LQO Manager Interrupt Mode 1
2216 field ENLQOINITSCBPERR 0x10
2217 field ENLQOSTOPI2 0x08
2218 field ENLQOBADQAS 0x04
2219 field ENLQOBUSFREE 0x02
2220 field ENLQOPHACHGINPKT 0x01
2224 * LQO Manager Status 2
2229 modes M_DFF0, M_DFF1, M_SCSI
2231 field LQOWAITFIFO 0x10
2232 field LQOPHACHGOUTPKT 0x02 /* outside of packet boundaries. */
2233 field LQOSTOP0 0x01 /* Stopped after sending all packets */
2237 * Output Synchronizer Space Count
2239 register OS_SPACE_CNT {
2246 * SCSI Interrupt Mode 1
2247 * Setting any bit will enable the corresponding function
2248 * in SIMODE1 to interrupt via the IRQ pin.
2253 modes M_DFF0, M_DFF1, M_SCSI
2254 field ENSELTIMO 0x80
2255 field ENATNTARG 0x40
2256 field ENSCSIRST 0x20
2257 field ENPHASEMIS 0x10
2258 field ENBUSFREE 0x08
2259 field ENSCSIPERR 0x04
2260 field ENSTRB2FAST 0x02
2261 field ENREQINIT 0x01
2271 modes M_DFF0, M_DFF1, M_SCSI
2275 * Data FIFO SCSI Transfer Control
2277 register DFFSXFRCTL {
2280 modes M_DFF0, M_DFF1
2281 field DFFBITBUCKET 0x08
2288 * Next SCSI Control Block
2298 register LQOSCSCTL {
2303 field LQOH2A_VERSION 0x80
2304 field LQONOCHKOVER 0x01
2310 register SEQINTSRC {
2313 modes M_DFF0, M_DFF1
2317 field CFG4ISTAT 0x08
2318 field CFG4TSTAT 0x04
2324 * Clear Arp Interrupts
2326 register CLRSEQINTSRC {
2329 modes M_DFF0, M_DFF1
2330 field CLRCTXTDONE 0x40
2331 field CLRSAVEPTRS 0x20
2332 field CLRCFG4DATA 0x10
2333 field CLRCFG4ISTAT 0x08
2334 field CLRCFG4TSTAT 0x04
2335 field CLRCFG4ICMD 0x02
2336 field CLRCFG4TCMD 0x01
2340 * SEQ Interrupt Enabled (Shared)
2345 modes M_DFF0, M_DFF1
2346 field ENCTXTDONE 0x40
2347 field ENSAVEPTRS 0x20
2348 field ENCFG4DATA 0x10
2349 field ENCFG4ISTAT 0x08
2350 field ENCFG4TSTAT 0x04
2351 field ENCFG4ICMD 0x02
2352 field ENCFG4TCMD 0x01
2356 * Current SCSI Control Block
2371 modes M_DFF0, M_DFF1
2372 field SHCNTNEGATIVE 0x40 /* Rev B or higher */
2373 field SHCNTMINUS1 0x20 /* Rev B or higher */
2374 field LASTSDONE 0x10
2376 field DLZERO 0x04 /* FIFO data ends on packet boundary. */
2377 field DATAINFIFO 0x02
2384 register CRCCONTROL {
2388 field CRCVALCHKEN 0x40
2399 field SEL_TXPLL_DEBUG 0x04
2403 * Data FIFO Queue Tag
2409 modes M_DFF0, M_DFF1
2413 * Last SCSI Control Block
2423 * SCSI I/O Cell Power-down Control
2429 field DISABLE_OE 0x80
2430 field PDN_IDIST 0x04
2431 field PDN_DIFFSENSE 0x01
2435 * Shaddow Host Address.
2441 modes M_DFF0, M_DFF1
2445 * Data Group CRC Interval.
2455 * Data Transfer Negotiation Address
2464 * Data Transfer Negotiation Data - Period Byte
2466 register NEGPERIOD {
2473 * Packetized CRC Interval
2483 * Data Transfer Negotiation Data - Offset Byte
2485 register NEGOFFSET {
2492 * Data Transfer Negotiation Data - PPR Options
2494 register NEGPPROPTS {
2498 field PPROPT_PACE 0x08
2499 field PPROPT_QAS 0x04
2500 field PPROPT_DT 0x02
2501 field PPROPT_IUT 0x01
2505 * Data Transfer Negotiation Data - Connection Options
2507 register NEGCONOPTS {
2511 field ENSNAPSHOT 0x40
2512 field RTI_WRTDIS 0x20
2513 field RTI_OVRDTRN 0x10
2514 field ENSLOWCRC 0x08
2515 field ENAUTOATNI 0x04
2516 field ENAUTOATNO 0x02
2521 * Negotiation Table Annex Column Index.
2533 field STSELSKIDDIS 0x40
2534 field CURRFIFODEF 0x20
2535 field WIDERESEN 0x10
2536 field SDONEMSKDIS 0x08
2537 field DFFACTCLR 0x04
2538 field SHVALIDSTDIS 0x02
2539 field LSTSGCLRDIS 0x01
2542 const AHD_ANNEXCOL_PER_DEV0 4
2543 const AHD_NUM_PER_DEV_ANNEXCOLS 4
2544 const AHD_ANNEXCOL_PRECOMP_SLEW 4
2545 const AHD_PRECOMP_MASK 0x07
2546 const AHD_PRECOMP_SHIFT 0
2547 const AHD_PRECOMP_CUTBACK_17 0x04
2548 const AHD_PRECOMP_CUTBACK_29 0x06
2549 const AHD_PRECOMP_CUTBACK_37 0x07
2550 const AHD_SLEWRATE_MASK 0x78
2551 const AHD_SLEWRATE_SHIFT 3
2553 * Rev A has only a single bit (high bit of field) of slew adjustment.
2554 * Rev B has 4 bits. The current default happens to be the same for both.
2556 const AHD_SLEWRATE_DEF_REVA 0x08
2557 const AHD_SLEWRATE_DEF_REVB 0x08
2559 /* Rev A does not have any amplitude setting. */
2560 const AHD_ANNEXCOL_AMPLITUDE 6
2561 const AHD_AMPLITUDE_MASK 0x7
2562 const AHD_AMPLITUDE_SHIFT 0
2563 const AHD_AMPLITUDE_DEF 0x7
2566 * Negotiation Table Annex Data Port.
2575 * Initiator's Own Id.
2576 * The SCSI ID to use for Selection Out and seen during a reselection..
2585 * 960MHz Phase-Locked Loop Control 0
2587 register PLL960CTL0 {
2591 field PLL_VCOSEL 0x80
2594 field PLL_ENLUD 0x08
2595 field PLL_ENLPF 0x04
2597 field PLL_ENFBM 0x01
2610 * 960MHz Phase-Locked Loop Control 1
2612 register PLL960CTL1 {
2616 field PLL_CNTEN 0x80
2617 field PLL_CNTCLR 0x40
2622 * Expander Signature
2637 modes M_DFF0, M_DFF1
2650 * 960-MHz Phase-Locked Loop Test Count
2652 register PLL960CNT0 {
2660 * 400-MHz Phase-Locked Loop Control 0
2662 register PLL400CTL0 {
2666 field PLL_VCOSEL 0x80
2669 field PLL_ENLUD 0x08
2670 field PLL_ENLPF 0x04
2672 field PLL_ENFBM 0x01
2676 * Arbitration Fairness
2686 * 400-MHz Phase-Locked Loop Control 1
2688 register PLL400CTL1 {
2692 field PLL_CNTEN 0x80
2693 field PLL_CNTCLR 0x40
2698 * Arbitration Unfairness
2700 register UNFAIRNESS {
2708 * 400-MHz Phase-Locked Loop Test Count
2710 register PLL400CNT0 {
2724 modes M_DFF0, M_DFF1, M_CCHAN, M_SCSI
2728 * CMC SCB Array Count
2729 * Number of bytes to transfer between CMC SCB memory and SCBRAM.
2730 * Transfers must be 8byte aligned and sized.
2732 register CCSCBACNT {
2740 * SCB-Next Address Snooping logic. When an SCB is transferred to
2741 * the card, the next SCB address to be used by the CMC array can
2742 * be autoloaded from that transfer.
2744 register SCBAUTOPTR {
2748 field AUSCBPTR_EN 0x80
2749 field SCBPTR_ADDR 0x38
2750 field SCBPTR_OFF 0x07
2754 * CMC SG Ram Address Pointer
2759 modes M_DFF0, M_DFF1
2763 * CMC SCB RAM Address Pointer
2765 register CCSCBADDR {
2772 * CMC SCB Ram Back-up Address Pointer
2773 * Indicates the true stop location of transfers halted prior
2774 * to SCBHCNT going to 0.
2776 register CCSCBADR_BK {
2788 modes M_DFF0, M_DFF1
2790 field SG_CACHE_AVAIL 0x10
2791 field CCSGENACK 0x08
2793 field SG_FETCH_REQ 0x02
2794 field CCSGRESET 0x01
2804 field CCSCBDONE 0x80
2809 field CCSCBRESET 0x01
2815 register CMC_RAMBIST {
2819 field SG_ELEMENT_SIZE 0x80
2820 field SCBRAMBIST_FAIL 0x40
2821 field SG_BIST_FAIL 0x20
2822 field SG_BIST_EN 0x10
2823 field CMC_BUFFER_BIST_FAIL 0x02
2824 field CMC_BUFFER_BIST_EN 0x01
2828 * CMC SG RAM Data Port
2833 modes M_DFF0, M_DFF1
2837 * CMC SCB RAM Data Port
2856 * Flex DMA Byte Count
2868 register FLEXDMASTAT {
2872 field FLEXDMAERR 0x02
2873 field FLEXDMADONE 0x01
2877 * Flex DMA Data Port
2901 field FLXARBACK 0x80
2902 field FLXARBREQ 0x40
2910 * Serial EEPROM Address
2919 * Serial EEPROM Data
2929 * Serial EEPROM Status
2935 field INIT_DONE 0x80
2936 field SEEOPCODE 0x70
2937 field LDALTID_L 0x08
2938 field SEEARBACK 0x04
2944 * Serial EEPROM Control
2950 field SEEOPCODE 0x70 {
2955 * The following four commands use special
2956 * addresses for differentiation.
2960 mask SEEOP_EWEN 0x40
2961 mask SEEOP_WALL 0x40
2962 mask SEEOP_EWDS 0x40
2967 const SEEOP_ERAL_ADDR 0x80
2968 const SEEOP_EWEN_ADDR 0xC0
2969 const SEEOP_WRAL_ADDR 0x40
2970 const SEEOP_EWDS_ADDR 0x00
2982 * Data FIFO Write Address
2983 * Pointer to the next QWD location to be written to the data FIFO.
2989 modes M_DFF0, M_DFF1
2993 * DSP Filter Control
2995 register DSPFLTRCTL {
2999 field FLTRDISABLE 0x20
3000 field EDGESENSE 0x10
3001 field DSPFCNTSEL 0x0F
3005 * DSP Data Channel Control
3007 register DSPDATACTL {
3011 field BYPASSENAB 0x80
3013 field RCVROFFSTDIS 0x04
3014 field XMITOFFSTDIS 0x02
3018 * Data FIFO Read Address
3019 * Pointer to the next QWD location to be read from the data FIFO.
3025 modes M_DFF0, M_DFF1
3031 register DSPREQCTL {
3035 field MANREQCTL 0xC0
3036 field MANREQDLY 0x3F
3042 register DSPACKCTL {
3046 field MANACKCTL 0xC0
3047 field MANACKDLY 0x3F
3052 * Read/Write byte port into the data FIFO. The read and write
3053 * FIFO pointers increment with each read and write respectively
3059 modes M_DFF0, M_DFF1
3063 * DSP Channel Select
3065 register DSPSELECT {
3069 field AUTOINCEN 0x80
3076 * Write Bias Control
3078 register WRTBIASCTL {
3082 field AUTOXBCDIS 0x80
3083 field XMITMANVAL 0x3F
3087 * Currently the WRTBIASCTL is the same as the default.
3089 const WRTBIASCTL_HP_DEFAULT 0x0
3092 * Receiver Bias Control
3094 register RCVRBIOSCTL {
3098 field AUTORBCDIS 0x80
3099 field RCVRMANVAL 0x3F
3103 * Write Bias Calculator
3105 register WRTBIASCALC {
3112 * Data FIFO Pointers
3113 * Contains the byte offset from DFWADDR and DWRADDR to the current
3114 * FIFO write/read locations.
3119 modes M_DFF0, M_DFF1
3123 * Receiver Bias Calculator
3125 register RCVRBIASCALC {
3132 * Data FIFO Backup Read Pointer
3133 * Contains the data FIFO address to be restored if the last
3134 * data accessed from the data FIFO was not transferred successfully.
3140 modes M_DFF0, M_DFF1
3153 * Data FIFO Debug Control
3158 modes M_DFF0, M_DFF1
3159 field DFF_CIO_WR_RDY 0x20
3160 field DFF_CIO_RD_RDY 0x10
3161 field DFF_DIR_ERR 0x08
3162 field DFF_RAMBIST_FAIL 0x04
3163 field DFF_RAMBIST_DONE 0x02
3164 field DFF_RAMBIST_EN 0x01
3168 * Data FIFO Space Count
3169 * Number of FIFO locations that are free.
3175 modes M_DFF0, M_DFF1
3179 * Data FIFO Byte Count
3180 * Number of filled FIFO locations.
3186 modes M_DFF0, M_DFF1
3190 * Sequencer Program Overlay Address.
3191 * Low address must be written prior to high address.
3201 * Sequencer Control 0
3202 * Error detection mode, speed configuration,
3203 * single step, breakpoints and program load.
3208 field PERRORDIS 0x80
3212 field BRKADRINTEN 0x08
3219 * Sequencer Control 1
3220 * Instruction RAM Diagnostics
3225 field OVRLAY_DATA_CHK 0x08
3226 field RAMBIST_DONE 0x04
3227 field RAMBIST_FAIL 0x02
3228 field RAMBIST_EN 0x01
3233 * Zero and Carry state of the ALU.
3243 * Sequencer Interrupt Control
3245 register SEQINTCTL {
3248 field INTVEC1DSL 0x80
3249 field INT1_CONTEXT 0x20
3250 field SCS_SEQ_INT1M1 0x10
3251 field SCS_SEQ_INT1M0 0x08
3258 * Sequencer RAM Data Port
3259 * Single byte window into the Sequencer Instruction Ram area starting
3260 * at the address specified by OVLYADDR. To write a full instruction word,
3261 * simply write four bytes in succession. OVLYADDR will increment after the
3262 * most significant instrution byte (the byte with the parity bit) is written.
3270 * Sequencer Program Counter
3271 * Low byte must be written prior to high byte.
3289 * Source Index Register
3290 * Incrementing index for reads of SINDIR and the destination (low byte only)
3291 * for any immediate operands passed in jmp, jc, jnc, call instructions.
3293 * mvi 0xFF call some_routine;
3295 * Will set SINDEX[0] to 0xFF and call the routine "some_routine.
3305 * Destination Index Register
3306 * Incrementing index for writes to DINDIR. Can be used as a scratch register.
3316 * Sequencer instruction breakpoint address address.
3326 field BRKDIS 0x80 /* Disable Breakpoint */
3331 * All reads to this register return the value 0xFF.
3341 * All reads to this register return the value 0.
3351 * Writes to this register have no effect.
3360 * Source Index Indirect
3361 * Reading this register is equivalent to reading (register_base + SINDEX) and
3362 * incrementing SINDEX by 1.
3370 * Destination Index Indirect
3371 * Writing this register is equivalent to writing to (register_base + DINDEX)
3372 * and incrementing DINDEX by 1.
3381 * 2's complement to bit value conversion. Write the 2's complement value
3382 * (0-7 only) to the top nibble and retrieve the bit indexed by that value
3383 * on the next read of this register.
3388 register FUNCTION1 {
3395 * Window into the stack. Each stack location is 10 bits wide reported
3396 * low byte followed by high byte. There are 8 stack locations.
3404 * Interrupt Vector 1 Address
3405 * Interrupt branch address for SCS SEQ_INT1 mode 0 and 1 interrupts.
3407 register INTVEC1_ADDR {
3416 * Address of the SEQRAM instruction currently executing instruction.
3426 * Interrupt Vector 2 Address
3427 * Interrupt branch address for HST_SEQ_INT2 interrupts.
3429 register INTVEC2_ADDR {
3438 * Address of the SEQRAM instruction executed prior to the current instruction.
3447 register AHD_PCI_CONFIG_BASE {
3454 /* ---------------------- Scratch RAM Offsets ------------------------- */
3471 field SEGS_AVAIL 0x01
3472 field LOADING_NEEDED 0x02
3473 field FETCH_INPROG 0x04
3476 * Track whether the transfer byte count for
3477 * the current data phase is odd.
3503 * Per "other-id" execution queues. We use an array of
3504 * tail pointers into lists of SCBs sorted by "other-id".
3505 * The execution head pointer threads the head SCBs for
3518 * SCBID of the next SCB in the new SCB queue.
3520 NEXT_QUEUED_SCB_ADDR {
3524 * head of list of SCBs that have
3525 * completed but have not been
3526 * put into the qoutfifo.
3532 * The list of completed SCBs in
3535 COMPLETE_SCB_DMAINPROG_HEAD {
3539 * head of list of SCBs that have
3540 * completed but need to be uploaded
3541 * to the host prior to being completed.
3543 COMPLETE_DMA_SCB_HEAD {
3546 /* Counting semaphore to prevent new select-outs */
3551 * Mode to restore on legacy idle loop exit.
3557 * Single byte buffer used to designate the type or message
3558 * to send to a target.
3563 /* Parameters for DMA Logic */
3566 field PRELOADEN 0x80
3570 field SDMAENACK 0x10
3572 field HDMAENACK 0x08
3573 field DIRECTION 0x04 /* Set indicates PCI->SCSI */
3574 field FIFOFLUSH 0x02
3575 field FIFORESET 0x01
3579 field NOT_IDENTIFIED 0x80
3580 field NO_CDB_SENT 0x40
3581 field TARGET_CMD_IS_TAGGED 0x40
3584 field TARG_CMD_PENDING 0x10
3585 field CMDPHASE_PENDING 0x08
3586 field DPHASE_PENDING 0x04
3587 field SPHASE_PENDING 0x02
3588 field NO_DISCONNECT 0x01
3591 * Temporary storage for the
3592 * target/channel/lun of a
3593 * reconnecting target
3602 * The last bus phase as seen by the sequencer.
3609 field P_BUSFREE 0x01
3610 enum PHASE_MASK CDO|IOO|MSGO {
3613 P_DATAOUT_DT P_DATAOUT|MSGO,
3614 P_DATAIN_DT P_DATAIN|MSGO,
3618 P_MESGIN CDO|IOO|MSGO
3622 * Value to "or" into the SCBPTR[1] value to
3623 * indicate that an entry in the QINFIFO is valid.
3625 QOUTFIFO_ENTRY_VALID_TAG {
3629 * Base address of our shared data with the kernel driver in host
3630 * memory. This includes the qoutfifo and target mode
3631 * incoming command queue.
3637 * Pointer to location in host memory for next
3638 * position in the qoutfifo.
3640 QOUTFIFO_NEXT_ADDR {
3644 * Kernel and sequencer offsets into the queue of
3645 * incoming target mode command descriptors. The
3646 * queue is full when the KERNEL_TQINPOS == TQINPOS.
3657 mask SEND_SENSE 0x40
3659 mask MSGOUT_PHASEMIS 0x10
3660 mask EXIT_MSG_LOOP 0x08
3661 mask CONT_MSG_LOOP_WRITE 0x04
3662 mask CONT_MSG_LOOP_READ 0x03
3663 mask CONT_MSG_LOOP_TARG 0x02
3672 * Snapshot of MSG_OUT taken after each message is sent.
3679 * Sequences the kernel driver has okayed for us. This allows
3680 * the driver to do things like prevent initiator or target
3685 field MANUALCTL 0x40
3689 field ENAUTOATNP 0x02
3694 * The initiator specified tag for this target mode transaction.
3702 field TARGET_MSG_PENDING 0x02
3703 field SELECTOUT_QFROZEN 0x04
3711 * The maximum amount of time to wait, when interrupt coalescing
3712 * is enabled, before issueing a CMDCMPLT interrupt for a completed
3715 INT_COALESCING_TIMER {
3720 * The maximum number of commands to coalesce into a single interrupt.
3721 * Actually the 2's complement of that value to simplify sequencer
3724 INT_COALESCING_MAXCMDS {
3729 * The minimum number of commands still outstanding required
3730 * to continue coalescing (2's complement of value).
3732 INT_COALESCING_MINCMDS {
3737 * Number of commands "in-flight".
3744 * The count of commands that have been coalesced.
3746 INT_COALESCING_CMDCOUNT {
3751 * Since the HS_MAIBOX is self clearing, copy its contents to
3752 * this position in scratch ram every time it changes.
3758 * Target-mode CDB type to CDB length table used
3759 * in non-packetized operation.
3766 /************************* Hardware SCB Definition ****************************/
3771 SCB_RESIDUAL_DATACNT {
3774 alias SCB_HOST_CDB_PTR
3776 SCB_RESIDUAL_SGPTR {
3778 field SG_ADDR_MASK 0xf8 /* In the last byte */
3779 field SG_OVERRUN_RESID 0x02 /* In the first byte */
3780 field SG_LIST_NULL 0x01 /* In the first byte */
3784 alias SCB_HOST_CDB_LEN
3789 SCB_TARGET_DATA_DIR {
3797 * Only valid if CDB length is less than 13 bytes or
3798 * we are using a CDB pointer. Otherwise contains
3799 * the last 4 bytes of embedded cdb information.
3802 alias SCB_NEXT_COMPLETE
3805 alias SCB_FIFO_USE_COUNT
3810 field TARGET_SCB 0x80
3813 field MK_MESSAGE 0x10
3814 field STATUS_RCVD 0x08
3815 field DISCONNECTED 0x04
3816 field SCB_TAG_TYPE 0x03
3827 SCB_TASK_ATTRIBUTE {
3830 * Overloaded field for non-packetized
3831 * ignore wide residue message handling.
3833 field SCB_XFERLEN_ODD 0x01
3837 field SCB_CDB_LEN_PTR 0x80 /* CDB in host memory */
3839 SCB_TASK_MANAGEMENT {
3847 * The last byte is really the high address bits for
3851 field SG_LAST_SEG 0x80 /* In the fourth byte */
3852 field SG_HIGH_ADDR_BITS 0x7F /* In the fourth byte */
3856 field SG_STATUS_VALID 0x04 /* In the first byte */
3857 field SG_FULL_RESID 0x02 /* In the first byte */
3858 field SG_LIST_NULL 0x01 /* In the first byte */
3864 alias SCB_NEXT_SCB_BUSADDR
3874 SCB_DISCONNECTED_LISTS {
3879 /*********************************** Constants ********************************/
3880 const MK_MESSAGE_BIT_OFFSET 4
3882 const TARGET_CMD_CMPLT 0xfe
3883 const INVALID_ADDR 0x80
3884 #define SCB_LIST_NULL 0xff
3885 #define QOUTFIFO_ENTRY_VALID_TOGGLE 0x80
3887 const CCSGADDR_MAX 0x80
3888 const CCSCBADDR_MAX 0x80
3889 const CCSGRAM_MAXSEGS 16
3891 /* Selection Timeout Timer Constants */
3892 const STIMESEL_SHIFT 3
3893 const STIMESEL_MIN 0x18
3894 const STIMESEL_BUG_ADJ 0x8
3896 /* WDTR Message values */
3897 const BUS_8_BIT 0x00
3898 const BUS_16_BIT 0x01
3899 const BUS_32_BIT 0x02
3901 /* Offset maximums */
3902 const MAX_OFFSET 0xfe
3903 const MAX_OFFSET_PACED 0xfe
3904 const MAX_OFFSET_PACED_BUG 0x7f
3906 * Some 160 devices incorrectly accept 0xfe as a
3907 * sync offset, but will overrun this value. Limit
3908 * to 0x7f for speed lower than U320 which will
3909 * avoid the persistent sync offset overruns.
3911 const MAX_OFFSET_NON_PACED 0x7f
3915 * The size of our sense buffers.
3916 * Sense buffer mapping can be handled in either of two ways.
3917 * The first is to allocate a dmamap for each transaction.
3918 * Depending on the architecture, dmamaps can be costly. The
3919 * alternative is to statically map the buffers in much the same
3920 * way we handle our scatter gather lists. The driver implements
3923 const AHD_SENSE_BUFSIZE 256
3925 /* Target mode command processing constants */
3926 const CMD_GROUP_CODE_SHIFT 0x05
3928 const STATUS_BUSY 0x08
3929 const STATUS_QUEUE_FULL 0x28
3930 const STATUS_PKT_SENSE 0xFF
3931 const TARGET_DATA_IN 1
3933 const SCB_TRANSFER_SIZE_FULL_LUN 56
3934 const SCB_TRANSFER_SIZE_1BYTE_LUN 48
3935 /* PKT_OVERRUN_BUFSIZE must be a multiple of 256 less than 64K */
3936 const PKT_OVERRUN_BUFSIZE 512
3941 const AHD_TIMER_US_PER_TICK 25
3942 const AHD_TIMER_MAX_TICKS 0xFFFF
3943 const AHD_TIMER_MAX_US (AHD_TIMER_MAX_TICKS * AHD_TIMER_US_PER_TICK)
3946 * Downloaded (kernel inserted) constants
3948 const SG_PREFETCH_CNT download
3949 const SG_PREFETCH_CNT_LIMIT download
3950 const SG_PREFETCH_ALIGN_MASK download
3951 const SG_PREFETCH_ADDR_MASK download
3952 const SG_SIZEOF download
3953 const PKT_OVERRUN_BUFOFFSET download
3954 const SCB_TRANSFER_SIZE download
3959 const NVRAM_SCB_OFFSET 0x2C