sys/dev/drm/i915/intel_ringbuffer.c

   1 /*
   2  * Copyright © 2008-2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Zou Nan hai <nanhai.zou@intel.com>
  26  *    Xiang Hai hao<haihao.xiang@intel.com>
  27  *
  28  */
  29
  30 #include <drm/drmP.h>
  31 #include "i915_drv.h"
  32 #include <drm/i915_drm.h>
  33 #include "i915_trace.h"
  34 #include "intel_drv.h"
  35
  36 /*
  37  * 965+ support PIPE_CONTROL commands, which provide finer grained control
  38  * over cache flushing.
  39  */
  40 struct pipe_control {
  41         struct drm_i915_gem_object *obj;
  42         volatile u32 *cpu_page;
  43         u32 gtt_offset;
  44 };
  45
  46 static inline int ring_space(struct intel_ring_buffer *ring)
  47 {
  48         int space = (ring->head & HEAD_ADDR) - (ring->tail + I915_RING_FREE_SPACE);
  49         if (space < 0)
  50                 space += ring->size;
  51         return space;
  52 }
  53
  54 static int
  55 gen2_render_ring_flush(struct intel_ring_buffer *ring,
  56                        u32      invalidate_domains,
  57                        u32      flush_domains)
  58 {
  59         u32 cmd;
  60         int ret;
  61
  62         cmd = MI_FLUSH;
  63         if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
  64                 cmd |= MI_NO_WRITE_FLUSH;
  65
  66         if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
  67                 cmd |= MI_READ_FLUSH;
  68
  69         ret = intel_ring_begin(ring, 2);
  70         if (ret)
  71                 return ret;
  72
  73         intel_ring_emit(ring, cmd);
  74         intel_ring_emit(ring, MI_NOOP);
  75         intel_ring_advance(ring);
  76
  77         return 0;
  78 }
  79
  80 static int
  81 gen4_render_ring_flush(struct intel_ring_buffer *ring,
  82                        u32      invalidate_domains,
  83                        u32      flush_domains)
  84 {
  85         struct drm_device *dev = ring->dev;
  86         u32 cmd;
  87         int ret;
  88
  89         /*
  90          * read/write caches:
  91          *
  92          * I915_GEM_DOMAIN_RENDER is always invalidated, but is
  93          * only flushed if MI_NO_WRITE_FLUSH is unset.  On 965, it is
  94          * also flushed at 2d versus 3d pipeline switches.
  95          *
  96          * read-only caches:
  97          *
  98          * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
  99          * MI_READ_FLUSH is set, and is always flushed on 965.
 100          *
 101          * I915_GEM_DOMAIN_COMMAND may not exist?
 102          *
 103          * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
 104          * invalidated when MI_EXE_FLUSH is set.
 105          *
 106          * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
 107          * invalidated with every MI_FLUSH.
 108          *
 109          * TLBs:
 110          *
 111          * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
 112          * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
 113          * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
 114          * are flushed at any MI_FLUSH.
 115          */
 116
 117         cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
 118         if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
 119                 cmd &= ~MI_NO_WRITE_FLUSH;
 120         if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
 121                 cmd |= MI_EXE_FLUSH;
 122
 123         if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
 124             (IS_G4X(dev) || IS_GEN5(dev)))
 125                 cmd |= MI_INVALIDATE_ISP;
 126
 127         ret = intel_ring_begin(ring, 2);
 128         if (ret)
 129                 return ret;
 130
 131         intel_ring_emit(ring, cmd);
 132         intel_ring_emit(ring, MI_NOOP);
 133         intel_ring_advance(ring);
 134
 135         return 0;
 136 }
 137
 138 /**
 139  * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
 140  * implementing two workarounds on gen6.  From section 1.4.7.1
 141  * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
 142  *
 143  * [DevSNB-C+{W/A}] Before any depth stall flush (including those
 144  * produced by non-pipelined state commands), software needs to first
 145  * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
 146  * 0.
 147  *
 148  * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
 149  * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
 150  *
 151  * And the workaround for these two requires this workaround first:
 152  *
 153  * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
 154  * BEFORE the pipe-control with a post-sync op and no write-cache
 155  * flushes.
 156  *
 157  * And this last workaround is tricky because of the requirements on
 158  * that bit.  From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
 159  * volume 2 part 1:
 160  *
 161  *     "1 of the following must also be set:
 162  *      - Render Target Cache Flush Enable ([12] of DW1)
 163  *      - Depth Cache Flush Enable ([0] of DW1)
 164  *      - Stall at Pixel Scoreboard ([1] of DW1)
 165  *      - Depth Stall ([13] of DW1)
 166  *      - Post-Sync Operation ([13] of DW1)
 167  *      - Notify Enable ([8] of DW1)"
 168  *
 169  * The cache flushes require the workaround flush that triggered this
 170  * one, so we can't use it.  Depth stall would trigger the same.
 171  * Post-sync nonzero is what triggered this second workaround, so we
 172  * can't use that one either.  Notify enable is IRQs, which aren't
 173  * really our business.  That leaves only stall at scoreboard.
 174  */
 175 static int
 176 intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer *ring)
 177 {
 178         struct pipe_control *pc = ring->private;
 179         u32 scratch_addr = pc->gtt_offset + 128;
 180         int ret;
 181
 182
 183         ret = intel_ring_begin(ring, 6);
 184         if (ret)
 185                 return ret;
 186
 187         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
 188         intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
 189                         PIPE_CONTROL_STALL_AT_SCOREBOARD);
 190         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 191         intel_ring_emit(ring, 0); /* low dword */
 192         intel_ring_emit(ring, 0); /* high dword */
 193         intel_ring_emit(ring, MI_NOOP);
 194         intel_ring_advance(ring);
 195
 196         ret = intel_ring_begin(ring, 6);
 197         if (ret)
 198                 return ret;
 199
 200         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
 201         intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
 202         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 203         intel_ring_emit(ring, 0);
 204         intel_ring_emit(ring, 0);
 205         intel_ring_emit(ring, MI_NOOP);
 206         intel_ring_advance(ring);
 207
 208         return 0;
 209 }
 210
 211 static int
 212 gen6_render_ring_flush(struct intel_ring_buffer *ring,
 213                          u32 invalidate_domains, u32 flush_domains)
 214 {
 215         u32 flags = 0;
 216         struct pipe_control *pc = ring->private;
 217         u32 scratch_addr = pc->gtt_offset + 128;
 218         int ret;
 219
 220         /* Force SNB workarounds for PIPE_CONTROL flushes */
 221         ret = intel_emit_post_sync_nonzero_flush(ring);
 222         if (ret)
 223                 return ret;
 224
 225         /* Just flush everything.  Experiments have shown that reducing the
 226          * number of bits based on the write domains has little performance
 227          * impact.
 228          */
 229         if (flush_domains) {
 230                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 231                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 232                 /*
 233                  * Ensure that any following seqno writes only happen
 234                  * when the render cache is indeed flushed.
 235                  */
 236                 flags |= PIPE_CONTROL_CS_STALL;
 237         }
 238         if (invalidate_domains) {
 239                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 240                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 241                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 242                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 243                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 244                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 245                 /*
 246                  * TLB invalidate requires a post-sync write.
 247                  */
 248                 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
 249         }
 250
 251         ret = intel_ring_begin(ring, 4);
 252         if (ret)
 253                 return ret;
 254
 255         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 256         intel_ring_emit(ring, flags);
 257         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
 258         intel_ring_emit(ring, 0);
 259         intel_ring_advance(ring);
 260
 261         return 0;
 262 }
 263
 264 static int
 265 gen7_render_ring_cs_stall_wa(struct intel_ring_buffer *ring)
 266 {
 267         int ret;
 268
 269         ret = intel_ring_begin(ring, 4);
 270         if (ret)
 271                 return ret;
 272
 273         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 274         intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
 275                               PIPE_CONTROL_STALL_AT_SCOREBOARD);
 276         intel_ring_emit(ring, 0);
 277         intel_ring_emit(ring, 0);
 278         intel_ring_advance(ring);
 279
 280         return 0;
 281 }
 282
 283 static int gen7_ring_fbc_flush(struct intel_ring_buffer *ring, u32 value)
 284 {
 285         int ret;
 286
 287         if (!ring->fbc_dirty)
 288                 return 0;
 289
 290         ret = intel_ring_begin(ring, 4);
 291         if (ret)
 292                 return ret;
 293         intel_ring_emit(ring, MI_NOOP);
 294         /* WaFbcNukeOn3DBlt:ivb/hsw */
 295         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
 296         intel_ring_emit(ring, MSG_FBC_REND_STATE);
 297         intel_ring_emit(ring, value);
 298         intel_ring_advance(ring);
 299
 300         ring->fbc_dirty = false;
 301         return 0;
 302 }
 303
 304 static int
 305 gen7_render_ring_flush(struct intel_ring_buffer *ring,
 306                        u32 invalidate_domains, u32 flush_domains)
 307 {
 308         u32 flags = 0;
 309         struct pipe_control *pc = ring->private;
 310         u32 scratch_addr = pc->gtt_offset + 128;
 311         int ret;
 312
 313         /*
 314          * Ensure that any following seqno writes only happen when the render
 315          * cache is indeed flushed.
 316          *
 317          * Workaround: 4th PIPE_CONTROL command (except the ones with only
 318          * read-cache invalidate bits set) must have the CS_STALL bit set. We
 319          * don't try to be clever and just set it unconditionally.
 320          */
 321         flags |= PIPE_CONTROL_CS_STALL;
 322
 323         /* Just flush everything.  Experiments have shown that reducing the
 324          * number of bits based on the write domains has little performance
 325          * impact.
 326          */
 327         if (flush_domains) {
 328                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 329                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 330         }
 331         if (invalidate_domains) {
 332                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 333                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 334                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 335                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 336                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 337                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 338                 /*
 339                  * TLB invalidate requires a post-sync write.
 340                  */
 341                 flags |= PIPE_CONTROL_QW_WRITE;
 342                 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
 343
 344                 /* Workaround: we must issue a pipe_control with CS-stall bit
 345                  * set before a pipe_control command that has the state cache
 346                  * invalidate bit set. */
 347                 gen7_render_ring_cs_stall_wa(ring);
 348         }
 349
 350         ret = intel_ring_begin(ring, 4);
 351         if (ret)
 352                 return ret;
 353
 354         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 355         intel_ring_emit(ring, flags);
 356         intel_ring_emit(ring, scratch_addr);
 357         intel_ring_emit(ring, 0);
 358         intel_ring_advance(ring);
 359
 360         if (flush_domains)
 361                 return gen7_ring_fbc_flush(ring, FBC_REND_NUKE);
 362
 363         return 0;
 364 }
 365
 366 static void ring_write_tail(struct intel_ring_buffer *ring,
 367                             u32 value)
 368 {
 369         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 370         I915_WRITE_TAIL(ring, value);
 371 }
 372
 373 u32 intel_ring_get_active_head(struct intel_ring_buffer *ring)
 374 {
 375         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 376         u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ?
 377                         RING_ACTHD(ring->mmio_base) : ACTHD;
 378
 379         return I915_READ(acthd_reg);
 380 }
 381
 382 static void ring_setup_phys_status_page(struct intel_ring_buffer *ring)
 383 {
 384         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 385         u32 addr;
 386
 387         addr = dev_priv->status_page_dmah->busaddr;
 388         if (INTEL_INFO(ring->dev)->gen >= 4)
 389                 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
 390         I915_WRITE(HWS_PGA, addr);
 391 }
 392
 393 static int init_ring_common(struct intel_ring_buffer *ring)
 394 {
 395         struct drm_device *dev = ring->dev;
 396         drm_i915_private_t *dev_priv = dev->dev_private;
 397         struct drm_i915_gem_object *obj = ring->obj;
 398         int ret = 0;
 399         u32 head;
 400
 401         if (HAS_FORCE_WAKE(dev))
 402                 gen6_gt_force_wake_get(dev_priv);
 403
 404         if (I915_NEED_GFX_HWS(dev))
 405                 intel_ring_setup_status_page(ring);
 406         else
 407                 ring_setup_phys_status_page(ring);
 408
 409         /* Stop the ring if it's running. */
 410         I915_WRITE_CTL(ring, 0);
 411         I915_WRITE_HEAD(ring, 0);
 412         ring->write_tail(ring, 0);
 413
 414         head = I915_READ_HEAD(ring) & HEAD_ADDR;
 415
 416         /* G45 ring initialization fails to reset head to zero */
 417         if (head != 0) {
 418                 DRM_DEBUG_KMS("%s head not reset to zero "
 419                               "ctl %08x head %08x tail %08x start %08x\n",
 420                               ring->name,
 421                               I915_READ_CTL(ring),
 422                               I915_READ_HEAD(ring),
 423                               I915_READ_TAIL(ring),
 424                               I915_READ_START(ring));
 425
 426                 I915_WRITE_HEAD(ring, 0);
 427
 428                 if (I915_READ_HEAD(ring) & HEAD_ADDR) {
 429                         DRM_ERROR("failed to set %s head to zero "
 430                                   "ctl %08x head %08x tail %08x start %08x\n",
 431                                   ring->name,
 432                                   I915_READ_CTL(ring),
 433                                   I915_READ_HEAD(ring),
 434                                   I915_READ_TAIL(ring),
 435                                   I915_READ_START(ring));
 436                 }
 437         }
 438
 439         /* Initialize the ring. This must happen _after_ we've cleared the ring
 440          * registers with the above sequence (the readback of the HEAD registers
 441          * also enforces ordering), otherwise the hw might lose the new ring
 442          * register values. */
 443         I915_WRITE_START(ring, obj->gtt_offset);
 444         I915_WRITE_CTL(ring,
 445                         ((ring->size - PAGE_SIZE) & RING_NR_PAGES)
 446                         | RING_VALID);
 447
 448         /* If the head is still not zero, the ring is dead */
 449         if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
 450                      I915_READ_START(ring) == obj->gtt_offset &&
 451                      (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
 452                 DRM_ERROR("%s initialization failed "
 453                                 "ctl %08x head %08x tail %08x start %08x\n",
 454                                 ring->name,
 455                                 I915_READ_CTL(ring),
 456                                 I915_READ_HEAD(ring),
 457                                 I915_READ_TAIL(ring),
 458                                 I915_READ_START(ring));
 459                 ret = -EIO;
 460                 goto out;
 461         }
 462
 463         if (!drm_core_check_feature(ring->dev, DRIVER_MODESET))
 464                 i915_kernel_lost_context(ring->dev);
 465         else {
 466                 ring->head = I915_READ_HEAD(ring);
 467                 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
 468                 ring->space = ring_space(ring);
 469                 ring->last_retired_head = -1;
 470         }
 471
 472         memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
 473
 474 out:
 475         if (HAS_FORCE_WAKE(dev))
 476                 gen6_gt_force_wake_put(dev_priv);
 477
 478         return ret;
 479 }
 480
 481 static int
 482 init_pipe_control(struct intel_ring_buffer *ring)
 483 {
 484         struct pipe_control *pc;
 485         struct drm_i915_gem_object *obj;
 486         int ret;
 487
 488         if (ring->private)
 489                 return 0;
 490
 491         pc = kmalloc(sizeof(*pc), M_DRM, M_WAITOK);
 492         if (!pc)
 493                 return -ENOMEM;
 494
 495         obj = i915_gem_alloc_object(ring->dev, 4096);
 496         if (obj == NULL) {
 497                 DRM_ERROR("Failed to allocate seqno page\n");
 498                 ret = -ENOMEM;
 499                 goto err;
 500         }
 501
 502         i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
 503
 504         ret = i915_gem_object_pin(obj, 4096, true, false);
 505         if (ret)
 506                 goto err_unref;
 507
 508         pc->gtt_offset = obj->gtt_offset;
 509         pc->cpu_page = kmap(obj->pages[0]);
 510         if (pc->cpu_page == NULL) {
 511                 ret = -ENOMEM;
 512                 goto err_unpin;
 513         }
 514
 515         pmap_qenter((uintptr_t)pc->cpu_page, &obj->pages[0], 1);
 516         pmap_invalidate_cache_range((vm_offset_t)pc->cpu_page,
 517             (vm_offset_t)pc->cpu_page + PAGE_SIZE);
 518         DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
 519                          ring->name, pc->gtt_offset);
 520
 521         pc->obj = obj;
 522         ring->private = pc;
 523         return 0;
 524
 525 err_unpin:
 526         i915_gem_object_unpin(obj);
 527 err_unref:
 528         drm_gem_object_unreference(&obj->base);
 529 err:
 530         kfree(pc);
 531         return ret;
 532 }
 533
 534 static void
 535 cleanup_pipe_control(struct intel_ring_buffer *ring)
 536 {
 537         struct pipe_control *pc = ring->private;
 538         struct drm_i915_gem_object *obj;
 539
 540         obj = pc->obj;
 541
 542         pmap_qremove((vm_offset_t)pc->cpu_page, 1);
 543         kmem_free(&kernel_map, (uintptr_t)pc->cpu_page, PAGE_SIZE);
 544         i915_gem_object_unpin(obj);
 545         drm_gem_object_unreference(&obj->base);
 546
 547         kfree(pc);
 548 }
 549
 550 static int init_render_ring(struct intel_ring_buffer *ring)
 551 {
 552         struct drm_device *dev = ring->dev;
 553         struct drm_i915_private *dev_priv = dev->dev_private;
 554         int ret = init_ring_common(ring);
 555
 556         if (INTEL_INFO(dev)->gen > 3)
 557                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
 558
 559         /* We need to disable the AsyncFlip performance optimisations in order
 560          * to use MI_WAIT_FOR_EVENT within the CS. It should already be
 561          * programmed to '1' on all products.
 562          *
 563          * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
 564          */
 565         if (INTEL_INFO(dev)->gen >= 6)
 566                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
 567
 568         /* Required for the hardware to program scanline values for waiting */
 569         if (INTEL_INFO(dev)->gen == 6)
 570                 I915_WRITE(GFX_MODE,
 571                            _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_ALWAYS));
 572
 573         if (IS_GEN7(dev))
 574                 I915_WRITE(GFX_MODE_GEN7,
 575                            _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) |
 576                            _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
 577
 578         if (INTEL_INFO(dev)->gen >= 5) {
 579                 ret = init_pipe_control(ring);
 580                 if (ret)
 581                         return ret;
 582         }
 583
 584         if (IS_GEN6(dev)) {
 585                 /* From the Sandybridge PRM, volume 1 part 3, page 24:
 586                  * "If this bit is set, STCunit will have LRA as replacement
 587                  *  policy. [...] This bit must be reset.  LRA replacement
 588                  *  policy is not supported."
 589                  */
 590                 I915_WRITE(CACHE_MODE_0,
 591                            _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
 592
 593                 /* This is not explicitly set for GEN6, so read the register.
 594                  * see intel_ring_mi_set_context() for why we care.
 595                  * TODO: consider explicitly setting the bit for GEN5
 596                  */
 597                 ring->itlb_before_ctx_switch =
 598                         !!(I915_READ(GFX_MODE) & GFX_TLB_INVALIDATE_ALWAYS);
 599         }
 600
 601         if (INTEL_INFO(dev)->gen >= 6)
 602                 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
 603
 604         if (HAS_L3_GPU_CACHE(dev))
 605                 I915_WRITE_IMR(ring, ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
 606
 607         return ret;
 608 }
 609
 610 static void render_ring_cleanup(struct intel_ring_buffer *ring)
 611 {
 612         struct drm_device *dev = ring->dev;
 613
 614         if (!ring->private)
 615                 return;
 616
 617         if (HAS_BROKEN_CS_TLB(dev))
 618                 drm_gem_object_unreference(to_gem_object(ring->private));
 619
 620         if (INTEL_INFO(dev)->gen >= 5)
 621                 cleanup_pipe_control(ring);
 622
 623         ring->private = NULL;
 624 }
 625
 626 static void
 627 update_mboxes(struct intel_ring_buffer *ring,
 628               u32 mmio_offset)
 629 {
 630 /* NB: In order to be able to do semaphore MBOX updates for varying number
 631  * of rings, it's easiest if we round up each individual update to a
 632  * multiple of 2 (since ring updates must always be a multiple of 2)
 633  * even though the actual update only requires 3 dwords.
 634  */
 635 #define MBOX_UPDATE_DWORDS 4
 636         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
 637         intel_ring_emit(ring, mmio_offset);
 638         intel_ring_emit(ring, ring->outstanding_lazy_request);
 639         intel_ring_emit(ring, MI_NOOP);
 640 }
 641
 642 /**
 643  * gen6_add_request - Update the semaphore mailbox registers
 644  *
 645  * @ring - ring that is adding a request
 646  * @seqno - return seqno stuck into the ring
 647  *
 648  * Update the mailbox registers in the *other* rings with the current seqno.
 649  * This acts like a signal in the canonical semaphore.
 650  */
 651 static int
 652 gen6_add_request(struct intel_ring_buffer *ring)
 653 {
 654         struct drm_device *dev = ring->dev;
 655         struct drm_i915_private *dev_priv = dev->dev_private;
 656         struct intel_ring_buffer *useless;
 657         int i, ret;
 658
 659         ret = intel_ring_begin(ring, ((I915_NUM_RINGS-1) *
 660                                       MBOX_UPDATE_DWORDS) +
 661                                       4);
 662         if (ret)
 663                 return ret;
 664 #undef MBOX_UPDATE_DWORDS
 665
 666         for_each_ring(useless, dev_priv, i) {
 667                 u32 mbox_reg = ring->signal_mbox[i];
 668                 if (mbox_reg != GEN6_NOSYNC)
 669                         update_mboxes(ring, mbox_reg);
 670         }
 671
 672         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
 673         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 674         intel_ring_emit(ring, ring->outstanding_lazy_request);
 675         intel_ring_emit(ring, MI_USER_INTERRUPT);
 676         intel_ring_advance(ring);
 677
 678         return 0;
 679 }
 680
 681 static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
 682                                               u32 seqno)
 683 {
 684         struct drm_i915_private *dev_priv = dev->dev_private;
 685         return dev_priv->last_seqno < seqno;
 686 }
 687
 688 /**
 689  * intel_ring_sync - sync the waiter to the signaller on seqno
 690  *
 691  * @waiter - ring that is waiting
 692  * @signaller - ring which has, or will signal
 693  * @seqno - seqno which the waiter will block on
 694  */
 695 static int
 696 gen6_ring_sync(struct intel_ring_buffer *waiter,
 697                struct intel_ring_buffer *signaller,
 698                u32 seqno)
 699 {
 700         int ret;
 701         u32 dw1 = MI_SEMAPHORE_MBOX |
 702                   MI_SEMAPHORE_COMPARE |
 703                   MI_SEMAPHORE_REGISTER;
 704
 705         /* Throughout all of the GEM code, seqno passed implies our current
 706          * seqno is >= the last seqno executed. However for hardware the
 707          * comparison is strictly greater than.
 708          */
 709         seqno -= 1;
 710
 711         WARN_ON(signaller->semaphore_register[waiter->id] ==
 712                 MI_SEMAPHORE_SYNC_INVALID);
 713
 714         ret = intel_ring_begin(waiter, 4);
 715         if (ret)
 716                 return ret;
 717
 718         /* If seqno wrap happened, omit the wait with no-ops */
 719         if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
 720                 intel_ring_emit(waiter,
 721                                 dw1 |
 722                                 signaller->semaphore_register[waiter->id]);
 723                 intel_ring_emit(waiter, seqno);
 724                 intel_ring_emit(waiter, 0);
 725                 intel_ring_emit(waiter, MI_NOOP);
 726         } else {
 727                 intel_ring_emit(waiter, MI_NOOP);
 728                 intel_ring_emit(waiter, MI_NOOP);
 729                 intel_ring_emit(waiter, MI_NOOP);
 730                 intel_ring_emit(waiter, MI_NOOP);
 731         }
 732         intel_ring_advance(waiter);
 733
 734         return 0;
 735 }
 736
 737 #define PIPE_CONTROL_FLUSH(ring__, addr__)                                      \
 738 do {                                                                    \
 739         intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |                \
 740                  PIPE_CONTROL_DEPTH_STALL);                             \
 741         intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT);                    \
 742         intel_ring_emit(ring__, 0);                                                     \
 743         intel_ring_emit(ring__, 0);                                                     \
 744 } while (0)
 745
 746 static int
 747 pc_render_add_request(struct intel_ring_buffer *ring)
 748 {
 749         struct pipe_control *pc = ring->private;
 750         u32 scratch_addr = pc->gtt_offset + 128;
 751         int ret;
 752
 753         /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
 754          * incoherent with writes to memory, i.e. completely fubar,
 755          * so we need to use PIPE_NOTIFY instead.
 756          *
 757          * However, we also need to workaround the qword write
 758          * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
 759          * memory before requesting an interrupt.
 760          */
 761         ret = intel_ring_begin(ring, 32);
 762         if (ret)
 763                 return ret;
 764
 765         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
 766                         PIPE_CONTROL_WRITE_FLUSH |
 767                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
 768         intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
 769         intel_ring_emit(ring, ring->outstanding_lazy_request);
 770         intel_ring_emit(ring, 0);
 771         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 772         scratch_addr += 128; /* write to separate cachelines */
 773         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 774         scratch_addr += 128;
 775         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 776         scratch_addr += 128;
 777         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 778         scratch_addr += 128;
 779         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 780         scratch_addr += 128;
 781         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 782
 783         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
 784                         PIPE_CONTROL_WRITE_FLUSH |
 785                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
 786                         PIPE_CONTROL_NOTIFY);
 787         intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
 788         intel_ring_emit(ring, ring->outstanding_lazy_request);
 789         intel_ring_emit(ring, 0);
 790         intel_ring_advance(ring);
 791
 792         return 0;
 793 }
 794
 795 static u32
 796 gen6_ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
 797 {
 798         /* Workaround to force correct ordering between irq and seqno writes on
 799          * ivb (and maybe also on snb) by reading from a CS register (like
 800          * ACTHD) before reading the status page. */
 801         if (!lazy_coherency)
 802                 intel_ring_get_active_head(ring);
 803         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
 804 }
 805
 806 static u32
 807 ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
 808 {
 809         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
 810 }
 811
 812 static void
 813 ring_set_seqno(struct intel_ring_buffer *ring, u32 seqno)
 814 {
 815         intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
 816 }
 817
 818 static u32
 819 pc_render_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
 820 {
 821         struct pipe_control *pc = ring->private;
 822         return pc->cpu_page[0];
 823 }
 824
 825 static void
 826 pc_render_set_seqno(struct intel_ring_buffer *ring, u32 seqno)
 827 {
 828         struct pipe_control *pc = ring->private;
 829         pc->cpu_page[0] = seqno;
 830 }
 831
 832 static bool
 833 gen5_ring_get_irq(struct intel_ring_buffer *ring)
 834 {
 835         struct drm_device *dev = ring->dev;
 836         drm_i915_private_t *dev_priv = dev->dev_private;
 837
 838         if (!dev->irq_enabled)
 839                 return false;
 840
 841         lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
 842         if (ring->irq_refcount.gt++ == 0) {
 843                 dev_priv->gt_irq_mask &= ~ring->irq_enable_mask;
 844                 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 845                 POSTING_READ(GTIMR);
 846         }
 847         lockmgr(&dev_priv->irq_lock, LK_RELEASE);
 848
 849         return true;
 850 }
 851
 852 static void
 853 gen5_ring_put_irq(struct intel_ring_buffer *ring)
 854 {
 855         struct drm_device *dev = ring->dev;
 856         drm_i915_private_t *dev_priv = dev->dev_private;
 857
 858         lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
 859         if (--ring->irq_refcount.gt == 0) {
 860                 dev_priv->gt_irq_mask |= ring->irq_enable_mask;
 861                 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 862                 POSTING_READ(GTIMR);
 863         }
 864         lockmgr(&dev_priv->irq_lock, LK_RELEASE);
 865 }
 866
 867 static bool
 868 i9xx_ring_get_irq(struct intel_ring_buffer *ring)
 869 {
 870         struct drm_device *dev = ring->dev;
 871         drm_i915_private_t *dev_priv = dev->dev_private;
 872
 873         if (!dev->irq_enabled)
 874                 return false;
 875
 876         lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
 877         if (ring->irq_refcount.gt++ == 0) {
 878                 dev_priv->irq_mask &= ~ring->irq_enable_mask;
 879                 I915_WRITE(IMR, dev_priv->irq_mask);
 880                 POSTING_READ(IMR);
 881         }
 882         lockmgr(&dev_priv->irq_lock, LK_RELEASE);
 883
 884         return true;
 885 }
 886
 887 static void
 888 i9xx_ring_put_irq(struct intel_ring_buffer *ring)
 889 {
 890         struct drm_device *dev = ring->dev;
 891         drm_i915_private_t *dev_priv = dev->dev_private;
 892
 893         lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
 894         if (--ring->irq_refcount.gt == 0) {
 895                 dev_priv->irq_mask |= ring->irq_enable_mask;
 896                 I915_WRITE(IMR, dev_priv->irq_mask);
 897                 POSTING_READ(IMR);
 898         }
 899         lockmgr(&dev_priv->irq_lock, LK_RELEASE);
 900 }
 901
 902 static bool
 903 i8xx_ring_get_irq(struct intel_ring_buffer *ring)
 904 {
 905         struct drm_device *dev = ring->dev;
 906         drm_i915_private_t *dev_priv = dev->dev_private;
 907
 908         if (!dev->irq_enabled)
 909                 return false;
 910
 911         lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
 912         if (ring->irq_refcount.gt++ == 0) {
 913                 dev_priv->irq_mask &= ~ring->irq_enable_mask;
 914                 I915_WRITE16(IMR, dev_priv->irq_mask);
 915                 POSTING_READ16(IMR);
 916         }
 917         lockmgr(&dev_priv->irq_lock, LK_RELEASE);
 918
 919         return true;
 920 }
 921
 922 static void
 923 i8xx_ring_put_irq(struct intel_ring_buffer *ring)
 924 {
 925         struct drm_device *dev = ring->dev;
 926         drm_i915_private_t *dev_priv = dev->dev_private;
 927
 928         lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
 929         if (--ring->irq_refcount.gt == 0) {
 930                 dev_priv->irq_mask |= ring->irq_enable_mask;
 931                 I915_WRITE16(IMR, dev_priv->irq_mask);
 932                 POSTING_READ16(IMR);
 933         }
 934         lockmgr(&dev_priv->irq_lock, LK_RELEASE);
 935 }
 936
 937 void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
 938 {
 939         struct drm_device *dev = ring->dev;
 940         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 941         u32 mmio = 0;
 942
 943         /* The ring status page addresses are no longer next to the rest of
 944          * the ring registers as of gen7.
 945          */
 946         if (IS_GEN7(dev)) {
 947                 switch (ring->id) {
 948                 case RCS:
 949                         mmio = RENDER_HWS_PGA_GEN7;
 950                         break;
 951                 case BCS:
 952                         mmio = BLT_HWS_PGA_GEN7;
 953                         break;
 954                 case VCS:
 955                         mmio = BSD_HWS_PGA_GEN7;
 956                         break;
 957                 case VECS:
 958                         mmio = VEBOX_HWS_PGA_GEN7;
 959                         break;
 960                 }
 961         } else if (IS_GEN6(ring->dev)) {
 962                 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
 963         } else {
 964                 mmio = RING_HWS_PGA(ring->mmio_base);
 965         }
 966
 967         I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
 968         POSTING_READ(mmio);
 969
 970         /* Flush the TLB for this page */
 971         if (INTEL_INFO(dev)->gen >= 6) {
 972                 u32 reg = RING_INSTPM(ring->mmio_base);
 973                 I915_WRITE(reg,
 974                            _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
 975                                               INSTPM_SYNC_FLUSH));
 976                 if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,
 977                              1000))
 978                         DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
 979                                   ring->name);
 980         }
 981 }
 982
 983 static int
 984 bsd_ring_flush(struct intel_ring_buffer *ring,
 985                u32     invalidate_domains,
 986                u32     flush_domains)
 987 {
 988         int ret;
 989
 990         ret = intel_ring_begin(ring, 2);
 991         if (ret)
 992                 return ret;
 993
 994         intel_ring_emit(ring, MI_FLUSH);
 995         intel_ring_emit(ring, MI_NOOP);
 996         intel_ring_advance(ring);
 997         return 0;
 998 }
 999
1000 static int
1001 i9xx_add_request(struct intel_ring_buffer *ring)
1002 {
1003         int ret;
1004
1005         ret = intel_ring_begin(ring, 4);
1006         if (ret)
1007                 return ret;
1008
1009         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1010         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1011         intel_ring_emit(ring, ring->outstanding_lazy_request);
1012         intel_ring_emit(ring, MI_USER_INTERRUPT);
1013         intel_ring_advance(ring);
1014
1015         return 0;
1016 }
1017
1018 static bool
1019 gen6_ring_get_irq(struct intel_ring_buffer *ring)
1020 {
1021         struct drm_device *dev = ring->dev;
1022         drm_i915_private_t *dev_priv = dev->dev_private;
1023
1024         if (!dev->irq_enabled)
1025                return false;
1026
1027         /* It looks like we need to prevent the gt from suspending while waiting
1028          * for an notifiy irq, otherwise irqs seem to get lost on at least the
1029          * blt/bsd rings on ivb. */
1030         gen6_gt_force_wake_get(dev_priv);
1031
1032         lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
1033         if (ring->irq_refcount.gt++ == 0) {
1034                 if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS)
1035                         I915_WRITE_IMR(ring,
1036                                        ~(ring->irq_enable_mask |
1037                                          GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
1038                 else
1039                         I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1040                 dev_priv->gt_irq_mask &= ~ring->irq_enable_mask;
1041                 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
1042                 POSTING_READ(GTIMR);
1043         }
1044         lockmgr(&dev_priv->irq_lock, LK_RELEASE);
1045
1046         return true;
1047 }
1048
1049 static void
1050 gen6_ring_put_irq(struct intel_ring_buffer *ring)
1051 {
1052         struct drm_device *dev = ring->dev;
1053         drm_i915_private_t *dev_priv = dev->dev_private;
1054
1055         lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
1056         if (--ring->irq_refcount.gt == 0) {
1057                 if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS)
1058                         I915_WRITE_IMR(ring,
1059                                        ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
1060                 else
1061                         I915_WRITE_IMR(ring, ~0);
1062                 dev_priv->gt_irq_mask |= ring->irq_enable_mask;
1063                 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
1064                 POSTING_READ(GTIMR);
1065         }
1066         lockmgr(&dev_priv->irq_lock, LK_RELEASE);
1067
1068         gen6_gt_force_wake_put(dev_priv);
1069 }
1070
1071 static bool
1072 hsw_vebox_get_irq(struct intel_ring_buffer *ring)
1073 {
1074         struct drm_device *dev = ring->dev;
1075         struct drm_i915_private *dev_priv = dev->dev_private;
1076
1077         if (!dev->irq_enabled)
1078                 return false;
1079
1080         lockmgr(&dev_priv->rps.lock, LK_EXCLUSIVE);
1081         if (ring->irq_refcount.pm++ == 0) {
1082                 u32 pm_imr = I915_READ(GEN6_PMIMR);
1083                 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1084                 I915_WRITE(GEN6_PMIMR, pm_imr & ~ring->irq_enable_mask);
1085                 POSTING_READ(GEN6_PMIMR);
1086         }
1087         lockmgr(&dev_priv->rps.lock, LK_RELEASE);
1088
1089         return true;
1090 }
1091
1092 static void
1093 hsw_vebox_put_irq(struct intel_ring_buffer *ring)
1094 {
1095         struct drm_device *dev = ring->dev;
1096         struct drm_i915_private *dev_priv = dev->dev_private;
1097
1098         if (!dev->irq_enabled)
1099                 return;
1100
1101         lockmgr(&dev_priv->rps.lock, LK_EXCLUSIVE);
1102         if (--ring->irq_refcount.pm == 0) {
1103                 u32 pm_imr = I915_READ(GEN6_PMIMR);
1104                 I915_WRITE_IMR(ring, ~0);
1105                 I915_WRITE(GEN6_PMIMR, pm_imr | ring->irq_enable_mask);
1106                 POSTING_READ(GEN6_PMIMR);
1107         }
1108         lockmgr(&dev_priv->rps.lock, LK_RELEASE);
1109 }
1110
1111 static int
1112 i965_dispatch_execbuffer(struct intel_ring_buffer *ring,
1113                          u32 offset, u32 length,
1114                          unsigned flags)
1115 {
1116         int ret;
1117
1118         ret = intel_ring_begin(ring, 2);
1119         if (ret)
1120                 return ret;
1121
1122         intel_ring_emit(ring,
1123                         MI_BATCH_BUFFER_START |
1124                         MI_BATCH_GTT |
1125                         (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
1126         intel_ring_emit(ring, offset);
1127         intel_ring_advance(ring);
1128
1129         return 0;
1130 }
1131
1132 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1133 #define I830_BATCH_LIMIT (256*1024)
1134 static int
1135 i830_dispatch_execbuffer(struct intel_ring_buffer *ring,
1136                                 u32 offset, u32 len,
1137                                 unsigned flags)
1138 {
1139         int ret;
1140
1141         if (flags & I915_DISPATCH_PINNED) {
1142                 ret = intel_ring_begin(ring, 4);
1143                 if (ret)
1144                         return ret;
1145
1146                 intel_ring_emit(ring, MI_BATCH_BUFFER);
1147                 intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1148                 intel_ring_emit(ring, offset + len - 8);
1149                 intel_ring_emit(ring, MI_NOOP);
1150                 intel_ring_advance(ring);
1151         } else {
1152                 struct drm_i915_gem_object *obj = ring->private;
1153                 u32 cs_offset = obj->gtt_offset;
1154
1155                 if (len > I830_BATCH_LIMIT)
1156                         return -ENOSPC;
1157
1158                 ret = intel_ring_begin(ring, 9+3);
1159                 if (ret)
1160                         return ret;
1161                 /* Blit the batch (which has now all relocs applied) to the stable batch
1162                  * scratch bo area (so that the CS never stumbles over its tlb
1163                  * invalidation bug) ... */
1164                 intel_ring_emit(ring, XY_SRC_COPY_BLT_CMD |
1165                                 XY_SRC_COPY_BLT_WRITE_ALPHA |
1166                                 XY_SRC_COPY_BLT_WRITE_RGB);
1167                 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_GXCOPY | 4096);
1168                 intel_ring_emit(ring, 0);
1169                 intel_ring_emit(ring, (DIV_ROUND_UP(len, 4096) << 16) | 1024);
1170                 intel_ring_emit(ring, cs_offset);
1171                 intel_ring_emit(ring, 0);
1172                 intel_ring_emit(ring, 4096);
1173                 intel_ring_emit(ring, offset);
1174                 intel_ring_emit(ring, MI_FLUSH);
1175
1176                 /* ... and execute it. */
1177                 intel_ring_emit(ring, MI_BATCH_BUFFER);
1178                 intel_ring_emit(ring, cs_offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1179                 intel_ring_emit(ring, cs_offset + len - 8);
1180                 intel_ring_advance(ring);
1181         }
1182
1183         return 0;
1184 }
1185
1186 static int
1187 i915_dispatch_execbuffer(struct intel_ring_buffer *ring,
1188                          u32 offset, u32 len,
1189                          unsigned flags)
1190 {
1191         int ret;
1192
1193         ret = intel_ring_begin(ring, 2);
1194         if (ret)
1195                 return ret;
1196
1197         intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1198         intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1199         intel_ring_advance(ring);
1200
1201         return 0;
1202 }
1203
1204 static void cleanup_status_page(struct intel_ring_buffer *ring)
1205 {
1206         struct drm_i915_gem_object *obj;
1207
1208         obj = ring->status_page.obj;
1209         if (obj == NULL)
1210                 return;
1211
1212         pmap_qremove((vm_offset_t)ring->status_page.page_addr, 1);
1213         kmem_free(&kernel_map, (vm_offset_t)ring->status_page.page_addr,
1214             PAGE_SIZE);
1215         i915_gem_object_unpin(obj);
1216         drm_gem_object_unreference(&obj->base);
1217         ring->status_page.obj = NULL;
1218 }
1219
1220 static int init_status_page(struct intel_ring_buffer *ring)
1221 {
1222         struct drm_device *dev = ring->dev;
1223         struct drm_i915_gem_object *obj;
1224         int ret;
1225
1226         obj = i915_gem_alloc_object(dev, 4096);
1227         if (obj == NULL) {
1228                 DRM_ERROR("Failed to allocate status page\n");
1229                 ret = -ENOMEM;
1230                 goto err;
1231         }
1232
1233         i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
1234
1235         ret = i915_gem_object_pin(obj, 4096, true, false);
1236         if (ret != 0) {
1237                 goto err_unref;
1238         }
1239
1240         ring->status_page.gfx_addr = obj->gtt_offset;
1241         ring->status_page.page_addr = kmap(obj->pages[0]);
1242         if (ring->status_page.page_addr == NULL) {
1243                 ret = -ENOMEM;
1244                 goto err_unpin;
1245         }
1246         pmap_qenter((vm_offset_t)ring->status_page.page_addr, &obj->pages[0], 1);
1247         pmap_invalidate_cache_range((vm_offset_t)ring->status_page.page_addr,
1248             (vm_offset_t)ring->status_page.page_addr + PAGE_SIZE);
1249         ring->status_page.obj = obj;
1250         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1251
1252         DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1253                         ring->name, ring->status_page.gfx_addr);
1254
1255         return 0;
1256
1257 err_unpin:
1258         i915_gem_object_unpin(obj);
1259 err_unref:
1260         drm_gem_object_unreference(&obj->base);
1261 err:
1262         return ret;
1263 }
1264
1265 static int init_phys_status_page(struct intel_ring_buffer *ring)
1266 {
1267         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1268
1269         if (!dev_priv->status_page_dmah) {
1270                 dev_priv->status_page_dmah =
1271                         drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE);
1272                 if (!dev_priv->status_page_dmah)
1273                         return -ENOMEM;
1274         }
1275
1276         ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1277         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1278
1279         return 0;
1280 }
1281
1282 static int intel_init_ring_buffer(struct drm_device *dev,
1283                                   struct intel_ring_buffer *ring)
1284 {
1285         struct drm_i915_gem_object *obj;
1286         int ret;
1287
1288         ring->dev = dev;
1289         INIT_LIST_HEAD(&ring->active_list);
1290         INIT_LIST_HEAD(&ring->request_list);
1291         ring->size = 32 * PAGE_SIZE;
1292         memset(ring->sync_seqno, 0, sizeof(ring->sync_seqno));
1293
1294         init_waitqueue_head(&ring->irq_queue);
1295
1296         if (I915_NEED_GFX_HWS(dev)) {
1297                 ret = init_status_page(ring);
1298                 if (ret)
1299                         return ret;
1300         } else {
1301                 BUG_ON(ring->id != RCS);
1302                 ret = init_phys_status_page(ring);
1303                 if (ret)
1304                         return ret;
1305         }
1306
1307         obj = NULL;
1308         if (!HAS_LLC(dev))
1309                 obj = i915_gem_alloc_object(dev, ring->size);
1310         if (obj == NULL)
1311                 obj = i915_gem_alloc_object(dev, ring->size);
1312         if (obj == NULL) {
1313                 DRM_ERROR("Failed to allocate ringbuffer\n");
1314                 ret = -ENOMEM;
1315                 goto err_hws;
1316         }
1317
1318         ring->obj = obj;
1319
1320         ret = i915_gem_object_pin(obj, PAGE_SIZE, true, false);
1321         if (ret)
1322                 goto err_unref;
1323
1324         ret = i915_gem_object_set_to_gtt_domain(obj, true);
1325         if (ret)
1326                 goto err_unpin;
1327
1328         ring->virtual_start =
1329                 ioremap_wc(dev->agp->base + obj->gtt_offset,
1330                            ring->size);
1331         if (ring->virtual_start == NULL) {
1332                 DRM_ERROR("Failed to map ringbuffer.\n");
1333                 ret = -EINVAL;
1334                 goto err_unpin;
1335         }
1336
1337         ret = ring->init(ring);
1338         if (ret)
1339                 goto err_unmap;
1340
1341         /* Workaround an erratum on the i830 which causes a hang if
1342          * the TAIL pointer points to within the last 2 cachelines
1343          * of the buffer.
1344          */
1345         ring->effective_size = ring->size;
1346         if (IS_I830(ring->dev) || IS_845G(ring->dev))
1347                 ring->effective_size -= 128;
1348
1349         return 0;
1350
1351 err_unmap:
1352         pmap_unmapdev((vm_offset_t)ring->virtual_start, ring->size);
1353 err_unpin:
1354         i915_gem_object_unpin(obj);
1355 err_unref:
1356         drm_gem_object_unreference(&obj->base);
1357         ring->obj = NULL;
1358 err_hws:
1359         cleanup_status_page(ring);
1360         return ret;
1361 }
1362
1363 void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring)
1364 {
1365         struct drm_i915_private *dev_priv;
1366         int ret;
1367
1368         if (ring->obj == NULL)
1369                 return;
1370
1371         /* Disable the ring buffer. The ring must be idle at this point */
1372         dev_priv = ring->dev->dev_private;
1373         ret = intel_ring_idle(ring);
1374         if (ret)
1375                 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
1376                           ring->name, ret);
1377
1378         I915_WRITE_CTL(ring, 0);
1379
1380         pmap_unmapdev((vm_offset_t)ring->virtual_start, ring->size);
1381
1382         i915_gem_object_unpin(ring->obj);
1383         drm_gem_object_unreference(&ring->obj->base);
1384         ring->obj = NULL;
1385
1386         if (ring->cleanup)
1387                 ring->cleanup(ring);
1388
1389         cleanup_status_page(ring);
1390 }
1391
1392 static int intel_ring_wait_seqno(struct intel_ring_buffer *ring, u32 seqno)
1393 {
1394         int ret;
1395
1396         ret = i915_wait_seqno(ring, seqno);
1397         if (!ret)
1398                 i915_gem_retire_requests_ring(ring);
1399
1400         return ret;
1401 }
1402
1403 static int intel_ring_wait_request(struct intel_ring_buffer *ring, int n)
1404 {
1405         struct drm_i915_gem_request *request;
1406         u32 seqno = 0;
1407         int ret;
1408
1409         i915_gem_retire_requests_ring(ring);
1410
1411         if (ring->last_retired_head != -1) {
1412                 ring->head = ring->last_retired_head;
1413                 ring->last_retired_head = -1;
1414                 ring->space = ring_space(ring);
1415                 if (ring->space >= n)
1416                         return 0;
1417         }
1418
1419         list_for_each_entry(request, &ring->request_list, list) {
1420                 int space;
1421
1422                 if (request->tail == -1)
1423                         continue;
1424
1425                 space = request->tail - (ring->tail + I915_RING_FREE_SPACE);
1426                 if (space < 0)
1427                         space += ring->size;
1428                 if (space >= n) {
1429                         seqno = request->seqno;
1430                         break;
1431                 }
1432
1433                 /* Consume this request in case we need more space than
1434                  * is available and so need to prevent a race between
1435                  * updating last_retired_head and direct reads of
1436                  * I915_RING_HEAD. It also provides a nice sanity check.
1437                  */
1438                 request->tail = -1;
1439         }
1440
1441         if (seqno == 0)
1442                 return -ENOSPC;
1443
1444         ret = intel_ring_wait_seqno(ring, seqno);
1445         if (ret)
1446                 return ret;
1447
1448         if (WARN_ON(ring->last_retired_head == -1))
1449                 return -ENOSPC;
1450
1451         ring->head = ring->last_retired_head;
1452         ring->last_retired_head = -1;
1453         ring->space = ring_space(ring);
1454         if (WARN_ON(ring->space < n))
1455                 return -ENOSPC;
1456
1457         return 0;
1458 }
1459
1460 static int ring_wait_for_space(struct intel_ring_buffer *ring, int n)
1461 {
1462         struct drm_device *dev = ring->dev;
1463         struct drm_i915_private *dev_priv = dev->dev_private;
1464         unsigned long end;
1465         int ret;
1466
1467         ret = intel_ring_wait_request(ring, n);
1468         if (ret != -ENOSPC)
1469                 return ret;
1470
1471         trace_i915_ring_wait_begin(ring);
1472         /* With GEM the hangcheck timer should kick us out of the loop,
1473          * leaving it early runs the risk of corrupting GEM state (due
1474          * to running on almost untested codepaths). But on resume
1475          * timers don't work yet, so prevent a complete hang in that
1476          * case by choosing an insanely large timeout. */
1477         end = jiffies + 60 * HZ;
1478
1479         do {
1480                 ring->head = I915_READ_HEAD(ring);
1481                 ring->space = ring_space(ring);
1482                 if (ring->space >= n) {
1483                         trace_i915_ring_wait_end(ring);
1484                         return 0;
1485                 }
1486
1487 #if 0
1488                 if (dev->primary->master) {
1489                         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1490                         if (master_priv->sarea_priv)
1491                                 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1492                 }
1493 #else
1494                 if (dev_priv->sarea_priv)
1495                         dev_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1496 #endif
1497
1498                 msleep(1);
1499
1500                 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
1501                                            dev_priv->mm.interruptible);
1502                 if (ret)
1503                         return ret;
1504         } while (!time_after(jiffies, end));
1505         trace_i915_ring_wait_end(ring);
1506         return -EBUSY;
1507 }
1508
1509 static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring)
1510 {
1511         uint32_t __iomem *virt;
1512         int rem = ring->size - ring->tail;
1513
1514         if (ring->space < rem) {
1515                 int ret = ring_wait_for_space(ring, rem);
1516                 if (ret)
1517                         return ret;
1518         }
1519
1520         virt = (unsigned int *)((char *)ring->virtual_start + ring->tail);
1521         rem /= 4;
1522         while (rem--)
1523                 iowrite32(MI_NOOP, virt++);
1524
1525         ring->tail = 0;
1526         ring->space = ring_space(ring);
1527
1528         return 0;
1529 }
1530
1531 int intel_ring_idle(struct intel_ring_buffer *ring)
1532 {
1533         u32 seqno;
1534         int ret;
1535
1536         /* We need to add any requests required to flush the objects and ring */
1537         if (ring->outstanding_lazy_request) {
1538                 ret = i915_add_request(ring, NULL);
1539                 if (ret)
1540                         return ret;
1541         }
1542
1543         /* Wait upon the last request to be completed */
1544         if (list_empty(&ring->request_list))
1545                 return 0;
1546
1547         seqno = list_entry(ring->request_list.prev,
1548                            struct drm_i915_gem_request,
1549                            list)->seqno;
1550
1551         return i915_wait_seqno(ring, seqno);
1552 }
1553
1554 static int
1555 intel_ring_alloc_seqno(struct intel_ring_buffer *ring)
1556 {
1557         if (ring->outstanding_lazy_request)
1558                 return 0;
1559
1560         return i915_gem_get_seqno(ring->dev, &ring->outstanding_lazy_request);
1561 }
1562
1563 static int __intel_ring_begin(struct intel_ring_buffer *ring,
1564                               int bytes)
1565 {
1566         int ret;
1567
1568         if (unlikely(ring->tail + bytes > ring->effective_size)) {
1569                 ret = intel_wrap_ring_buffer(ring);
1570                 if (unlikely(ret))
1571                         return ret;
1572         }
1573
1574         if (unlikely(ring->space < bytes)) {
1575                 ret = ring_wait_for_space(ring, bytes);
1576                 if (unlikely(ret))
1577                         return ret;
1578         }
1579
1580         ring->space -= bytes;
1581         return 0;
1582 }
1583
1584 int intel_ring_begin(struct intel_ring_buffer *ring,
1585                      int num_dwords)
1586 {
1587         drm_i915_private_t *dev_priv = ring->dev->dev_private;
1588         int ret;
1589
1590         ret = i915_gem_check_wedge(&dev_priv->gpu_error,
1591                                    dev_priv->mm.interruptible);
1592         if (ret)
1593                 return ret;
1594
1595         /* Preallocate the olr before touching the ring */
1596         ret = intel_ring_alloc_seqno(ring);
1597         if (ret)
1598                 return ret;
1599
1600         return __intel_ring_begin(ring, num_dwords * sizeof(uint32_t));
1601 }
1602
1603 void intel_ring_init_seqno(struct intel_ring_buffer *ring, u32 seqno)
1604 {
1605         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1606
1607         BUG_ON(ring->outstanding_lazy_request);
1608
1609         if (INTEL_INFO(ring->dev)->gen >= 6) {
1610                 I915_WRITE(RING_SYNC_0(ring->mmio_base), 0);
1611                 I915_WRITE(RING_SYNC_1(ring->mmio_base), 0);
1612         }
1613
1614         ring->set_seqno(ring, seqno);
1615         ring->hangcheck.seqno = seqno;
1616 }
1617
1618 void intel_ring_advance(struct intel_ring_buffer *ring)
1619 {
1620         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1621
1622         ring->tail &= ring->size - 1;
1623         if (dev_priv->gpu_error.stop_rings & intel_ring_flag(ring))
1624                 return;
1625         ring->write_tail(ring, ring->tail);
1626 }
1627
1628
1629 static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring,
1630                                      u32 value)
1631 {
1632         drm_i915_private_t *dev_priv = ring->dev->dev_private;
1633
1634        /* Every tail move must follow the sequence below */
1635
1636         /* Disable notification that the ring is IDLE. The GT
1637          * will then assume that it is busy and bring it out of rc6.
1638          */
1639         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1640                    _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
1641
1642         /* Clear the context id. Here be magic! */
1643         I915_WRITE64(GEN6_BSD_RNCID, 0x0);
1644
1645         /* Wait for the ring not to be idle, i.e. for it to wake up. */
1646         if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
1647                       GEN6_BSD_SLEEP_INDICATOR) == 0,
1648                      50))
1649                 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
1650
1651         /* Now that the ring is fully powered up, update the tail */
1652         I915_WRITE_TAIL(ring, value);
1653         POSTING_READ(RING_TAIL(ring->mmio_base));
1654
1655         /* Let the ring send IDLE messages to the GT again,
1656          * and so let it sleep to conserve power when idle.
1657          */
1658         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1659                    _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
1660 }
1661
1662 static int gen6_bsd_ring_flush(struct intel_ring_buffer *ring,
1663                                u32 invalidate, u32 flush)
1664 {
1665         uint32_t cmd;
1666         int ret;
1667
1668         ret = intel_ring_begin(ring, 4);
1669         if (ret)
1670                 return ret;
1671
1672         cmd = MI_FLUSH_DW;
1673         /*
1674          * Bspec vol 1c.5 - video engine command streamer:
1675          * "If ENABLED, all TLBs will be invalidated once the flush
1676          * operation is complete. This bit is only valid when the
1677          * Post-Sync Operation field is a value of 1h or 3h."
1678          */
1679         if (invalidate & I915_GEM_GPU_DOMAINS)
1680                 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD |
1681                         MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
1682         intel_ring_emit(ring, cmd);
1683         intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
1684         intel_ring_emit(ring, 0);
1685         intel_ring_emit(ring, MI_NOOP);
1686         intel_ring_advance(ring);
1687         return 0;
1688 }
1689
1690 static int
1691 hsw_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1692                               u32 offset, u32 len,
1693                               unsigned flags)
1694 {
1695         int ret;
1696
1697         ret = intel_ring_begin(ring, 2);
1698         if (ret)
1699                 return ret;
1700
1701         intel_ring_emit(ring,
1702                         MI_BATCH_BUFFER_START | MI_BATCH_PPGTT_HSW |
1703                         (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_HSW));
1704         /* bit0-7 is the length on GEN6+ */
1705         intel_ring_emit(ring, offset);
1706         intel_ring_advance(ring);
1707
1708         return 0;
1709 }
1710
1711 static int
1712 gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1713                               u32 offset, u32 len,
1714                               unsigned flags)
1715 {
1716         int ret;
1717
1718         ret = intel_ring_begin(ring, 2);
1719         if (ret)
1720                 return ret;
1721
1722         intel_ring_emit(ring,
1723                         MI_BATCH_BUFFER_START |
1724                         (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
1725         /* bit0-7 is the length on GEN6+ */
1726         intel_ring_emit(ring, offset);
1727         intel_ring_advance(ring);
1728
1729         return 0;
1730 }
1731
1732 /* Blitter support (SandyBridge+) */
1733
1734 static int gen6_ring_flush(struct intel_ring_buffer *ring,
1735                            u32 invalidate, u32 flush)
1736 {
1737         struct drm_device *dev = ring->dev;
1738         uint32_t cmd;
1739         int ret;
1740
1741         ret = intel_ring_begin(ring, 4);
1742         if (ret)
1743                 return ret;
1744
1745         cmd = MI_FLUSH_DW;
1746         /*
1747          * Bspec vol 1c.3 - blitter engine command streamer:
1748          * "If ENABLED, all TLBs will be invalidated once the flush
1749          * operation is complete. This bit is only valid when the
1750          * Post-Sync Operation field is a value of 1h or 3h."
1751          */
1752         if (invalidate & I915_GEM_DOMAIN_RENDER)
1753                 cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX |
1754                         MI_FLUSH_DW_OP_STOREDW;
1755         intel_ring_emit(ring, cmd);
1756         intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
1757         intel_ring_emit(ring, 0);
1758         intel_ring_emit(ring, MI_NOOP);
1759         intel_ring_advance(ring);
1760
1761         if (IS_GEN7(dev) && flush)
1762                 return gen7_ring_fbc_flush(ring, FBC_REND_CACHE_CLEAN);
1763
1764         return 0;
1765 }
1766
1767 int intel_init_render_ring_buffer(struct drm_device *dev)
1768 {
1769         drm_i915_private_t *dev_priv = dev->dev_private;
1770         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1771
1772         ring->name = "render ring";
1773         ring->id = RCS;
1774         ring->mmio_base = RENDER_RING_BASE;
1775
1776         if (INTEL_INFO(dev)->gen >= 6) {
1777                 ring->add_request = gen6_add_request;
1778                 ring->flush = gen7_render_ring_flush;
1779                 if (INTEL_INFO(dev)->gen == 6)
1780                         ring->flush = gen6_render_ring_flush;
1781                 ring->irq_get = gen6_ring_get_irq;
1782                 ring->irq_put = gen6_ring_put_irq;
1783                 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
1784                 ring->get_seqno = gen6_ring_get_seqno;
1785                 ring->set_seqno = ring_set_seqno;
1786                 ring->sync_to = gen6_ring_sync;
1787                 ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_INVALID;
1788                 ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_RV;
1789                 ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_RB;
1790                 ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_RVE;
1791                 ring->signal_mbox[RCS] = GEN6_NOSYNC;
1792                 ring->signal_mbox[VCS] = GEN6_VRSYNC;
1793                 ring->signal_mbox[BCS] = GEN6_BRSYNC;
1794                 ring->signal_mbox[VECS] = GEN6_VERSYNC;
1795         } else if (IS_GEN5(dev)) {
1796                 ring->add_request = pc_render_add_request;
1797                 ring->flush = gen4_render_ring_flush;
1798                 ring->get_seqno = pc_render_get_seqno;
1799                 ring->set_seqno = pc_render_set_seqno;
1800                 ring->irq_get = gen5_ring_get_irq;
1801                 ring->irq_put = gen5_ring_put_irq;
1802                 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
1803                                         GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
1804         } else {
1805                 ring->add_request = i9xx_add_request;
1806                 if (INTEL_INFO(dev)->gen < 4)
1807                         ring->flush = gen2_render_ring_flush;
1808                 else
1809                         ring->flush = gen4_render_ring_flush;
1810                 ring->get_seqno = ring_get_seqno;
1811                 ring->set_seqno = ring_set_seqno;
1812                 if (IS_GEN2(dev)) {
1813                         ring->irq_get = i8xx_ring_get_irq;
1814                         ring->irq_put = i8xx_ring_put_irq;
1815                 } else {
1816                         ring->irq_get = i9xx_ring_get_irq;
1817                         ring->irq_put = i9xx_ring_put_irq;
1818                 }
1819                 ring->irq_enable_mask = I915_USER_INTERRUPT;
1820         }
1821         ring->write_tail = ring_write_tail;
1822         if (IS_HASWELL(dev))
1823                 ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
1824         else if (INTEL_INFO(dev)->gen >= 6)
1825                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1826         else if (INTEL_INFO(dev)->gen >= 4)
1827                 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1828         else if (IS_I830(dev) || IS_845G(dev))
1829                 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
1830         else
1831                 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
1832         ring->init = init_render_ring;
1833         ring->cleanup = render_ring_cleanup;
1834
1835         /* Workaround batchbuffer to combat CS tlb bug. */
1836         if (HAS_BROKEN_CS_TLB(dev)) {
1837                 struct drm_i915_gem_object *obj;
1838                 int ret;
1839
1840                 obj = i915_gem_alloc_object(dev, I830_BATCH_LIMIT);
1841                 if (obj == NULL) {
1842                         DRM_ERROR("Failed to allocate batch bo\n");
1843                         return -ENOMEM;
1844                 }
1845
1846                 ret = i915_gem_object_pin(obj, 0, true, false);
1847                 if (ret != 0) {
1848                         drm_gem_object_unreference(&obj->base);
1849                         DRM_ERROR("Failed to ping batch bo\n");
1850                         return ret;
1851                 }
1852
1853                 ring->private = obj;
1854         }
1855
1856         return intel_init_ring_buffer(dev, ring);
1857 }
1858
1859 int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)
1860 {
1861         drm_i915_private_t *dev_priv = dev->dev_private;
1862         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1863         int ret;
1864
1865         ring->name = "render ring";
1866         ring->id = RCS;
1867         ring->mmio_base = RENDER_RING_BASE;
1868
1869         if (INTEL_INFO(dev)->gen >= 6) {
1870                 /* non-kms not supported on gen6+ */
1871                 return -ENODEV;
1872         }
1873
1874         /* Note: gem is not supported on gen5/ilk without kms (the corresponding
1875          * gem_init ioctl returns with -ENODEV). Hence we do not need to set up
1876          * the special gen5 functions. */
1877         ring->add_request = i9xx_add_request;
1878         if (INTEL_INFO(dev)->gen < 4)
1879                 ring->flush = gen2_render_ring_flush;
1880         else
1881                 ring->flush = gen4_render_ring_flush;
1882         ring->get_seqno = ring_get_seqno;
1883         ring->set_seqno = ring_set_seqno;
1884         if (IS_GEN2(dev)) {
1885                 ring->irq_get = i8xx_ring_get_irq;
1886                 ring->irq_put = i8xx_ring_put_irq;
1887         } else {
1888                 ring->irq_get = i9xx_ring_get_irq;
1889                 ring->irq_put = i9xx_ring_put_irq;
1890         }
1891         ring->irq_enable_mask = I915_USER_INTERRUPT;
1892         ring->write_tail = ring_write_tail;
1893         if (INTEL_INFO(dev)->gen >= 4)
1894                 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1895         else if (IS_I830(dev) || IS_845G(dev))
1896                 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
1897         else
1898                 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
1899         ring->init = init_render_ring;
1900         ring->cleanup = render_ring_cleanup;
1901
1902         ring->dev = dev;
1903         INIT_LIST_HEAD(&ring->active_list);
1904         INIT_LIST_HEAD(&ring->request_list);
1905
1906         ring->size = size;
1907         ring->effective_size = ring->size;
1908         if (IS_I830(ring->dev) || IS_845G(ring->dev))
1909                 ring->effective_size -= 128;
1910
1911         ring->virtual_start = ioremap_wc(start, size);
1912         if (ring->virtual_start == NULL) {
1913                 DRM_ERROR("can not ioremap virtual address for"
1914                           " ring buffer\n");
1915                 return -ENOMEM;
1916         }
1917
1918         if (!I915_NEED_GFX_HWS(dev)) {
1919                 ret = init_phys_status_page(ring);
1920                 if (ret)
1921                         return ret;
1922         }
1923
1924         return 0;
1925 }
1926
1927 int intel_init_bsd_ring_buffer(struct drm_device *dev)
1928 {
1929         drm_i915_private_t *dev_priv = dev->dev_private;
1930         struct intel_ring_buffer *ring = &dev_priv->ring[VCS];
1931
1932         ring->name = "bsd ring";
1933         ring->id = VCS;
1934
1935         ring->write_tail = ring_write_tail;
1936         if (IS_GEN6(dev) || IS_GEN7(dev)) {
1937                 ring->mmio_base = GEN6_BSD_RING_BASE;
1938                 /* gen6 bsd needs a special wa for tail updates */
1939                 if (IS_GEN6(dev))
1940                         ring->write_tail = gen6_bsd_ring_write_tail;
1941                 ring->flush = gen6_bsd_ring_flush;
1942                 ring->add_request = gen6_add_request;
1943                 ring->get_seqno = gen6_ring_get_seqno;
1944                 ring->set_seqno = ring_set_seqno;
1945                 ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
1946                 ring->irq_get = gen6_ring_get_irq;
1947                 ring->irq_put = gen6_ring_put_irq;
1948                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1949                 ring->sync_to = gen6_ring_sync;
1950                 ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_VR;
1951                 ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_INVALID;
1952                 ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_VB;
1953                 ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_VVE;
1954                 ring->signal_mbox[RCS] = GEN6_RVSYNC;
1955                 ring->signal_mbox[VCS] = GEN6_NOSYNC;
1956                 ring->signal_mbox[BCS] = GEN6_BVSYNC;
1957                 ring->signal_mbox[VECS] = GEN6_VEVSYNC;
1958         } else {
1959                 ring->mmio_base = BSD_RING_BASE;
1960                 ring->flush = bsd_ring_flush;
1961                 ring->add_request = i9xx_add_request;
1962                 ring->get_seqno = ring_get_seqno;
1963                 ring->set_seqno = ring_set_seqno;
1964                 if (IS_GEN5(dev)) {
1965                         ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
1966                         ring->irq_get = gen5_ring_get_irq;
1967                         ring->irq_put = gen5_ring_put_irq;
1968                 } else {
1969                         ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
1970                         ring->irq_get = i9xx_ring_get_irq;
1971                         ring->irq_put = i9xx_ring_put_irq;
1972                 }
1973                 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1974         }
1975         ring->init = init_ring_common;
1976
1977         return intel_init_ring_buffer(dev, ring);
1978 }
1979
1980 int intel_init_blt_ring_buffer(struct drm_device *dev)
1981 {
1982         drm_i915_private_t *dev_priv = dev->dev_private;
1983         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
1984
1985         ring->name = "blitter ring";
1986         ring->id = BCS;
1987
1988         ring->mmio_base = BLT_RING_BASE;
1989         ring->write_tail = ring_write_tail;
1990         ring->flush = gen6_ring_flush;
1991         ring->add_request = gen6_add_request;
1992         ring->get_seqno = gen6_ring_get_seqno;
1993         ring->set_seqno = ring_set_seqno;
1994         ring->irq_enable_mask = GT_BLT_USER_INTERRUPT;
1995         ring->irq_get = gen6_ring_get_irq;
1996         ring->irq_put = gen6_ring_put_irq;
1997         ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1998         ring->sync_to = gen6_ring_sync;
1999         ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_BR;
2000         ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_BV;
2001         ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_INVALID;
2002         ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_BVE;
2003         ring->signal_mbox[RCS] = GEN6_RBSYNC;
2004         ring->signal_mbox[VCS] = GEN6_VBSYNC;
2005         ring->signal_mbox[BCS] = GEN6_NOSYNC;
2006         ring->signal_mbox[VECS] = GEN6_VEBSYNC;
2007         ring->init = init_ring_common;
2008
2009         return intel_init_ring_buffer(dev, ring);
2010 }
2011
2012 int intel_init_vebox_ring_buffer(struct drm_device *dev)
2013 {
2014         drm_i915_private_t *dev_priv = dev->dev_private;
2015         struct intel_ring_buffer *ring = &dev_priv->ring[VECS];
2016
2017         ring->name = "video enhancement ring";
2018         ring->id = VECS;
2019
2020         ring->mmio_base = VEBOX_RING_BASE;
2021         ring->write_tail = ring_write_tail;
2022         ring->flush = gen6_ring_flush;
2023         ring->add_request = gen6_add_request;
2024         ring->get_seqno = gen6_ring_get_seqno;
2025         ring->set_seqno = ring_set_seqno;
2026         ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT |
2027                 PM_VEBOX_CS_ERROR_INTERRUPT;
2028         ring->irq_get = hsw_vebox_get_irq;
2029         ring->irq_put = hsw_vebox_put_irq;
2030         ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2031         ring->sync_to = gen6_ring_sync;
2032         ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_VER;
2033         ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_VEV;
2034         ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_VEB;
2035         ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_INVALID;
2036         ring->signal_mbox[RCS] = GEN6_RVESYNC;
2037         ring->signal_mbox[VCS] = GEN6_VVESYNC;
2038         ring->signal_mbox[BCS] = GEN6_BVESYNC;
2039         ring->signal_mbox[VECS] = GEN6_NOSYNC;
2040         ring->init = init_ring_common;
2041
2042         return intel_init_ring_buffer(dev, ring);
2043 }
2044
2045 int
2046 intel_ring_flush_all_caches(struct intel_ring_buffer *ring)
2047 {
2048         int ret;
2049
2050         if (!ring->gpu_caches_dirty)
2051                 return 0;
2052
2053         ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS);
2054         if (ret)
2055                 return ret;
2056
2057         trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS);
2058
2059         ring->gpu_caches_dirty = false;
2060         return 0;
2061 }
2062
2063 int
2064 intel_ring_invalidate_all_caches(struct intel_ring_buffer *ring)
2065 {
2066         uint32_t flush_domains;
2067         int ret;
2068
2069         flush_domains = 0;
2070         if (ring->gpu_caches_dirty)
2071                 flush_domains = I915_GEM_GPU_DOMAINS;
2072
2073         ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2074         if (ret)
2075                 return ret;
2076
2077         trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2078
2079         ring->gpu_caches_dirty = false;
2080         return 0;
2081 }