2 * Copyright (c) 2006-2007 Broadcom Corporation
3 * David Christensen <davidch@broadcom.com>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. Neither the name of Broadcom Corporation nor the name of its contributors
14 * may be used to endorse or promote products derived from this software
15 * without specific prior written consent.
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
18 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
27 * THE POSSIBILITY OF SUCH DAMAGE.
29 * $FreeBSD: src/sys/dev/bce/if_bcereg.h,v 1.13 2007/05/16 23:34:11 davidch Exp $
30 * $DragonFly: src/sys/dev/netif/bce/if_bcereg.h,v 1.3 2008/06/15 05:14:41 sephe Exp $
33 #ifndef _BCE_H_DEFINED
34 #define _BCE_H_DEFINED
36 /****************************************************************************/
37 /* Debugging macros and definitions. */
38 /****************************************************************************/
41 #define BCE_CP_LOAD 0x00000001
42 #define BCE_CP_SEND 0x00000002
43 #define BCE_CP_RECV 0x00000004
44 #define BCE_CP_INTR 0x00000008
45 #define BCE_CP_UNLOAD 0x00000010
46 #define BCE_CP_RESET 0x00000020
47 #define BCE_CP_ALL 0x00FFFFFF
49 #define BCE_CP_MASK 0x00FFFFFF
51 #define BCE_LEVEL_FATAL 0x00000000
52 #define BCE_LEVEL_WARN 0x01000000
53 #define BCE_LEVEL_INFO 0x02000000
54 #define BCE_LEVEL_VERBOSE 0x03000000
55 #define BCE_LEVEL_EXCESSIVE 0x04000000
57 #define BCE_LEVEL_MASK 0xFF000000
59 #define BCE_WARN_LOAD (BCE_CP_LOAD | BCE_LEVEL_WARN)
60 #define BCE_INFO_LOAD (BCE_CP_LOAD | BCE_LEVEL_INFO)
61 #define BCE_VERBOSE_LOAD (BCE_CP_LOAD | BCE_LEVEL_VERBOSE)
62 #define BCE_EXCESSIVE_LOAD (BCE_CP_LOAD | BCE_LEVEL_EXCESSIVE)
64 #define BCE_WARN_SEND (BCE_CP_SEND | BCE_LEVEL_WARN)
65 #define BCE_INFO_SEND (BCE_CP_SEND | BCE_LEVEL_INFO)
66 #define BCE_VERBOSE_SEND (BCE_CP_SEND | BCE_LEVEL_VERBOSE)
67 #define BCE_EXCESSIVE_SEND (BCE_CP_SEND | BCE_LEVEL_EXCESSIVE)
69 #define BCE_WARN_RECV (BCE_CP_RECV | BCE_LEVEL_WARN)
70 #define BCE_INFO_RECV (BCE_CP_RECV | BCE_LEVEL_INFO)
71 #define BCE_VERBOSE_RECV (BCE_CP_RECV | BCE_LEVEL_VERBOSE)
72 #define BCE_EXCESSIVE_RECV (BCE_CP_RECV | BCE_LEVEL_EXCESSIVE)
74 #define BCE_WARN_INTR (BCE_CP_INTR | BCE_LEVEL_WARN)
75 #define BCE_INFO_INTR (BCE_CP_INTR | BCE_LEVEL_INFO)
76 #define BCE_VERBOSE_INTR (BCE_CP_INTR | BCE_LEVEL_VERBOSE)
77 #define BCE_EXCESSIVE_INTR (BCE_CP_INTR | BCE_LEVEL_EXCESSIVE)
79 #define BCE_WARN_UNLOAD (BCE_CP_UNLOAD | BCE_LEVEL_WARN)
80 #define BCE_INFO_UNLOAD (BCE_CP_UNLOAD | BCE_LEVEL_INFO)
81 #define BCE_VERBOSE_UNLOAD (BCE_CP_UNLOAD | BCE_LEVEL_VERBOSE)
82 #define BCE_EXCESSIVE_UNLOAD (BCE_CP_UNLOAD | BCE_LEVEL_EXCESSIVE)
84 #define BCE_WARN_RESET (BCE_CP_RESET | BCE_LEVEL_WARN)
85 #define BCE_INFO_RESET (BCE_CP_RESET | BCE_LEVEL_INFO)
86 #define BCE_VERBOSE_RESET (BCE_CP_RESET | BCE_LEVEL_VERBOSE)
87 #define BCE_EXCESSIVE_RESET (BCE_CP_RESET | BCE_LEVEL_EXCESSIVE)
89 #define BCE_FATAL (BCE_CP_ALL | BCE_LEVEL_FATAL)
90 #define BCE_WARN (BCE_CP_ALL | BCE_LEVEL_WARN)
91 #define BCE_INFO (BCE_CP_ALL | BCE_LEVEL_INFO)
92 #define BCE_VERBOSE (BCE_CP_ALL | BCE_LEVEL_VERBOSE)
93 #define BCE_EXCESSIVE (BCE_CP_ALL | BCE_LEVEL_EXCESSIVE)
95 #define BCE_CODE_PATH(cp) ((cp & BCE_CP_MASK) & bce_debug)
96 #define BCE_MSG_LEVEL(lv) \
97 ((lv & BCE_LEVEL_MASK) <= (bce_debug & BCE_LEVEL_MASK))
98 #define BCE_LOG_MSG(m) (BCE_CODE_PATH(m) && BCE_MSG_LEVEL(m))
100 /* Print a message based on the logging level and code path. */
101 #define DBPRINT(sc, level, format, args...) \
103 if (BCE_LOG_MSG(level)) \
104 if_printf(&sc->arpcom.ac_if, format, ## args); \
107 /* Runs a particular command based on the logging level and code path. */
108 #define DBRUN(m, args...) \
110 if (BCE_LOG_MSG(m)) { \
115 /* Runs a particular command based on the logging level. */
116 #define DBRUNLV(level, args...) \
118 if (BCE_MSG_LEVEL(level)) { \
123 /* Runs a particular command based on the code path. */
124 #define DBRUNCP(cp, args...) \
126 if (BCE_CODE_PATH(cp)) { \
131 /* Runs a particular command based on a condition. */
132 #define DBRUNIF(cond, args...) \
139 /* Returns FALSE in "defects" per 2^31 - 1 calls, otherwise returns TRUE. */
140 #define DB_RANDOMFALSE(defects) (krandom() > defects)
141 #define DB_OR_RANDOMFALSE(defects) || (krandom() > defects)
142 #define DB_AND_RANDOMFALSE(defects) && (krandom() > ddfects)
144 /* Returns TRUE in "defects" per 2^31 - 1 calls, otherwise returns FALSE. */
145 #define DB_RANDOMTRUE(defects) (krandom() < defects)
146 #define DB_OR_RANDOMTRUE(defects) || (krandom() < defects)
147 #define DB_AND_RANDOMTRUE(defects) && (krandom() < defects)
149 #else /* !BCE_DEBUG */
151 #define DBPRINT(level, format, args...)
152 #define DBRUN(m, args...)
153 #define DBRUNLV(level, args...)
154 #define DBRUNCP(cp, args...)
155 #define DBRUNIF(cond, args...)
156 #define DB_RANDOMFALSE(defects)
157 #define DB_OR_RANDOMFALSE(percent)
158 #define DB_AND_RANDOMFALSE(percent)
159 #define DB_RANDOMTRUE(defects)
160 #define DB_OR_RANDOMTRUE(percent)
161 #define DB_AND_RANDOMTRUE(percent)
163 #endif /* BCE_DEBUG */
166 /****************************************************************************/
167 /* Device identification definitions. */
168 /****************************************************************************/
169 #define BRCM_VENDORID 0x14E4
170 #define BRCM_DEVICEID_BCM5706 0x164A
171 #define BRCM_DEVICEID_BCM5706S 0x16AA
172 #define BRCM_DEVICEID_BCM5708 0x164C
173 #define BRCM_DEVICEID_BCM5708S 0x16AC
175 #define HP_VENDORID 0x103C
177 #define PCI_ANY_ID (uint16_t) (~0U)
179 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
181 #define BCE_CHIP_NUM(sc) (((sc)->bce_chipid) & 0xffff0000)
182 #define BCE_CHIP_NUM_5706 0x57060000
183 #define BCE_CHIP_NUM_5708 0x57080000
185 #define BCE_CHIP_REV(sc) (((sc)->bce_chipid) & 0x0000f000)
186 #define BCE_CHIP_REV_Ax 0x00000000
187 #define BCE_CHIP_REV_Bx 0x00001000
188 #define BCE_CHIP_REV_Cx 0x00002000
190 #define BCE_CHIP_METAL(sc) (((sc)->bce_chipid) & 0x00000ff0)
191 #define BCE_CHIP_BOND(bp) (((sc)->bce_chipid) & 0x0000000f)
193 #define BCE_CHIP_ID(sc) (((sc)->bce_chipid) & 0xfffffff0)
194 #define BCE_CHIP_ID_5706_A0 0x57060000
195 #define BCE_CHIP_ID_5706_A1 0x57060010
196 #define BCE_CHIP_ID_5706_A2 0x57060020
197 #define BCE_CHIP_ID_5706_A3 0x57060030
198 #define BCE_CHIP_ID_5708_A0 0x57080000
199 #define BCE_CHIP_ID_5708_B0 0x57081000
200 #define BCE_CHIP_ID_5708_B1 0x57081010
201 #define BCE_CHIP_ID_5708_B2 0x57081020
203 #define BCE_CHIP_BOND_ID(sc) (((sc)->bce_chipid) & 0xf)
205 /* A serdes chip will have the first bit of the bond id set. */
206 #define BCE_CHIP_BOND_ID_SERDES_BIT 0x01
210 #define BCE_ASICREV(x) ((x) >> 28)
211 #define BCE_ASICREV_BCM5700 0x06
214 #define BCE_CHIPREV(x) ((x) >> 24)
215 #define BCE_CHIPREV_5700_AX 0x70
216 #define BCE_CHIPREV_5700_BX 0x71
217 #define BCE_CHIPREV_5700_CX 0x72
218 #define BCE_CHIPREV_5701_AX 0x00
225 const char *bce_name;
228 /****************************************************************************/
230 /****************************************************************************/
232 /* Buffered flash (Atmel: AT45DB011B) specific information */
233 #define SEEPROM_PAGE_BITS 2
234 #define SEEPROM_PHY_PAGE_SIZE (1 << SEEPROM_PAGE_BITS)
235 #define SEEPROM_BYTE_ADDR_MASK (SEEPROM_PHY_PAGE_SIZE-1)
236 #define SEEPROM_PAGE_SIZE 4
237 #define SEEPROM_TOTAL_SIZE 65536
239 #define BUFFERED_FLASH_PAGE_BITS 9
240 #define BUFFERED_FLASH_PHY_PAGE_SIZE (1 << BUFFERED_FLASH_PAGE_BITS)
241 #define BUFFERED_FLASH_BYTE_ADDR_MASK (BUFFERED_FLASH_PHY_PAGE_SIZE-1)
242 #define BUFFERED_FLASH_PAGE_SIZE 264
243 #define BUFFERED_FLASH_TOTAL_SIZE 0x21000
245 #define SAIFUN_FLASH_PAGE_BITS 8
246 #define SAIFUN_FLASH_PHY_PAGE_SIZE (1 << SAIFUN_FLASH_PAGE_BITS)
247 #define SAIFUN_FLASH_BYTE_ADDR_MASK (SAIFUN_FLASH_PHY_PAGE_SIZE-1)
248 #define SAIFUN_FLASH_PAGE_SIZE 256
249 #define SAIFUN_FLASH_BASE_TOTAL_SIZE 65536
251 #define ST_MICRO_FLASH_PAGE_BITS 8
252 #define ST_MICRO_FLASH_PHY_PAGE_SIZE (1 << ST_MICRO_FLASH_PAGE_BITS)
253 #define ST_MICRO_FLASH_BYTE_ADDR_MASK (ST_MICRO_FLASH_PHY_PAGE_SIZE-1)
254 #define ST_MICRO_FLASH_PAGE_SIZE 256
255 #define ST_MICRO_FLASH_BASE_TOTAL_SIZE 65536
257 #define NVRAM_TIMEOUT_COUNT 30000
258 #define BCE_FLASHDESC_MAX 64
260 #define FLASH_STRAP_MASK (BCE_NVM_CFG1_FLASH_MODE | \
261 BCE_NVM_CFG1_BUFFER_MODE | \
262 BCE_NVM_CFG1_PROTECT_MODE | \
263 BCE_NVM_CFG1_FLASH_SIZE)
265 #define FLASH_BACKUP_STRAP_MASK (0xf << 26)
282 /****************************************************************************/
283 /* Shared Memory layout */
284 /* The BCE bootcode will initialize this data area with port configurtion */
285 /* information which can be accessed by the driver. */
286 /****************************************************************************/
289 * This value (in milliseconds) determines the frequency of the driver
290 * issuing the PULSE message code. The firmware monitors this periodic
291 * pulse to determine when to switch to an OS-absent mode.
293 #define DRV_PULSE_PERIOD_MS 250
296 * This value (in milliseconds) determines how long the driver should
297 * wait for an acknowledgement from the firmware before timing out. Once
298 * the firmware has timed out, the driver will assume there is no firmware
299 * running and there won't be any firmware-driver synchronization during a
302 #define FW_ACK_TIME_OUT_MS 100
305 #define BCE_DRV_RESET_SIGNATURE 0x00000000
306 #define BCE_DRV_RESET_SIGNATURE_MAGIC 0x4841564b /* HAVK */
308 #define BCE_DRV_MB 0x00000004
309 #define BCE_DRV_MSG_CODE 0xff000000
310 #define BCE_DRV_MSG_CODE_RESET 0x01000000
311 #define BCE_DRV_MSG_CODE_UNLOAD 0x02000000
312 #define BCE_DRV_MSG_CODE_SHUTDOWN 0x03000000
313 #define BCE_DRV_MSG_CODE_SUSPEND_WOL 0x04000000
314 #define BCE_DRV_MSG_CODE_FW_TIMEOUT 0x05000000
315 #define BCE_DRV_MSG_CODE_PULSE 0x06000000
316 #define BCE_DRV_MSG_CODE_DIAG 0x07000000
317 #define BCE_DRV_MSG_CODE_SUSPEND_NO_WOL 0x09000000
319 #define BCE_DRV_MSG_DATA 0x00ff0000
320 #define BCE_DRV_MSG_DATA_WAIT0 0x00010000
321 #define BCE_DRV_MSG_DATA_WAIT1 0x00020000
322 #define BCE_DRV_MSG_DATA_WAIT2 0x00030000
323 #define BCE_DRV_MSG_DATA_WAIT3 0x00040000
325 #define BCE_DRV_MSG_SEQ 0x0000ffff
327 #define BCE_FW_MB 0x00000008
328 #define BCE_FW_MSG_ACK 0x0000ffff
329 #define BCE_FW_MSG_STATUS_MASK 0x00ff0000
330 #define BCE_FW_MSG_STATUS_OK 0x00000000
331 #define BCE_FW_MSG_STATUS_FAILURE 0x00ff0000
333 #define BCE_LINK_STATUS 0x0000000c
334 #define BCE_LINK_STATUS_INIT_VALUE 0xffffffff
335 #define BCE_LINK_STATUS_LINK_UP 0x1
336 #define BCE_LINK_STATUS_LINK_DOWN 0x0
337 #define BCE_LINK_STATUS_SPEED_MASK 0x1e
338 #define BCE_LINK_STATUS_AN_INCOMPLETE (0<<1)
339 #define BCE_LINK_STATUS_10HALF (1<<1)
340 #define BCE_LINK_STATUS_10FULL (2<<1)
341 #define BCE_LINK_STATUS_100HALF (3<<1)
342 #define BCE_LINK_STATUS_100BASE_T4 (4<<1)
343 #define BCE_LINK_STATUS_100FULL (5<<1)
344 #define BCE_LINK_STATUS_1000HALF (6<<1)
345 #define BCE_LINK_STATUS_1000FULL (7<<1)
346 #define BCE_LINK_STATUS_2500HALF (8<<1)
347 #define BCE_LINK_STATUS_2500FULL (9<<1)
348 #define BCE_LINK_STATUS_AN_ENABLED (1<<5)
349 #define BCE_LINK_STATUS_AN_COMPLETE (1<<6)
350 #define BCE_LINK_STATUS_PARALLEL_DET (1<<7)
351 #define BCE_LINK_STATUS_RESERVED (1<<8)
352 #define BCE_LINK_STATUS_PARTNER_AD_1000FULL (1<<9)
353 #define BCE_LINK_STATUS_PARTNER_AD_1000HALF (1<<10)
354 #define BCE_LINK_STATUS_PARTNER_AD_100BT4 (1<<11)
355 #define BCE_LINK_STATUS_PARTNER_AD_100FULL (1<<12)
356 #define BCE_LINK_STATUS_PARTNER_AD_100HALF (1<<13)
357 #define BCE_LINK_STATUS_PARTNER_AD_10FULL (1<<14)
358 #define BCE_LINK_STATUS_PARTNER_AD_10HALF (1<<15)
359 #define BCE_LINK_STATUS_TX_FC_ENABLED (1<<16)
360 #define BCE_LINK_STATUS_RX_FC_ENABLED (1<<17)
361 #define BCE_LINK_STATUS_PARTNER_SYM_PAUSE_CAP (1<<18)
362 #define BCE_LINK_STATUS_PARTNER_ASYM_PAUSE_CAP (1<<19)
363 #define BCE_LINK_STATUS_SERDES_LINK (1<<20)
364 #define BCE_LINK_STATUS_PARTNER_AD_2500FULL (1<<21)
365 #define BCE_LINK_STATUS_PARTNER_AD_2500HALF (1<<22)
367 #define BCE_DRV_PULSE_MB 0x00000010
368 #define BCE_DRV_PULSE_SEQ_MASK 0x00007fff
370 /* Indicate to the firmware not to go into the
371 * OS absent when it is not getting driver pulse.
372 * This is used for debugging. */
373 #define BCE_DRV_MSG_DATA_PULSE_CODE_ALWAYS_ALIVE 0x00080000
375 #define BCE_DEV_INFO_SIGNATURE 0x00000020
376 #define BCE_DEV_INFO_SIGNATURE_MAGIC 0x44564900
377 #define BCE_DEV_INFO_SIGNATURE_MAGIC_MASK 0xffffff00
378 #define BCE_DEV_INFO_FEATURE_CFG_VALID 0x01
379 #define BCE_DEV_INFO_SECONDARY_PORT 0x80
380 #define BCE_DEV_INFO_DRV_ALWAYS_ALIVE 0x40
382 #define BCE_SHARED_HW_CFG_PART_NUM 0x00000024
384 #define BCE_SHARED_HW_CFG_POWER_DISSIPATED 0x00000034
385 #define BCE_SHARED_HW_CFG_POWER_STATE_D3_MASK 0xff000000
386 #define BCE_SHARED_HW_CFG_POWER_STATE_D2_MASK 0xff0000
387 #define BCE_SHARED_HW_CFG_POWER_STATE_D1_MASK 0xff00
388 #define BCE_SHARED_HW_CFG_POWER_STATE_D0_MASK 0xff
390 #define BCE_SHARED_HW_CFG_POWER_CONSUMED 0x00000038
391 #define BCE_SHARED_HW_CFG_CONFIG 0x0000003c
392 #define BCE_SHARED_HW_CFG_DESIGN_NIC 0
393 #define BCE_SHARED_HW_CFG_DESIGN_LOM 0x1
394 #define BCE_SHARED_HW_CFG_PHY_COPPER 0
395 #define BCE_SHARED_HW_CFG_PHY_FIBER 0x2
396 #define BCE_SHARED_HW_CFG_PHY_2_5G 0x20
397 #define BCE_SHARED_HW_CFG_PHY_BACKPLANE 0x40
398 #define BCE_SHARED_HW_CFG_LED_MODE_SHIFT_BITS 8
399 #define BCE_SHARED_HW_CFG_LED_MODE_MASK 0x300
400 #define BCE_SHARED_HW_CFG_LED_MODE_MAC 0
401 #define BCE_SHARED_HW_CFG_LED_MODE_GPHY1 0x100
402 #define BCE_SHARED_HW_CFG_LED_MODE_GPHY2 0x200
404 #define BCE_SHARED_HW_CFG_CONFIG2 0x00000040
405 #define BCE_SHARED_HW_CFG2_NVM_SIZE_MASK 0x00fff000
407 #define BCE_DEV_INFO_BC_REV 0x0000004c
409 #define BCE_PORT_HW_CFG_MAC_UPPER 0x00000050
410 #define BCE_PORT_HW_CFG_UPPERMAC_MASK 0xffff
412 #define BCE_PORT_HW_CFG_MAC_LOWER 0x00000054
413 #define BCE_PORT_HW_CFG_CONFIG 0x00000058
414 #define BCE_PORT_HW_CFG_CFG_TXCTL3_MASK 0x0000ffff
415 #define BCE_PORT_HW_CFG_CFG_DFLT_LINK_MASK 0x001f0000
416 #define BCE_PORT_HW_CFG_CFG_DFLT_LINK_AN 0x00000000
417 #define BCE_PORT_HW_CFG_CFG_DFLT_LINK_1G 0x00030000
418 #define BCE_PORT_HW_CFG_CFG_DFLT_LINK_2_5G 0x00040000
420 #define BCE_PORT_HW_CFG_IMD_MAC_A_UPPER 0x00000068
421 #define BCE_PORT_HW_CFG_IMD_MAC_A_LOWER 0x0000006c
422 #define BCE_PORT_HW_CFG_IMD_MAC_B_UPPER 0x00000070
423 #define BCE_PORT_HW_CFG_IMD_MAC_B_LOWER 0x00000074
424 #define BCE_PORT_HW_CFG_ISCSI_MAC_UPPER 0x00000078
425 #define BCE_PORT_HW_CFG_ISCSI_MAC_LOWER 0x0000007c
427 #define BCE_DEV_INFO_PER_PORT_HW_CONFIG2 0x000000b4
429 #define BCE_DEV_INFO_FORMAT_REV 0x000000c4
430 #define BCE_DEV_INFO_FORMAT_REV_MASK 0xff000000
431 #define BCE_DEV_INFO_FORMAT_REV_ID ('A' << 24)
433 #define BCE_SHARED_FEATURE 0x000000c8
434 #define BCE_SHARED_FEATURE_MASK 0xffffffff
436 #define BCE_PORT_FEATURE 0x000000d8
437 #define BCE_PORT2_FEATURE 0x00000014c
438 #define BCE_PORT_FEATURE_WOL_ENABLED 0x01000000
439 #define BCE_PORT_FEATURE_MBA_ENABLED 0x02000000
440 #define BCE_PORT_FEATURE_ASF_ENABLED 0x04000000
441 #define BCE_PORT_FEATURE_IMD_ENABLED 0x08000000
442 #define BCE_PORT_FEATURE_BAR1_SIZE_MASK 0xf
443 #define BCE_PORT_FEATURE_BAR1_SIZE_DISABLED 0x0
444 #define BCE_PORT_FEATURE_BAR1_SIZE_64K 0x1
445 #define BCE_PORT_FEATURE_BAR1_SIZE_128K 0x2
446 #define BCE_PORT_FEATURE_BAR1_SIZE_256K 0x3
447 #define BCE_PORT_FEATURE_BAR1_SIZE_512K 0x4
448 #define BCE_PORT_FEATURE_BAR1_SIZE_1M 0x5
449 #define BCE_PORT_FEATURE_BAR1_SIZE_2M 0x6
450 #define BCE_PORT_FEATURE_BAR1_SIZE_4M 0x7
451 #define BCE_PORT_FEATURE_BAR1_SIZE_8M 0x8
452 #define BCE_PORT_FEATURE_BAR1_SIZE_16M 0x9
453 #define BCE_PORT_FEATURE_BAR1_SIZE_32M 0xa
454 #define BCE_PORT_FEATURE_BAR1_SIZE_64M 0xb
455 #define BCE_PORT_FEATURE_BAR1_SIZE_128M 0xc
456 #define BCE_PORT_FEATURE_BAR1_SIZE_256M 0xd
457 #define BCE_PORT_FEATURE_BAR1_SIZE_512M 0xe
458 #define BCE_PORT_FEATURE_BAR1_SIZE_1G 0xf
460 #define BCE_PORT_FEATURE_WOL 0xdc
461 #define BCE_PORT2_FEATURE_WOL 0x150
462 #define BCE_PORT_FEATURE_WOL_DEFAULT_SHIFT_BITS 4
463 #define BCE_PORT_FEATURE_WOL_DEFAULT_MASK 0x30
464 #define BCE_PORT_FEATURE_WOL_DEFAULT_DISABLE 0
465 #define BCE_PORT_FEATURE_WOL_DEFAULT_MAGIC 0x10
466 #define BCE_PORT_FEATURE_WOL_DEFAULT_ACPI 0x20
467 #define BCE_PORT_FEATURE_WOL_DEFAULT_MAGIC_AND_ACPI 0x30
468 #define BCE_PORT_FEATURE_WOL_LINK_SPEED_MASK 0xf
469 #define BCE_PORT_FEATURE_WOL_LINK_SPEED_AUTONEG 0
470 #define BCE_PORT_FEATURE_WOL_LINK_SPEED_10HALF 1
471 #define BCE_PORT_FEATURE_WOL_LINK_SPEED_10FULL 2
472 #define BCE_PORT_FEATURE_WOL_LINK_SPEED_100HALF 3
473 #define BCE_PORT_FEATURE_WOL_LINK_SPEED_100FULL 4
474 #define BCE_PORT_FEATURE_WOL_LINK_SPEED_1000HALF 5
475 #define BCE_PORT_FEATURE_WOL_LINK_SPEED_1000FULL 6
476 #define BCE_PORT_FEATURE_WOL_AUTONEG_ADVERTISE_1000 0x40
477 #define BCE_PORT_FEATURE_WOL_RESERVED_PAUSE_CAP 0x400
478 #define BCE_PORT_FEATURE_WOL_RESERVED_ASYM_PAUSE_CAP 0x800
480 #define BCE_PORT_FEATURE_MBA 0xe0
481 #define BCE_PORT2_FEATURE_MBA 0x154
482 #define BCE_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT_BITS 0
483 #define BCE_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK 0x3
484 #define BCE_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE 0
485 #define BCE_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL 1
486 #define BCE_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP 2
487 #define BCE_PORT_FEATURE_MBA_LINK_SPEED_SHIFT_BITS 2
488 #define BCE_PORT_FEATURE_MBA_LINK_SPEED_MASK 0x3c
489 #define BCE_PORT_FEATURE_MBA_LINK_SPEED_AUTONEG 0
490 #define BCE_PORT_FEATURE_MBA_LINK_SPEED_10HALF 0x4
491 #define BCE_PORT_FEATURE_MBA_LINK_SPEED_10FULL 0x8
492 #define BCE_PORT_FEATURE_MBA_LINK_SPEED_100HALF 0xc
493 #define BCE_PORT_FEATURE_MBA_LINK_SPEED_100FULL 0x10
494 #define BCE_PORT_FEATURE_MBA_LINK_SPEED_1000HALF 0x14
495 #define BCE_PORT_FEATURE_MBA_LINK_SPEED_1000FULL 0x18
496 #define BCE_PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE 0x40
497 #define BCE_PORT_FEATURE_MBA_HOTKEY_CTRL_S 0
498 #define BCE_PORT_FEATURE_MBA_HOTKEY_CTRL_B 0x80
499 #define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT_BITS 8
500 #define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK 0xff00
501 #define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED 0
502 #define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_1K 0x100
503 #define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_2K 0x200
504 #define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_4K 0x300
505 #define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_8K 0x400
506 #define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_16K 0x500
507 #define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_32K 0x600
508 #define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_64K 0x700
509 #define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_128K 0x800
510 #define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_256K 0x900
511 #define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_512K 0xa00
512 #define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_1M 0xb00
513 #define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_2M 0xc00
514 #define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_4M 0xd00
515 #define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_8M 0xe00
516 #define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_16M 0xf00
517 #define BCE_PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT_BITS 16
518 #define BCE_PORT_FEATURE_MBA_MSG_TIMEOUT_MASK 0xf0000
519 #define BCE_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT_BITS 20
520 #define BCE_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK 0x300000
521 #define BCE_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO 0
522 #define BCE_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS 0x100000
523 #define BCE_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H 0x200000
524 #define BCE_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H 0x300000
526 #define BCE_PORT_FEATURE_IMD 0xe4
527 #define BCE_PORT2_FEATURE_IMD 0x158
528 #define BCE_PORT_FEATURE_IMD_LINK_OVERRIDE_DEFAULT 0
529 #define BCE_PORT_FEATURE_IMD_LINK_OVERRIDE_ENABLE 1
531 #define BCE_PORT_FEATURE_VLAN 0xe8
532 #define BCE_PORT2_FEATURE_VLAN 0x15c
533 #define BCE_PORT_FEATURE_MBA_VLAN_TAG_MASK 0xffff
534 #define BCE_PORT_FEATURE_MBA_VLAN_ENABLE 0x10000
536 #define BCE_BC_STATE_RESET_TYPE 0x000001c0
537 #define BCE_BC_STATE_RESET_TYPE_SIG 0x00005254
538 #define BCE_BC_STATE_RESET_TYPE_SIG_MASK 0x0000ffff
539 #define BCE_BC_STATE_RESET_TYPE_NONE (BCE_BC_STATE_RESET_TYPE_SIG | \
541 #define BCE_BC_STATE_RESET_TYPE_PCI (BCE_BC_STATE_RESET_TYPE_SIG | \
543 #define BCE_BC_STATE_RESET_TYPE_VAUX (BCE_BC_STATE_RESET_TYPE_SIG | \
545 #define BCE_BC_STATE_RESET_TYPE_DRV_MASK DRV_MSG_CODE
546 #define BCE_BC_STATE_RESET_TYPE_DRV_RESET (BCE_BC_STATE_RESET_TYPE_SIG | \
548 #define BCE_BC_STATE_RESET_TYPE_DRV_UNLOAD (BCE_BC_STATE_RESET_TYPE_SIG | \
550 #define BCE_BC_STATE_RESET_TYPE_DRV_SHUTDOWN (BCE_BC_STATE_RESET_TYPE_SIG | \
551 DRV_MSG_CODE_SHUTDOWN)
552 #define BCE_BC_STATE_RESET_TYPE_DRV_WOL (BCE_BC_STATE_RESET_TYPE_SIG | \
554 #define BCE_BC_STATE_RESET_TYPE_DRV_DIAG (BCE_BC_STATE_RESET_TYPE_SIG | \
556 #define BCE_BC_STATE_RESET_TYPE_VALUE(msg) (BCE_BC_STATE_RESET_TYPE_SIG | \
559 #define BCE_BC_STATE 0x000001c4
560 #define BCE_BC_STATE_ERR_MASK 0x0000ff00
561 #define BCE_BC_STATE_SIGN 0x42530000
562 #define BCE_BC_STATE_SIGN_MASK 0xffff0000
563 #define BCE_BC_STATE_BC1_START (BCE_BC_STATE_SIGN | 0x1)
564 #define BCE_BC_STATE_GET_NVM_CFG1 (BCE_BC_STATE_SIGN | 0x2)
565 #define BCE_BC_STATE_PROG_BAR (BCE_BC_STATE_SIGN | 0x3)
566 #define BCE_BC_STATE_INIT_VID (BCE_BC_STATE_SIGN | 0x4)
567 #define BCE_BC_STATE_GET_NVM_CFG2 (BCE_BC_STATE_SIGN | 0x5)
568 #define BCE_BC_STATE_APPLY_WKARND (BCE_BC_STATE_SIGN | 0x6)
569 #define BCE_BC_STATE_LOAD_BC2 (BCE_BC_STATE_SIGN | 0x7)
570 #define BCE_BC_STATE_GOING_BC2 (BCE_BC_STATE_SIGN | 0x8)
571 #define BCE_BC_STATE_GOING_DIAG (BCE_BC_STATE_SIGN | 0x9)
572 #define BCE_BC_STATE_RT_FINAL_INIT (BCE_BC_STATE_SIGN | 0x81)
573 #define BCE_BC_STATE_RT_WKARND (BCE_BC_STATE_SIGN | 0x82)
574 #define BCE_BC_STATE_RT_DRV_PULSE (BCE_BC_STATE_SIGN | 0x83)
575 #define BCE_BC_STATE_RT_FIOEVTS (BCE_BC_STATE_SIGN | 0x84)
576 #define BCE_BC_STATE_RT_DRV_CMD (BCE_BC_STATE_SIGN | 0x85)
577 #define BCE_BC_STATE_RT_LOW_POWER (BCE_BC_STATE_SIGN | 0x86)
578 #define BCE_BC_STATE_RT_SET_WOL (BCE_BC_STATE_SIGN | 0x87)
579 #define BCE_BC_STATE_RT_OTHER_FW (BCE_BC_STATE_SIGN | 0x88)
580 #define BCE_BC_STATE_RT_GOING_D3 (BCE_BC_STATE_SIGN | 0x89)
581 #define BCE_BC_STATE_ERR_BAD_VERSION (BCE_BC_STATE_SIGN | 0x0100)
582 #define BCE_BC_STATE_ERR_BAD_BC2_CRC (BCE_BC_STATE_SIGN | 0x0200)
583 #define BCE_BC_STATE_ERR_BC1_LOOP (BCE_BC_STATE_SIGN | 0x0300)
584 #define BCE_BC_STATE_ERR_UNKNOWN_CMD (BCE_BC_STATE_SIGN | 0x0400)
585 #define BCE_BC_STATE_ERR_DRV_DEAD (BCE_BC_STATE_SIGN | 0x0500)
586 #define BCE_BC_STATE_ERR_NO_RXP (BCE_BC_STATE_SIGN | 0x0600)
587 #define BCE_BC_STATE_ERR_TOO_MANY_RBUF (BCE_BC_STATE_SIGN | 0x0700)
589 #define BCE_BC_STATE_DEBUG_CMD 0x1dc
590 #define BCE_BC_STATE_BC_DBG_CMD_SIGNATURE 0x42440000
591 #define BCE_BC_STATE_BC_DBG_CMD_SIGNATURE_MASK 0xffff0000
592 #define BCE_BC_STATE_BC_DBG_CMD_LOOP_CNT_MASK 0xffff
593 #define BCE_BC_STATE_BC_DBG_CMD_LOOP_INFINITE 0xffff
595 #define HOST_VIEW_SHMEM_BASE 0x167c00
598 * PCI registers defined in the PCI 2.2 spec.
600 #define BCE_PCI_PCIX_CMD 0x42
603 /****************************************************************************/
604 /* Convenience definitions. */
605 /****************************************************************************/
606 #define REG_WR(sc, reg, val) \
607 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, reg, val)
608 #define REG_WR16(sc, reg, val) \
609 bus_space_write_2(sc->bce_btag, sc->bce_bhandle, reg, val)
610 #define REG_RD(sc, reg) \
611 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, reg)
613 #define REG_RD_IND(sc, offset) bce_reg_rd_ind(sc, offset)
614 #define REG_WR_IND(sc, offset, val) bce_reg_wr_ind(sc, offset, val)
616 #define CTX_WR(sc, cid_addr, offset, val) \
617 bce_ctx_wr(sc, cid_addr, offset, val)
619 #define BCE_SETBIT(sc, reg, x) REG_WR(sc, reg, (REG_RD(sc, reg) | (x)))
620 #define BCE_CLRBIT(sc, reg, x) REG_WR(sc, reg, (REG_RD(sc, reg) & ~(x)))
622 #define PCI_SETBIT(dev, reg, x, s) \
623 pci_write_config(dev, reg, (pci_read_config(dev, reg, s) | (x)), s)
624 #define PCI_CLRBIT(dev, reg, x, s) \
625 pci_write_config(dev, reg, (pci_read_config(dev, reg, s) & ~(x)), s)
627 #define BCE_STATS(x) (u_long) stats->stat_ ## x ## _lo
628 #if (BUS_SPACE_MAXADDR > 0xFFFFFFFF)
629 #define BCE_ADDR_LO(y) ((uint64_t) (y) & 0xFFFFFFFF)
630 #define BCE_ADDR_HI(y) ((uint64_t) (y) >> 32)
632 #define BCE_ADDR_LO(y) ((uint32_t)y)
633 #define BCE_ADDR_HI(y) (0)
638 * The following data structures are generated from RTL code.
639 * Do not modify any values below this line.
642 /****************************************************************************/
643 /* Do not modify any of the following data structures, they are generated */
646 /* Begin machine generated definitions. */
647 /****************************************************************************/
653 uint32_t tx_bd_haddr_hi;
654 uint32_t tx_bd_haddr_lo;
655 uint32_t tx_bd_mss_nbytes;
656 uint16_t tx_bd_flags;
657 uint16_t tx_bd_vlan_tag;
658 #define TX_BD_FLAGS_CONN_FAULT (1<<0)
659 #define TX_BD_FLAGS_TCP_UDP_CKSUM (1<<1)
660 #define TX_BD_FLAGS_IP_CKSUM (1<<2)
661 #define TX_BD_FLAGS_VLAN_TAG (1<<3)
662 #define TX_BD_FLAGS_COAL_NOW (1<<4)
663 #define TX_BD_FLAGS_DONT_GEN_CRC (1<<5)
664 #define TX_BD_FLAGS_END (1<<6)
665 #define TX_BD_FLAGS_START (1<<7)
666 #define TX_BD_FLAGS_SW_OPTION_WORD (0x1f<<8)
667 #define TX_BD_FLAGS_SW_FLAGS (1<<13)
668 #define TX_BD_FLAGS_SW_SNAP (1<<14)
669 #define TX_BD_FLAGS_SW_LSO (1<<15)
677 uint32_t rx_bd_haddr_hi;
678 uint32_t rx_bd_haddr_lo;
680 uint32_t rx_bd_flags;
681 #define RX_BD_FLAGS_NOPUSH (1<<0)
682 #define RX_BD_FLAGS_DUMMY (1<<1)
683 #define RX_BD_FLAGS_END (1<<2)
684 #define RX_BD_FLAGS_START (1<<3)
689 * status_block definition
691 struct status_block {
692 uint32_t status_attn_bits;
693 #define STATUS_ATTN_BITS_LINK_STATE (1L<<0)
694 #define STATUS_ATTN_BITS_TX_SCHEDULER_ABORT (1L<<1)
695 #define STATUS_ATTN_BITS_TX_BD_READ_ABORT (1L<<2)
696 #define STATUS_ATTN_BITS_TX_BD_CACHE_ABORT (1L<<3)
697 #define STATUS_ATTN_BITS_TX_PROCESSOR_ABORT (1L<<4)
698 #define STATUS_ATTN_BITS_TX_DMA_ABORT (1L<<5)
699 #define STATUS_ATTN_BITS_TX_PATCHUP_ABORT (1L<<6)
700 #define STATUS_ATTN_BITS_TX_ASSEMBLER_ABORT (1L<<7)
701 #define STATUS_ATTN_BITS_RX_PARSER_MAC_ABORT (1L<<8)
702 #define STATUS_ATTN_BITS_RX_PARSER_CATCHUP_ABORT (1L<<9)
703 #define STATUS_ATTN_BITS_RX_MBUF_ABORT (1L<<10)
704 #define STATUS_ATTN_BITS_RX_LOOKUP_ABORT (1L<<11)
705 #define STATUS_ATTN_BITS_RX_PROCESSOR_ABORT (1L<<12)
706 #define STATUS_ATTN_BITS_RX_V2P_ABORT (1L<<13)
707 #define STATUS_ATTN_BITS_RX_BD_CACHE_ABORT (1L<<14)
708 #define STATUS_ATTN_BITS_RX_DMA_ABORT (1L<<15)
709 #define STATUS_ATTN_BITS_COMPLETION_ABORT (1L<<16)
710 #define STATUS_ATTN_BITS_HOST_COALESCE_ABORT (1L<<17)
711 #define STATUS_ATTN_BITS_MAILBOX_QUEUE_ABORT (1L<<18)
712 #define STATUS_ATTN_BITS_CONTEXT_ABORT (1L<<19)
713 #define STATUS_ATTN_BITS_CMD_SCHEDULER_ABORT (1L<<20)
714 #define STATUS_ATTN_BITS_CMD_PROCESSOR_ABORT (1L<<21)
715 #define STATUS_ATTN_BITS_MGMT_PROCESSOR_ABORT (1L<<22)
716 #define STATUS_ATTN_BITS_MAC_ABORT (1L<<23)
717 #define STATUS_ATTN_BITS_TIMER_ABORT (1L<<24)
718 #define STATUS_ATTN_BITS_DMAE_ABORT (1L<<25)
719 #define STATUS_ATTN_BITS_FLSH_ABORT (1L<<26)
720 #define STATUS_ATTN_BITS_GRC_ABORT (1L<<27)
721 #define STATUS_ATTN_BITS_PARITY_ERROR (1L<<31)
723 uint32_t status_attn_bits_ack;
724 #if BYTE_ORDER == BIG_ENDIAN
725 uint16_t status_tx_quick_consumer_index0;
726 uint16_t status_tx_quick_consumer_index1;
727 uint16_t status_tx_quick_consumer_index2;
728 uint16_t status_tx_quick_consumer_index3;
729 uint16_t status_rx_quick_consumer_index0;
730 uint16_t status_rx_quick_consumer_index1;
731 uint16_t status_rx_quick_consumer_index2;
732 uint16_t status_rx_quick_consumer_index3;
733 uint16_t status_rx_quick_consumer_index4;
734 uint16_t status_rx_quick_consumer_index5;
735 uint16_t status_rx_quick_consumer_index6;
736 uint16_t status_rx_quick_consumer_index7;
737 uint16_t status_rx_quick_consumer_index8;
738 uint16_t status_rx_quick_consumer_index9;
739 uint16_t status_rx_quick_consumer_index10;
740 uint16_t status_rx_quick_consumer_index11;
741 uint16_t status_rx_quick_consumer_index12;
742 uint16_t status_rx_quick_consumer_index13;
743 uint16_t status_rx_quick_consumer_index14;
744 uint16_t status_rx_quick_consumer_index15;
745 uint16_t status_completion_producer_index;
746 uint16_t status_cmd_consumer_index;
748 uint16_t status_unused;
750 uint16_t status_tx_quick_consumer_index1;
751 uint16_t status_tx_quick_consumer_index0;
752 uint16_t status_tx_quick_consumer_index3;
753 uint16_t status_tx_quick_consumer_index2;
754 uint16_t status_rx_quick_consumer_index1;
755 uint16_t status_rx_quick_consumer_index0;
756 uint16_t status_rx_quick_consumer_index3;
757 uint16_t status_rx_quick_consumer_index2;
758 uint16_t status_rx_quick_consumer_index5;
759 uint16_t status_rx_quick_consumer_index4;
760 uint16_t status_rx_quick_consumer_index7;
761 uint16_t status_rx_quick_consumer_index6;
762 uint16_t status_rx_quick_consumer_index9;
763 uint16_t status_rx_quick_consumer_index8;
764 uint16_t status_rx_quick_consumer_index11;
765 uint16_t status_rx_quick_consumer_index10;
766 uint16_t status_rx_quick_consumer_index13;
767 uint16_t status_rx_quick_consumer_index12;
768 uint16_t status_rx_quick_consumer_index15;
769 uint16_t status_rx_quick_consumer_index14;
770 uint16_t status_cmd_consumer_index;
771 uint16_t status_completion_producer_index;
772 uint16_t status_unused;
779 * statistics_block definition
781 struct statistics_block {
782 uint32_t stat_IfHCInOctets_hi;
783 uint32_t stat_IfHCInOctets_lo;
784 uint32_t stat_IfHCInBadOctets_hi;
785 uint32_t stat_IfHCInBadOctets_lo;
786 uint32_t stat_IfHCOutOctets_hi;
787 uint32_t stat_IfHCOutOctets_lo;
788 uint32_t stat_IfHCOutBadOctets_hi;
789 uint32_t stat_IfHCOutBadOctets_lo;
790 uint32_t stat_IfHCInUcastPkts_hi;
791 uint32_t stat_IfHCInUcastPkts_lo;
792 uint32_t stat_IfHCInMulticastPkts_hi;
793 uint32_t stat_IfHCInMulticastPkts_lo;
794 uint32_t stat_IfHCInBroadcastPkts_hi;
795 uint32_t stat_IfHCInBroadcastPkts_lo;
796 uint32_t stat_IfHCOutUcastPkts_hi;
797 uint32_t stat_IfHCOutUcastPkts_lo;
798 uint32_t stat_IfHCOutMulticastPkts_hi;
799 uint32_t stat_IfHCOutMulticastPkts_lo;
800 uint32_t stat_IfHCOutBroadcastPkts_hi;
801 uint32_t stat_IfHCOutBroadcastPkts_lo;
802 uint32_t stat_emac_tx_stat_dot3statsinternalmactransmiterrors;
803 uint32_t stat_Dot3StatsCarrierSenseErrors;
804 uint32_t stat_Dot3StatsFCSErrors;
805 uint32_t stat_Dot3StatsAlignmentErrors;
806 uint32_t stat_Dot3StatsSingleCollisionFrames;
807 uint32_t stat_Dot3StatsMultipleCollisionFrames;
808 uint32_t stat_Dot3StatsDeferredTransmissions;
809 uint32_t stat_Dot3StatsExcessiveCollisions;
810 uint32_t stat_Dot3StatsLateCollisions;
811 uint32_t stat_EtherStatsCollisions;
812 uint32_t stat_EtherStatsFragments;
813 uint32_t stat_EtherStatsJabbers;
814 uint32_t stat_EtherStatsUndersizePkts;
815 uint32_t stat_EtherStatsOverrsizePkts;
816 uint32_t stat_EtherStatsPktsRx64Octets;
817 uint32_t stat_EtherStatsPktsRx65Octetsto127Octets;
818 uint32_t stat_EtherStatsPktsRx128Octetsto255Octets;
819 uint32_t stat_EtherStatsPktsRx256Octetsto511Octets;
820 uint32_t stat_EtherStatsPktsRx512Octetsto1023Octets;
821 uint32_t stat_EtherStatsPktsRx1024Octetsto1522Octets;
822 uint32_t stat_EtherStatsPktsRx1523Octetsto9022Octets;
823 uint32_t stat_EtherStatsPktsTx64Octets;
824 uint32_t stat_EtherStatsPktsTx65Octetsto127Octets;
825 uint32_t stat_EtherStatsPktsTx128Octetsto255Octets;
826 uint32_t stat_EtherStatsPktsTx256Octetsto511Octets;
827 uint32_t stat_EtherStatsPktsTx512Octetsto1023Octets;
828 uint32_t stat_EtherStatsPktsTx1024Octetsto1522Octets;
829 uint32_t stat_EtherStatsPktsTx1523Octetsto9022Octets;
830 uint32_t stat_XonPauseFramesReceived;
831 uint32_t stat_XoffPauseFramesReceived;
832 uint32_t stat_OutXonSent;
833 uint32_t stat_OutXoffSent;
834 uint32_t stat_FlowControlDone;
835 uint32_t stat_MacControlFramesReceived;
836 uint32_t stat_XoffStateEntered;
837 uint32_t stat_IfInFramesL2FilterDiscards;
838 uint32_t stat_IfInRuleCheckerDiscards;
839 uint32_t stat_IfInFTQDiscards;
840 uint32_t stat_IfInMBUFDiscards;
841 uint32_t stat_IfInRuleCheckerP4Hit;
842 uint32_t stat_CatchupInRuleCheckerDiscards;
843 uint32_t stat_CatchupInFTQDiscards;
844 uint32_t stat_CatchupInMBUFDiscards;
845 uint32_t stat_CatchupInRuleCheckerP4Hit;
846 uint32_t stat_GenStat00;
847 uint32_t stat_GenStat01;
848 uint32_t stat_GenStat02;
849 uint32_t stat_GenStat03;
850 uint32_t stat_GenStat04;
851 uint32_t stat_GenStat05;
852 uint32_t stat_GenStat06;
853 uint32_t stat_GenStat07;
854 uint32_t stat_GenStat08;
855 uint32_t stat_GenStat09;
856 uint32_t stat_GenStat10;
857 uint32_t stat_GenStat11;
858 uint32_t stat_GenStat12;
859 uint32_t stat_GenStat13;
860 uint32_t stat_GenStat14;
861 uint32_t stat_GenStat15;
869 uint32_t l2_fhdr_status;
870 #define L2_FHDR_STATUS_RULE_CLASS (0x7<<0)
871 #define L2_FHDR_STATUS_RULE_P2 (1<<3)
872 #define L2_FHDR_STATUS_RULE_P3 (1<<4)
873 #define L2_FHDR_STATUS_RULE_P4 (1<<5)
874 #define L2_FHDR_STATUS_L2_VLAN_TAG (1<<6)
875 #define L2_FHDR_STATUS_L2_LLC_SNAP (1<<7)
876 #define L2_FHDR_STATUS_RSS_HASH (1<<8)
877 #define L2_FHDR_STATUS_IP_DATAGRAM (1<<13)
878 #define L2_FHDR_STATUS_TCP_SEGMENT (1<<14)
879 #define L2_FHDR_STATUS_UDP_DATAGRAM (1<<15)
881 #define L2_FHDR_ERRORS_BAD_CRC (1<<17)
882 #define L2_FHDR_ERRORS_PHY_DECODE (1<<18)
883 #define L2_FHDR_ERRORS_ALIGNMENT (1<<19)
884 #define L2_FHDR_ERRORS_TOO_SHORT (1<<20)
885 #define L2_FHDR_ERRORS_GIANT_FRAME (1<<21)
886 #define L2_FHDR_ERRORS_TCP_XSUM (1<<28)
887 #define L2_FHDR_ERRORS_UDP_XSUM (1<<31)
889 uint32_t l2_fhdr_hash;
890 #if BYTE_ORDER == BIG_ENDIAN
891 uint16_t l2_fhdr_pkt_len;
892 uint16_t l2_fhdr_vlan_tag;
893 uint16_t l2_fhdr_ip_xsum;
894 uint16_t l2_fhdr_tcp_udp_xsum;
896 uint16_t l2_fhdr_vlan_tag;
897 uint16_t l2_fhdr_pkt_len;
898 uint16_t l2_fhdr_tcp_udp_xsum;
899 uint16_t l2_fhdr_ip_xsum;
905 * l2_context definition
907 #define BCE_L2CTX_TYPE 0x00000000
908 #define BCE_L2CTX_TYPE_SIZE_L2 ((0xc0/0x20)<<16)
909 #define BCE_L2CTX_TYPE_TYPE (0xf<<28)
910 #define BCE_L2CTX_TYPE_TYPE_EMPTY (0<<28)
911 #define BCE_L2CTX_TYPE_TYPE_L2 (1<<28)
913 #define BCE_L2CTX_TX_HOST_BIDX 0x00000088
914 #define BCE_L2CTX_EST_NBD 0x00000088
915 #define BCE_L2CTX_CMD_TYPE 0x00000088
916 #define BCE_L2CTX_CMD_TYPE_TYPE (0xf<<24)
917 #define BCE_L2CTX_CMD_TYPE_TYPE_L2 (0<<24)
918 #define BCE_L2CTX_CMD_TYPE_TYPE_TCP (1<<24)
920 #define BCE_L2CTX_TX_HOST_BSEQ 0x00000090
921 #define BCE_L2CTX_TSCH_BSEQ 0x00000094
922 #define BCE_L2CTX_TBDR_BSEQ 0x00000098
923 #define BCE_L2CTX_TBDR_BOFF 0x0000009c
924 #define BCE_L2CTX_TBDR_BIDX 0x0000009c
925 #define BCE_L2CTX_TBDR_BHADDR_HI 0x000000a0
926 #define BCE_L2CTX_TBDR_BHADDR_LO 0x000000a4
927 #define BCE_L2CTX_TXP_BOFF 0x000000a8
928 #define BCE_L2CTX_TXP_BIDX 0x000000a8
929 #define BCE_L2CTX_TXP_BSEQ 0x000000ac
933 * l2_bd_chain_context definition
935 #define BCE_L2CTX_BD_PRE_READ 0x00000000
936 #define BCE_L2CTX_CTX_SIZE 0x00000000
937 #define BCE_L2CTX_CTX_TYPE 0x00000000
938 #define BCE_L2CTX_CTX_TYPE_SIZE_L2 ((0x20/20)<<16)
939 #define BCE_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE (0xf<<28)
940 #define BCE_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_UNDEFINED (0<<28)
941 #define BCE_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE (1<<28)
943 #define BCE_L2CTX_HOST_BDIDX 0x00000004
944 #define BCE_L2CTX_HOST_BSEQ 0x00000008
945 #define BCE_L2CTX_NX_BSEQ 0x0000000c
946 #define BCE_L2CTX_NX_BDHADDR_HI 0x00000010
947 #define BCE_L2CTX_NX_BDHADDR_LO 0x00000014
948 #define BCE_L2CTX_NX_BDIDX 0x00000018
952 * pci_config_l definition
955 #define BCE_PCICFG_MISC_CONFIG 0x00000068
956 #define BCE_PCICFG_MISC_CONFIG_TARGET_BYTE_SWAP (1L<<2)
957 #define BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP (1L<<3)
958 #define BCE_PCICFG_MISC_CONFIG_CLOCK_CTL_ENA (1L<<5)
959 #define BCE_PCICFG_MISC_CONFIG_TARGET_GRC_WORD_SWAP (1L<<6)
960 #define BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA (1L<<7)
961 #define BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ (1L<<8)
962 #define BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY (1L<<9)
963 #define BCE_PCICFG_MISC_CONFIG_ASIC_METAL_REV (0xffL<<16)
964 #define BCE_PCICFG_MISC_CONFIG_ASIC_BASE_REV (0xfL<<24)
965 #define BCE_PCICFG_MISC_CONFIG_ASIC_ID (0xfL<<28)
966 #define BCE_PCICFG_MISC_CONFIG_ASIC_REV (0xffffL<<16)
968 #define BCE_PCICFG_MISC_STATUS 0x0000006c
969 #define BCE_PCICFG_MISC_STATUS_INTA_VALUE (1L<<0)
970 #define BCE_PCICFG_MISC_STATUS_32BIT_DET (1L<<1)
971 #define BCE_PCICFG_MISC_STATUS_M66EN (1L<<2)
972 #define BCE_PCICFG_MISC_STATUS_PCIX_DET (1L<<3)
973 #define BCE_PCICFG_MISC_STATUS_PCIX_SPEED (0x3L<<4)
974 #define BCE_PCICFG_MISC_STATUS_PCIX_SPEED_66 (0L<<4)
975 #define BCE_PCICFG_MISC_STATUS_PCIX_SPEED_100 (1L<<4)
976 #define BCE_PCICFG_MISC_STATUS_PCIX_SPEED_133 (2L<<4)
977 #define BCE_PCICFG_MISC_STATUS_PCIX_SPEED_PCI_MODE (3L<<4)
979 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS 0x00000070
980 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET (0xfL<<0)
981 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ (0L<<0)
982 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ (1L<<0)
983 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ (2L<<0)
984 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ (3L<<0)
985 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ (4L<<0)
986 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ (5L<<0)
987 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ (6L<<0)
988 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ (7L<<0)
989 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW (0xfL<<0)
990 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_DISABLE (1L<<6)
991 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT (1L<<7)
992 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC (0x7L<<8)
993 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_UNDEF (0L<<8)
994 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12 (1L<<8)
995 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6 (2L<<8)
996 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62 (4L<<8)
997 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PLAY_DEAD (1L<<11)
998 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED (0xfL<<12)
999 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100 (0L<<12)
1000 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80 (1L<<12)
1001 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_50 (2L<<12)
1002 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40 (4L<<12)
1003 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25 (8L<<12)
1004 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP (1L<<16)
1005 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_PLL_STOP (1L<<17)
1006 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED_18 (1L<<18)
1007 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_USE_SPD_DET (1L<<19)
1008 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED (0xfffL<<20)
1010 #define BCE_PCICFG_REG_WINDOW_ADDRESS 0x00000078
1011 #define BCE_PCICFG_REG_WINDOW 0x00000080
1012 #define BCE_PCICFG_INT_ACK_CMD 0x00000084
1013 #define BCE_PCICFG_INT_ACK_CMD_INDEX (0xffffL<<0)
1014 #define BCE_PCICFG_INT_ACK_CMD_INDEX_VALID (1L<<16)
1015 #define BCE_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM (1L<<17)
1016 #define BCE_PCICFG_INT_ACK_CMD_MASK_INT (1L<<18)
1018 #define BCE_PCICFG_STATUS_BIT_SET_CMD 0x00000088
1019 #define BCE_PCICFG_STATUS_BIT_CLEAR_CMD 0x0000008c
1020 #define BCE_PCICFG_MAILBOX_QUEUE_ADDR 0x00000090
1021 #define BCE_PCICFG_MAILBOX_QUEUE_DATA 0x00000094
1025 * pci_reg definition
1028 #define BCE_PCI_GRC_WINDOW_ADDR 0x00000400
1029 #define BCE_PCI_GRC_WINDOW_ADDR_PCI_GRC_WINDOW_ADDR_VALUE (0x3ffffL<<8)
1031 #define BCE_PCI_CONFIG_1 0x00000404
1032 #define BCE_PCI_CONFIG_1_READ_BOUNDARY (0x7L<<8)
1033 #define BCE_PCI_CONFIG_1_READ_BOUNDARY_OFF (0L<<8)
1034 #define BCE_PCI_CONFIG_1_READ_BOUNDARY_16 (1L<<8)
1035 #define BCE_PCI_CONFIG_1_READ_BOUNDARY_32 (2L<<8)
1036 #define BCE_PCI_CONFIG_1_READ_BOUNDARY_64 (3L<<8)
1037 #define BCE_PCI_CONFIG_1_READ_BOUNDARY_128 (4L<<8)
1038 #define BCE_PCI_CONFIG_1_READ_BOUNDARY_256 (5L<<8)
1039 #define BCE_PCI_CONFIG_1_READ_BOUNDARY_512 (6L<<8)
1040 #define BCE_PCI_CONFIG_1_READ_BOUNDARY_1024 (7L<<8)
1041 #define BCE_PCI_CONFIG_1_WRITE_BOUNDARY (0x7L<<11)
1042 #define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_OFF (0L<<11)
1043 #define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_16 (1L<<11)
1044 #define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_32 (2L<<11)
1045 #define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_64 (3L<<11)
1046 #define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_128 (4L<<11)
1047 #define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_256 (5L<<11)
1048 #define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_512 (6L<<11)
1049 #define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_1024 (7L<<11)
1051 #define BCE_PCI_CONFIG_2 0x00000408
1052 #define BCE_PCI_CONFIG_2_BAR1_SIZE (0xfL<<0)
1053 #define BCE_PCI_CONFIG_2_BAR1_SIZE_DISABLED (0L<<0)
1054 #define BCE_PCI_CONFIG_2_BAR1_SIZE_64K (1L<<0)
1055 #define BCE_PCI_CONFIG_2_BAR1_SIZE_128K (2L<<0)
1056 #define BCE_PCI_CONFIG_2_BAR1_SIZE_256K (3L<<0)
1057 #define BCE_PCI_CONFIG_2_BAR1_SIZE_512K (4L<<0)
1058 #define BCE_PCI_CONFIG_2_BAR1_SIZE_1M (5L<<0)
1059 #define BCE_PCI_CONFIG_2_BAR1_SIZE_2M (6L<<0)
1060 #define BCE_PCI_CONFIG_2_BAR1_SIZE_4M (7L<<0)
1061 #define BCE_PCI_CONFIG_2_BAR1_SIZE_8M (8L<<0)
1062 #define BCE_PCI_CONFIG_2_BAR1_SIZE_16M (9L<<0)
1063 #define BCE_PCI_CONFIG_2_BAR1_SIZE_32M (10L<<0)
1064 #define BCE_PCI_CONFIG_2_BAR1_SIZE_64M (11L<<0)
1065 #define BCE_PCI_CONFIG_2_BAR1_SIZE_128M (12L<<0)
1066 #define BCE_PCI_CONFIG_2_BAR1_SIZE_256M (13L<<0)
1067 #define BCE_PCI_CONFIG_2_BAR1_SIZE_512M (14L<<0)
1068 #define BCE_PCI_CONFIG_2_BAR1_SIZE_1G (15L<<0)
1069 #define BCE_PCI_CONFIG_2_BAR1_64ENA (1L<<4)
1070 #define BCE_PCI_CONFIG_2_EXP_ROM_RETRY (1L<<5)
1071 #define BCE_PCI_CONFIG_2_CFG_CYCLE_RETRY (1L<<6)
1072 #define BCE_PCI_CONFIG_2_FIRST_CFG_DONE (1L<<7)
1073 #define BCE_PCI_CONFIG_2_EXP_ROM_SIZE (0xffL<<8)
1074 #define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED (0L<<8)
1075 #define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_1K (1L<<8)
1076 #define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_2K (2L<<8)
1077 #define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_4K (3L<<8)
1078 #define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_8K (4L<<8)
1079 #define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_16K (5L<<8)
1080 #define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_32K (6L<<8)
1081 #define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_64K (7L<<8)
1082 #define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_128K (8L<<8)
1083 #define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_256K (9L<<8)
1084 #define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_512K (10L<<8)
1085 #define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_1M (11L<<8)
1086 #define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_2M (12L<<8)
1087 #define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_4M (13L<<8)
1088 #define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_8M (14L<<8)
1089 #define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_16M (15L<<8)
1090 #define BCE_PCI_CONFIG_2_MAX_SPLIT_LIMIT (0x1fL<<16)
1091 #define BCE_PCI_CONFIG_2_MAX_READ_LIMIT (0x3L<<21)
1092 #define BCE_PCI_CONFIG_2_MAX_READ_LIMIT_512 (0L<<21)
1093 #define BCE_PCI_CONFIG_2_MAX_READ_LIMIT_1K (1L<<21)
1094 #define BCE_PCI_CONFIG_2_MAX_READ_LIMIT_2K (2L<<21)
1095 #define BCE_PCI_CONFIG_2_MAX_READ_LIMIT_4K (3L<<21)
1096 #define BCE_PCI_CONFIG_2_FORCE_32_BIT_MSTR (1L<<23)
1097 #define BCE_PCI_CONFIG_2_FORCE_32_BIT_TGT (1L<<24)
1098 #define BCE_PCI_CONFIG_2_KEEP_REQ_ASSERT (1L<<25)
1100 #define BCE_PCI_CONFIG_3 0x0000040c
1101 #define BCE_PCI_CONFIG_3_STICKY_BYTE (0xffL<<0)
1102 #define BCE_PCI_CONFIG_3_FORCE_PME (1L<<24)
1103 #define BCE_PCI_CONFIG_3_PME_STATUS (1L<<25)
1104 #define BCE_PCI_CONFIG_3_PME_ENABLE (1L<<26)
1105 #define BCE_PCI_CONFIG_3_PM_STATE (0x3L<<27)
1106 #define BCE_PCI_CONFIG_3_VAUX_PRESET (1L<<30)
1107 #define BCE_PCI_CONFIG_3_PCI_POWER (1L<<31)
1109 #define BCE_PCI_PM_DATA_A 0x00000410
1110 #define BCE_PCI_PM_DATA_A_PM_DATA_0_PRG (0xffL<<0)
1111 #define BCE_PCI_PM_DATA_A_PM_DATA_1_PRG (0xffL<<8)
1112 #define BCE_PCI_PM_DATA_A_PM_DATA_2_PRG (0xffL<<16)
1113 #define BCE_PCI_PM_DATA_A_PM_DATA_3_PRG (0xffL<<24)
1115 #define BCE_PCI_PM_DATA_B 0x00000414
1116 #define BCE_PCI_PM_DATA_B_PM_DATA_4_PRG (0xffL<<0)
1117 #define BCE_PCI_PM_DATA_B_PM_DATA_5_PRG (0xffL<<8)
1118 #define BCE_PCI_PM_DATA_B_PM_DATA_6_PRG (0xffL<<16)
1119 #define BCE_PCI_PM_DATA_B_PM_DATA_7_PRG (0xffL<<24)
1121 #define BCE_PCI_SWAP_DIAG0 0x00000418
1122 #define BCE_PCI_SWAP_DIAG1 0x0000041c
1123 #define BCE_PCI_EXP_ROM_ADDR 0x00000420
1124 #define BCE_PCI_EXP_ROM_ADDR_ADDRESS (0x3fffffL<<2)
1125 #define BCE_PCI_EXP_ROM_ADDR_REQ (1L<<31)
1127 #define BCE_PCI_EXP_ROM_DATA 0x00000424
1128 #define BCE_PCI_VPD_INTF 0x00000428
1129 #define BCE_PCI_VPD_INTF_INTF_REQ (1L<<0)
1131 #define BCE_PCI_VPD_ADDR_FLAG 0x0000042c
1132 #define BCE_PCI_VPD_ADDR_FLAG_ADDRESS (0x1fff<<2)
1133 #define BCE_PCI_VPD_ADDR_FLAG_WR (1<<15)
1135 #define BCE_PCI_VPD_DATA 0x00000430
1136 #define BCE_PCI_ID_VAL1 0x00000434
1137 #define BCE_PCI_ID_VAL1_DEVICE_ID (0xffffL<<0)
1138 #define BCE_PCI_ID_VAL1_VENDOR_ID (0xffffL<<16)
1140 #define BCE_PCI_ID_VAL2 0x00000438
1141 #define BCE_PCI_ID_VAL2_SUBSYSTEM_VENDOR_ID (0xffffL<<0)
1142 #define BCE_PCI_ID_VAL2_SUBSYSTEM_ID (0xffffL<<16)
1144 #define BCE_PCI_ID_VAL3 0x0000043c
1145 #define BCE_PCI_ID_VAL3_CLASS_CODE (0xffffffL<<0)
1146 #define BCE_PCI_ID_VAL3_REVISION_ID (0xffL<<24)
1148 #define BCE_PCI_ID_VAL4 0x00000440
1149 #define BCE_PCI_ID_VAL4_CAP_ENA (0xfL<<0)
1150 #define BCE_PCI_ID_VAL4_CAP_ENA_0 (0L<<0)
1151 #define BCE_PCI_ID_VAL4_CAP_ENA_1 (1L<<0)
1152 #define BCE_PCI_ID_VAL4_CAP_ENA_2 (2L<<0)
1153 #define BCE_PCI_ID_VAL4_CAP_ENA_3 (3L<<0)
1154 #define BCE_PCI_ID_VAL4_CAP_ENA_4 (4L<<0)
1155 #define BCE_PCI_ID_VAL4_CAP_ENA_5 (5L<<0)
1156 #define BCE_PCI_ID_VAL4_CAP_ENA_6 (6L<<0)
1157 #define BCE_PCI_ID_VAL4_CAP_ENA_7 (7L<<0)
1158 #define BCE_PCI_ID_VAL4_CAP_ENA_8 (8L<<0)
1159 #define BCE_PCI_ID_VAL4_CAP_ENA_9 (9L<<0)
1160 #define BCE_PCI_ID_VAL4_CAP_ENA_10 (10L<<0)
1161 #define BCE_PCI_ID_VAL4_CAP_ENA_11 (11L<<0)
1162 #define BCE_PCI_ID_VAL4_CAP_ENA_12 (12L<<0)
1163 #define BCE_PCI_ID_VAL4_CAP_ENA_13 (13L<<0)
1164 #define BCE_PCI_ID_VAL4_CAP_ENA_14 (14L<<0)
1165 #define BCE_PCI_ID_VAL4_CAP_ENA_15 (15L<<0)
1166 #define BCE_PCI_ID_VAL4_PM_SCALE_PRG (0x3L<<6)
1167 #define BCE_PCI_ID_VAL4_PM_SCALE_PRG_0 (0L<<6)
1168 #define BCE_PCI_ID_VAL4_PM_SCALE_PRG_1 (1L<<6)
1169 #define BCE_PCI_ID_VAL4_PM_SCALE_PRG_2 (2L<<6)
1170 #define BCE_PCI_ID_VAL4_PM_SCALE_PRG_3 (3L<<6)
1171 #define BCE_PCI_ID_VAL4_MSI_LIMIT (0x7L<<9)
1172 #define BCE_PCI_ID_VAL4_MSI_ADVERTIZE (0x7L<<12)
1173 #define BCE_PCI_ID_VAL4_MSI_ENABLE (1L<<15)
1174 #define BCE_PCI_ID_VAL4_MAX_64_ADVERTIZE (1L<<16)
1175 #define BCE_PCI_ID_VAL4_MAX_133_ADVERTIZE (1L<<17)
1176 #define BCE_PCI_ID_VAL4_MAX_MEM_READ_SIZE (0x3L<<21)
1177 #define BCE_PCI_ID_VAL4_MAX_SPLIT_SIZE (0x7L<<23)
1178 #define BCE_PCI_ID_VAL4_MAX_CUMULATIVE_SIZE (0x7L<<26)
1180 #define BCE_PCI_ID_VAL5 0x00000444
1181 #define BCE_PCI_ID_VAL5_D1_SUPPORT (1L<<0)
1182 #define BCE_PCI_ID_VAL5_D2_SUPPORT (1L<<1)
1183 #define BCE_PCI_ID_VAL5_PME_IN_D0 (1L<<2)
1184 #define BCE_PCI_ID_VAL5_PME_IN_D1 (1L<<3)
1185 #define BCE_PCI_ID_VAL5_PME_IN_D2 (1L<<4)
1186 #define BCE_PCI_ID_VAL5_PME_IN_D3_HOT (1L<<5)
1188 #define BCE_PCI_PCIX_EXTENDED_STATUS 0x00000448
1189 #define BCE_PCI_PCIX_EXTENDED_STATUS_NO_SNOOP (1L<<8)
1190 #define BCE_PCI_PCIX_EXTENDED_STATUS_LONG_BURST (1L<<9)
1191 #define BCE_PCI_PCIX_EXTENDED_STATUS_SPLIT_COMP_MSG_CLASS (0xfL<<16)
1192 #define BCE_PCI_PCIX_EXTENDED_STATUS_SPLIT_COMP_MSG_IDX (0xffL<<24)
1194 #define BCE_PCI_ID_VAL6 0x0000044c
1195 #define BCE_PCI_ID_VAL6_MAX_LAT (0xffL<<0)
1196 #define BCE_PCI_ID_VAL6_MIN_GNT (0xffL<<8)
1197 #define BCE_PCI_ID_VAL6_BIST (0xffL<<16)
1199 #define BCE_PCI_MSI_DATA 0x00000450
1200 #define BCE_PCI_MSI_DATA_PCI_MSI_DATA (0xffffL<<0)
1202 #define BCE_PCI_MSI_ADDR_H 0x00000454
1203 #define BCE_PCI_MSI_ADDR_L 0x00000458
1207 * misc_reg definition
1210 #define BCE_MISC_COMMAND 0x00000800
1211 #define BCE_MISC_COMMAND_ENABLE_ALL (1L<<0)
1212 #define BCE_MISC_COMMAND_DISABLE_ALL (1L<<1)
1213 #define BCE_MISC_COMMAND_CORE_RESET (1L<<4)
1214 #define BCE_MISC_COMMAND_HARD_RESET (1L<<5)
1215 #define BCE_MISC_COMMAND_PAR_ERROR (1L<<8)
1216 #define BCE_MISC_COMMAND_PAR_ERR_RAM (0x7fL<<16)
1218 #define BCE_MISC_CFG 0x00000804
1219 #define BCE_MISC_CFG_PCI_GRC_TMOUT (1L<<0)
1220 #define BCE_MISC_CFG_NVM_WR_EN (0x3L<<1)
1221 #define BCE_MISC_CFG_NVM_WR_EN_PROTECT (0L<<1)
1222 #define BCE_MISC_CFG_NVM_WR_EN_PCI (1L<<1)
1223 #define BCE_MISC_CFG_NVM_WR_EN_ALLOW (2L<<1)
1224 #define BCE_MISC_CFG_NVM_WR_EN_ALLOW2 (3L<<1)
1225 #define BCE_MISC_CFG_BIST_EN (1L<<3)
1226 #define BCE_MISC_CFG_CK25_OUT_ALT_SRC (1L<<4)
1227 #define BCE_MISC_CFG_BYPASS_BSCAN (1L<<5)
1228 #define BCE_MISC_CFG_BYPASS_EJTAG (1L<<6)
1229 #define BCE_MISC_CFG_CLK_CTL_OVERRIDE (1L<<7)
1230 #define BCE_MISC_CFG_LEDMODE (0x3L<<8)
1231 #define BCE_MISC_CFG_LEDMODE_MAC (0L<<8)
1232 #define BCE_MISC_CFG_LEDMODE_GPHY1 (1L<<8)
1233 #define BCE_MISC_CFG_LEDMODE_GPHY2 (2L<<8)
1235 #define BCE_MISC_ID 0x00000808
1236 #define BCE_MISC_ID_BOND_ID (0xfL<<0)
1237 #define BCE_MISC_ID_CHIP_METAL (0xffL<<4)
1238 #define BCE_MISC_ID_CHIP_REV (0xfL<<12)
1239 #define BCE_MISC_ID_CHIP_NUM (0xffffL<<16)
1241 #define BCE_MISC_ENABLE_STATUS_BITS 0x0000080c
1242 #define BCE_MISC_ENABLE_STATUS_BITS_TX_SCHEDULER_ENABLE (1L<<0)
1243 #define BCE_MISC_ENABLE_STATUS_BITS_TX_BD_READ_ENABLE (1L<<1)
1244 #define BCE_MISC_ENABLE_STATUS_BITS_TX_BD_CACHE_ENABLE (1L<<2)
1245 #define BCE_MISC_ENABLE_STATUS_BITS_TX_PROCESSOR_ENABLE (1L<<3)
1246 #define BCE_MISC_ENABLE_STATUS_BITS_TX_DMA_ENABLE (1L<<4)
1247 #define BCE_MISC_ENABLE_STATUS_BITS_TX_PATCHUP_ENABLE (1L<<5)
1248 #define BCE_MISC_ENABLE_STATUS_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6)
1249 #define BCE_MISC_ENABLE_STATUS_BITS_TX_HEADER_Q_ENABLE (1L<<7)
1250 #define BCE_MISC_ENABLE_STATUS_BITS_TX_ASSEMBLER_ENABLE (1L<<8)
1251 #define BCE_MISC_ENABLE_STATUS_BITS_EMAC_ENABLE (1L<<9)
1252 #define BCE_MISC_ENABLE_STATUS_BITS_RX_PARSER_MAC_ENABLE (1L<<10)
1253 #define BCE_MISC_ENABLE_STATUS_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11)
1254 #define BCE_MISC_ENABLE_STATUS_BITS_RX_MBUF_ENABLE (1L<<12)
1255 #define BCE_MISC_ENABLE_STATUS_BITS_RX_LOOKUP_ENABLE (1L<<13)
1256 #define BCE_MISC_ENABLE_STATUS_BITS_RX_PROCESSOR_ENABLE (1L<<14)
1257 #define BCE_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE (1L<<15)
1258 #define BCE_MISC_ENABLE_STATUS_BITS_RX_BD_CACHE_ENABLE (1L<<16)
1259 #define BCE_MISC_ENABLE_STATUS_BITS_RX_DMA_ENABLE (1L<<17)
1260 #define BCE_MISC_ENABLE_STATUS_BITS_COMPLETION_ENABLE (1L<<18)
1261 #define BCE_MISC_ENABLE_STATUS_BITS_HOST_COALESCE_ENABLE (1L<<19)
1262 #define BCE_MISC_ENABLE_STATUS_BITS_MAILBOX_QUEUE_ENABLE (1L<<20)
1263 #define BCE_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE (1L<<21)
1264 #define BCE_MISC_ENABLE_STATUS_BITS_CMD_SCHEDULER_ENABLE (1L<<22)
1265 #define BCE_MISC_ENABLE_STATUS_BITS_CMD_PROCESSOR_ENABLE (1L<<23)
1266 #define BCE_MISC_ENABLE_STATUS_BITS_MGMT_PROCESSOR_ENABLE (1L<<24)
1267 #define BCE_MISC_ENABLE_STATUS_BITS_TIMER_ENABLE (1L<<25)
1268 #define BCE_MISC_ENABLE_STATUS_BITS_DMA_ENGINE_ENABLE (1L<<26)
1269 #define BCE_MISC_ENABLE_STATUS_BITS_UMP_ENABLE (1L<<27)
1271 #define BCE_MISC_ENABLE_SET_BITS 0x00000810
1272 #define BCE_MISC_ENABLE_SET_BITS_TX_SCHEDULER_ENABLE (1L<<0)
1273 #define BCE_MISC_ENABLE_SET_BITS_TX_BD_READ_ENABLE (1L<<1)
1274 #define BCE_MISC_ENABLE_SET_BITS_TX_BD_CACHE_ENABLE (1L<<2)
1275 #define BCE_MISC_ENABLE_SET_BITS_TX_PROCESSOR_ENABLE (1L<<3)
1276 #define BCE_MISC_ENABLE_SET_BITS_TX_DMA_ENABLE (1L<<4)
1277 #define BCE_MISC_ENABLE_SET_BITS_TX_PATCHUP_ENABLE (1L<<5)
1278 #define BCE_MISC_ENABLE_SET_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6)
1279 #define BCE_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE (1L<<7)
1280 #define BCE_MISC_ENABLE_SET_BITS_TX_ASSEMBLER_ENABLE (1L<<8)
1281 #define BCE_MISC_ENABLE_SET_BITS_EMAC_ENABLE (1L<<9)
1282 #define BCE_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE (1L<<10)
1283 #define BCE_MISC_ENABLE_SET_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11)
1284 #define BCE_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE (1L<<12)
1285 #define BCE_MISC_ENABLE_SET_BITS_RX_LOOKUP_ENABLE (1L<<13)
1286 #define BCE_MISC_ENABLE_SET_BITS_RX_PROCESSOR_ENABLE (1L<<14)
1287 #define BCE_MISC_ENABLE_SET_BITS_RX_V2P_ENABLE (1L<<15)
1288 #define BCE_MISC_ENABLE_SET_BITS_RX_BD_CACHE_ENABLE (1L<<16)
1289 #define BCE_MISC_ENABLE_SET_BITS_RX_DMA_ENABLE (1L<<17)
1290 #define BCE_MISC_ENABLE_SET_BITS_COMPLETION_ENABLE (1L<<18)
1291 #define BCE_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE (1L<<19)
1292 #define BCE_MISC_ENABLE_SET_BITS_MAILBOX_QUEUE_ENABLE (1L<<20)
1293 #define BCE_MISC_ENABLE_SET_BITS_CONTEXT_ENABLE (1L<<21)
1294 #define BCE_MISC_ENABLE_SET_BITS_CMD_SCHEDULER_ENABLE (1L<<22)
1295 #define BCE_MISC_ENABLE_SET_BITS_CMD_PROCESSOR_ENABLE (1L<<23)
1296 #define BCE_MISC_ENABLE_SET_BITS_MGMT_PROCESSOR_ENABLE (1L<<24)
1297 #define BCE_MISC_ENABLE_SET_BITS_TIMER_ENABLE (1L<<25)
1298 #define BCE_MISC_ENABLE_SET_BITS_DMA_ENGINE_ENABLE (1L<<26)
1299 #define BCE_MISC_ENABLE_SET_BITS_UMP_ENABLE (1L<<27)
1301 #define BCE_MISC_ENABLE_CLR_BITS 0x00000814
1302 #define BCE_MISC_ENABLE_CLR_BITS_TX_SCHEDULER_ENABLE (1L<<0)
1303 #define BCE_MISC_ENABLE_CLR_BITS_TX_BD_READ_ENABLE (1L<<1)
1304 #define BCE_MISC_ENABLE_CLR_BITS_TX_BD_CACHE_ENABLE (1L<<2)
1305 #define BCE_MISC_ENABLE_CLR_BITS_TX_PROCESSOR_ENABLE (1L<<3)
1306 #define BCE_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE (1L<<4)
1307 #define BCE_MISC_ENABLE_CLR_BITS_TX_PATCHUP_ENABLE (1L<<5)
1308 #define BCE_MISC_ENABLE_CLR_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6)
1309 #define BCE_MISC_ENABLE_CLR_BITS_TX_HEADER_Q_ENABLE (1L<<7)
1310 #define BCE_MISC_ENABLE_CLR_BITS_TX_ASSEMBLER_ENABLE (1L<<8)
1311 #define BCE_MISC_ENABLE_CLR_BITS_EMAC_ENABLE (1L<<9)
1312 #define BCE_MISC_ENABLE_CLR_BITS_RX_PARSER_MAC_ENABLE (1L<<10)
1313 #define BCE_MISC_ENABLE_CLR_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11)
1314 #define BCE_MISC_ENABLE_CLR_BITS_RX_MBUF_ENABLE (1L<<12)
1315 #define BCE_MISC_ENABLE_CLR_BITS_RX_LOOKUP_ENABLE (1L<<13)
1316 #define BCE_MISC_ENABLE_CLR_BITS_RX_PROCESSOR_ENABLE (1L<<14)
1317 #define BCE_MISC_ENABLE_CLR_BITS_RX_V2P_ENABLE (1L<<15)
1318 #define BCE_MISC_ENABLE_CLR_BITS_RX_BD_CACHE_ENABLE (1L<<16)
1319 #define BCE_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE (1L<<17)
1320 #define BCE_MISC_ENABLE_CLR_BITS_COMPLETION_ENABLE (1L<<18)
1321 #define BCE_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE (1L<<19)
1322 #define BCE_MISC_ENABLE_CLR_BITS_MAILBOX_QUEUE_ENABLE (1L<<20)
1323 #define BCE_MISC_ENABLE_CLR_BITS_CONTEXT_ENABLE (1L<<21)
1324 #define BCE_MISC_ENABLE_CLR_BITS_CMD_SCHEDULER_ENABLE (1L<<22)
1325 #define BCE_MISC_ENABLE_CLR_BITS_CMD_PROCESSOR_ENABLE (1L<<23)
1326 #define BCE_MISC_ENABLE_CLR_BITS_MGMT_PROCESSOR_ENABLE (1L<<24)
1327 #define BCE_MISC_ENABLE_CLR_BITS_TIMER_ENABLE (1L<<25)
1328 #define BCE_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE (1L<<26)
1329 #define BCE_MISC_ENABLE_CLR_BITS_UMP_ENABLE (1L<<27)
1331 #define BCE_MISC_CLOCK_CONTROL_BITS 0x00000818
1332 #define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET (0xfL<<0)
1333 #define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ (0L<<0)
1334 #define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ (1L<<0)
1335 #define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ (2L<<0)
1336 #define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ (3L<<0)
1337 #define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ (4L<<0)
1338 #define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ (5L<<0)
1339 #define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ (6L<<0)
1340 #define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ (7L<<0)
1341 #define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW (0xfL<<0)
1342 #define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_DISABLE (1L<<6)
1343 #define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT (1L<<7)
1344 #define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC (0x7L<<8)
1345 #define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_UNDEF (0L<<8)
1346 #define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12 (1L<<8)
1347 #define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6 (2L<<8)
1348 #define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62 (4L<<8)
1349 #define BCE_MISC_CLOCK_CONTROL_BITS_PLAY_DEAD (1L<<11)
1350 #define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED (0xfL<<12)
1351 #define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100 (0L<<12)
1352 #define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80 (1L<<12)
1353 #define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_50 (2L<<12)
1354 #define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40 (4L<<12)
1355 #define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25 (8L<<12)
1356 #define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP (1L<<16)
1357 #define BCE_MISC_CLOCK_CONTROL_BITS_PCI_PLL_STOP (1L<<17)
1358 #define BCE_MISC_CLOCK_CONTROL_BITS_RESERVED_18 (1L<<18)
1359 #define BCE_MISC_CLOCK_CONTROL_BITS_USE_SPD_DET (1L<<19)
1360 #define BCE_MISC_CLOCK_CONTROL_BITS_RESERVED (0xfffL<<20)
1362 #define BCE_MISC_GPIO 0x0000081c
1363 #define BCE_MISC_GPIO_VALUE (0xffL<<0)
1364 #define BCE_MISC_GPIO_SET (0xffL<<8)
1365 #define BCE_MISC_GPIO_CLR (0xffL<<16)
1366 #define BCE_MISC_GPIO_FLOAT (0xffL<<24)
1368 #define BCE_MISC_GPIO_INT 0x00000820
1369 #define BCE_MISC_GPIO_INT_INT_STATE (0xfL<<0)
1370 #define BCE_MISC_GPIO_INT_OLD_VALUE (0xfL<<8)
1371 #define BCE_MISC_GPIO_INT_OLD_SET (0xfL<<16)
1372 #define BCE_MISC_GPIO_INT_OLD_CLR (0xfL<<24)
1374 #define BCE_MISC_CONFIG_LFSR 0x00000824
1375 #define BCE_MISC_CONFIG_LFSR_DIV (0xffffL<<0)
1377 #define BCE_MISC_LFSR_MASK_BITS 0x00000828
1378 #define BCE_MISC_LFSR_MASK_BITS_TX_SCHEDULER_ENABLE (1L<<0)
1379 #define BCE_MISC_LFSR_MASK_BITS_TX_BD_READ_ENABLE (1L<<1)
1380 #define BCE_MISC_LFSR_MASK_BITS_TX_BD_CACHE_ENABLE (1L<<2)
1381 #define BCE_MISC_LFSR_MASK_BITS_TX_PROCESSOR_ENABLE (1L<<3)
1382 #define BCE_MISC_LFSR_MASK_BITS_TX_DMA_ENABLE (1L<<4)
1383 #define BCE_MISC_LFSR_MASK_BITS_TX_PATCHUP_ENABLE (1L<<5)
1384 #define BCE_MISC_LFSR_MASK_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6)
1385 #define BCE_MISC_LFSR_MASK_BITS_TX_HEADER_Q_ENABLE (1L<<7)
1386 #define BCE_MISC_LFSR_MASK_BITS_TX_ASSEMBLER_ENABLE (1L<<8)
1387 #define BCE_MISC_LFSR_MASK_BITS_EMAC_ENABLE (1L<<9)
1388 #define BCE_MISC_LFSR_MASK_BITS_RX_PARSER_MAC_ENABLE (1L<<10)
1389 #define BCE_MISC_LFSR_MASK_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11)
1390 #define BCE_MISC_LFSR_MASK_BITS_RX_MBUF_ENABLE (1L<<12)
1391 #define BCE_MISC_LFSR_MASK_BITS_RX_LOOKUP_ENABLE (1L<<13)
1392 #define BCE_MISC_LFSR_MASK_BITS_RX_PROCESSOR_ENABLE (1L<<14)
1393 #define BCE_MISC_LFSR_MASK_BITS_RX_V2P_ENABLE (1L<<15)
1394 #define BCE_MISC_LFSR_MASK_BITS_RX_BD_CACHE_ENABLE (1L<<16)
1395 #define BCE_MISC_LFSR_MASK_BITS_RX_DMA_ENABLE (1L<<17)
1396 #define BCE_MISC_LFSR_MASK_BITS_COMPLETION_ENABLE (1L<<18)
1397 #define BCE_MISC_LFSR_MASK_BITS_HOST_COALESCE_ENABLE (1L<<19)
1398 #define BCE_MISC_LFSR_MASK_BITS_MAILBOX_QUEUE_ENABLE (1L<<20)
1399 #define BCE_MISC_LFSR_MASK_BITS_CONTEXT_ENABLE (1L<<21)
1400 #define BCE_MISC_LFSR_MASK_BITS_CMD_SCHEDULER_ENABLE (1L<<22)
1401 #define BCE_MISC_LFSR_MASK_BITS_CMD_PROCESSOR_ENABLE (1L<<23)
1402 #define BCE_MISC_LFSR_MASK_BITS_MGMT_PROCESSOR_ENABLE (1L<<24)
1403 #define BCE_MISC_LFSR_MASK_BITS_TIMER_ENABLE (1L<<25)
1404 #define BCE_MISC_LFSR_MASK_BITS_DMA_ENGINE_ENABLE (1L<<26)
1405 #define BCE_MISC_LFSR_MASK_BITS_UMP_ENABLE (1L<<27)
1407 #define BCE_MISC_ARB_REQ0 0x0000082c
1408 #define BCE_MISC_ARB_REQ1 0x00000830
1409 #define BCE_MISC_ARB_REQ2 0x00000834
1410 #define BCE_MISC_ARB_REQ3 0x00000838
1411 #define BCE_MISC_ARB_REQ4 0x0000083c
1412 #define BCE_MISC_ARB_FREE0 0x00000840
1413 #define BCE_MISC_ARB_FREE1 0x00000844
1414 #define BCE_MISC_ARB_FREE2 0x00000848
1415 #define BCE_MISC_ARB_FREE3 0x0000084c
1416 #define BCE_MISC_ARB_FREE4 0x00000850
1417 #define BCE_MISC_ARB_REQ_STATUS0 0x00000854
1418 #define BCE_MISC_ARB_REQ_STATUS1 0x00000858
1419 #define BCE_MISC_ARB_REQ_STATUS2 0x0000085c
1420 #define BCE_MISC_ARB_REQ_STATUS3 0x00000860
1421 #define BCE_MISC_ARB_REQ_STATUS4 0x00000864
1422 #define BCE_MISC_ARB_GNT0 0x00000868
1423 #define BCE_MISC_ARB_GNT0_0 (0x7L<<0)
1424 #define BCE_MISC_ARB_GNT0_1 (0x7L<<4)
1425 #define BCE_MISC_ARB_GNT0_2 (0x7L<<8)
1426 #define BCE_MISC_ARB_GNT0_3 (0x7L<<12)
1427 #define BCE_MISC_ARB_GNT0_4 (0x7L<<16)
1428 #define BCE_MISC_ARB_GNT0_5 (0x7L<<20)
1429 #define BCE_MISC_ARB_GNT0_6 (0x7L<<24)
1430 #define BCE_MISC_ARB_GNT0_7 (0x7L<<28)
1432 #define BCE_MISC_ARB_GNT1 0x0000086c
1433 #define BCE_MISC_ARB_GNT1_8 (0x7L<<0)
1434 #define BCE_MISC_ARB_GNT1_9 (0x7L<<4)
1435 #define BCE_MISC_ARB_GNT1_10 (0x7L<<8)
1436 #define BCE_MISC_ARB_GNT1_11 (0x7L<<12)
1437 #define BCE_MISC_ARB_GNT1_12 (0x7L<<16)
1438 #define BCE_MISC_ARB_GNT1_13 (0x7L<<20)
1439 #define BCE_MISC_ARB_GNT1_14 (0x7L<<24)
1440 #define BCE_MISC_ARB_GNT1_15 (0x7L<<28)
1442 #define BCE_MISC_ARB_GNT2 0x00000870
1443 #define BCE_MISC_ARB_GNT2_16 (0x7L<<0)
1444 #define BCE_MISC_ARB_GNT2_17 (0x7L<<4)
1445 #define BCE_MISC_ARB_GNT2_18 (0x7L<<8)
1446 #define BCE_MISC_ARB_GNT2_19 (0x7L<<12)
1447 #define BCE_MISC_ARB_GNT2_20 (0x7L<<16)
1448 #define BCE_MISC_ARB_GNT2_21 (0x7L<<20)
1449 #define BCE_MISC_ARB_GNT2_22 (0x7L<<24)
1450 #define BCE_MISC_ARB_GNT2_23 (0x7L<<28)
1452 #define BCE_MISC_ARB_GNT3 0x00000874
1453 #define BCE_MISC_ARB_GNT3_24 (0x7L<<0)
1454 #define BCE_MISC_ARB_GNT3_25 (0x7L<<4)
1455 #define BCE_MISC_ARB_GNT3_26 (0x7L<<8)
1456 #define BCE_MISC_ARB_GNT3_27 (0x7L<<12)
1457 #define BCE_MISC_ARB_GNT3_28 (0x7L<<16)
1458 #define BCE_MISC_ARB_GNT3_29 (0x7L<<20)
1459 #define BCE_MISC_ARB_GNT3_30 (0x7L<<24)
1460 #define BCE_MISC_ARB_GNT3_31 (0x7L<<28)
1462 #define BCE_MISC_PRBS_CONTROL 0x00000878
1463 #define BCE_MISC_PRBS_CONTROL_EN (1L<<0)
1464 #define BCE_MISC_PRBS_CONTROL_RSTB (1L<<1)
1465 #define BCE_MISC_PRBS_CONTROL_INV (1L<<2)
1466 #define BCE_MISC_PRBS_CONTROL_ERR_CLR (1L<<3)
1467 #define BCE_MISC_PRBS_CONTROL_ORDER (0x3L<<4)
1468 #define BCE_MISC_PRBS_CONTROL_ORDER_7TH (0L<<4)
1469 #define BCE_MISC_PRBS_CONTROL_ORDER_15TH (1L<<4)
1470 #define BCE_MISC_PRBS_CONTROL_ORDER_23RD (2L<<4)
1471 #define BCE_MISC_PRBS_CONTROL_ORDER_31ST (3L<<4)
1473 #define BCE_MISC_PRBS_STATUS 0x0000087c
1474 #define BCE_MISC_PRBS_STATUS_LOCK (1L<<0)
1475 #define BCE_MISC_PRBS_STATUS_STKY (1L<<1)
1476 #define BCE_MISC_PRBS_STATUS_ERRORS (0x3fffL<<2)
1477 #define BCE_MISC_PRBS_STATUS_STATE (0xfL<<16)
1479 #define BCE_MISC_SM_ASF_CONTROL 0x00000880
1480 #define BCE_MISC_SM_ASF_CONTROL_ASF_RST (1L<<0)
1481 #define BCE_MISC_SM_ASF_CONTROL_TSC_EN (1L<<1)
1482 #define BCE_MISC_SM_ASF_CONTROL_WG_TO (1L<<2)
1483 #define BCE_MISC_SM_ASF_CONTROL_HB_TO (1L<<3)
1484 #define BCE_MISC_SM_ASF_CONTROL_PA_TO (1L<<4)
1485 #define BCE_MISC_SM_ASF_CONTROL_PL_TO (1L<<5)
1486 #define BCE_MISC_SM_ASF_CONTROL_RT_TO (1L<<6)
1487 #define BCE_MISC_SM_ASF_CONTROL_SMB_EVENT (1L<<7)
1488 #define BCE_MISC_SM_ASF_CONTROL_RES (0xfL<<8)
1489 #define BCE_MISC_SM_ASF_CONTROL_SMB_EN (1L<<12)
1490 #define BCE_MISC_SM_ASF_CONTROL_SMB_BB_EN (1L<<13)
1491 #define BCE_MISC_SM_ASF_CONTROL_SMB_NO_ADDR_FILT (1L<<14)
1492 #define BCE_MISC_SM_ASF_CONTROL_SMB_AUTOREAD (1L<<15)
1493 #define BCE_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR1 (0x3fL<<16)
1494 #define BCE_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR2 (0x3fL<<24)
1495 #define BCE_MISC_SM_ASF_CONTROL_EN_NIC_SMB_ADDR_0 (1L<<30)
1496 #define BCE_MISC_SM_ASF_CONTROL_SMB_EARLY_ATTN (1L<<31)
1498 #define BCE_MISC_SMB_IN 0x00000884
1499 #define BCE_MISC_SMB_IN_DAT_IN (0xffL<<0)
1500 #define BCE_MISC_SMB_IN_RDY (1L<<8)
1501 #define BCE_MISC_SMB_IN_DONE (1L<<9)
1502 #define BCE_MISC_SMB_IN_FIRSTBYTE (1L<<10)
1503 #define BCE_MISC_SMB_IN_STATUS (0x7L<<11)
1504 #define BCE_MISC_SMB_IN_STATUS_OK (0x0L<<11)
1505 #define BCE_MISC_SMB_IN_STATUS_PEC (0x1L<<11)
1506 #define BCE_MISC_SMB_IN_STATUS_OFLOW (0x2L<<11)
1507 #define BCE_MISC_SMB_IN_STATUS_STOP (0x3L<<11)
1508 #define BCE_MISC_SMB_IN_STATUS_TIMEOUT (0x4L<<11)
1510 #define BCE_MISC_SMB_OUT 0x00000888
1511 #define BCE_MISC_SMB_OUT_DAT_OUT (0xffL<<0)
1512 #define BCE_MISC_SMB_OUT_RDY (1L<<8)
1513 #define BCE_MISC_SMB_OUT_START (1L<<9)
1514 #define BCE_MISC_SMB_OUT_LAST (1L<<10)
1515 #define BCE_MISC_SMB_OUT_ACC_TYPE (1L<<11)
1516 #define BCE_MISC_SMB_OUT_ENB_PEC (1L<<12)
1517 #define BCE_MISC_SMB_OUT_GET_RX_LEN (1L<<13)
1518 #define BCE_MISC_SMB_OUT_SMB_READ_LEN (0x3fL<<14)
1519 #define BCE_MISC_SMB_OUT_SMB_OUT_STATUS (0xfL<<20)
1520 #define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_OK (0L<<20)
1521 #define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_NACK (1L<<20)
1522 #define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_NACK (9L<<20)
1523 #define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_UFLOW (2L<<20)
1524 #define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_STOP (3L<<20)
1525 #define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_TIMEOUT (4L<<20)
1526 #define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_LOST (5L<<20)
1527 #define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_LOST (0xdL<<20)
1528 #define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_BADACK (0x6L<<20)
1529 #define BCE_MISC_SMB_OUT_SMB_OUT_SLAVEMODE (1L<<24)
1530 #define BCE_MISC_SMB_OUT_SMB_OUT_DAT_EN (1L<<25)
1531 #define BCE_MISC_SMB_OUT_SMB_OUT_DAT_IN (1L<<26)
1532 #define BCE_MISC_SMB_OUT_SMB_OUT_CLK_EN (1L<<27)
1533 #define BCE_MISC_SMB_OUT_SMB_OUT_CLK_IN (1L<<28)
1535 #define BCE_MISC_SMB_WATCHDOG 0x0000088c
1536 #define BCE_MISC_SMB_WATCHDOG_WATCHDOG (0xffffL<<0)
1538 #define BCE_MISC_SMB_HEARTBEAT 0x00000890
1539 #define BCE_MISC_SMB_HEARTBEAT_HEARTBEAT (0xffffL<<0)
1541 #define BCE_MISC_SMB_POLL_ASF 0x00000894
1542 #define BCE_MISC_SMB_POLL_ASF_POLL_ASF (0xffffL<<0)
1544 #define BCE_MISC_SMB_POLL_LEGACY 0x00000898
1545 #define BCE_MISC_SMB_POLL_LEGACY_POLL_LEGACY (0xffffL<<0)
1547 #define BCE_MISC_SMB_RETRAN 0x0000089c
1548 #define BCE_MISC_SMB_RETRAN_RETRAN (0xffL<<0)
1550 #define BCE_MISC_SMB_TIMESTAMP 0x000008a0
1551 #define BCE_MISC_SMB_TIMESTAMP_TIMESTAMP (0xffffffffL<<0)
1553 #define BCE_MISC_PERR_ENA0 0x000008a4
1554 #define BCE_MISC_PERR_ENA0_COM_MISC_CTXC (1L<<0)
1555 #define BCE_MISC_PERR_ENA0_COM_MISC_REGF (1L<<1)
1556 #define BCE_MISC_PERR_ENA0_COM_MISC_SCPAD (1L<<2)
1557 #define BCE_MISC_PERR_ENA0_CP_MISC_CTXC (1L<<3)
1558 #define BCE_MISC_PERR_ENA0_CP_MISC_REGF (1L<<4)
1559 #define BCE_MISC_PERR_ENA0_CP_MISC_SCPAD (1L<<5)
1560 #define BCE_MISC_PERR_ENA0_CS_MISC_TMEM (1L<<6)
1561 #define BCE_MISC_PERR_ENA0_CTX_MISC_ACCM0 (1L<<7)
1562 #define BCE_MISC_PERR_ENA0_CTX_MISC_ACCM1 (1L<<8)
1563 #define BCE_MISC_PERR_ENA0_CTX_MISC_ACCM2 (1L<<9)
1564 #define BCE_MISC_PERR_ENA0_CTX_MISC_ACCM3 (1L<<10)
1565 #define BCE_MISC_PERR_ENA0_CTX_MISC_ACCM4 (1L<<11)
1566 #define BCE_MISC_PERR_ENA0_CTX_MISC_ACCM5 (1L<<12)
1567 #define BCE_MISC_PERR_ENA0_CTX_MISC_PGTBL (1L<<13)
1568 #define BCE_MISC_PERR_ENA0_DMAE_MISC_DR0 (1L<<14)
1569 #define BCE_MISC_PERR_ENA0_DMAE_MISC_DR1 (1L<<15)
1570 #define BCE_MISC_PERR_ENA0_DMAE_MISC_DR2 (1L<<16)
1571 #define BCE_MISC_PERR_ENA0_DMAE_MISC_DR3 (1L<<17)
1572 #define BCE_MISC_PERR_ENA0_DMAE_MISC_DR4 (1L<<18)
1573 #define BCE_MISC_PERR_ENA0_DMAE_MISC_DW0 (1L<<19)
1574 #define BCE_MISC_PERR_ENA0_DMAE_MISC_DW1 (1L<<20)
1575 #define BCE_MISC_PERR_ENA0_DMAE_MISC_DW2 (1L<<21)
1576 #define BCE_MISC_PERR_ENA0_HC_MISC_DMA (1L<<22)
1577 #define BCE_MISC_PERR_ENA0_MCP_MISC_REGF (1L<<23)
1578 #define BCE_MISC_PERR_ENA0_MCP_MISC_SCPAD (1L<<24)
1579 #define BCE_MISC_PERR_ENA0_MQ_MISC_CTX (1L<<25)
1580 #define BCE_MISC_PERR_ENA0_RBDC_MISC (1L<<26)
1581 #define BCE_MISC_PERR_ENA0_RBUF_MISC_MB (1L<<27)
1582 #define BCE_MISC_PERR_ENA0_RBUF_MISC_PTR (1L<<28)
1583 #define BCE_MISC_PERR_ENA0_RDE_MISC_RPC (1L<<29)
1584 #define BCE_MISC_PERR_ENA0_RDE_MISC_RPM (1L<<30)
1585 #define BCE_MISC_PERR_ENA0_RV2P_MISC_CB0REGS (1L<<31)
1587 #define BCE_MISC_PERR_ENA1 0x000008a8
1588 #define BCE_MISC_PERR_ENA1_RV2P_MISC_CB1REGS (1L<<0)
1589 #define BCE_MISC_PERR_ENA1_RV2P_MISC_P1IRAM (1L<<1)
1590 #define BCE_MISC_PERR_ENA1_RV2P_MISC_P2IRAM (1L<<2)
1591 #define BCE_MISC_PERR_ENA1_RXP_MISC_CTXC (1L<<3)
1592 #define BCE_MISC_PERR_ENA1_RXP_MISC_REGF (1L<<4)
1593 #define BCE_MISC_PERR_ENA1_RXP_MISC_SCPAD (1L<<5)
1594 #define BCE_MISC_PERR_ENA1_RXP_MISC_RBUFC (1L<<6)
1595 #define BCE_MISC_PERR_ENA1_TBDC_MISC (1L<<7)
1596 #define BCE_MISC_PERR_ENA1_TDMA_MISC (1L<<8)
1597 #define BCE_MISC_PERR_ENA1_THBUF_MISC_MB0 (1L<<9)
1598 #define BCE_MISC_PERR_ENA1_THBUF_MISC_MB1 (1L<<10)
1599 #define BCE_MISC_PERR_ENA1_TPAT_MISC_REGF (1L<<11)
1600 #define BCE_MISC_PERR_ENA1_TPAT_MISC_SCPAD (1L<<12)
1601 #define BCE_MISC_PERR_ENA1_TPBUF_MISC_MB (1L<<13)
1602 #define BCE_MISC_PERR_ENA1_TSCH_MISC_LR (1L<<14)
1603 #define BCE_MISC_PERR_ENA1_TXP_MISC_CTXC (1L<<15)
1604 #define BCE_MISC_PERR_ENA1_TXP_MISC_REGF (1L<<16)
1605 #define BCE_MISC_PERR_ENA1_TXP_MISC_SCPAD (1L<<17)
1606 #define BCE_MISC_PERR_ENA1_UMP_MISC_FIORX (1L<<18)
1607 #define BCE_MISC_PERR_ENA1_UMP_MISC_FIOTX (1L<<19)
1608 #define BCE_MISC_PERR_ENA1_UMP_MISC_RX (1L<<20)
1609 #define BCE_MISC_PERR_ENA1_UMP_MISC_TX (1L<<21)
1610 #define BCE_MISC_PERR_ENA1_RDMAQ_MISC (1L<<22)
1611 #define BCE_MISC_PERR_ENA1_CSQ_MISC (1L<<23)
1612 #define BCE_MISC_PERR_ENA1_CPQ_MISC (1L<<24)
1613 #define BCE_MISC_PERR_ENA1_MCPQ_MISC (1L<<25)
1614 #define BCE_MISC_PERR_ENA1_RV2PMQ_MISC (1L<<26)
1615 #define BCE_MISC_PERR_ENA1_RV2PPQ_MISC (1L<<27)
1616 #define BCE_MISC_PERR_ENA1_RV2PTQ_MISC (1L<<28)
1617 #define BCE_MISC_PERR_ENA1_RXPQ_MISC (1L<<29)
1618 #define BCE_MISC_PERR_ENA1_RXPCQ_MISC (1L<<30)
1619 #define BCE_MISC_PERR_ENA1_RLUPQ_MISC (1L<<31)
1621 #define BCE_MISC_PERR_ENA2 0x000008ac
1622 #define BCE_MISC_PERR_ENA2_COMQ_MISC (1L<<0)
1623 #define BCE_MISC_PERR_ENA2_COMXQ_MISC (1L<<1)
1624 #define BCE_MISC_PERR_ENA2_COMTQ_MISC (1L<<2)
1625 #define BCE_MISC_PERR_ENA2_TSCHQ_MISC (1L<<3)
1626 #define BCE_MISC_PERR_ENA2_TBDRQ_MISC (1L<<4)
1627 #define BCE_MISC_PERR_ENA2_TXPQ_MISC (1L<<5)
1628 #define BCE_MISC_PERR_ENA2_TDMAQ_MISC (1L<<6)
1629 #define BCE_MISC_PERR_ENA2_TPATQ_MISC (1L<<7)
1630 #define BCE_MISC_PERR_ENA2_TASQ_MISC (1L<<8)
1632 #define BCE_MISC_DEBUG_VECTOR_SEL 0x000008b0
1633 #define BCE_MISC_DEBUG_VECTOR_SEL_0 (0xfffL<<0)
1634 #define BCE_MISC_DEBUG_VECTOR_SEL_1 (0xfffL<<12)
1636 #define BCE_MISC_VREG_CONTROL 0x000008b4
1637 #define BCE_MISC_VREG_CONTROL_1_2 (0xfL<<0)
1638 #define BCE_MISC_VREG_CONTROL_2_5 (0xfL<<4)
1640 #define BCE_MISC_FINAL_CLK_CTL_VAL 0x000008b8
1641 #define BCE_MISC_FINAL_CLK_CTL_VAL_MISC_FINAL_CLK_CTL_VAL (0x3ffffffL<<6)
1643 #define BCE_MISC_UNUSED0 0x000008bc
1647 * nvm_reg definition
1650 #define BCE_NVM_COMMAND 0x00006400
1651 #define BCE_NVM_COMMAND_RST (1L<<0)
1652 #define BCE_NVM_COMMAND_DONE (1L<<3)
1653 #define BCE_NVM_COMMAND_DOIT (1L<<4)
1654 #define BCE_NVM_COMMAND_WR (1L<<5)
1655 #define BCE_NVM_COMMAND_ERASE (1L<<6)
1656 #define BCE_NVM_COMMAND_FIRST (1L<<7)
1657 #define BCE_NVM_COMMAND_LAST (1L<<8)
1658 #define BCE_NVM_COMMAND_WREN (1L<<16)
1659 #define BCE_NVM_COMMAND_WRDI (1L<<17)
1660 #define BCE_NVM_COMMAND_EWSR (1L<<18)
1661 #define BCE_NVM_COMMAND_WRSR (1L<<19)
1663 #define BCE_NVM_STATUS 0x00006404
1664 #define BCE_NVM_STATUS_PI_FSM_STATE (0xfL<<0)
1665 #define BCE_NVM_STATUS_EE_FSM_STATE (0xfL<<4)
1666 #define BCE_NVM_STATUS_EQ_FSM_STATE (0xfL<<8)
1668 #define BCE_NVM_WRITE 0x00006408
1669 #define BCE_NVM_WRITE_NVM_WRITE_VALUE (0xffffffffL<<0)
1670 #define BCE_NVM_WRITE_NVM_WRITE_VALUE_BIT_BANG (0L<<0)
1671 #define BCE_NVM_WRITE_NVM_WRITE_VALUE_EECLK (1L<<0)
1672 #define BCE_NVM_WRITE_NVM_WRITE_VALUE_EEDATA (2L<<0)
1673 #define BCE_NVM_WRITE_NVM_WRITE_VALUE_SCLK (4L<<0)
1674 #define BCE_NVM_WRITE_NVM_WRITE_VALUE_CS_B (8L<<0)
1675 #define BCE_NVM_WRITE_NVM_WRITE_VALUE_SO (16L<<0)
1676 #define BCE_NVM_WRITE_NVM_WRITE_VALUE_SI (32L<<0)
1678 #define BCE_NVM_ADDR 0x0000640c
1679 #define BCE_NVM_ADDR_NVM_ADDR_VALUE (0xffffffL<<0)
1680 #define BCE_NVM_ADDR_NVM_ADDR_VALUE_BIT_BANG (0L<<0)
1681 #define BCE_NVM_ADDR_NVM_ADDR_VALUE_EECLK (1L<<0)
1682 #define BCE_NVM_ADDR_NVM_ADDR_VALUE_EEDATA (2L<<0)
1683 #define BCE_NVM_ADDR_NVM_ADDR_VALUE_SCLK (4L<<0)
1684 #define BCE_NVM_ADDR_NVM_ADDR_VALUE_CS_B (8L<<0)
1685 #define BCE_NVM_ADDR_NVM_ADDR_VALUE_SO (16L<<0)
1686 #define BCE_NVM_ADDR_NVM_ADDR_VALUE_SI (32L<<0)
1688 #define BCE_NVM_READ 0x00006410
1689 #define BCE_NVM_READ_NVM_READ_VALUE (0xffffffffL<<0)
1690 #define BCE_NVM_READ_NVM_READ_VALUE_BIT_BANG (0L<<0)
1691 #define BCE_NVM_READ_NVM_READ_VALUE_EECLK (1L<<0)
1692 #define BCE_NVM_READ_NVM_READ_VALUE_EEDATA (2L<<0)
1693 #define BCE_NVM_READ_NVM_READ_VALUE_SCLK (4L<<0)
1694 #define BCE_NVM_READ_NVM_READ_VALUE_CS_B (8L<<0)
1695 #define BCE_NVM_READ_NVM_READ_VALUE_SO (16L<<0)
1696 #define BCE_NVM_READ_NVM_READ_VALUE_SI (32L<<0)
1698 #define BCE_NVM_CFG1 0x00006414
1699 #define BCE_NVM_CFG1_FLASH_MODE (1L<<0)
1700 #define BCE_NVM_CFG1_BUFFER_MODE (1L<<1)
1701 #define BCE_NVM_CFG1_PASS_MODE (1L<<2)
1702 #define BCE_NVM_CFG1_BITBANG_MODE (1L<<3)
1703 #define BCE_NVM_CFG1_STATUS_BIT (0x7L<<4)
1704 #define BCE_NVM_CFG1_STATUS_BIT_FLASH_RDY (0L<<4)
1705 #define BCE_NVM_CFG1_STATUS_BIT_BUFFER_RDY (7L<<4)
1706 #define BCE_NVM_CFG1_SPI_CLK_DIV (0xfL<<7)
1707 #define BCE_NVM_CFG1_SEE_CLK_DIV (0x7ffL<<11)
1708 #define BCE_NVM_CFG1_PROTECT_MODE (1L<<24)
1709 #define BCE_NVM_CFG1_FLASH_SIZE (1L<<25)
1710 #define BCE_NVM_CFG1_COMPAT_BYPASSS (1L<<31)
1712 #define BCE_NVM_CFG2 0x00006418
1713 #define BCE_NVM_CFG2_ERASE_CMD (0xffL<<0)
1714 #define BCE_NVM_CFG2_DUMMY (0xffL<<8)
1715 #define BCE_NVM_CFG2_STATUS_CMD (0xffL<<16)
1717 #define BCE_NVM_CFG3 0x0000641c
1718 #define BCE_NVM_CFG3_BUFFER_RD_CMD (0xffL<<0)
1719 #define BCE_NVM_CFG3_WRITE_CMD (0xffL<<8)
1720 #define BCE_NVM_CFG3_BUFFER_WRITE_CMD (0xffL<<16)
1721 #define BCE_NVM_CFG3_READ_CMD (0xffL<<24)
1723 #define BCE_NVM_SW_ARB 0x00006420
1724 #define BCE_NVM_SW_ARB_ARB_REQ_SET0 (1L<<0)
1725 #define BCE_NVM_SW_ARB_ARB_REQ_SET1 (1L<<1)
1726 #define BCE_NVM_SW_ARB_ARB_REQ_SET2 (1L<<2)
1727 #define BCE_NVM_SW_ARB_ARB_REQ_SET3 (1L<<3)
1728 #define BCE_NVM_SW_ARB_ARB_REQ_CLR0 (1L<<4)
1729 #define BCE_NVM_SW_ARB_ARB_REQ_CLR1 (1L<<5)
1730 #define BCE_NVM_SW_ARB_ARB_REQ_CLR2 (1L<<6)
1731 #define BCE_NVM_SW_ARB_ARB_REQ_CLR3 (1L<<7)
1732 #define BCE_NVM_SW_ARB_ARB_ARB0 (1L<<8)
1733 #define BCE_NVM_SW_ARB_ARB_ARB1 (1L<<9)
1734 #define BCE_NVM_SW_ARB_ARB_ARB2 (1L<<10)
1735 #define BCE_NVM_SW_ARB_ARB_ARB3 (1L<<11)
1736 #define BCE_NVM_SW_ARB_REQ0 (1L<<12)
1737 #define BCE_NVM_SW_ARB_REQ1 (1L<<13)
1738 #define BCE_NVM_SW_ARB_REQ2 (1L<<14)
1739 #define BCE_NVM_SW_ARB_REQ3 (1L<<15)
1741 #define BCE_NVM_ACCESS_ENABLE 0x00006424
1742 #define BCE_NVM_ACCESS_ENABLE_EN (1L<<0)
1743 #define BCE_NVM_ACCESS_ENABLE_WR_EN (1L<<1)
1745 #define BCE_NVM_WRITE1 0x00006428
1746 #define BCE_NVM_WRITE1_WREN_CMD (0xffL<<0)
1747 #define BCE_NVM_WRITE1_WRDI_CMD (0xffL<<8)
1748 #define BCE_NVM_WRITE1_SR_DATA (0xffL<<16)
1753 * dma_reg definition
1756 #define BCE_DMA_COMMAND 0x00000c00
1757 #define BCE_DMA_COMMAND_ENABLE (1L<<0)
1759 #define BCE_DMA_STATUS 0x00000c04
1760 #define BCE_DMA_STATUS_PAR_ERROR_STATE (1L<<0)
1761 #define BCE_DMA_STATUS_READ_TRANSFERS_STAT (1L<<16)
1762 #define BCE_DMA_STATUS_READ_DELAY_PCI_CLKS_STAT (1L<<17)
1763 #define BCE_DMA_STATUS_BIG_READ_TRANSFERS_STAT (1L<<18)
1764 #define BCE_DMA_STATUS_BIG_READ_DELAY_PCI_CLKS_STAT (1L<<19)
1765 #define BCE_DMA_STATUS_BIG_READ_RETRY_AFTER_DATA_STAT (1L<<20)
1766 #define BCE_DMA_STATUS_WRITE_TRANSFERS_STAT (1L<<21)
1767 #define BCE_DMA_STATUS_WRITE_DELAY_PCI_CLKS_STAT (1L<<22)
1768 #define BCE_DMA_STATUS_BIG_WRITE_TRANSFERS_STAT (1L<<23)
1769 #define BCE_DMA_STATUS_BIG_WRITE_DELAY_PCI_CLKS_STAT (1L<<24)
1770 #define BCE_DMA_STATUS_BIG_WRITE_RETRY_AFTER_DATA_STAT (1L<<25)
1772 #define BCE_DMA_CONFIG 0x00000c08
1773 #define BCE_DMA_CONFIG_DATA_BYTE_SWAP (1L<<0)
1774 #define BCE_DMA_CONFIG_DATA_WORD_SWAP (1L<<1)
1775 #define BCE_DMA_CONFIG_CNTL_BYTE_SWAP (1L<<4)
1776 #define BCE_DMA_CONFIG_CNTL_WORD_SWAP (1L<<5)
1777 #define BCE_DMA_CONFIG_ONE_DMA (1L<<6)
1778 #define BCE_DMA_CONFIG_CNTL_TWO_DMA (1L<<7)
1779 #define BCE_DMA_CONFIG_CNTL_FPGA_MODE (1L<<8)
1780 #define BCE_DMA_CONFIG_CNTL_PING_PONG_DMA (1L<<10)
1781 #define BCE_DMA_CONFIG_CNTL_PCI_COMP_DLY (1L<<11)
1782 #define BCE_DMA_CONFIG_NO_RCHANS_IN_USE (0xfL<<12)
1783 #define BCE_DMA_CONFIG_NO_WCHANS_IN_USE (0xfL<<16)
1784 #define BCE_DMA_CONFIG_PCI_CLK_CMP_BITS (0x7L<<20)
1785 #define BCE_DMA_CONFIG_PCI_FAST_CLK_CMP (1L<<23)
1786 #define BCE_DMA_CONFIG_BIG_SIZE (0xfL<<24)
1787 #define BCE_DMA_CONFIG_BIG_SIZE_NONE (0x0L<<24)
1788 #define BCE_DMA_CONFIG_BIG_SIZE_64 (0x1L<<24)
1789 #define BCE_DMA_CONFIG_BIG_SIZE_128 (0x2L<<24)
1790 #define BCE_DMA_CONFIG_BIG_SIZE_256 (0x4L<<24)
1791 #define BCE_DMA_CONFIG_BIG_SIZE_512 (0x8L<<24)
1793 #define BCE_DMA_BLACKOUT 0x00000c0c
1794 #define BCE_DMA_BLACKOUT_RD_RETRY_BLACKOUT (0xffL<<0)
1795 #define BCE_DMA_BLACKOUT_2ND_RD_RETRY_BLACKOUT (0xffL<<8)
1796 #define BCE_DMA_BLACKOUT_WR_RETRY_BLACKOUT (0xffL<<16)
1798 #define BCE_DMA_RCHAN_STAT 0x00000c30
1799 #define BCE_DMA_RCHAN_STAT_COMP_CODE_0 (0x7L<<0)
1800 #define BCE_DMA_RCHAN_STAT_PAR_ERR_0 (1L<<3)
1801 #define BCE_DMA_RCHAN_STAT_COMP_CODE_1 (0x7L<<4)
1802 #define BCE_DMA_RCHAN_STAT_PAR_ERR_1 (1L<<7)
1803 #define BCE_DMA_RCHAN_STAT_COMP_CODE_2 (0x7L<<8)
1804 #define BCE_DMA_RCHAN_STAT_PAR_ERR_2 (1L<<11)
1805 #define BCE_DMA_RCHAN_STAT_COMP_CODE_3 (0x7L<<12)
1806 #define BCE_DMA_RCHAN_STAT_PAR_ERR_3 (1L<<15)
1807 #define BCE_DMA_RCHAN_STAT_COMP_CODE_4 (0x7L<<16)
1808 #define BCE_DMA_RCHAN_STAT_PAR_ERR_4 (1L<<19)
1809 #define BCE_DMA_RCHAN_STAT_COMP_CODE_5 (0x7L<<20)
1810 #define BCE_DMA_RCHAN_STAT_PAR_ERR_5 (1L<<23)
1811 #define BCE_DMA_RCHAN_STAT_COMP_CODE_6 (0x7L<<24)
1812 #define BCE_DMA_RCHAN_STAT_PAR_ERR_6 (1L<<27)
1813 #define BCE_DMA_RCHAN_STAT_COMP_CODE_7 (0x7L<<28)
1814 #define BCE_DMA_RCHAN_STAT_PAR_ERR_7 (1L<<31)
1816 #define BCE_DMA_WCHAN_STAT 0x00000c34
1817 #define BCE_DMA_WCHAN_STAT_COMP_CODE_0 (0x7L<<0)
1818 #define BCE_DMA_WCHAN_STAT_PAR_ERR_0 (1L<<3)
1819 #define BCE_DMA_WCHAN_STAT_COMP_CODE_1 (0x7L<<4)
1820 #define BCE_DMA_WCHAN_STAT_PAR_ERR_1 (1L<<7)
1821 #define BCE_DMA_WCHAN_STAT_COMP_CODE_2 (0x7L<<8)
1822 #define BCE_DMA_WCHAN_STAT_PAR_ERR_2 (1L<<11)
1823 #define BCE_DMA_WCHAN_STAT_COMP_CODE_3 (0x7L<<12)
1824 #define BCE_DMA_WCHAN_STAT_PAR_ERR_3 (1L<<15)
1825 #define BCE_DMA_WCHAN_STAT_COMP_CODE_4 (0x7L<<16)
1826 #define BCE_DMA_WCHAN_STAT_PAR_ERR_4 (1L<<19)
1827 #define BCE_DMA_WCHAN_STAT_COMP_CODE_5 (0x7L<<20)
1828 #define BCE_DMA_WCHAN_STAT_PAR_ERR_5 (1L<<23)
1829 #define BCE_DMA_WCHAN_STAT_COMP_CODE_6 (0x7L<<24)
1830 #define BCE_DMA_WCHAN_STAT_PAR_ERR_6 (1L<<27)
1831 #define BCE_DMA_WCHAN_STAT_COMP_CODE_7 (0x7L<<28)
1832 #define BCE_DMA_WCHAN_STAT_PAR_ERR_7 (1L<<31)
1834 #define BCE_DMA_RCHAN_ASSIGNMENT 0x00000c38
1835 #define BCE_DMA_RCHAN_ASSIGNMENT_0 (0xfL<<0)
1836 #define BCE_DMA_RCHAN_ASSIGNMENT_1 (0xfL<<4)
1837 #define BCE_DMA_RCHAN_ASSIGNMENT_2 (0xfL<<8)
1838 #define BCE_DMA_RCHAN_ASSIGNMENT_3 (0xfL<<12)
1839 #define BCE_DMA_RCHAN_ASSIGNMENT_4 (0xfL<<16)
1840 #define BCE_DMA_RCHAN_ASSIGNMENT_5 (0xfL<<20)
1841 #define BCE_DMA_RCHAN_ASSIGNMENT_6 (0xfL<<24)
1842 #define BCE_DMA_RCHAN_ASSIGNMENT_7 (0xfL<<28)
1844 #define BCE_DMA_WCHAN_ASSIGNMENT 0x00000c3c
1845 #define BCE_DMA_WCHAN_ASSIGNMENT_0 (0xfL<<0)
1846 #define BCE_DMA_WCHAN_ASSIGNMENT_1 (0xfL<<4)
1847 #define BCE_DMA_WCHAN_ASSIGNMENT_2 (0xfL<<8)
1848 #define BCE_DMA_WCHAN_ASSIGNMENT_3 (0xfL<<12)
1849 #define BCE_DMA_WCHAN_ASSIGNMENT_4 (0xfL<<16)
1850 #define BCE_DMA_WCHAN_ASSIGNMENT_5 (0xfL<<20)
1851 #define BCE_DMA_WCHAN_ASSIGNMENT_6 (0xfL<<24)
1852 #define BCE_DMA_WCHAN_ASSIGNMENT_7 (0xfL<<28)
1854 #define BCE_DMA_RCHAN_STAT_00 0x00000c40
1855 #define BCE_DMA_RCHAN_STAT_00_RCHAN_STA_HOST_ADDR_LOW (0xffffffffL<<0)
1857 #define BCE_DMA_RCHAN_STAT_01 0x00000c44
1858 #define BCE_DMA_RCHAN_STAT_01_RCHAN_STA_HOST_ADDR_HIGH (0xffffffffL<<0)
1860 #define BCE_DMA_RCHAN_STAT_02 0x00000c48
1861 #define BCE_DMA_RCHAN_STAT_02_LENGTH (0xffffL<<0)
1862 #define BCE_DMA_RCHAN_STAT_02_WORD_SWAP (1L<<16)
1863 #define BCE_DMA_RCHAN_STAT_02_BYTE_SWAP (1L<<17)
1864 #define BCE_DMA_RCHAN_STAT_02_PRIORITY_LVL (1L<<18)
1866 #define BCE_DMA_RCHAN_STAT_10 0x00000c4c
1867 #define BCE_DMA_RCHAN_STAT_11 0x00000c50
1868 #define BCE_DMA_RCHAN_STAT_12 0x00000c54
1869 #define BCE_DMA_RCHAN_STAT_20 0x00000c58
1870 #define BCE_DMA_RCHAN_STAT_21 0x00000c5c
1871 #define BCE_DMA_RCHAN_STAT_22 0x00000c60
1872 #define BCE_DMA_RCHAN_STAT_30 0x00000c64
1873 #define BCE_DMA_RCHAN_STAT_31 0x00000c68
1874 #define BCE_DMA_RCHAN_STAT_32 0x00000c6c
1875 #define BCE_DMA_RCHAN_STAT_40 0x00000c70
1876 #define BCE_DMA_RCHAN_STAT_41 0x00000c74
1877 #define BCE_DMA_RCHAN_STAT_42 0x00000c78
1878 #define BCE_DMA_RCHAN_STAT_50 0x00000c7c
1879 #define BCE_DMA_RCHAN_STAT_51 0x00000c80
1880 #define BCE_DMA_RCHAN_STAT_52 0x00000c84
1881 #define BCE_DMA_RCHAN_STAT_60 0x00000c88
1882 #define BCE_DMA_RCHAN_STAT_61 0x00000c8c
1883 #define BCE_DMA_RCHAN_STAT_62 0x00000c90
1884 #define BCE_DMA_RCHAN_STAT_70 0x00000c94
1885 #define BCE_DMA_RCHAN_STAT_71 0x00000c98
1886 #define BCE_DMA_RCHAN_STAT_72 0x00000c9c
1887 #define BCE_DMA_WCHAN_STAT_00 0x00000ca0
1888 #define BCE_DMA_WCHAN_STAT_00_WCHAN_STA_HOST_ADDR_LOW (0xffffffffL<<0)
1890 #define BCE_DMA_WCHAN_STAT_01 0x00000ca4
1891 #define BCE_DMA_WCHAN_STAT_01_WCHAN_STA_HOST_ADDR_HIGH (0xffffffffL<<0)
1893 #define BCE_DMA_WCHAN_STAT_02 0x00000ca8
1894 #define BCE_DMA_WCHAN_STAT_02_LENGTH (0xffffL<<0)
1895 #define BCE_DMA_WCHAN_STAT_02_WORD_SWAP (1L<<16)
1896 #define BCE_DMA_WCHAN_STAT_02_BYTE_SWAP (1L<<17)
1897 #define BCE_DMA_WCHAN_STAT_02_PRIORITY_LVL (1L<<18)
1899 #define BCE_DMA_WCHAN_STAT_10 0x00000cac
1900 #define BCE_DMA_WCHAN_STAT_11 0x00000cb0
1901 #define BCE_DMA_WCHAN_STAT_12 0x00000cb4
1902 #define BCE_DMA_WCHAN_STAT_20 0x00000cb8
1903 #define BCE_DMA_WCHAN_STAT_21 0x00000cbc
1904 #define BCE_DMA_WCHAN_STAT_22 0x00000cc0
1905 #define BCE_DMA_WCHAN_STAT_30 0x00000cc4
1906 #define BCE_DMA_WCHAN_STAT_31 0x00000cc8
1907 #define BCE_DMA_WCHAN_STAT_32 0x00000ccc
1908 #define BCE_DMA_WCHAN_STAT_40 0x00000cd0
1909 #define BCE_DMA_WCHAN_STAT_41 0x00000cd4
1910 #define BCE_DMA_WCHAN_STAT_42 0x00000cd8
1911 #define BCE_DMA_WCHAN_STAT_50 0x00000cdc
1912 #define BCE_DMA_WCHAN_STAT_51 0x00000ce0
1913 #define BCE_DMA_WCHAN_STAT_52 0x00000ce4
1914 #define BCE_DMA_WCHAN_STAT_60 0x00000ce8
1915 #define BCE_DMA_WCHAN_STAT_61 0x00000cec
1916 #define BCE_DMA_WCHAN_STAT_62 0x00000cf0
1917 #define BCE_DMA_WCHAN_STAT_70 0x00000cf4
1918 #define BCE_DMA_WCHAN_STAT_71 0x00000cf8
1919 #define BCE_DMA_WCHAN_STAT_72 0x00000cfc
1920 #define BCE_DMA_ARB_STAT_00 0x00000d00
1921 #define BCE_DMA_ARB_STAT_00_MASTER (0xffffL<<0)
1922 #define BCE_DMA_ARB_STAT_00_MASTER_ENC (0xffL<<16)
1923 #define BCE_DMA_ARB_STAT_00_CUR_BINMSTR (0xffL<<24)
1925 #define BCE_DMA_ARB_STAT_01 0x00000d04
1926 #define BCE_DMA_ARB_STAT_01_LPR_RPTR (0xfL<<0)
1927 #define BCE_DMA_ARB_STAT_01_LPR_WPTR (0xfL<<4)
1928 #define BCE_DMA_ARB_STAT_01_LPB_RPTR (0xfL<<8)
1929 #define BCE_DMA_ARB_STAT_01_LPB_WPTR (0xfL<<12)
1930 #define BCE_DMA_ARB_STAT_01_HPR_RPTR (0xfL<<16)
1931 #define BCE_DMA_ARB_STAT_01_HPR_WPTR (0xfL<<20)
1932 #define BCE_DMA_ARB_STAT_01_HPB_RPTR (0xfL<<24)
1933 #define BCE_DMA_ARB_STAT_01_HPB_WPTR (0xfL<<28)
1935 #define BCE_DMA_FUSE_CTRL0_CMD 0x00000f00
1936 #define BCE_DMA_FUSE_CTRL0_CMD_PWRUP_DONE (1L<<0)
1937 #define BCE_DMA_FUSE_CTRL0_CMD_SHIFT_DONE (1L<<1)
1938 #define BCE_DMA_FUSE_CTRL0_CMD_SHIFT (1L<<2)
1939 #define BCE_DMA_FUSE_CTRL0_CMD_LOAD (1L<<3)
1940 #define BCE_DMA_FUSE_CTRL0_CMD_SEL (0xfL<<8)
1942 #define BCE_DMA_FUSE_CTRL0_DATA 0x00000f04
1943 #define BCE_DMA_FUSE_CTRL1_CMD 0x00000f08
1944 #define BCE_DMA_FUSE_CTRL1_CMD_PWRUP_DONE (1L<<0)
1945 #define BCE_DMA_FUSE_CTRL1_CMD_SHIFT_DONE (1L<<1)
1946 #define BCE_DMA_FUSE_CTRL1_CMD_SHIFT (1L<<2)
1947 #define BCE_DMA_FUSE_CTRL1_CMD_LOAD (1L<<3)
1948 #define BCE_DMA_FUSE_CTRL1_CMD_SEL (0xfL<<8)
1950 #define BCE_DMA_FUSE_CTRL1_DATA 0x00000f0c
1951 #define BCE_DMA_FUSE_CTRL2_CMD 0x00000f10
1952 #define BCE_DMA_FUSE_CTRL2_CMD_PWRUP_DONE (1L<<0)
1953 #define BCE_DMA_FUSE_CTRL2_CMD_SHIFT_DONE (1L<<1)
1954 #define BCE_DMA_FUSE_CTRL2_CMD_SHIFT (1L<<2)
1955 #define BCE_DMA_FUSE_CTRL2_CMD_LOAD (1L<<3)
1956 #define BCE_DMA_FUSE_CTRL2_CMD_SEL (0xfL<<8)
1958 #define BCE_DMA_FUSE_CTRL2_DATA 0x00000f14
1962 * context_reg definition
1965 #define BCE_CTX_COMMAND 0x00001000
1966 #define BCE_CTX_COMMAND_ENABLED (1L<<0)
1968 #define BCE_CTX_STATUS 0x00001004
1969 #define BCE_CTX_STATUS_LOCK_WAIT (1L<<0)
1970 #define BCE_CTX_STATUS_READ_STAT (1L<<16)
1971 #define BCE_CTX_STATUS_WRITE_STAT (1L<<17)
1972 #define BCE_CTX_STATUS_ACC_STALL_STAT (1L<<18)
1973 #define BCE_CTX_STATUS_LOCK_STALL_STAT (1L<<19)
1975 #define BCE_CTX_VIRT_ADDR 0x00001008
1976 #define BCE_CTX_VIRT_ADDR_VIRT_ADDR (0x7fffL<<6)
1978 #define BCE_CTX_PAGE_TBL 0x0000100c
1979 #define BCE_CTX_PAGE_TBL_PAGE_TBL (0x3fffL<<6)
1981 #define BCE_CTX_DATA_ADR 0x00001010
1982 #define BCE_CTX_DATA_ADR_DATA_ADR (0x7ffffL<<2)
1984 #define BCE_CTX_DATA 0x00001014
1985 #define BCE_CTX_LOCK 0x00001018
1986 #define BCE_CTX_LOCK_TYPE (0x7L<<0)
1987 #define BCE_CTX_LOCK_TYPE_LOCK_TYPE_VOID (0x0L<<0)
1988 #define BCE_CTX_LOCK_TYPE_LOCK_TYPE_COMPLETE (0x7L<<0)
1989 #define BCE_CTX_LOCK_TYPE_LOCK_TYPE_PROTOCOL (0x1L<<0)
1990 #define BCE_CTX_LOCK_TYPE_LOCK_TYPE_TX (0x2L<<0)
1991 #define BCE_CTX_LOCK_TYPE_LOCK_TYPE_TIMER (0x4L<<0)
1992 #define BCE_CTX_LOCK_CID_VALUE (0x3fffL<<7)
1993 #define BCE_CTX_LOCK_GRANTED (1L<<26)
1994 #define BCE_CTX_LOCK_MODE (0x7L<<27)
1995 #define BCE_CTX_LOCK_MODE_UNLOCK (0x0L<<27)
1996 #define BCE_CTX_LOCK_MODE_IMMEDIATE (0x1L<<27)
1997 #define BCE_CTX_LOCK_MODE_SURE (0x2L<<27)
1998 #define BCE_CTX_LOCK_STATUS (1L<<30)
1999 #define BCE_CTX_LOCK_REQ (1L<<31)
2001 #define BCE_CTX_ACCESS_STATUS 0x00001040
2002 #define BCE_CTX_ACCESS_STATUS_MASTERENCODED (0xfL<<0)
2003 #define BCE_CTX_ACCESS_STATUS_ACCESSMEMORYSM (0x3L<<10)
2004 #define BCE_CTX_ACCESS_STATUS_PAGETABLEINITSM (0x3L<<12)
2005 #define BCE_CTX_ACCESS_STATUS_ACCESSMEMORYINITSM (0x3L<<14)
2006 #define BCE_CTX_ACCESS_STATUS_QUALIFIED_REQUEST (0x7ffL<<17)
2008 #define BCE_CTX_DBG_LOCK_STATUS 0x00001044
2009 #define BCE_CTX_DBG_LOCK_STATUS_SM (0x3ffL<<0)
2010 #define BCE_CTX_DBG_LOCK_STATUS_MATCH (0x3ffL<<22)
2012 #define BCE_CTX_CHNL_LOCK_STATUS_0 0x00001080
2013 #define BCE_CTX_CHNL_LOCK_STATUS_0_CID (0x3fffL<<0)
2014 #define BCE_CTX_CHNL_LOCK_STATUS_0_TYPE (0x3L<<14)
2015 #define BCE_CTX_CHNL_LOCK_STATUS_0_MODE (1L<<16)
2017 #define BCE_CTX_CHNL_LOCK_STATUS_1 0x00001084
2018 #define BCE_CTX_CHNL_LOCK_STATUS_2 0x00001088
2019 #define BCE_CTX_CHNL_LOCK_STATUS_3 0x0000108c
2020 #define BCE_CTX_CHNL_LOCK_STATUS_4 0x00001090
2021 #define BCE_CTX_CHNL_LOCK_STATUS_5 0x00001094
2022 #define BCE_CTX_CHNL_LOCK_STATUS_6 0x00001098
2023 #define BCE_CTX_CHNL_LOCK_STATUS_7 0x0000109c
2024 #define BCE_CTX_CHNL_LOCK_STATUS_8 0x000010a0
2028 * emac_reg definition
2031 #define BCE_EMAC_MODE 0x00001400
2032 #define BCE_EMAC_MODE_RESET (1L<<0)
2033 #define BCE_EMAC_MODE_HALF_DUPLEX (1L<<1)
2034 #define BCE_EMAC_MODE_PORT (0x3L<<2)
2035 #define BCE_EMAC_MODE_PORT_NONE (0L<<2)
2036 #define BCE_EMAC_MODE_PORT_MII (1L<<2)
2037 #define BCE_EMAC_MODE_PORT_GMII (2L<<2)
2038 #define BCE_EMAC_MODE_PORT_MII_10 (3L<<2)
2039 #define BCE_EMAC_MODE_MAC_LOOP (1L<<4)
2040 #define BCE_EMAC_MODE_25G (1L<<5)
2041 #define BCE_EMAC_MODE_TAGGED_MAC_CTL (1L<<7)
2042 #define BCE_EMAC_MODE_TX_BURST (1L<<8)
2043 #define BCE_EMAC_MODE_MAX_DEFER_DROP_ENA (1L<<9)
2044 #define BCE_EMAC_MODE_EXT_LINK_POL (1L<<10)
2045 #define BCE_EMAC_MODE_FORCE_LINK (1L<<11)
2046 #define BCE_EMAC_MODE_MPKT (1L<<18)
2047 #define BCE_EMAC_MODE_MPKT_RCVD (1L<<19)
2048 #define BCE_EMAC_MODE_ACPI_RCVD (1L<<20)
2050 #define BCE_EMAC_STATUS 0x00001404
2051 #define BCE_EMAC_STATUS_LINK (1L<<11)
2052 #define BCE_EMAC_STATUS_LINK_CHANGE (1L<<12)
2053 #define BCE_EMAC_STATUS_MI_COMPLETE (1L<<22)
2054 #define BCE_EMAC_STATUS_MI_INT (1L<<23)
2055 #define BCE_EMAC_STATUS_AP_ERROR (1L<<24)
2056 #define BCE_EMAC_STATUS_PARITY_ERROR_STATE (1L<<31)
2058 #define BCE_EMAC_ATTENTION_ENA 0x00001408
2059 #define BCE_EMAC_ATTENTION_ENA_LINK (1L<<11)
2060 #define BCE_EMAC_ATTENTION_ENA_MI_COMPLETE (1L<<22)
2061 #define BCE_EMAC_ATTENTION_ENA_MI_INT (1L<<23)
2062 #define BCE_EMAC_ATTENTION_ENA_AP_ERROR (1L<<24)
2064 #define BCE_EMAC_LED 0x0000140c
2065 #define BCE_EMAC_LED_OVERRIDE (1L<<0)
2066 #define BCE_EMAC_LED_1000MB_OVERRIDE (1L<<1)
2067 #define BCE_EMAC_LED_100MB_OVERRIDE (1L<<2)
2068 #define BCE_EMAC_LED_10MB_OVERRIDE (1L<<3)
2069 #define BCE_EMAC_LED_TRAFFIC_OVERRIDE (1L<<4)
2070 #define BCE_EMAC_LED_BLNK_TRAFFIC (1L<<5)
2071 #define BCE_EMAC_LED_TRAFFIC (1L<<6)
2072 #define BCE_EMAC_LED_1000MB (1L<<7)
2073 #define BCE_EMAC_LED_100MB (1L<<8)
2074 #define BCE_EMAC_LED_10MB (1L<<9)
2075 #define BCE_EMAC_LED_TRAFFIC_STAT (1L<<10)
2076 #define BCE_EMAC_LED_BLNK_RATE (0xfffL<<19)
2077 #define BCE_EMAC_LED_BLNK_RATE_ENA (1L<<31)
2079 #define BCE_EMAC_MAC_MATCH0 0x00001410
2080 #define BCE_EMAC_MAC_MATCH1 0x00001414
2081 #define BCE_EMAC_MAC_MATCH2 0x00001418
2082 #define BCE_EMAC_MAC_MATCH3 0x0000141c
2083 #define BCE_EMAC_MAC_MATCH4 0x00001420
2084 #define BCE_EMAC_MAC_MATCH5 0x00001424
2085 #define BCE_EMAC_MAC_MATCH6 0x00001428
2086 #define BCE_EMAC_MAC_MATCH7 0x0000142c
2087 #define BCE_EMAC_MAC_MATCH8 0x00001430
2088 #define BCE_EMAC_MAC_MATCH9 0x00001434
2089 #define BCE_EMAC_MAC_MATCH10 0x00001438
2090 #define BCE_EMAC_MAC_MATCH11 0x0000143c
2091 #define BCE_EMAC_MAC_MATCH12 0x00001440
2092 #define BCE_EMAC_MAC_MATCH13 0x00001444
2093 #define BCE_EMAC_MAC_MATCH14 0x00001448
2094 #define BCE_EMAC_MAC_MATCH15 0x0000144c
2095 #define BCE_EMAC_MAC_MATCH16 0x00001450
2096 #define BCE_EMAC_MAC_MATCH17 0x00001454
2097 #define BCE_EMAC_MAC_MATCH18 0x00001458
2098 #define BCE_EMAC_MAC_MATCH19 0x0000145c
2099 #define BCE_EMAC_MAC_MATCH20 0x00001460
2100 #define BCE_EMAC_MAC_MATCH21 0x00001464
2101 #define BCE_EMAC_MAC_MATCH22 0x00001468
2102 #define BCE_EMAC_MAC_MATCH23 0x0000146c
2103 #define BCE_EMAC_MAC_MATCH24 0x00001470
2104 #define BCE_EMAC_MAC_MATCH25 0x00001474
2105 #define BCE_EMAC_MAC_MATCH26 0x00001478
2106 #define BCE_EMAC_MAC_MATCH27 0x0000147c
2107 #define BCE_EMAC_MAC_MATCH28 0x00001480
2108 #define BCE_EMAC_MAC_MATCH29 0x00001484
2109 #define BCE_EMAC_MAC_MATCH30 0x00001488
2110 #define BCE_EMAC_MAC_MATCH31 0x0000148c
2111 #define BCE_EMAC_BACKOFF_SEED 0x00001498
2112 #define BCE_EMAC_BACKOFF_SEED_EMAC_BACKOFF_SEED (0x3ffL<<0)
2114 #define BCE_EMAC_RX_MTU_SIZE 0x0000149c
2115 #define BCE_EMAC_RX_MTU_SIZE_MTU_SIZE (0xffffL<<0)
2116 #define BCE_EMAC_RX_MTU_SIZE_JUMBO_ENA (1L<<31)
2118 #define BCE_EMAC_SERDES_CNTL 0x000014a4
2119 #define BCE_EMAC_SERDES_CNTL_RXR (0x7L<<0)
2120 #define BCE_EMAC_SERDES_CNTL_RXG (0x3L<<3)
2121 #define BCE_EMAC_SERDES_CNTL_RXCKSEL (1L<<6)
2122 #define BCE_EMAC_SERDES_CNTL_TXBIAS (0x7L<<7)
2123 #define BCE_EMAC_SERDES_CNTL_BGMAX (1L<<10)
2124 #define BCE_EMAC_SERDES_CNTL_BGMIN (1L<<11)
2125 #define BCE_EMAC_SERDES_CNTL_TXMODE (1L<<12)
2126 #define BCE_EMAC_SERDES_CNTL_TXEDGE (1L<<13)
2127 #define BCE_EMAC_SERDES_CNTL_SERDES_MODE (1L<<14)
2128 #define BCE_EMAC_SERDES_CNTL_PLLTEST (1L<<15)
2129 #define BCE_EMAC_SERDES_CNTL_CDET_EN (1L<<16)
2130 #define BCE_EMAC_SERDES_CNTL_TBI_LBK (1L<<17)
2131 #define BCE_EMAC_SERDES_CNTL_REMOTE_LBK (1L<<18)
2132 #define BCE_EMAC_SERDES_CNTL_REV_PHASE (1L<<19)
2133 #define BCE_EMAC_SERDES_CNTL_REGCTL12 (0x3L<<20)
2134 #define BCE_EMAC_SERDES_CNTL_REGCTL25 (0x3L<<22)
2136 #define BCE_EMAC_SERDES_STATUS 0x000014a8
2137 #define BCE_EMAC_SERDES_STATUS_RX_STAT (0xffL<<0)
2138 #define BCE_EMAC_SERDES_STATUS_COMMA_DET (1L<<8)
2140 #define BCE_EMAC_MDIO_COMM 0x000014ac
2141 #define BCE_EMAC_MDIO_COMM_DATA (0xffffL<<0)
2142 #define BCE_EMAC_MDIO_COMM_REG_ADDR (0x1fL<<16)
2143 #define BCE_EMAC_MDIO_COMM_PHY_ADDR (0x1fL<<21)
2144 #define BCE_EMAC_MDIO_COMM_COMMAND (0x3L<<26)
2145 #define BCE_EMAC_MDIO_COMM_COMMAND_UNDEFINED_0 (0L<<26)
2146 #define BCE_EMAC_MDIO_COMM_COMMAND_WRITE (1L<<26)
2147 #define BCE_EMAC_MDIO_COMM_COMMAND_READ (2L<<26)
2148 #define BCE_EMAC_MDIO_COMM_COMMAND_UNDEFINED_3 (3L<<26)
2149 #define BCE_EMAC_MDIO_COMM_FAIL (1L<<28)
2150 #define BCE_EMAC_MDIO_COMM_START_BUSY (1L<<29)
2151 #define BCE_EMAC_MDIO_COMM_DISEXT (1L<<30)
2153 #define BCE_EMAC_MDIO_STATUS 0x000014b0
2154 #define BCE_EMAC_MDIO_STATUS_LINK (1L<<0)
2155 #define BCE_EMAC_MDIO_STATUS_10MB (1L<<1)
2157 #define BCE_EMAC_MDIO_MODE 0x000014b4
2158 #define BCE_EMAC_MDIO_MODE_SHORT_PREAMBLE (1L<<1)
2159 #define BCE_EMAC_MDIO_MODE_AUTO_POLL (1L<<4)
2160 #define BCE_EMAC_MDIO_MODE_BIT_BANG (1L<<8)
2161 #define BCE_EMAC_MDIO_MODE_MDIO (1L<<9)
2162 #define BCE_EMAC_MDIO_MODE_MDIO_OE (1L<<10)
2163 #define BCE_EMAC_MDIO_MODE_MDC (1L<<11)
2164 #define BCE_EMAC_MDIO_MODE_MDINT (1L<<12)
2165 #define BCE_EMAC_MDIO_MODE_CLOCK_CNT (0x1fL<<16)
2167 #define BCE_EMAC_MDIO_AUTO_STATUS 0x000014b8
2168 #define BCE_EMAC_MDIO_AUTO_STATUS_AUTO_ERR (1L<<0)
2170 #define BCE_EMAC_TX_MODE 0x000014bc
2171 #define BCE_EMAC_TX_MODE_RESET (1L<<0)
2172 #define BCE_EMAC_TX_MODE_EXT_PAUSE_EN (1L<<3)
2173 #define BCE_EMAC_TX_MODE_FLOW_EN (1L<<4)
2174 #define BCE_EMAC_TX_MODE_BIG_BACKOFF (1L<<5)
2175 #define BCE_EMAC_TX_MODE_LONG_PAUSE (1L<<6)
2176 #define BCE_EMAC_TX_MODE_LINK_AWARE (1L<<7)
2178 #define BCE_EMAC_TX_STATUS 0x000014c0
2179 #define BCE_EMAC_TX_STATUS_XOFFED (1L<<0)
2180 #define BCE_EMAC_TX_STATUS_XOFF_SENT (1L<<1)
2181 #define BCE_EMAC_TX_STATUS_XON_SENT (1L<<2)
2182 #define BCE_EMAC_TX_STATUS_LINK_UP (1L<<3)
2183 #define BCE_EMAC_TX_STATUS_UNDERRUN (1L<<4)
2185 #define BCE_EMAC_TX_LENGTHS 0x000014c4
2186 #define BCE_EMAC_TX_LENGTHS_SLOT (0xffL<<0)
2187 #define BCE_EMAC_TX_LENGTHS_IPG (0xfL<<8)
2188 #define BCE_EMAC_TX_LENGTHS_IPG_CRS (0x3L<<12)
2190 #define BCE_EMAC_RX_MODE 0x000014c8
2191 #define BCE_EMAC_RX_MODE_RESET (1L<<0)
2192 #define BCE_EMAC_RX_MODE_FLOW_EN (1L<<2)
2193 #define BCE_EMAC_RX_MODE_KEEP_MAC_CONTROL (1L<<3)
2194 #define BCE_EMAC_RX_MODE_KEEP_PAUSE (1L<<4)
2195 #define BCE_EMAC_RX_MODE_ACCEPT_OVERSIZE (1L<<5)
2196 #define BCE_EMAC_RX_MODE_ACCEPT_RUNTS (1L<<6)
2197 #define BCE_EMAC_RX_MODE_LLC_CHK (1L<<7)
2198 #define BCE_EMAC_RX_MODE_PROMISCUOUS (1L<<8)
2199 #define BCE_EMAC_RX_MODE_NO_CRC_CHK (1L<<9)
2200 #define BCE_EMAC_RX_MODE_KEEP_VLAN_TAG (1L<<10)
2201 #define BCE_EMAC_RX_MODE_FILT_BROADCAST (1L<<11)
2202 #define BCE_EMAC_RX_MODE_SORT_MODE (1L<<12)
2204 #define BCE_EMAC_RX_STATUS 0x000014cc
2205 #define BCE_EMAC_RX_STATUS_FFED (1L<<0)
2206 #define BCE_EMAC_RX_STATUS_FF_RECEIVED (1L<<1)
2207 #define BCE_EMAC_RX_STATUS_N_RECEIVED (1L<<2)
2209 #define BCE_EMAC_MULTICAST_HASH0 0x000014d0
2210 #define BCE_EMAC_MULTICAST_HASH1 0x000014d4
2211 #define BCE_EMAC_MULTICAST_HASH2 0x000014d8
2212 #define BCE_EMAC_MULTICAST_HASH3 0x000014dc
2213 #define BCE_EMAC_MULTICAST_HASH4 0x000014e0
2214 #define BCE_EMAC_MULTICAST_HASH5 0x000014e4
2215 #define BCE_EMAC_MULTICAST_HASH6 0x000014e8
2216 #define BCE_EMAC_MULTICAST_HASH7 0x000014ec
2217 #define BCE_EMAC_RX_STAT_IFHCINOCTETS 0x00001500
2218 #define BCE_EMAC_RX_STAT_IFHCINBADOCTETS 0x00001504
2219 #define BCE_EMAC_RX_STAT_ETHERSTATSFRAGMENTS 0x00001508
2220 #define BCE_EMAC_RX_STAT_IFHCINUCASTPKTS 0x0000150c
2221 #define BCE_EMAC_RX_STAT_IFHCINMULTICASTPKTS 0x00001510
2222 #define BCE_EMAC_RX_STAT_IFHCINBROADCASTPKTS 0x00001514
2223 #define BCE_EMAC_RX_STAT_DOT3STATSFCSERRORS 0x00001518
2224 #define BCE_EMAC_RX_STAT_DOT3STATSALIGNMENTERRORS 0x0000151c
2225 #define BCE_EMAC_RX_STAT_DOT3STATSCARRIERSENSEERRORS 0x00001520
2226 #define BCE_EMAC_RX_STAT_XONPAUSEFRAMESRECEIVED 0x00001524
2227 #define BCE_EMAC_RX_STAT_XOFFPAUSEFRAMESRECEIVED 0x00001528
2228 #define BCE_EMAC_RX_STAT_MACCONTROLFRAMESRECEIVED 0x0000152c
2229 #define BCE_EMAC_RX_STAT_XOFFSTATEENTERED 0x00001530
2230 #define BCE_EMAC_RX_STAT_DOT3STATSFRAMESTOOLONG 0x00001534
2231 #define BCE_EMAC_RX_STAT_ETHERSTATSJABBERS 0x00001538
2232 #define BCE_EMAC_RX_STAT_ETHERSTATSUNDERSIZEPKTS 0x0000153c
2233 #define BCE_EMAC_RX_STAT_ETHERSTATSPKTS64OCTETS 0x00001540
2234 #define BCE_EMAC_RX_STAT_ETHERSTATSPKTS65OCTETSTO127OCTETS 0x00001544
2235 #define BCE_EMAC_RX_STAT_ETHERSTATSPKTS128OCTETSTO255OCTETS 0x00001548
2236 #define BCE_EMAC_RX_STAT_ETHERSTATSPKTS256OCTETSTO511OCTETS 0x0000154c
2237 #define BCE_EMAC_RX_STAT_ETHERSTATSPKTS512OCTETSTO1023OCTETS 0x00001550
2238 #define BCE_EMAC_RX_STAT_ETHERSTATSPKTS1024OCTETSTO1522OCTETS 0x00001554
2239 #define BCE_EMAC_RX_STAT_ETHERSTATSPKTS1523OCTETSTO9022OCTETS 0x00001558
2240 #define BCE_EMAC_RXMAC_DEBUG0 0x0000155c
2241 #define BCE_EMAC_RXMAC_DEBUG1 0x00001560
2242 #define BCE_EMAC_RXMAC_DEBUG1_LENGTH_NE_BYTE_COUNT (1L<<0)
2243 #define BCE_EMAC_RXMAC_DEBUG1_LENGTH_OUT_RANGE (1L<<1)
2244 #define BCE_EMAC_RXMAC_DEBUG1_BAD_CRC (1L<<2)
2245 #define BCE_EMAC_RXMAC_DEBUG1_RX_ERROR (1L<<3)
2246 #define BCE_EMAC_RXMAC_DEBUG1_ALIGN_ERROR (1L<<4)
2247 #define BCE_EMAC_RXMAC_DEBUG1_LAST_DATA (1L<<5)
2248 #define BCE_EMAC_RXMAC_DEBUG1_ODD_BYTE_START (1L<<6)
2249 #define BCE_EMAC_RXMAC_DEBUG1_BYTE_COUNT (0xffffL<<7)
2250 #define BCE_EMAC_RXMAC_DEBUG1_SLOT_TIME (0xffL<<23)
2252 #define BCE_EMAC_RXMAC_DEBUG2 0x00001564
2253 #define BCE_EMAC_RXMAC_DEBUG2_SM_STATE (0x7L<<0)
2254 #define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_IDLE (0x0L<<0)
2255 #define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_SFD (0x1L<<0)
2256 #define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_DATA (0x2L<<0)
2257 #define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_SKEEP (0x3L<<0)
2258 #define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_EXT (0x4L<<0)
2259 #define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_DROP (0x5L<<0)
2260 #define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_SDROP (0x6L<<0)
2261 #define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_FC (0x7L<<0)
2262 #define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE (0xfL<<3)
2263 #define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_IDLE (0x0L<<3)
2264 #define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA0 (0x1L<<3)
2265 #define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA1 (0x2L<<3)
2266 #define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA2 (0x3L<<3)
2267 #define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA3 (0x4L<<3)
2268 #define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_ABORT (0x5L<<3)
2269 #define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_WAIT (0x6L<<3)
2270 #define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_STATUS (0x7L<<3)
2271 #define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_LAST (0x8L<<3)
2272 #define BCE_EMAC_RXMAC_DEBUG2_BYTE_IN (0xffL<<7)
2273 #define BCE_EMAC_RXMAC_DEBUG2_FALSEC (1L<<15)
2274 #define BCE_EMAC_RXMAC_DEBUG2_TAGGED (1L<<16)
2275 #define BCE_EMAC_RXMAC_DEBUG2_PAUSE_STATE (1L<<18)
2276 #define BCE_EMAC_RXMAC_DEBUG2_PAUSE_STATE_IDLE (0L<<18)
2277 #define BCE_EMAC_RXMAC_DEBUG2_PAUSE_STATE_PAUSED (1L<<18)
2278 #define BCE_EMAC_RXMAC_DEBUG2_SE_COUNTER (0xfL<<19)
2279 #define BCE_EMAC_RXMAC_DEBUG2_QUANTA (0x1fL<<23)
2281 #define BCE_EMAC_RXMAC_DEBUG3 0x00001568
2282 #define BCE_EMAC_RXMAC_DEBUG3_PAUSE_CTR (0xffffL<<0)
2283 #define BCE_EMAC_RXMAC_DEBUG3_TMP_PAUSE_CTR (0xffffL<<16)
2285 #define BCE_EMAC_RXMAC_DEBUG4 0x0000156c
2286 #define BCE_EMAC_RXMAC_DEBUG4_TYPE_FIELD (0xffffL<<0)
2287 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE (0x3fL<<16)
2288 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_IDLE (0x0L<<16)
2289 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC2 (0x1L<<16)
2290 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC3 (0x2L<<16)
2291 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_UNI (0x3L<<16)
2292 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC2 (0x7L<<16)
2293 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC3 (0x5L<<16)
2294 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA1 (0x6L<<16)
2295 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA2 (0x7L<<16)
2296 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA3 (0x8L<<16)
2297 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MC2 (0x9L<<16)
2298 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MC3 (0xaL<<16)
2299 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MWAIT1 (0xeL<<16)
2300 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MWAIT2 (0xfL<<16)
2301 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MCHECK (0x10L<<16)
2302 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MC (0x11L<<16)
2303 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_BC2 (0x12L<<16)
2304 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_BC3 (0x13L<<16)
2305 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA1 (0x14L<<16)
2306 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA2 (0x15L<<16)
2307 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA3 (0x16L<<16)
2308 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_BTYPE (0x17L<<16)
2309 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_BC (0x18L<<16)
2310 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_PTYPE (0x19L<<16)
2311 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_CMD (0x1aL<<16)
2312 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MAC (0x1bL<<16)
2313 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_LATCH (0x1cL<<16)
2314 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_XOFF (0x1dL<<16)
2315 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_XON (0x1eL<<16)
2316 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_PAUSED (0x1fL<<16)
2317 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_NPAUSED (0x20L<<16)
2318 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_TTYPE (0x21L<<16)
2319 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_TVAL (0x22L<<16)
2320 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_USA1 (0x23L<<16)
2321 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_USA2 (0x24L<<16)
2322 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_USA3 (0x25L<<16)
2323 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_UTYPE (0x26L<<16)
2324 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_UTTYPE (0x27L<<16)
2325 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_UTVAL (0x28L<<16)
2326 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MTYPE (0x29L<<16)
2327 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_DROP (0x2aL<<16)
2328 #define BCE_EMAC_RXMAC_DEBUG4_DROP_PKT (1L<<22)
2329 #define BCE_EMAC_RXMAC_DEBUG4_SLOT_FILLED (1L<<23)
2330 #define BCE_EMAC_RXMAC_DEBUG4_FALSE_CARRIER (1L<<24)
2331 #define BCE_EMAC_RXMAC_DEBUG4_LAST_DATA (1L<<25)
2332 #define BCE_EMAC_RXMAC_DEBUG4_sfd_FOUND (1L<<26)
2333 #define BCE_EMAC_RXMAC_DEBUG4_ADVANCE (1L<<27)
2334 #define BCE_EMAC_RXMAC_DEBUG4_START (1L<<28)
2336 #define BCE_EMAC_RXMAC_DEBUG5 0x00001570
2337 #define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM (0x7L<<0)
2338 #define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM_IDLE (0L<<0)
2339 #define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_EOF (1L<<0)
2340 #define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_STAT (2L<<0)
2341 #define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4FCRC (3L<<0)
2342 #define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4RDE (4L<<0)
2343 #define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4ALL (5L<<0)
2344 #define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM_1WD_WAIT_STAT (6L<<0)
2345 #define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF1 (0x7L<<4)
2346 #define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF1_VDW (0x0L<<4)
2347 #define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF1_STAT (0x1L<<4)
2348 #define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF1_AEOF (0x2L<<4)
2349 #define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF1_NEOF (0x3L<<4)
2350 #define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SOF (0x4L<<4)
2351 #define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SAEOF (0x6L<<4)
2352 #define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SNEOF (0x7L<<4)
2353 #define BCE_EMAC_RXMAC_DEBUG5_EOF_DETECTED (1L<<7)
2354 #define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF0 (0x7L<<8)
2355 #define BCE_EMAC_RXMAC_DEBUG5_RPM_IDI_FIFO_FULL (1L<<11)
2356 #define BCE_EMAC_RXMAC_DEBUG5_LOAD_CCODE (1L<<12)
2357 #define BCE_EMAC_RXMAC_DEBUG5_LOAD_DATA (1L<<13)
2358 #define BCE_EMAC_RXMAC_DEBUG5_LOAD_STAT (1L<<14)
2359 #define BCE_EMAC_RXMAC_DEBUG5_CLR_STAT (1L<<15)
2360 #define BCE_EMAC_RXMAC_DEBUG5_IDI_RPM_CCODE (0x3L<<16)
2361 #define BCE_EMAC_RXMAC_DEBUG5_IDI_RPM_ACCEPT (1L<<19)
2362 #define BCE_EMAC_RXMAC_DEBUG5_FMLEN (0xfffL<<20)
2364 #define BCE_EMAC_RX_STAT_AC0 0x00001580
2365 #define BCE_EMAC_RX_STAT_AC1 0x00001584
2366 #define BCE_EMAC_RX_STAT_AC2 0x00001588
2367 #define BCE_EMAC_RX_STAT_AC3 0x0000158c
2368 #define BCE_EMAC_RX_STAT_AC4 0x00001590
2369 #define BCE_EMAC_RX_STAT_AC5 0x00001594
2370 #define BCE_EMAC_RX_STAT_AC6 0x00001598
2371 #define BCE_EMAC_RX_STAT_AC7 0x0000159c
2372 #define BCE_EMAC_RX_STAT_AC8 0x000015a0
2373 #define BCE_EMAC_RX_STAT_AC9 0x000015a4
2374 #define BCE_EMAC_RX_STAT_AC10 0x000015a8
2375 #define BCE_EMAC_RX_STAT_AC11 0x000015ac
2376 #define BCE_EMAC_RX_STAT_AC12 0x000015b0
2377 #define BCE_EMAC_RX_STAT_AC13 0x000015b4
2378 #define BCE_EMAC_RX_STAT_AC14 0x000015b8
2379 #define BCE_EMAC_RX_STAT_AC15 0x000015bc
2380 #define BCE_EMAC_RX_STAT_AC16 0x000015c0
2381 #define BCE_EMAC_RX_STAT_AC17 0x000015c4
2382 #define BCE_EMAC_RX_STAT_AC18 0x000015c8
2383 #define BCE_EMAC_RX_STAT_AC19 0x000015cc
2384 #define BCE_EMAC_RX_STAT_AC20 0x000015d0
2385 #define BCE_EMAC_RX_STAT_AC21 0x000015d4
2386 #define BCE_EMAC_RX_STAT_AC22 0x000015d8
2387 #define BCE_EMAC_RXMAC_SUC_DBG_OVERRUNVEC 0x000015dc
2388 #define BCE_EMAC_TX_STAT_IFHCOUTOCTETS 0x00001600
2389 #define BCE_EMAC_TX_STAT_IFHCOUTBADOCTETS 0x00001604
2390 #define BCE_EMAC_TX_STAT_ETHERSTATSCOLLISIONS 0x00001608
2391 #define BCE_EMAC_TX_STAT_OUTXONSENT 0x0000160c
2392 #define BCE_EMAC_TX_STAT_OUTXOFFSENT 0x00001610
2393 #define BCE_EMAC_TX_STAT_FLOWCONTROLDONE 0x00001614
2394 #define BCE_EMAC_TX_STAT_DOT3STATSSINGLECOLLISIONFRAMES 0x00001618
2395 #define BCE_EMAC_TX_STAT_DOT3STATSMULTIPLECOLLISIONFRAMES 0x0000161c
2396 #define BCE_EMAC_TX_STAT_DOT3STATSDEFERREDTRANSMISSIONS 0x00001620
2397 #define BCE_EMAC_TX_STAT_DOT3STATSEXCESSIVECOLLISIONS 0x00001624
2398 #define BCE_EMAC_TX_STAT_DOT3STATSLATECOLLISIONS 0x00001628
2399 #define BCE_EMAC_TX_STAT_IFHCOUTUCASTPKTS 0x0000162c
2400 #define BCE_EMAC_TX_STAT_IFHCOUTMULTICASTPKTS 0x00001630
2401 #define BCE_EMAC_TX_STAT_IFHCOUTBROADCASTPKTS 0x00001634
2402 #define BCE_EMAC_TX_STAT_ETHERSTATSPKTS64OCTETS 0x00001638
2403 #define BCE_EMAC_TX_STAT_ETHERSTATSPKTS65OCTETSTO127OCTETS 0x0000163c
2404 #define BCE_EMAC_TX_STAT_ETHERSTATSPKTS128OCTETSTO255OCTETS 0x00001640
2405 #define BCE_EMAC_TX_STAT_ETHERSTATSPKTS256OCTETSTO511OCTETS 0x00001644
2406 #define BCE_EMAC_TX_STAT_ETHERSTATSPKTS512OCTETSTO1023OCTETS 0x00001648
2407 #define BCE_EMAC_TX_STAT_ETHERSTATSPKTS1024OCTETSTO1522OCTETS 0x0000164c
2408 #define BCE_EMAC_TX_STAT_ETHERSTATSPKTS1523OCTETSTO9022OCTETS 0x00001650
2409 #define BCE_EMAC_TX_STAT_DOT3STATSINTERNALMACTRANSMITERRORS 0x00001654
2410 #define BCE_EMAC_TXMAC_DEBUG0 0x00001658
2411 #define BCE_EMAC_TXMAC_DEBUG1 0x0000165c
2412 #define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE (0xfL<<0)
2413 #define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE_IDLE (0x0L<<0)
2414 #define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE_START0 (0x1L<<0)
2415 #define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA0 (0x4L<<0)
2416 #define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA1 (0x5L<<0)
2417 #define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA2 (0x6L<<0)
2418 #define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA3 (0x7L<<0)
2419 #define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE_WAIT0 (0x8L<<0)
2420 #define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE_WAIT1 (0x9L<<0)
2421 #define BCE_EMAC_TXMAC_DEBUG1_CRS_ENABLE (1L<<4)
2422 #define BCE_EMAC_TXMAC_DEBUG1_BAD_CRC (1L<<5)
2423 #define BCE_EMAC_TXMAC_DEBUG1_SE_COUNTER (0xfL<<6)
2424 #define BCE_EMAC_TXMAC_DEBUG1_SEND_PAUSE (1L<<10)
2425 #define BCE_EMAC_TXMAC_DEBUG1_LATE_COLLISION (1L<<11)
2426 #define BCE_EMAC_TXMAC_DEBUG1_MAX_DEFER (1L<<12)
2427 #define BCE_EMAC_TXMAC_DEBUG1_DEFERRED (1L<<13)
2428 #define BCE_EMAC_TXMAC_DEBUG1_ONE_BYTE (1L<<14)
2429 #define BCE_EMAC_TXMAC_DEBUG1_IPG_TIME (0xfL<<15)
2430 #define BCE_EMAC_TXMAC_DEBUG1_SLOT_TIME (0xffL<<19)
2432 #define BCE_EMAC_TXMAC_DEBUG2 0x00001660
2433 #define BCE_EMAC_TXMAC_DEBUG2_BACK_OFF (0x3ffL<<0)
2434 #define BCE_EMAC_TXMAC_DEBUG2_BYTE_COUNT (0xffffL<<10)
2435 #define BCE_EMAC_TXMAC_DEBUG2_COL_COUNT (0x1fL<<26)
2436 #define BCE_EMAC_TXMAC_DEBUG2_COL_BIT (1L<<31)
2438 #define BCE_EMAC_TXMAC_DEBUG3 0x00001664
2439 #define BCE_EMAC_TXMAC_DEBUG3_SM_STATE (0xfL<<0)
2440 #define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_IDLE (0x0L<<0)
2441 #define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_PRE1 (0x1L<<0)
2442 #define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_PRE2 (0x2L<<0)
2443 #define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_SFD (0x3L<<0)
2444 #define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_DATA (0x4L<<0)
2445 #define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_CRC1 (0x5L<<0)
2446 #define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_CRC2 (0x6L<<0)
2447 #define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_EXT (0x7L<<0)
2448 #define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_STATB (0x8L<<0)
2449 #define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_STATG (0x9L<<0)
2450 #define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_JAM (0xaL<<0)
2451 #define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_EJAM (0xbL<<0)
2452 #define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_BJAM (0xcL<<0)
2453 #define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_SWAIT (0xdL<<0)
2454 #define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_BACKOFF (0xeL<<0)
2455 #define BCE_EMAC_TXMAC_DEBUG3_FILT_STATE (0x7L<<4)
2456 #define BCE_EMAC_TXMAC_DEBUG3_FILT_STATE_IDLE (0x0L<<4)
2457 #define BCE_EMAC_TXMAC_DEBUG3_FILT_STATE_WAIT (0x1L<<4)
2458 #define BCE_EMAC_TXMAC_DEBUG3_FILT_STATE_UNI (0x2L<<4)
2459 #define BCE_EMAC_TXMAC_DEBUG3_FILT_STATE_MC (0x3L<<4)
2460 #define BCE_EMAC_TXMAC_DEBUG3_FILT_STATE_BC2 (0x4L<<4)
2461 #define BCE_EMAC_TXMAC_DEBUG3_FILT_STATE_BC3 (0x5L<<4)
2462 #define BCE_EMAC_TXMAC_DEBUG3_FILT_STATE_BC (0x6L<<4)
2463 #define BCE_EMAC_TXMAC_DEBUG3_CRS_DONE (1L<<7)
2464 #define BCE_EMAC_TXMAC_DEBUG3_XOFF (1L<<8)
2465 #define BCE_EMAC_TXMAC_DEBUG3_SE_COUNTER (0xfL<<9)
2466 #define BCE_EMAC_TXMAC_DEBUG3_QUANTA_COUNTER (0x1fL<<13)
2468 #define BCE_EMAC_TXMAC_DEBUG4 0x00001668
2469 #define BCE_EMAC_TXMAC_DEBUG4_PAUSE_COUNTER (0xffffL<<0)
2470 #define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE (0xfL<<16)
2471 #define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_IDLE (0x0L<<16)
2472 #define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA1 (0x2L<<16)
2473 #define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA2 (0x3L<<16)
2474 #define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA3 (0x6L<<16)
2475 #define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC1 (0x7L<<16)
2476 #define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC2 (0x5L<<16)
2477 #define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC3 (0x4L<<16)
2478 #define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_TYPE (0xcL<<16)
2479 #define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CMD (0xeL<<16)
2480 #define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_TIME (0xaL<<16)
2481 #define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC1 (0x8L<<16)
2482 #define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC2 (0x9L<<16)
2483 #define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_WAIT (0xdL<<16)
2484 #define BCE_EMAC_TXMAC_DEBUG4_STATS0_VALID (1L<<20)
2485 #define BCE_EMAC_TXMAC_DEBUG4_APPEND_CRC (1L<<21)
2486 #define BCE_EMAC_TXMAC_DEBUG4_SLOT_FILLED (1L<<22)
2487 #define BCE_EMAC_TXMAC_DEBUG4_MAX_DEFER (1L<<23)
2488 #define BCE_EMAC_TXMAC_DEBUG4_SEND_EXTEND (1L<<24)
2489 #define BCE_EMAC_TXMAC_DEBUG4_SEND_PADDING (1L<<25)
2490 #define BCE_EMAC_TXMAC_DEBUG4_EOF_LOC (1L<<26)
2491 #define BCE_EMAC_TXMAC_DEBUG4_COLLIDING (1L<<27)
2492 #define BCE_EMAC_TXMAC_DEBUG4_COL_IN (1L<<28)
2493 #define BCE_EMAC_TXMAC_DEBUG4_BURSTING (1L<<29)
2494 #define BCE_EMAC_TXMAC_DEBUG4_ADVANCE (1L<<30)
2495 #define BCE_EMAC_TXMAC_DEBUG4_GO (1L<<31)
2497 #define BCE_EMAC_TX_STAT_AC0 0x00001680
2498 #define BCE_EMAC_TX_STAT_AC1 0x00001684
2499 #define BCE_EMAC_TX_STAT_AC2 0x00001688
2500 #define BCE_EMAC_TX_STAT_AC3 0x0000168c
2501 #define BCE_EMAC_TX_STAT_AC4 0x00001690
2502 #define BCE_EMAC_TX_STAT_AC5 0x00001694
2503 #define BCE_EMAC_TX_STAT_AC6 0x00001698
2504 #define BCE_EMAC_TX_STAT_AC7 0x0000169c
2505 #define BCE_EMAC_TX_STAT_AC8 0x000016a0
2506 #define BCE_EMAC_TX_STAT_AC9 0x000016a4
2507 #define BCE_EMAC_TX_STAT_AC10 0x000016a8
2508 #define BCE_EMAC_TX_STAT_AC11 0x000016ac
2509 #define BCE_EMAC_TX_STAT_AC12 0x000016b0
2510 #define BCE_EMAC_TX_STAT_AC13 0x000016b4
2511 #define BCE_EMAC_TX_STAT_AC14 0x000016b8
2512 #define BCE_EMAC_TX_STAT_AC15 0x000016bc
2513 #define BCE_EMAC_TX_STAT_AC16 0x000016c0
2514 #define BCE_EMAC_TX_STAT_AC17 0x000016c4
2515 #define BCE_EMAC_TX_STAT_AC18 0x000016c8
2516 #define BCE_EMAC_TX_STAT_AC19 0x000016cc
2517 #define BCE_EMAC_TX_STAT_AC20 0x000016d0
2518 #define BCE_EMAC_TX_STAT_AC21 0x000016d4
2519 #define BCE_EMAC_TXMAC_SUC_DBG_OVERRUNVEC 0x000016d8
2523 * rpm_reg definition
2526 #define BCE_RPM_COMMAND 0x00001800
2527 #define BCE_RPM_COMMAND_ENABLED (1L<<0)
2528 #define BCE_RPM_COMMAND_OVERRUN_ABORT (1L<<4)
2530 #define BCE_RPM_STATUS 0x00001804
2531 #define BCE_RPM_STATUS_MBUF_WAIT (1L<<0)
2532 #define BCE_RPM_STATUS_FREE_WAIT (1L<<1)
2534 #define BCE_RPM_CONFIG 0x00001808
2535 #define BCE_RPM_CONFIG_NO_PSD_HDR_CKSUM (1L<<0)
2536 #define BCE_RPM_CONFIG_ACPI_ENA (1L<<1)
2537 #define BCE_RPM_CONFIG_ACPI_KEEP (1L<<2)
2538 #define BCE_RPM_CONFIG_MP_KEEP (1L<<3)
2539 #define BCE_RPM_CONFIG_SORT_VECT_VAL (0xfL<<4)
2540 #define BCE_RPM_CONFIG_IGNORE_VLAN (1L<<31)
2542 #define BCE_RPM_VLAN_MATCH0 0x00001810
2543 #define BCE_RPM_VLAN_MATCH0_RPM_VLAN_MTCH0_VALUE (0xfffL<<0)
2545 #define BCE_RPM_VLAN_MATCH1 0x00001814
2546 #define BCE_RPM_VLAN_MATCH1_RPM_VLAN_MTCH1_VALUE (0xfffL<<0)
2548 #define BCE_RPM_VLAN_MATCH2 0x00001818
2549 #define BCE_RPM_VLAN_MATCH2_RPM_VLAN_MTCH2_VALUE (0xfffL<<0)
2551 #define BCE_RPM_VLAN_MATCH3 0x0000181c
2552 #define BCE_RPM_VLAN_MATCH3_RPM_VLAN_MTCH3_VALUE (0xfffL<<0)
2554 #define BCE_RPM_SORT_USER0 0x00001820
2555 #define BCE_RPM_SORT_USER0_PM_EN (0xffffL<<0)
2556 #define BCE_RPM_SORT_USER0_BC_EN (1L<<16)
2557 #define BCE_RPM_SORT_USER0_MC_EN (1L<<17)
2558 #define BCE_RPM_SORT_USER0_MC_HSH_EN (1L<<18)
2559 #define BCE_RPM_SORT_USER0_PROM_EN (1L<<19)
2560 #define BCE_RPM_SORT_USER0_VLAN_EN (0xfL<<20)
2561 #define BCE_RPM_SORT_USER0_PROM_VLAN (1L<<24)
2562 #define BCE_RPM_SORT_USER0_ENA (1L<<31)
2564 #define BCE_RPM_SORT_USER1 0x00001824
2565 #define BCE_RPM_SORT_USER1_PM_EN (0xffffL<<0)
2566 #define BCE_RPM_SORT_USER1_BC_EN (1L<<16)
2567 #define BCE_RPM_SORT_USER1_MC_EN (1L<<17)
2568 #define BCE_RPM_SORT_USER1_MC_HSH_EN (1L<<18)
2569 #define BCE_RPM_SORT_USER1_PROM_EN (1L<<19)
2570 #define BCE_RPM_SORT_USER1_VLAN_EN (0xfL<<20)
2571 #define BCE_RPM_SORT_USER1_PROM_VLAN (1L<<24)
2572 #define BCE_RPM_SORT_USER1_ENA (1L<<31)
2574 #define BCE_RPM_SORT_USER2 0x00001828
2575 #define BCE_RPM_SORT_USER2_PM_EN (0xffffL<<0)
2576 #define BCE_RPM_SORT_USER2_BC_EN (1L<<16)
2577 #define BCE_RPM_SORT_USER2_MC_EN (1L<<17)
2578 #define BCE_RPM_SORT_USER2_MC_HSH_EN (1L<<18)
2579 #define BCE_RPM_SORT_USER2_PROM_EN (1L<<19)
2580 #define BCE_RPM_SORT_USER2_VLAN_EN (0xfL<<20)
2581 #define BCE_RPM_SORT_USER2_PROM_VLAN (1L<<24)
2582 #define BCE_RPM_SORT_USER2_ENA (1L<<31)
2584 #define BCE_RPM_SORT_USER3 0x0000182c
2585 #define BCE_RPM_SORT_USER3_PM_EN (0xffffL<<0)
2586 #define BCE_RPM_SORT_USER3_BC_EN (1L<<16)
2587 #define BCE_RPM_SORT_USER3_MC_EN (1L<<17)
2588 #define BCE_RPM_SORT_USER3_MC_HSH_EN (1L<<18)
2589 #define BCE_RPM_SORT_USER3_PROM_EN (1L<<19)
2590 #define BCE_RPM_SORT_USER3_VLAN_EN (0xfL<<20)
2591 #define BCE_RPM_SORT_USER3_PROM_VLAN (1L<<24)
2592 #define BCE_RPM_SORT_USER3_ENA (1L<<31)
2594 #define BCE_RPM_STAT_L2_FILTER_DISCARDS 0x00001840
2595 #define BCE_RPM_STAT_RULE_CHECKER_DISCARDS 0x00001844
2596 #define BCE_RPM_STAT_IFINFTQDISCARDS 0x00001848
2597 #define BCE_RPM_STAT_IFINMBUFDISCARD 0x0000184c
2598 #define BCE_RPM_STAT_RULE_CHECKER_P4_HIT 0x00001850
2599 #define BCE_RPM_STAT_AC0 0x00001880
2600 #define BCE_RPM_STAT_AC1 0x00001884
2601 #define BCE_RPM_STAT_AC2 0x00001888
2602 #define BCE_RPM_STAT_AC3 0x0000188c
2603 #define BCE_RPM_STAT_AC4 0x00001890
2604 #define BCE_RPM_RC_CNTL_0 0x00001900
2605 #define BCE_RPM_RC_CNTL_0_OFFSET (0xffL<<0)
2606 #define BCE_RPM_RC_CNTL_0_CLASS (0x7L<<8)
2607 #define BCE_RPM_RC_CNTL_0_PRIORITY (1L<<11)
2608 #define BCE_RPM_RC_CNTL_0_P4 (1L<<12)
2609 #define BCE_RPM_RC_CNTL_0_HDR_TYPE (0x7L<<13)
2610 #define BCE_RPM_RC_CNTL_0_HDR_TYPE_START (0L<<13)
2611 #define BCE_RPM_RC_CNTL_0_HDR_TYPE_IP (1L<<13)
2612 #define BCE_RPM_RC_CNTL_0_HDR_TYPE_TCP (2L<<13)
2613 #define BCE_RPM_RC_CNTL_0_HDR_TYPE_UDP (3L<<13)
2614 #define BCE_RPM_RC_CNTL_0_HDR_TYPE_DATA (4L<<13)
2615 #define BCE_RPM_RC_CNTL_0_COMP (0x3L<<16)
2616 #define BCE_RPM_RC_CNTL_0_COMP_EQUAL (0L<<16)
2617 #define BCE_RPM_RC_CNTL_0_COMP_NEQUAL (1L<<16)
2618 #define BCE_RPM_RC_CNTL_0_COMP_GREATER (2L<<16)
2619 #define BCE_RPM_RC_CNTL_0_COMP_LESS (3L<<16)
2620 #define BCE_RPM_RC_CNTL_0_SBIT (1L<<19)
2621 #define BCE_RPM_RC_CNTL_0_CMDSEL (0xfL<<20)
2622 #define BCE_RPM_RC_CNTL_0_MAP (1L<<24)
2623 #define BCE_RPM_RC_CNTL_0_DISCARD (1L<<25)
2624 #define BCE_RPM_RC_CNTL_0_MASK (1L<<26)
2625 #define BCE_RPM_RC_CNTL_0_P1 (1L<<27)
2626 #define BCE_RPM_RC_CNTL_0_P2 (1L<<28)
2627 #define BCE_RPM_RC_CNTL_0_P3 (1L<<29)
2628 #define BCE_RPM_RC_CNTL_0_NBIT (1L<<30)
2630 #define BCE_RPM_RC_VALUE_MASK_0 0x00001904
2631 #define BCE_RPM_RC_VALUE_MASK_0_VALUE (0xffffL<<0)
2632 #define BCE_RPM_RC_VALUE_MASK_0_MASK (0xffffL<<16)
2634 #define BCE_RPM_RC_CNTL_1 0x00001908
2635 #define BCE_RPM_RC_CNTL_1_A (0x3ffffL<<0)
2636 #define BCE_RPM_RC_CNTL_1_B (0xfffL<<19)
2638 #define BCE_RPM_RC_VALUE_MASK_1 0x0000190c
2639 #define BCE_RPM_RC_CNTL_2 0x00001910
2640 #define BCE_RPM_RC_CNTL_2_A (0x3ffffL<<0)
2641 #define BCE_RPM_RC_CNTL_2_B (0xfffL<<19)
2643 #define BCE_RPM_RC_VALUE_MASK_2 0x00001914
2644 #define BCE_RPM_RC_CNTL_3 0x00001918
2645 #define BCE_RPM_RC_CNTL_3_A (0x3ffffL<<0)
2646 #define BCE_RPM_RC_CNTL_3_B (0xfffL<<19)
2648 #define BCE_RPM_RC_VALUE_MASK_3 0x0000191c
2649 #define BCE_RPM_RC_CNTL_4 0x00001920
2650 #define BCE_RPM_RC_CNTL_4_A (0x3ffffL<<0)
2651 #define BCE_RPM_RC_CNTL_4_B (0xfffL<<19)
2653 #define BCE_RPM_RC_VALUE_MASK_4 0x00001924
2654 #define BCE_RPM_RC_CNTL_5 0x00001928
2655 #define BCE_RPM_RC_CNTL_5_A (0x3ffffL<<0)
2656 #define BCE_RPM_RC_CNTL_5_B (0xfffL<<19)
2658 #define BCE_RPM_RC_VALUE_MASK_5 0x0000192c
2659 #define BCE_RPM_RC_CNTL_6 0x00001930
2660 #define BCE_RPM_RC_CNTL_6_A (0x3ffffL<<0)
2661 #define BCE_RPM_RC_CNTL_6_B (0xfffL<<19)
2663 #define BCE_RPM_RC_VALUE_MASK_6 0x00001934
2664 #define BCE_RPM_RC_CNTL_7 0x00001938
2665 #define BCE_RPM_RC_CNTL_7_A (0x3ffffL<<0)
2666 #define BCE_RPM_RC_CNTL_7_B (0xfffL<<19)
2668 #define BCE_RPM_RC_VALUE_MASK_7 0x0000193c
2669 #define BCE_RPM_RC_CNTL_8 0x00001940
2670 #define BCE_RPM_RC_CNTL_8_A (0x3ffffL<<0)
2671 #define BCE_RPM_RC_CNTL_8_B (0xfffL<<19)
2673 #define BCE_RPM_RC_VALUE_MASK_8 0x00001944
2674 #define BCE_RPM_RC_CNTL_9 0x00001948
2675 #define BCE_RPM_RC_CNTL_9_A (0x3ffffL<<0)
2676 #define BCE_RPM_RC_CNTL_9_B (0xfffL<<19)
2678 #define BCE_RPM_RC_VALUE_MASK_9 0x0000194c
2679 #define BCE_RPM_RC_CNTL_10 0x00001950
2680 #define BCE_RPM_RC_CNTL_10_A (0x3ffffL<<0)
2681 #define BCE_RPM_RC_CNTL_10_B (0xfffL<<19)
2683 #define BCE_RPM_RC_VALUE_MASK_10 0x00001954
2684 #define BCE_RPM_RC_CNTL_11 0x00001958
2685 #define BCE_RPM_RC_CNTL_11_A (0x3ffffL<<0)
2686 #define BCE_RPM_RC_CNTL_11_B (0xfffL<<19)
2688 #define BCE_RPM_RC_VALUE_MASK_11 0x0000195c
2689 #define BCE_RPM_RC_CNTL_12 0x00001960
2690 #define BCE_RPM_RC_CNTL_12_A (0x3ffffL<<0)
2691 #define BCE_RPM_RC_CNTL_12_B (0xfffL<<19)
2693 #define BCE_RPM_RC_VALUE_MASK_12 0x00001964
2694 #define BCE_RPM_RC_CNTL_13 0x00001968
2695 #define BCE_RPM_RC_CNTL_13_A (0x3ffffL<<0)
2696 #define BCE_RPM_RC_CNTL_13_B (0xfffL<<19)
2698 #define BCE_RPM_RC_VALUE_MASK_13 0x0000196c
2699 #define BCE_RPM_RC_CNTL_14 0x00001970
2700 #define BCE_RPM_RC_CNTL_14_A (0x3ffffL<<0)
2701 #define BCE_RPM_RC_CNTL_14_B (0xfffL<<19)
2703 #define BCE_RPM_RC_VALUE_MASK_14 0x00001974
2704 #define BCE_RPM_RC_CNTL_15 0x00001978
2705 #define BCE_RPM_RC_CNTL_15_A (0x3ffffL<<0)
2706 #define BCE_RPM_RC_CNTL_15_B (0xfffL<<19)
2708 #define BCE_RPM_RC_VALUE_MASK_15 0x0000197c
2709 #define BCE_RPM_RC_CONFIG 0x00001980
2710 #define BCE_RPM_RC_CONFIG_RULE_ENABLE (0xffffL<<0)
2711 #define BCE_RPM_RC_CONFIG_DEF_CLASS (0x7L<<24)
2713 #define BCE_RPM_DEBUG0 0x00001984
2714 #define BCE_RPM_DEBUG0_FM_BCNT (0xffffL<<0)
2715 #define BCE_RPM_DEBUG0_T_DATA_OFST_VLD (1L<<16)
2716 #define BCE_RPM_DEBUG0_T_UDP_OFST_VLD (1L<<17)
2717 #define BCE_RPM_DEBUG0_T_TCP_OFST_VLD (1L<<18)
2718 #define BCE_RPM_DEBUG0_T_IP_OFST_VLD (1L<<19)
2719 #define BCE_RPM_DEBUG0_IP_MORE_FRGMT (1L<<20)
2720 #define BCE_RPM_DEBUG0_T_IP_NO_TCP_UDP_HDR (1L<<21)
2721 #define BCE_RPM_DEBUG0_LLC_SNAP (1L<<22)
2722 #define BCE_RPM_DEBUG0_FM_STARTED (1L<<23)
2723 #define BCE_RPM_DEBUG0_DONE (1L<<24)
2724 #define BCE_RPM_DEBUG0_WAIT_4_DONE (1L<<25)
2725 #define BCE_RPM_DEBUG0_USE_TPBUF_CKSUM (1L<<26)
2726 #define BCE_RPM_DEBUG0_RX_NO_PSD_HDR_CKSUM (1L<<27)
2727 #define BCE_RPM_DEBUG0_IGNORE_VLAN (1L<<28)
2728 #define BCE_RPM_DEBUG0_RP_ENA_ACTIVE (1L<<31)
2730 #define BCE_RPM_DEBUG1 0x00001988
2731 #define BCE_RPM_DEBUG1_FSM_CUR_ST (0xffffL<<0)
2732 #define BCE_RPM_DEBUG1_FSM_CUR_ST_IDLE (0L<<0)
2733 #define BCE_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B6_ALL (1L<<0)
2734 #define BCE_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B2_IPLLC (2L<<0)
2735 #define BCE_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B6_IP (4L<<0)
2736 #define BCE_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B2_IP (8L<<0)
2737 #define BCE_RPM_DEBUG1_FSM_CUR_ST_IP_START (16L<<0)
2738 #define BCE_RPM_DEBUG1_FSM_CUR_ST_IP (32L<<0)
2739 #define BCE_RPM_DEBUG1_FSM_CUR_ST_TCP (64L<<0)
2740 #define BCE_RPM_DEBUG1_FSM_CUR_ST_UDP (128L<<0)
2741 #define BCE_RPM_DEBUG1_FSM_CUR_ST_AH (256L<<0)
2742 #define BCE_RPM_DEBUG1_FSM_CUR_ST_ESP (512L<<0)
2743 #define BCE_RPM_DEBUG1_FSM_CUR_ST_ESP_PAYLOAD (1024L<<0)
2744 #define BCE_RPM_DEBUG1_FSM_CUR_ST_DATA (2048L<<0)
2745 #define BCE_RPM_DEBUG1_FSM_CUR_ST_ADD_CARRY (0x2000L<<0)
2746 #define BCE_RPM_DEBUG1_FSM_CUR_ST_ADD_CARRYOUT (0x4000L<<0)
2747 #define BCE_RPM_DEBUG1_FSM_CUR_ST_LATCH_RESULT (0x8000L<<0)
2748 #define BCE_RPM_DEBUG1_HDR_BCNT (0x7ffL<<16)
2749 #define BCE_RPM_DEBUG1_UNKNOWN_ETYPE_D (1L<<28)
2750 #define BCE_RPM_DEBUG1_VLAN_REMOVED_D2 (1L<<29)
2751 #define BCE_RPM_DEBUG1_VLAN_REMOVED_D1 (1L<<30)
2752 #define BCE_RPM_DEBUG1_EOF_0XTRA_WD (1L<<31)
2754 #define BCE_RPM_DEBUG2 0x0000198c
2755 #define BCE_RPM_DEBUG2_CMD_HIT_VEC (0xffffL<<0)
2756 #define BCE_RPM_DEBUG2_IP_BCNT (0xffL<<16)
2757 #define BCE_RPM_DEBUG2_THIS_CMD_M4 (1L<<24)
2758 #define BCE_RPM_DEBUG2_THIS_CMD_M3 (1L<<25)
2759 #define BCE_RPM_DEBUG2_THIS_CMD_M2 (1L<<26)
2760 #define BCE_RPM_DEBUG2_THIS_CMD_M1 (1L<<27)
2761 #define BCE_RPM_DEBUG2_IPIPE_EMPTY (1L<<28)
2762 #define BCE_RPM_DEBUG2_FM_DISCARD (1L<<29)
2763 #define BCE_RPM_DEBUG2_LAST_RULE_IN_FM_D2 (1L<<30)
2764 #define BCE_RPM_DEBUG2_LAST_RULE_IN_FM_D1 (1L<<31)
2766 #define BCE_RPM_DEBUG3 0x00001990
2767 #define BCE_RPM_DEBUG3_AVAIL_MBUF_PTR (0x1ffL<<0)
2768 #define BCE_RPM_DEBUG3_RDE_RLUPQ_WR_REQ_INT (1L<<9)
2769 #define BCE_RPM_DEBUG3_RDE_RBUF_WR_LAST_INT (1L<<10)
2770 #define BCE_RPM_DEBUG3_RDE_RBUF_WR_REQ_INT (1L<<11)
2771 #define BCE_RPM_DEBUG3_RDE_RBUF_FREE_REQ (1L<<12)
2772 #define BCE_RPM_DEBUG3_RDE_RBUF_ALLOC_REQ (1L<<13)
2773 #define BCE_RPM_DEBUG3_DFSM_MBUF_NOTAVAIL (1L<<14)
2774 #define BCE_RPM_DEBUG3_RBUF_RDE_SOF_DROP (1L<<15)
2775 #define BCE_RPM_DEBUG3_DFIFO_VLD_ENTRY_CT (0xfL<<16)
2776 #define BCE_RPM_DEBUG3_RDE_SRC_FIFO_ALMFULL (1L<<21)
2777 #define BCE_RPM_DEBUG3_DROP_NXT_VLD (1L<<22)
2778 #define BCE_RPM_DEBUG3_DROP_NXT (1L<<23)
2779 #define BCE_RPM_DEBUG3_FTQ_FSM (0x3L<<24)
2780 #define BCE_RPM_DEBUG3_FTQ_FSM_IDLE (0x0L<<24)
2781 #define BCE_RPM_DEBUG3_FTQ_FSM_WAIT_ACK (0x1L<<24)
2782 #define BCE_RPM_DEBUG3_FTQ_FSM_WAIT_FREE (0x2L<<24)
2783 #define BCE_RPM_DEBUG3_MBWRITE_FSM (0x3L<<26)
2784 #define BCE_RPM_DEBUG3_MBWRITE_FSM_WAIT_SOF (0x0L<<26)
2785 #define BCE_RPM_DEBUG3_MBWRITE_FSM_GET_MBUF (0x1L<<26)
2786 #define BCE_RPM_DEBUG3_MBWRITE_FSM_DMA_DATA (0x2L<<26)
2787 #define BCE_RPM_DEBUG3_MBWRITE_FSM_WAIT_DATA (0x3L<<26)
2788 #define BCE_RPM_DEBUG3_MBWRITE_FSM_WAIT_EOF (0x4L<<26)
2789 #define BCE_RPM_DEBUG3_MBWRITE_FSM_WAIT_MF_ACK (0x5L<<26)
2790 #define BCE_RPM_DEBUG3_MBWRITE_FSM_WAIT_DROP_NXT_VLD (0x6L<<26)
2791 #define BCE_RPM_DEBUG3_MBWRITE_FSM_DONE (0x7L<<26)
2792 #define BCE_RPM_DEBUG3_MBFREE_FSM (1L<<29)
2793 #define BCE_RPM_DEBUG3_MBFREE_FSM_IDLE (0L<<29)
2794 #define BCE_RPM_DEBUG3_MBFREE_FSM_WAIT_ACK (1L<<29)
2795 #define BCE_RPM_DEBUG3_MBALLOC_FSM (1L<<30)
2796 #define BCE_RPM_DEBUG3_MBALLOC_FSM_ET_MBUF (0x0L<<30)
2797 #define BCE_RPM_DEBUG3_MBALLOC_FSM_IVE_MBUF (0x1L<<30)
2798 #define BCE_RPM_DEBUG3_CCODE_EOF_ERROR (1L<<31)
2800 #define BCE_RPM_DEBUG4 0x00001994
2801 #define BCE_RPM_DEBUG4_DFSM_MBUF_CLUSTER (0x1ffffffL<<0)
2802 #define BCE_RPM_DEBUG4_DFIFO_CUR_CCODE (0x7L<<25)
2803 #define BCE_RPM_DEBUG4_MBWRITE_FSM (0x7L<<28)
2804 #define BCE_RPM_DEBUG4_DFIFO_EMPTY (1L<<31)
2806 #define BCE_RPM_DEBUG5 0x00001998
2807 #define BCE_RPM_DEBUG5_RDROP_WPTR (0x1fL<<0)
2808 #define BCE_RPM_DEBUG5_RDROP_ACPI_RPTR (0x1fL<<5)
2809 #define BCE_RPM_DEBUG5_RDROP_MC_RPTR (0x1fL<<10)
2810 #define BCE_RPM_DEBUG5_RDROP_RC_RPTR (0x1fL<<15)
2811 #define BCE_RPM_DEBUG5_RDROP_ACPI_EMPTY (1L<<20)
2812 #define BCE_RPM_DEBUG5_RDROP_MC_EMPTY (1L<<21)
2813 #define BCE_RPM_DEBUG5_RDROP_AEOF_VEC_AT_RDROP_MC_RPTR (1L<<22)
2814 #define BCE_RPM_DEBUG5_HOLDREG_WOL_DROP_INT (1L<<23)
2815 #define BCE_RPM_DEBUG5_HOLDREG_DISCARD (1L<<24)
2816 #define BCE_RPM_DEBUG5_HOLDREG_MBUF_NOTAVAIL (1L<<25)
2817 #define BCE_RPM_DEBUG5_HOLDREG_MC_EMPTY (1L<<26)
2818 #define BCE_RPM_DEBUG5_HOLDREG_RC_EMPTY (1L<<27)
2819 #define BCE_RPM_DEBUG5_HOLDREG_FC_EMPTY (1L<<28)
2820 #define BCE_RPM_DEBUG5_HOLDREG_ACPI_EMPTY (1L<<29)
2821 #define BCE_RPM_DEBUG5_HOLDREG_FULL_T (1L<<30)
2822 #define BCE_RPM_DEBUG5_HOLDREG_RD (1L<<31)
2824 #define BCE_RPM_DEBUG6 0x0000199c
2825 #define BCE_RPM_DEBUG6_ACPI_VEC (0xffffL<<0)
2826 #define BCE_RPM_DEBUG6_VEC (0xffffL<<16)
2828 #define BCE_RPM_DEBUG7 0x000019a0
2829 #define BCE_RPM_DEBUG7_RPM_DBG7_LAST_CRC (0xffffffffL<<0)
2831 #define BCE_RPM_DEBUG8 0x000019a4
2832 #define BCE_RPM_DEBUG8_PS_ACPI_FSM (0xfL<<0)
2833 #define BCE_RPM_DEBUG8_PS_ACPI_FSM_IDLE (0L<<0)
2834 #define BCE_RPM_DEBUG8_PS_ACPI_FSM_SOF_W1_ADDR (1L<<0)
2835 #define BCE_RPM_DEBUG8_PS_ACPI_FSM_SOF_W2_ADDR (2L<<0)
2836 #define BCE_RPM_DEBUG8_PS_ACPI_FSM_SOF_W3_ADDR (3L<<0)
2837 #define BCE_RPM_DEBUG8_PS_ACPI_FSM_SOF_WAIT_THBUF (4L<<0)
2838 #define BCE_RPM_DEBUG8_PS_ACPI_FSM_W3_DATA (5L<<0)
2839 #define BCE_RPM_DEBUG8_PS_ACPI_FSM_W0_ADDR (6L<<0)
2840 #define BCE_RPM_DEBUG8_PS_ACPI_FSM_W1_ADDR (7L<<0)
2841 #define BCE_RPM_DEBUG8_PS_ACPI_FSM_W2_ADDR (8L<<0)
2842 #define BCE_RPM_DEBUG8_PS_ACPI_FSM_W3_ADDR (9L<<0)
2843 #define BCE_RPM_DEBUG8_PS_ACPI_FSM_WAIT_THBUF (10L<<0)
2844 #define BCE_RPM_DEBUG8_COMPARE_AT_W0 (1L<<4)
2845 #define BCE_RPM_DEBUG8_COMPARE_AT_W3_DATA (1L<<5)
2846 #define BCE_RPM_DEBUG8_COMPARE_AT_SOF_WAIT (1L<<6)
2847 #define BCE_RPM_DEBUG8_COMPARE_AT_SOF_W3 (1L<<7)
2848 #define BCE_RPM_DEBUG8_COMPARE_AT_SOF_W2 (1L<<8)
2849 #define BCE_RPM_DEBUG8_EOF_W_LTEQ6_VLDBYTES (1L<<9)
2850 #define BCE_RPM_DEBUG8_EOF_W_LTEQ4_VLDBYTES (1L<<10)
2851 #define BCE_RPM_DEBUG8_NXT_EOF_W_12_VLDBYTES (1L<<11)
2852 #define BCE_RPM_DEBUG8_EOF_DET (1L<<12)
2853 #define BCE_RPM_DEBUG8_SOF_DET (1L<<13)
2854 #define BCE_RPM_DEBUG8_WAIT_4_SOF (1L<<14)
2855 #define BCE_RPM_DEBUG8_ALL_DONE (1L<<15)
2856 #define BCE_RPM_DEBUG8_THBUF_ADDR (0x7fL<<16)
2857 #define BCE_RPM_DEBUG8_BYTE_CTR (0xffL<<24)
2859 #define BCE_RPM_DEBUG9 0x000019a8
2860 #define BCE_RPM_DEBUG9_OUTFIFO_COUNT (0x7L<<0)
2861 #define BCE_RPM_DEBUG9_RDE_ACPI_RDY (1L<<3)
2862 #define BCE_RPM_DEBUG9_VLD_RD_ENTRY_CT (0x7L<<4)
2863 #define BCE_RPM_DEBUG9_OUTFIFO_OVERRUN_OCCURRED (1L<<28)
2864 #define BCE_RPM_DEBUG9_INFIFO_OVERRUN_OCCURRED (1L<<29)
2865 #define BCE_RPM_DEBUG9_ACPI_MATCH_INT (1L<<30)
2866 #define BCE_RPM_DEBUG9_ACPI_ENABLE_SYN (1L<<31)
2868 #define BCE_RPM_ACPI_DBG_BUF_W00 0x000019c0
2869 #define BCE_RPM_ACPI_DBG_BUF_W01 0x000019c4
2870 #define BCE_RPM_ACPI_DBG_BUF_W02 0x000019c8
2871 #define BCE_RPM_ACPI_DBG_BUF_W03 0x000019cc
2872 #define BCE_RPM_ACPI_DBG_BUF_W10 0x000019d0
2873 #define BCE_RPM_ACPI_DBG_BUF_W11 0x000019d4
2874 #define BCE_RPM_ACPI_DBG_BUF_W12 0x000019d8
2875 #define BCE_RPM_ACPI_DBG_BUF_W13 0x000019dc
2876 #define BCE_RPM_ACPI_DBG_BUF_W20 0x000019e0
2877 #define BCE_RPM_ACPI_DBG_BUF_W21 0x000019e4
2878 #define BCE_RPM_ACPI_DBG_BUF_W22 0x000019e8
2879 #define BCE_RPM_ACPI_DBG_BUF_W23 0x000019ec
2880 #define BCE_RPM_ACPI_DBG_BUF_W30 0x000019f0
2881 #define BCE_RPM_ACPI_DBG_BUF_W31 0x000019f4
2882 #define BCE_RPM_ACPI_DBG_BUF_W32 0x000019f8
2883 #define BCE_RPM_ACPI_DBG_BUF_W33 0x000019fc
2887 * rbuf_reg definition
2890 #define BCE_RBUF_COMMAND 0x00200000
2891 #define BCE_RBUF_COMMAND_ENABLED (1L<<0)
2892 #define BCE_RBUF_COMMAND_FREE_INIT (1L<<1)
2893 #define BCE_RBUF_COMMAND_RAM_INIT (1L<<2)
2894 #define BCE_RBUF_COMMAND_OVER_FREE (1L<<4)
2895 #define BCE_RBUF_COMMAND_ALLOC_REQ (1L<<5)
2897 #define BCE_RBUF_STATUS1 0x00200004
2898 #define BCE_RBUF_STATUS1_FREE_COUNT (0x3ffL<<0)
2900 #define BCE_RBUF_STATUS2 0x00200008
2901 #define BCE_RBUF_STATUS2_FREE_TAIL (0x3ffL<<0)
2902 #define BCE_RBUF_STATUS2_FREE_HEAD (0x3ffL<<16)
2904 #define BCE_RBUF_CONFIG 0x0020000c
2905 #define BCE_RBUF_CONFIG_XOFF_TRIP (0x3ffL<<0)
2906 #define BCE_RBUF_CONFIG_XON_TRIP (0x3ffL<<16)
2908 #define BCE_RBUF_FW_BUF_ALLOC 0x00200010
2909 #define BCE_RBUF_FW_BUF_ALLOC_VALUE (0x1ffL<<7)
2911 #define BCE_RBUF_FW_BUF_FREE 0x00200014
2912 #define BCE_RBUF_FW_BUF_FREE_COUNT (0x7fL<<0)
2913 #define BCE_RBUF_FW_BUF_FREE_TAIL (0x1ffL<<7)
2914 #define BCE_RBUF_FW_BUF_FREE_HEAD (0x1ffL<<16)
2916 #define BCE_RBUF_FW_BUF_SEL 0x00200018
2917 #define BCE_RBUF_FW_BUF_SEL_COUNT (0x7fL<<0)
2918 #define BCE_RBUF_FW_BUF_SEL_TAIL (0x1ffL<<7)
2919 #define BCE_RBUF_FW_BUF_SEL_HEAD (0x1ffL<<16)
2921 #define BCE_RBUF_CONFIG2 0x0020001c
2922 #define BCE_RBUF_CONFIG2_MAC_DROP_TRIP (0x3ffL<<0)
2923 #define BCE_RBUF_CONFIG2_MAC_KEEP_TRIP (0x3ffL<<16)
2925 #define BCE_RBUF_CONFIG3 0x00200020
2926 #define BCE_RBUF_CONFIG3_CU_DROP_TRIP (0x3ffL<<0)
2927 #define BCE_RBUF_CONFIG3_CU_KEEP_TRIP (0x3ffL<<16)
2929 #define BCE_RBUF_PKT_DATA 0x00208000
2930 #define BCE_RBUF_CLIST_DATA 0x00210000
2931 #define BCE_RBUF_BUF_DATA 0x00220000
2935 * rv2p_reg definition
2938 #define BCE_RV2P_COMMAND 0x00002800
2939 #define BCE_RV2P_COMMAND_ENABLED (1L<<0)
2940 #define BCE_RV2P_COMMAND_PROC1_INTRPT (1L<<1)
2941 #define BCE_RV2P_COMMAND_PROC2_INTRPT (1L<<2)
2942 #define BCE_RV2P_COMMAND_ABORT0 (1L<<4)
2943 #define BCE_RV2P_COMMAND_ABORT1 (1L<<5)
2944 #define BCE_RV2P_COMMAND_ABORT2 (1L<<6)
2945 #define BCE_RV2P_COMMAND_ABORT3 (1L<<7)
2946 #define BCE_RV2P_COMMAND_ABORT4 (1L<<8)
2947 #define BCE_RV2P_COMMAND_ABORT5 (1L<<9)
2948 #define BCE_RV2P_COMMAND_PROC1_RESET (1L<<16)
2949 #define BCE_RV2P_COMMAND_PROC2_RESET (1L<<17)
2950 #define BCE_RV2P_COMMAND_CTXIF_RESET (1L<<18)
2952 #define BCE_RV2P_STATUS 0x00002804
2953 #define BCE_RV2P_STATUS_ALWAYS_0 (1L<<0)
2954 #define BCE_RV2P_STATUS_RV2P_GEN_STAT0_CNT (1L<<8)
2955 #define BCE_RV2P_STATUS_RV2P_GEN_STAT1_CNT (1L<<9)
2956 #define BCE_RV2P_STATUS_RV2P_GEN_STAT2_CNT (1L<<10)
2957 #define BCE_RV2P_STATUS_RV2P_GEN_STAT3_CNT (1L<<11)
2958 #define BCE_RV2P_STATUS_RV2P_GEN_STAT4_CNT (1L<<12)
2959 #define BCE_RV2P_STATUS_RV2P_GEN_STAT5_CNT (1L<<13)
2961 #define BCE_RV2P_CONFIG 0x00002808
2962 #define BCE_RV2P_CONFIG_STALL_PROC1 (1L<<0)
2963 #define BCE_RV2P_CONFIG_STALL_PROC2 (1L<<1)
2964 #define BCE_RV2P_CONFIG_PROC1_STALL_ON_ABORT0 (1L<<8)
2965 #define BCE_RV2P_CONFIG_PROC1_STALL_ON_ABORT1 (1L<<9)
2966 #define BCE_RV2P_CONFIG_PROC1_STALL_ON_ABORT2 (1L<<10)
2967 #define BCE_RV2P_CONFIG_PROC1_STALL_ON_ABORT3 (1L<<11)
2968 #define BCE_RV2P_CONFIG_PROC1_STALL_ON_ABORT4 (1L<<12)
2969 #define BCE_RV2P_CONFIG_PROC1_STALL_ON_ABORT5 (1L<<13)
2970 #define BCE_RV2P_CONFIG_PROC2_STALL_ON_ABORT0 (1L<<16)
2971 #define BCE_RV2P_CONFIG_PROC2_STALL_ON_ABORT1 (1L<<17)
2972 #define BCE_RV2P_CONFIG_PROC2_STALL_ON_ABORT2 (1L<<18)
2973 #define BCE_RV2P_CONFIG_PROC2_STALL_ON_ABORT3 (1L<<19)
2974 #define BCE_RV2P_CONFIG_PROC2_STALL_ON_ABORT4 (1L<<20)
2975 #define BCE_RV2P_CONFIG_PROC2_STALL_ON_ABORT5 (1L<<21)
2976 #define BCE_RV2P_CONFIG_PAGE_SIZE (0xfL<<24)
2977 #define BCE_RV2P_CONFIG_PAGE_SIZE_256 (0L<<24)
2978 #define BCE_RV2P_CONFIG_PAGE_SIZE_512 (1L<<24)
2979 #define BCE_RV2P_CONFIG_PAGE_SIZE_1K (2L<<24)
2980 #define BCE_RV2P_CONFIG_PAGE_SIZE_2K (3L<<24)
2981 #define BCE_RV2P_CONFIG_PAGE_SIZE_4K (4L<<24)
2982 #define BCE_RV2P_CONFIG_PAGE_SIZE_8K (5L<<24)
2983 #define BCE_RV2P_CONFIG_PAGE_SIZE_16K (6L<<24)
2984 #define BCE_RV2P_CONFIG_PAGE_SIZE_32K (7L<<24)
2985 #define BCE_RV2P_CONFIG_PAGE_SIZE_64K (8L<<24)
2986 #define BCE_RV2P_CONFIG_PAGE_SIZE_128K (9L<<24)
2987 #define BCE_RV2P_CONFIG_PAGE_SIZE_256K (10L<<24)
2988 #define BCE_RV2P_CONFIG_PAGE_SIZE_512K (11L<<24)
2989 #define BCE_RV2P_CONFIG_PAGE_SIZE_1M (12L<<24)
2991 #define BCE_RV2P_GEN_BFR_ADDR_0 0x00002810
2992 #define BCE_RV2P_GEN_BFR_ADDR_0_VALUE (0xffffL<<16)
2994 #define BCE_RV2P_GEN_BFR_ADDR_1 0x00002814
2995 #define BCE_RV2P_GEN_BFR_ADDR_1_VALUE (0xffffL<<16)
2997 #define BCE_RV2P_GEN_BFR_ADDR_2 0x00002818
2998 #define BCE_RV2P_GEN_BFR_ADDR_2_VALUE (0xffffL<<16)
3000 #define BCE_RV2P_GEN_BFR_ADDR_3 0x0000281c
3001 #define BCE_RV2P_GEN_BFR_ADDR_3_VALUE (0xffffL<<16)
3003 #define BCE_RV2P_INSTR_HIGH 0x00002830
3004 #define BCE_RV2P_INSTR_HIGH_HIGH (0x1fL<<0)
3006 #define BCE_RV2P_INSTR_LOW 0x00002834
3007 #define BCE_RV2P_PROC1_ADDR_CMD 0x00002838
3008 #define BCE_RV2P_PROC1_ADDR_CMD_ADD (0x3ffL<<0)
3009 #define BCE_RV2P_PROC1_ADDR_CMD_RDWR (1L<<31)
3011 #define BCE_RV2P_PROC2_ADDR_CMD 0x0000283c
3012 #define BCE_RV2P_PROC2_ADDR_CMD_ADD (0x3ffL<<0)
3013 #define BCE_RV2P_PROC2_ADDR_CMD_RDWR (1L<<31)
3015 #define BCE_RV2P_PROC1_GRC_DEBUG 0x00002840
3016 #define BCE_RV2P_PROC2_GRC_DEBUG 0x00002844
3017 #define BCE_RV2P_GRC_PROC_DEBUG 0x00002848
3018 #define BCE_RV2P_DEBUG_VECT_PEEK 0x0000284c
3019 #define BCE_RV2P_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
3020 #define BCE_RV2P_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
3021 #define BCE_RV2P_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
3022 #define BCE_RV2P_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
3023 #define BCE_RV2P_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
3024 #define BCE_RV2P_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
3026 #define BCE_RV2P_PFTQ_DATA 0x00002b40
3027 #define BCE_RV2P_PFTQ_CMD 0x00002b78
3028 #define BCE_RV2P_PFTQ_CMD_OFFSET (0x3ffL<<0)
3029 #define BCE_RV2P_PFTQ_CMD_WR_TOP (1L<<10)
3030 #define BCE_RV2P_PFTQ_CMD_WR_TOP_0 (0L<<10)
3031 #define BCE_RV2P_PFTQ_CMD_WR_TOP_1 (1L<<10)
3032 #define BCE_RV2P_PFTQ_CMD_SFT_RESET (1L<<25)
3033 #define BCE_RV2P_PFTQ_CMD_RD_DATA (1L<<26)
3034 #define BCE_RV2P_PFTQ_CMD_ADD_INTERVEN (1L<<27)
3035 #define BCE_RV2P_PFTQ_CMD_ADD_DATA (1L<<28)
3036 #define BCE_RV2P_PFTQ_CMD_INTERVENE_CLR (1L<<29)
3037 #define BCE_RV2P_PFTQ_CMD_POP (1L<<30)
3038 #define BCE_RV2P_PFTQ_CMD_BUSY (1L<<31)
3040 #define BCE_RV2P_PFTQ_CTL 0x00002b7c
3041 #define BCE_RV2P_PFTQ_CTL_INTERVENE (1L<<0)
3042 #define BCE_RV2P_PFTQ_CTL_OVERFLOW (1L<<1)
3043 #define BCE_RV2P_PFTQ_CTL_FORCE_INTERVENE (1L<<2)
3044 #define BCE_RV2P_PFTQ_CTL_MAX_DEPTH (0x3ffL<<12)
3045 #define BCE_RV2P_PFTQ_CTL_CUR_DEPTH (0x3ffL<<22)
3047 #define BCE_RV2P_TFTQ_DATA 0x00002b80
3048 #define BCE_RV2P_TFTQ_CMD 0x00002bb8
3049 #define BCE_RV2P_TFTQ_CMD_OFFSET (0x3ffL<<0)
3050 #define BCE_RV2P_TFTQ_CMD_WR_TOP (1L<<10)
3051 #define BCE_RV2P_TFTQ_CMD_WR_TOP_0 (0L<<10)
3052 #define BCE_RV2P_TFTQ_CMD_WR_TOP_1 (1L<<10)
3053 #define BCE_RV2P_TFTQ_CMD_SFT_RESET (1L<<25)
3054 #define BCE_RV2P_TFTQ_CMD_RD_DATA (1L<<26)
3055 #define BCE_RV2P_TFTQ_CMD_ADD_INTERVEN (1L<<27)
3056 #define BCE_RV2P_TFTQ_CMD_ADD_DATA (1L<<28)
3057 #define BCE_RV2P_TFTQ_CMD_INTERVENE_CLR (1L<<29)
3058 #define BCE_RV2P_TFTQ_CMD_POP (1L<<30)
3059 #define BCE_RV2P_TFTQ_CMD_BUSY (1L<<31)
3061 #define BCE_RV2P_TFTQ_CTL 0x00002bbc
3062 #define BCE_RV2P_TFTQ_CTL_INTERVENE (1L<<0)
3063 #define BCE_RV2P_TFTQ_CTL_OVERFLOW (1L<<1)
3064 #define BCE_RV2P_TFTQ_CTL_FORCE_INTERVENE (1L<<2)
3065 #define BCE_RV2P_TFTQ_CTL_MAX_DEPTH (0x3ffL<<12)
3066 #define BCE_RV2P_TFTQ_CTL_CUR_DEPTH (0x3ffL<<22)
3068 #define BCE_RV2P_MFTQ_DATA 0x00002bc0
3069 #define BCE_RV2P_MFTQ_CMD 0x00002bf8
3070 #define BCE_RV2P_MFTQ_CMD_OFFSET (0x3ffL<<0)
3071 #define BCE_RV2P_MFTQ_CMD_WR_TOP (1L<<10)
3072 #define BCE_RV2P_MFTQ_CMD_WR_TOP_0 (0L<<10)
3073 #define BCE_RV2P_MFTQ_CMD_WR_TOP_1 (1L<<10)
3074 #define BCE_RV2P_MFTQ_CMD_SFT_RESET (1L<<25)
3075 #define BCE_RV2P_MFTQ_CMD_RD_DATA (1L<<26)
3076 #define BCE_RV2P_MFTQ_CMD_ADD_INTERVEN (1L<<27)
3077 #define BCE_RV2P_MFTQ_CMD_ADD_DATA (1L<<28)
3078 #define BCE_RV2P_MFTQ_CMD_INTERVENE_CLR (1L<<29)
3079 #define BCE_RV2P_MFTQ_CMD_POP (1L<<30)
3080 #define BCE_RV2P_MFTQ_CMD_BUSY (1L<<31)
3082 #define BCE_RV2P_MFTQ_CTL 0x00002bfc
3083 #define BCE_RV2P_MFTQ_CTL_INTERVENE (1L<<0)
3084 #define BCE_RV2P_MFTQ_CTL_OVERFLOW (1L<<1)
3085 #define BCE_RV2P_MFTQ_CTL_FORCE_INTERVENE (1L<<2)
3086 #define BCE_RV2P_MFTQ_CTL_MAX_DEPTH (0x3ffL<<12)
3087 #define BCE_RV2P_MFTQ_CTL_CUR_DEPTH (0x3ffL<<22)
3095 #define BCE_MQ_COMMAND 0x00003c00
3096 #define BCE_MQ_COMMAND_ENABLED (1L<<0)
3097 #define BCE_MQ_COMMAND_OVERFLOW (1L<<4)
3098 #define BCE_MQ_COMMAND_WR_ERROR (1L<<5)
3099 #define BCE_MQ_COMMAND_RD_ERROR (1L<<6)
3101 #define BCE_MQ_STATUS 0x00003c04
3102 #define BCE_MQ_STATUS_CTX_ACCESS_STAT (1L<<16)
3103 #define BCE_MQ_STATUS_CTX_ACCESS64_STAT (1L<<17)
3104 #define BCE_MQ_STATUS_PCI_STALL_STAT (1L<<18)
3106 #define BCE_MQ_CONFIG 0x00003c08
3107 #define BCE_MQ_CONFIG_TX_HIGH_PRI (1L<<0)
3108 #define BCE_MQ_CONFIG_HALT_DIS (1L<<1)
3109 #define BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE (0x7L<<4)
3110 #define BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_256 (0L<<4)
3111 #define BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_512 (1L<<4)
3112 #define BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_1K (2L<<4)
3113 #define BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_2K (3L<<4)
3114 #define BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_4K (4L<<4)
3115 #define BCE_MQ_CONFIG_MAX_DEPTH (0x7fL<<8)
3116 #define BCE_MQ_CONFIG_CUR_DEPTH (0x7fL<<20)
3118 #define BCE_MQ_ENQUEUE1 0x00003c0c
3119 #define BCE_MQ_ENQUEUE1_OFFSET (0x3fL<<2)
3120 #define BCE_MQ_ENQUEUE1_CID (0x3fffL<<8)
3121 #define BCE_MQ_ENQUEUE1_BYTE_MASK (0xfL<<24)
3122 #define BCE_MQ_ENQUEUE1_KNL_MODE (1L<<28)
3124 #define BCE_MQ_ENQUEUE2 0x00003c10
3125 #define BCE_MQ_BAD_WR_ADDR 0x00003c14
3126 #define BCE_MQ_BAD_RD_ADDR 0x00003c18
3127 #define BCE_MQ_KNL_BYP_WIND_START 0x00003c1c
3128 #define BCE_MQ_KNL_BYP_WIND_START_VALUE (0xfffffL<<12)
3130 #define BCE_MQ_KNL_WIND_END 0x00003c20
3131 #define BCE_MQ_KNL_WIND_END_VALUE (0xffffffL<<8)
3133 #define BCE_MQ_KNL_WRITE_MASK1 0x00003c24
3134 #define BCE_MQ_KNL_TX_MASK1 0x00003c28
3135 #define BCE_MQ_KNL_CMD_MASK1 0x00003c2c
3136 #define BCE_MQ_KNL_COND_ENQUEUE_MASK1 0x00003c30
3137 #define BCE_MQ_KNL_RX_V2P_MASK1 0x00003c34
3138 #define BCE_MQ_KNL_WRITE_MASK2 0x00003c38
3139 #define BCE_MQ_KNL_TX_MASK2 0x00003c3c
3140 #define BCE_MQ_KNL_CMD_MASK2 0x00003c40
3141 #define BCE_MQ_KNL_COND_ENQUEUE_MASK2 0x00003c44
3142 #define BCE_MQ_KNL_RX_V2P_MASK2 0x00003c48
3143 #define BCE_MQ_KNL_BYP_WRITE_MASK1 0x00003c4c
3144 #define BCE_MQ_KNL_BYP_TX_MASK1 0x00003c50
3145 #define BCE_MQ_KNL_BYP_CMD_MASK1 0x00003c54
3146 #define BCE_MQ_KNL_BYP_COND_ENQUEUE_MASK1 0x00003c58
3147 #define BCE_MQ_KNL_BYP_RX_V2P_MASK1 0x00003c5c
3148 #define BCE_MQ_KNL_BYP_WRITE_MASK2 0x00003c60
3149 #define BCE_MQ_KNL_BYP_TX_MASK2 0x00003c64
3150 #define BCE_MQ_KNL_BYP_CMD_MASK2 0x00003c68
3151 #define BCE_MQ_KNL_BYP_COND_ENQUEUE_MASK2 0x00003c6c
3152 #define BCE_MQ_KNL_BYP_RX_V2P_MASK2 0x00003c70
3153 #define BCE_MQ_MEM_WR_ADDR 0x00003c74
3154 #define BCE_MQ_MEM_WR_ADDR_VALUE (0x3fL<<0)
3156 #define BCE_MQ_MEM_WR_DATA0 0x00003c78
3157 #define BCE_MQ_MEM_WR_DATA0_VALUE (0xffffffffL<<0)
3159 #define BCE_MQ_MEM_WR_DATA1 0x00003c7c
3160 #define BCE_MQ_MEM_WR_DATA1_VALUE (0xffffffffL<<0)
3162 #define BCE_MQ_MEM_WR_DATA2 0x00003c80
3163 #define BCE_MQ_MEM_WR_DATA2_VALUE (0x3fffffffL<<0)
3165 #define BCE_MQ_MEM_RD_ADDR 0x00003c84
3166 #define BCE_MQ_MEM_RD_ADDR_VALUE (0x3fL<<0)
3168 #define BCE_MQ_MEM_RD_DATA0 0x00003c88
3169 #define BCE_MQ_MEM_RD_DATA0_VALUE (0xffffffffL<<0)
3171 #define BCE_MQ_MEM_RD_DATA1 0x00003c8c
3172 #define BCE_MQ_MEM_RD_DATA1_VALUE (0xffffffffL<<0)
3174 #define BCE_MQ_MEM_RD_DATA2 0x00003c90
3175 #define BCE_MQ_MEM_RD_DATA2_VALUE (0x3fffffffL<<0)
3180 * tbdr_reg definition
3183 #define BCE_TBDR_COMMAND 0x00005000
3184 #define BCE_TBDR_COMMAND_ENABLE (1L<<0)
3185 #define BCE_TBDR_COMMAND_SOFT_RST (1L<<1)
3186 #define BCE_TBDR_COMMAND_MSTR_ABORT (1L<<4)
3188 #define BCE_TBDR_STATUS 0x00005004
3189 #define BCE_TBDR_STATUS_DMA_WAIT (1L<<0)
3190 #define BCE_TBDR_STATUS_FTQ_WAIT (1L<<1)
3191 #define BCE_TBDR_STATUS_FIFO_OVERFLOW (1L<<2)
3192 #define BCE_TBDR_STATUS_FIFO_UNDERFLOW (1L<<3)
3193 #define BCE_TBDR_STATUS_SEARCHMISS_ERROR (1L<<4)
3194 #define BCE_TBDR_STATUS_FTQ_ENTRY_CNT (1L<<5)
3195 #define BCE_TBDR_STATUS_BURST_CNT (1L<<6)
3197 #define BCE_TBDR_CONFIG 0x00005008
3198 #define BCE_TBDR_CONFIG_MAX_BDS (0xffL<<0)
3199 #define BCE_TBDR_CONFIG_SWAP_MODE (1L<<8)
3200 #define BCE_TBDR_CONFIG_PRIORITY (1L<<9)
3201 #define BCE_TBDR_CONFIG_CACHE_NEXT_PAGE_PTRS (1L<<10)
3202 #define BCE_TBDR_CONFIG_PAGE_SIZE (0xfL<<24)
3203 #define BCE_TBDR_CONFIG_PAGE_SIZE_256 (0L<<24)
3204 #define BCE_TBDR_CONFIG_PAGE_SIZE_512 (1L<<24)
3205 #define BCE_TBDR_CONFIG_PAGE_SIZE_1K (2L<<24)
3206 #define BCE_TBDR_CONFIG_PAGE_SIZE_2K (3L<<24)
3207 #define BCE_TBDR_CONFIG_PAGE_SIZE_4K (4L<<24)
3208 #define BCE_TBDR_CONFIG_PAGE_SIZE_8K (5L<<24)
3209 #define BCE_TBDR_CONFIG_PAGE_SIZE_16K (6L<<24)
3210 #define BCE_TBDR_CONFIG_PAGE_SIZE_32K (7L<<24)
3211 #define BCE_TBDR_CONFIG_PAGE_SIZE_64K (8L<<24)
3212 #define BCE_TBDR_CONFIG_PAGE_SIZE_128K (9L<<24)
3213 #define BCE_TBDR_CONFIG_PAGE_SIZE_256K (10L<<24)
3214 #define BCE_TBDR_CONFIG_PAGE_SIZE_512K (11L<<24)
3215 #define BCE_TBDR_CONFIG_PAGE_SIZE_1M (12L<<24)
3217 #define BCE_TBDR_DEBUG_VECT_PEEK 0x0000500c
3218 #define BCE_TBDR_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
3219 #define BCE_TBDR_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
3220 #define BCE_TBDR_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
3221 #define BCE_TBDR_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
3222 #define BCE_TBDR_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
3223 #define BCE_TBDR_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
3225 #define BCE_TBDR_FTQ_DATA 0x000053c0
3226 #define BCE_TBDR_FTQ_CMD 0x000053f8
3227 #define BCE_TBDR_FTQ_CMD_OFFSET (0x3ffL<<0)
3228 #define BCE_TBDR_FTQ_CMD_WR_TOP (1L<<10)
3229 #define BCE_TBDR_FTQ_CMD_WR_TOP_0 (0L<<10)
3230 #define BCE_TBDR_FTQ_CMD_WR_TOP_1 (1L<<10)
3231 #define BCE_TBDR_FTQ_CMD_SFT_RESET (1L<<25)
3232 #define BCE_TBDR_FTQ_CMD_RD_DATA (1L<<26)
3233 #define BCE_TBDR_FTQ_CMD_ADD_INTERVEN (1L<<27)
3234 #define BCE_TBDR_FTQ_CMD_ADD_DATA (1L<<28)
3235 #define BCE_TBDR_FTQ_CMD_INTERVENE_CLR (1L<<29)
3236 #define BCE_TBDR_FTQ_CMD_POP (1L<<30)
3237 #define BCE_TBDR_FTQ_CMD_BUSY (1L<<31)
3239 #define BCE_TBDR_FTQ_CTL 0x000053fc
3240 #define BCE_TBDR_FTQ_CTL_INTERVENE (1L<<0)
3241 #define BCE_TBDR_FTQ_CTL_OVERFLOW (1L<<1)
3242 #define BCE_TBDR_FTQ_CTL_FORCE_INTERVENE (1L<<2)
3243 #define BCE_TBDR_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
3244 #define BCE_TBDR_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
3249 * tdma_reg definition
3252 #define BCE_TDMA_COMMAND 0x00005c00
3253 #define BCE_TDMA_COMMAND_ENABLED (1L<<0)
3254 #define BCE_TDMA_COMMAND_MASTER_ABORT (1L<<4)
3255 #define BCE_TDMA_COMMAND_BAD_L2_LENGTH_ABORT (1L<<7)
3257 #define BCE_TDMA_STATUS 0x00005c04
3258 #define BCE_TDMA_STATUS_DMA_WAIT (1L<<0)
3259 #define BCE_TDMA_STATUS_PAYLOAD_WAIT (1L<<1)
3260 #define BCE_TDMA_STATUS_PATCH_FTQ_WAIT (1L<<2)
3261 #define BCE_TDMA_STATUS_LOCK_WAIT (1L<<3)
3262 #define BCE_TDMA_STATUS_FTQ_ENTRY_CNT (1L<<16)
3263 #define BCE_TDMA_STATUS_BURST_CNT (1L<<17)
3265 #define BCE_TDMA_CONFIG 0x00005c08
3266 #define BCE_TDMA_CONFIG_ONE_DMA (1L<<0)
3267 #define BCE_TDMA_CONFIG_ONE_RECORD (1L<<1)
3268 #define BCE_TDMA_CONFIG_LIMIT_SZ (0xfL<<4)
3269 #define BCE_TDMA_CONFIG_LIMIT_SZ_64 (0L<<4)
3270 #define BCE_TDMA_CONFIG_LIMIT_SZ_128 (0x4L<<4)
3271 #define BCE_TDMA_CONFIG_LIMIT_SZ_256 (0x6L<<4)
3272 #define BCE_TDMA_CONFIG_LIMIT_SZ_512 (0x8L<<4)
3273 #define BCE_TDMA_CONFIG_LINE_SZ (0xfL<<8)
3274 #define BCE_TDMA_CONFIG_LINE_SZ_64 (0L<<8)
3275 #define BCE_TDMA_CONFIG_LINE_SZ_128 (4L<<8)
3276 #define BCE_TDMA_CONFIG_LINE_SZ_256 (6L<<8)
3277 #define BCE_TDMA_CONFIG_LINE_SZ_512 (8L<<8)
3278 #define BCE_TDMA_CONFIG_ALIGN_ENA (1L<<15)
3279 #define BCE_TDMA_CONFIG_CHK_L2_BD (1L<<16)
3280 #define BCE_TDMA_CONFIG_FIFO_CMP (0xfL<<20)
3282 #define BCE_TDMA_PAYLOAD_PROD 0x00005c0c
3283 #define BCE_TDMA_PAYLOAD_PROD_VALUE (0x1fffL<<3)
3285 #define BCE_TDMA_DBG_WATCHDOG 0x00005c10
3286 #define BCE_TDMA_DBG_TRIGGER 0x00005c14
3287 #define BCE_TDMA_DMAD_FSM 0x00005c80
3288 #define BCE_TDMA_DMAD_FSM_BD_INVLD (1L<<0)
3289 #define BCE_TDMA_DMAD_FSM_PUSH (0xfL<<4)
3290 #define BCE_TDMA_DMAD_FSM_ARB_TBDC (0x3L<<8)
3291 #define BCE_TDMA_DMAD_FSM_ARB_CTX (1L<<12)
3292 #define BCE_TDMA_DMAD_FSM_DR_INTF (1L<<16)
3293 #define BCE_TDMA_DMAD_FSM_DMAD (0x7L<<20)
3294 #define BCE_TDMA_DMAD_FSM_BD (0xfL<<24)
3296 #define BCE_TDMA_DMAD_STATUS 0x00005c84
3297 #define BCE_TDMA_DMAD_STATUS_RHOLD_PUSH_ENTRY (0x3L<<0)
3298 #define BCE_TDMA_DMAD_STATUS_RHOLD_DMAD_ENTRY (0x3L<<4)
3299 #define BCE_TDMA_DMAD_STATUS_RHOLD_BD_ENTRY (0x3L<<8)
3300 #define BCE_TDMA_DMAD_STATUS_IFTQ_ENUM (0xfL<<12)
3302 #define BCE_TDMA_DR_INTF_FSM 0x00005c88
3303 #define BCE_TDMA_DR_INTF_FSM_L2_COMP (0x3L<<0)
3304 #define BCE_TDMA_DR_INTF_FSM_TPATQ (0x7L<<4)
3305 #define BCE_TDMA_DR_INTF_FSM_TPBUF (0x3L<<8)
3306 #define BCE_TDMA_DR_INTF_FSM_DR_BUF (0x7L<<12)
3307 #define BCE_TDMA_DR_INTF_FSM_DMAD (0x7L<<16)
3309 #define BCE_TDMA_DR_INTF_STATUS 0x00005c8c
3310 #define BCE_TDMA_DR_INTF_STATUS_HOLE_PHASE (0x7L<<0)
3311 #define BCE_TDMA_DR_INTF_STATUS_DATA_AVAIL (0x3L<<4)
3312 #define BCE_TDMA_DR_INTF_STATUS_SHIFT_ADDR (0x7L<<8)
3313 #define BCE_TDMA_DR_INTF_STATUS_NXT_PNTR (0xfL<<12)
3314 #define BCE_TDMA_DR_INTF_STATUS_BYTE_COUNT (0x7L<<16)
3316 #define BCE_TDMA_FTQ_DATA 0x00005fc0
3317 #define BCE_TDMA_FTQ_CMD 0x00005ff8
3318 #define BCE_TDMA_FTQ_CMD_OFFSET (0x3ffL<<0)
3319 #define BCE_TDMA_FTQ_CMD_WR_TOP (1L<<10)
3320 #define BCE_TDMA_FTQ_CMD_WR_TOP_0 (0L<<10)
3321 #define BCE_TDMA_FTQ_CMD_WR_TOP_1 (1L<<10)
3322 #define BCE_TDMA_FTQ_CMD_SFT_RESET (1L<<25)
3323 #define BCE_TDMA_FTQ_CMD_RD_DATA (1L<<26)
3324 #define BCE_TDMA_FTQ_CMD_ADD_INTERVEN (1L<<27)
3325 #define BCE_TDMA_FTQ_CMD_ADD_DATA (1L<<28)
3326 #define BCE_TDMA_FTQ_CMD_INTERVENE_CLR (1L<<29)
3327 #define BCE_TDMA_FTQ_CMD_POP (1L<<30)
3328 #define BCE_TDMA_FTQ_CMD_BUSY (1L<<31)
3330 #define BCE_TDMA_FTQ_CTL 0x00005ffc
3331 #define BCE_TDMA_FTQ_CTL_INTERVENE (1L<<0)
3332 #define BCE_TDMA_FTQ_CTL_OVERFLOW (1L<<1)
3333 #define BCE_TDMA_FTQ_CTL_FORCE_INTERVENE (1L<<2)
3334 #define BCE_TDMA_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
3335 #define BCE_TDMA_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
3343 #define BCE_HC_COMMAND 0x00006800
3344 #define BCE_HC_COMMAND_ENABLE (1L<<0)
3345 #define BCE_HC_COMMAND_SKIP_ABORT (1L<<4)
3346 #define BCE_HC_COMMAND_COAL_NOW (1L<<16)
3347 #define BCE_HC_COMMAND_COAL_NOW_WO_INT (1L<<17)
3348 #define BCE_HC_COMMAND_STATS_NOW (1L<<18)
3349 #define BCE_HC_COMMAND_FORCE_INT (0x3L<<19)
3350 #define BCE_HC_COMMAND_FORCE_INT_NULL (0L<<19)
3351 #define BCE_HC_COMMAND_FORCE_INT_HIGH (1L<<19)
3352 #define BCE_HC_COMMAND_FORCE_INT_LOW (2L<<19)
3353 #define BCE_HC_COMMAND_FORCE_INT_FREE (3L<<19)
3354 #define BCE_HC_COMMAND_CLR_STAT_NOW (1L<<21)
3356 #define BCE_HC_STATUS 0x00006804
3357 #define BCE_HC_STATUS_MASTER_ABORT (1L<<0)
3358 #define BCE_HC_STATUS_PARITY_ERROR_STATE (1L<<1)
3359 #define BCE_HC_STATUS_PCI_CLK_CNT_STAT (1L<<16)
3360 #define BCE_HC_STATUS_CORE_CLK_CNT_STAT (1L<<17)
3361 #define BCE_HC_STATUS_NUM_STATUS_BLOCKS_STAT (1L<<18)
3362 #define BCE_HC_STATUS_NUM_INT_GEN_STAT (1L<<19)
3363 #define BCE_HC_STATUS_NUM_INT_MBOX_WR_STAT (1L<<20)
3364 #define BCE_HC_STATUS_CORE_CLKS_TO_HW_INTACK_STAT (1L<<23)
3365 #define BCE_HC_STATUS_CORE_CLKS_TO_SW_INTACK_STAT (1L<<24)
3366 #define BCE_HC_STATUS_CORE_CLKS_DURING_SW_INTACK_STAT (1L<<25)
3368 #define BCE_HC_CONFIG 0x00006808
3369 #define BCE_HC_CONFIG_COLLECT_STATS (1L<<0)
3370 #define BCE_HC_CONFIG_RX_TMR_MODE (1L<<1)
3371 #define BCE_HC_CONFIG_TX_TMR_MODE (1L<<2)
3372 #define BCE_HC_CONFIG_COM_TMR_MODE (1L<<3)
3373 #define BCE_HC_CONFIG_CMD_TMR_MODE (1L<<4)
3374 #define BCE_HC_CONFIG_STATISTIC_PRIORITY (1L<<5)
3375 #define BCE_HC_CONFIG_STATUS_PRIORITY (1L<<6)
3376 #define BCE_HC_CONFIG_STAT_MEM_ADDR (0xffL<<8)
3378 #define BCE_HC_ATTN_BITS_ENABLE 0x0000680c
3379 #define BCE_HC_STATUS_ADDR_L 0x00006810
3380 #define BCE_HC_STATUS_ADDR_H 0x00006814
3381 #define BCE_HC_STATISTICS_ADDR_L 0x00006818
3382 #define BCE_HC_STATISTICS_ADDR_H 0x0000681c
3383 #define BCE_HC_TX_QUICK_CONS_TRIP 0x00006820
3384 #define BCE_HC_TX_QUICK_CONS_TRIP_VALUE (0xffL<<0)
3385 #define BCE_HC_TX_QUICK_CONS_TRIP_INT (0xffL<<16)
3387 #define BCE_HC_COMP_PROD_TRIP 0x00006824
3388 #define BCE_HC_COMP_PROD_TRIP_VALUE (0xffL<<0)
3389 #define BCE_HC_COMP_PROD_TRIP_INT (0xffL<<16)
3391 #define BCE_HC_RX_QUICK_CONS_TRIP 0x00006828
3392 #define BCE_HC_RX_QUICK_CONS_TRIP_VALUE (0xffL<<0)
3393 #define BCE_HC_RX_QUICK_CONS_TRIP_INT (0xffL<<16)
3395 #define BCE_HC_RX_TICKS 0x0000682c
3396 #define BCE_HC_RX_TICKS_VALUE (0x3ffL<<0)
3397 #define BCE_HC_RX_TICKS_INT (0x3ffL<<16)
3399 #define BCE_HC_TX_TICKS 0x00006830
3400 #define BCE_HC_TX_TICKS_VALUE (0x3ffL<<0)
3401 #define BCE_HC_TX_TICKS_INT (0x3ffL<<16)
3403 #define BCE_HC_COM_TICKS 0x00006834
3404 #define BCE_HC_COM_TICKS_VALUE (0x3ffL<<0)
3405 #define BCE_HC_COM_TICKS_INT (0x3ffL<<16)
3407 #define BCE_HC_CMD_TICKS 0x00006838
3408 #define BCE_HC_CMD_TICKS_VALUE (0x3ffL<<0)
3409 #define BCE_HC_CMD_TICKS_INT (0x3ffL<<16)
3411 #define BCE_HC_PERIODIC_TICKS 0x0000683c
3412 #define BCE_HC_PERIODIC_TICKS_HC_PERIODIC_TICKS (0xffffL<<0)
3414 #define BCE_HC_STAT_COLLECT_TICKS 0x00006840
3415 #define BCE_HC_STAT_COLLECT_TICKS_HC_STAT_COLL_TICKS (0xffL<<4)
3417 #define BCE_HC_STATS_TICKS 0x00006844
3418 #define BCE_HC_STATS_TICKS_HC_STAT_TICKS (0xffffL<<8)
3420 #define BCE_HC_STAT_MEM_DATA 0x0000684c
3421 #define BCE_HC_STAT_GEN_SEL_0 0x00006850
3422 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0 (0x7fL<<0)
3423 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT0 (0L<<0)
3424 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT1 (1L<<0)
3425 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT2 (2L<<0)
3426 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT3 (3L<<0)
3427 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT4 (4L<<0)
3428 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT5 (5L<<0)
3429 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT6 (6L<<0)
3430 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT7 (7L<<0)
3431 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT8 (8L<<0)
3432 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT9 (9L<<0)
3433 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT10 (10L<<0)
3434 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT11 (11L<<0)
3435 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT0 (12L<<0)
3436 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT1 (13L<<0)
3437 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT2 (14L<<0)
3438 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT3 (15L<<0)
3439 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT4 (16L<<0)
3440 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT5 (17L<<0)
3441 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT6 (18L<<0)
3442 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT7 (19L<<0)
3443 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT0 (20L<<0)
3444 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT1 (21L<<0)
3445 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT2 (22L<<0)
3446 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT3 (23L<<0)
3447 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT4 (24L<<0)
3448 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT5 (25L<<0)
3449 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT6 (26L<<0)
3450 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT7 (27L<<0)
3451 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT8 (28L<<0)
3452 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT9 (29L<<0)
3453 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT10 (30L<<0)
3454 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT11 (31L<<0)
3455 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT0 (32L<<0)
3456 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT1 (33L<<0)
3457 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT2 (34L<<0)
3458 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT3 (35L<<0)
3459 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT0 (36L<<0)
3460 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT1 (37L<<0)
3461 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT2 (38L<<0)
3462 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT3 (39L<<0)
3463 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT4 (40L<<0)
3464 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT5 (41L<<0)
3465 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT6 (42L<<0)
3466 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT7 (43L<<0)
3467 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT0 (44L<<0)
3468 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT1 (45L<<0)
3469 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT2 (46L<<0)
3470 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT3 (47L<<0)
3471 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT4 (48L<<0)
3472 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT5 (49L<<0)
3473 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT6 (50L<<0)
3474 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT7 (51L<<0)
3475 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_PCI_CLK_CNT (52L<<0)
3476 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CORE_CLK_CNT (53L<<0)
3477 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS (54L<<0)
3478 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN (55L<<0)
3479 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR (56L<<0)
3480 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK (59L<<0)
3481 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK (60L<<0)
3482 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK (61L<<0)
3483 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCH_CMD_CNT (62L<<0)
3484 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCH_SLOT_CNT (63L<<0)
3485 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSCH_CMD_CNT (64L<<0)
3486 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSCH_SLOT_CNT (65L<<0)
3487 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUPQ_VALID_CNT (66L<<0)
3488 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPQ_VALID_CNT (67L<<0)
3489 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPCQ_VALID_CNT (68L<<0)
3490 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PPQ_VALID_CNT (69L<<0)
3491 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PMQ_VALID_CNT (70L<<0)
3492 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PTQ_VALID_CNT (71L<<0)
3493 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMAQ_VALID_CNT (72L<<0)
3494 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCHQ_VALID_CNT (73L<<0)
3495 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDRQ_VALID_CNT (74L<<0)
3496 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXPQ_VALID_CNT (75L<<0)
3497 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMAQ_VALID_CNT (76L<<0)
3498 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPATQ_VALID_CNT (77L<<0)
3499 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TASQ_VALID_CNT (78L<<0)
3500 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSQ_VALID_CNT (79L<<0)
3501 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CPQ_VALID_CNT (80L<<0)
3502 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMXQ_VALID_CNT (81L<<0)
3503 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMTQ_VALID_CNT (82L<<0)
3504 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMQ_VALID_CNT (83L<<0)
3505 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MGMQ_VALID_CNT (84L<<0)
3506 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_READ_TRANSFERS_CNT (85L<<0)
3507 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_READ_DELAY_PCI_CLKS_CNT (86L<<0)
3508 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_TRANSFERS_CNT (87L<<0)
3509 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_DELAY_PCI_CLKS_CNT \
3511 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_RETRY_AFTER_DATA_CNT \
3513 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_WRITE_TRANSFERS_CNT (90L<<0)
3514 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_WRITE_DELAY_PCI_CLKS_CNT (91L<<0)
3515 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_TRANSFERS_CNT (92L<<0)
3516 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_DELAY_PCI_CLKS_CNT \
3518 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_RETRY_AFTER_DATA_CNT\
3520 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_WR_CNT64 (95L<<0)
3521 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_RD_CNT64 (96L<<0)
3522 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_ACC_STALL_CLKS (97L<<0)
3523 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_LOCK_STALL_CLKS (98L<<0)
3524 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_CTX_ACCESS_STAT (99L<<0)
3525 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_CTX_ACCESS64_STAT (100L<<0)
3526 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_PCI_STALL_STAT (101L<<0)
3527 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDR_FTQ_ENTRY_CNT (102L<<0)
3528 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDR_BURST_CNT (103L<<0)
3529 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMA_FTQ_ENTRY_CNT (104L<<0)
3530 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMA_BURST_CNT (105L<<0)
3531 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMA_FTQ_ENTRY_CNT (106L<<0)
3532 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMA_BURST_CNT (107L<<0)
3533 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUP_MATCH_CNT (108L<<0)
3534 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_POLL_PASS_CNT (109L<<0)
3535 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR1_CNT (110L<<0)
3536 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR2_CNT (111L<<0)
3537 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR3_CNT (112L<<0)
3538 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR4_CNT (113L<<0)
3539 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR5_CNT (114L<<0)
3540 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT0 (115L<<0)
3541 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT1 (116L<<0)
3542 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT2 (117L<<0)
3543 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT3 (118L<<0)
3544 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT4 (119L<<0)
3545 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT5 (120L<<0)
3546 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_PROC1_MISS (121L<<0)
3547 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_PROC2_MISS (122L<<0)
3548 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_BURST_CNT (127L<<0)
3549 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_1 (0x7fL<<8)
3550 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_2 (0x7fL<<16)
3551 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_3 (0x7fL<<24)
3553 #define BCE_HC_STAT_GEN_SEL_1 0x00006854
3554 #define BCE_HC_STAT_GEN_SEL_1_GEN_SEL_4 (0x7fL<<0)
3555 #define BCE_HC_STAT_GEN_SEL_1_GEN_SEL_5 (0x7fL<<8)
3556 #define BCE_HC_STAT_GEN_SEL_1_GEN_SEL_6 (0x7fL<<16)
3557 #define BCE_HC_STAT_GEN_SEL_1_GEN_SEL_7 (0x7fL<<24)
3559 #define BCE_HC_STAT_GEN_SEL_2 0x00006858
3560 #define BCE_HC_STAT_GEN_SEL_2_GEN_SEL_8 (0x7fL<<0)
3561 #define BCE_HC_STAT_GEN_SEL_2_GEN_SEL_9 (0x7fL<<8)
3562 #define BCE_HC_STAT_GEN_SEL_2_GEN_SEL_10 (0x7fL<<16)
3563 #define BCE_HC_STAT_GEN_SEL_2_GEN_SEL_11 (0x7fL<<24)
3565 #define BCE_HC_STAT_GEN_SEL_3 0x0000685c
3566 #define BCE_HC_STAT_GEN_SEL_3_GEN_SEL_12 (0x7fL<<0)
3567 #define BCE_HC_STAT_GEN_SEL_3_GEN_SEL_13 (0x7fL<<8)
3568 #define BCE_HC_STAT_GEN_SEL_3_GEN_SEL_14 (0x7fL<<16)
3569 #define BCE_HC_STAT_GEN_SEL_3_GEN_SEL_15 (0x7fL<<24)
3571 #define BCE_HC_STAT_GEN_STAT0 0x00006888
3572 #define BCE_HC_STAT_GEN_STAT1 0x0000688c
3573 #define BCE_HC_STAT_GEN_STAT2 0x00006890
3574 #define BCE_HC_STAT_GEN_STAT3 0x00006894
3575 #define BCE_HC_STAT_GEN_STAT4 0x00006898
3576 #define BCE_HC_STAT_GEN_STAT5 0x0000689c
3577 #define BCE_HC_STAT_GEN_STAT6 0x000068a0
3578 #define BCE_HC_STAT_GEN_STAT7 0x000068a4
3579 #define BCE_HC_STAT_GEN_STAT8 0x000068a8
3580 #define BCE_HC_STAT_GEN_STAT9 0x000068ac
3581 #define BCE_HC_STAT_GEN_STAT10 0x000068b0
3582 #define BCE_HC_STAT_GEN_STAT11 0x000068b4
3583 #define BCE_HC_STAT_GEN_STAT12 0x000068b8
3584 #define BCE_HC_STAT_GEN_STAT13 0x000068bc
3585 #define BCE_HC_STAT_GEN_STAT14 0x000068c0
3586 #define BCE_HC_STAT_GEN_STAT15 0x000068c4
3587 #define BCE_HC_STAT_GEN_STAT_AC0 0x000068c8
3588 #define BCE_HC_STAT_GEN_STAT_AC1 0x000068cc
3589 #define BCE_HC_STAT_GEN_STAT_AC2 0x000068d0
3590 #define BCE_HC_STAT_GEN_STAT_AC3 0x000068d4
3591 #define BCE_HC_STAT_GEN_STAT_AC4 0x000068d8
3592 #define BCE_HC_STAT_GEN_STAT_AC5 0x000068dc
3593 #define BCE_HC_STAT_GEN_STAT_AC6 0x000068e0
3594 #define BCE_HC_STAT_GEN_STAT_AC7 0x000068e4
3595 #define BCE_HC_STAT_GEN_STAT_AC8 0x000068e8
3596 #define BCE_HC_STAT_GEN_STAT_AC9 0x000068ec
3597 #define BCE_HC_STAT_GEN_STAT_AC10 0x000068f0
3598 #define BCE_HC_STAT_GEN_STAT_AC11 0x000068f4
3599 #define BCE_HC_STAT_GEN_STAT_AC12 0x000068f8
3600 #define BCE_HC_STAT_GEN_STAT_AC13 0x000068fc
3601 #define BCE_HC_STAT_GEN_STAT_AC14 0x00006900
3602 #define BCE_HC_STAT_GEN_STAT_AC15 0x00006904
3603 #define BCE_HC_VIS 0x00006908
3604 #define BCE_HC_VIS_STAT_BUILD_STATE (0xfL<<0)
3605 #define BCE_HC_VIS_STAT_BUILD_STATE_IDLE (0L<<0)
3606 #define BCE_HC_VIS_STAT_BUILD_STATE_START (1L<<0)
3607 #define BCE_HC_VIS_STAT_BUILD_STATE_REQUEST (2L<<0)
3608 #define BCE_HC_VIS_STAT_BUILD_STATE_UPDATE64 (3L<<0)
3609 #define BCE_HC_VIS_STAT_BUILD_STATE_UPDATE32 (4L<<0)
3610 #define BCE_HC_VIS_STAT_BUILD_STATE_UPDATE_DONE (5L<<0)
3611 #define BCE_HC_VIS_STAT_BUILD_STATE_DMA (6L<<0)
3612 #define BCE_HC_VIS_STAT_BUILD_STATE_MSI_CONTROL (7L<<0)
3613 #define BCE_HC_VIS_STAT_BUILD_STATE_MSI_LOW (8L<<0)
3614 #define BCE_HC_VIS_STAT_BUILD_STATE_MSI_HIGH (9L<<0)
3615 #define BCE_HC_VIS_STAT_BUILD_STATE_MSI_DATA (10L<<0)
3616 #define BCE_HC_VIS_DMA_STAT_STATE (0xfL<<8)
3617 #define BCE_HC_VIS_DMA_STAT_STATE_IDLE (0L<<8)
3618 #define BCE_HC_VIS_DMA_STAT_STATE_STATUS_PARAM (1L<<8)
3619 #define BCE_HC_VIS_DMA_STAT_STATE_STATUS_DMA (2L<<8)
3620 #define BCE_HC_VIS_DMA_STAT_STATE_WRITE_COMP (3L<<8)
3621 #define BCE_HC_VIS_DMA_STAT_STATE_COMP (4L<<8)
3622 #define BCE_HC_VIS_DMA_STAT_STATE_STATISTIC_PARAM (5L<<8)
3623 #define BCE_HC_VIS_DMA_STAT_STATE_STATISTIC_DMA (6L<<8)
3624 #define BCE_HC_VIS_DMA_STAT_STATE_WRITE_COMP_1 (7L<<8)
3625 #define BCE_HC_VIS_DMA_STAT_STATE_WRITE_COMP_2 (8L<<8)
3626 #define BCE_HC_VIS_DMA_STAT_STATE_WAIT (9L<<8)
3627 #define BCE_HC_VIS_DMA_STAT_STATE_ABORT (15L<<8)
3628 #define BCE_HC_VIS_DMA_MSI_STATE (0x7L<<12)
3629 #define BCE_HC_VIS_STATISTIC_DMA_EN_STATE (0x3L<<15)
3630 #define BCE_HC_VIS_STATISTIC_DMA_EN_STATE_IDLE (0L<<15)
3631 #define BCE_HC_VIS_STATISTIC_DMA_EN_STATE_COUNT (1L<<15)
3632 #define BCE_HC_VIS_STATISTIC_DMA_EN_STATE_START (2L<<15)
3634 #define BCE_HC_VIS_1 0x0000690c
3635 #define BCE_HC_VIS_1_HW_INTACK_STATE (1L<<4)
3636 #define BCE_HC_VIS_1_HW_INTACK_STATE_IDLE (0L<<4)
3637 #define BCE_HC_VIS_1_HW_INTACK_STATE_COUNT (1L<<4)
3638 #define BCE_HC_VIS_1_SW_INTACK_STATE (1L<<5)
3639 #define BCE_HC_VIS_1_SW_INTACK_STATE_IDLE (0L<<5)
3640 #define BCE_HC_VIS_1_SW_INTACK_STATE_COUNT (1L<<5)
3641 #define BCE_HC_VIS_1_DURING_SW_INTACK_STATE (1L<<6)
3642 #define BCE_HC_VIS_1_DURING_SW_INTACK_STATE_IDLE (0L<<6)
3643 #define BCE_HC_VIS_1_DURING_SW_INTACK_STATE_COUNT (1L<<6)
3644 #define BCE_HC_VIS_1_MAILBOX_COUNT_STATE (1L<<7)
3645 #define BCE_HC_VIS_1_MAILBOX_COUNT_STATE_IDLE (0L<<7)
3646 #define BCE_HC_VIS_1_MAILBOX_COUNT_STATE_COUNT (1L<<7)
3647 #define BCE_HC_VIS_1_RAM_RD_ARB_STATE (0xfL<<17)
3648 #define BCE_HC_VIS_1_RAM_RD_ARB_STATE_IDLE (0L<<17)
3649 #define BCE_HC_VIS_1_RAM_RD_ARB_STATE_DMA (1L<<17)
3650 #define BCE_HC_VIS_1_RAM_RD_ARB_STATE_UPDATE (2L<<17)
3651 #define BCE_HC_VIS_1_RAM_RD_ARB_STATE_ASSIGN (3L<<17)
3652 #define BCE_HC_VIS_1_RAM_RD_ARB_STATE_WAIT (4L<<17)
3653 #define BCE_HC_VIS_1_RAM_RD_ARB_STATE_REG_UPDATE (5L<<17)
3654 #define BCE_HC_VIS_1_RAM_RD_ARB_STATE_REG_ASSIGN (6L<<17)
3655 #define BCE_HC_VIS_1_RAM_RD_ARB_STATE_REG_WAIT (7L<<17)
3656 #define BCE_HC_VIS_1_RAM_WR_ARB_STATE (0x3L<<21)
3657 #define BCE_HC_VIS_1_RAM_WR_ARB_STATE_NORMAL (0L<<21)
3658 #define BCE_HC_VIS_1_RAM_WR_ARB_STATE_CLEAR (1L<<21)
3659 #define BCE_HC_VIS_1_INT_GEN_STATE (1L<<23)
3660 #define BCE_HC_VIS_1_INT_GEN_STATE_DLE (0L<<23)
3661 #define BCE_HC_VIS_1_INT_GEN_STATE_NTERRUPT (1L<<23)
3662 #define BCE_HC_VIS_1_STAT_CHAN_ID (0x7L<<24)
3663 #define BCE_HC_VIS_1_INT_B (1L<<27)
3665 #define BCE_HC_DEBUG_VECT_PEEK 0x00006910
3666 #define BCE_HC_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
3667 #define BCE_HC_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
3668 #define BCE_HC_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
3669 #define BCE_HC_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
3670 #define BCE_HC_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
3671 #define BCE_HC_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
3676 * txp_reg definition
3679 #define BCE_TXP_CPU_MODE 0x00045000
3680 #define BCE_TXP_CPU_MODE_LOCAL_RST (1L<<0)
3681 #define BCE_TXP_CPU_MODE_STEP_ENA (1L<<1)
3682 #define BCE_TXP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2)
3683 #define BCE_TXP_CPU_MODE_PAGE_0_INST_ENA (1L<<3)
3684 #define BCE_TXP_CPU_MODE_MSG_BIT1 (1L<<6)
3685 #define BCE_TXP_CPU_MODE_INTERRUPT_ENA (1L<<7)
3686 #define BCE_TXP_CPU_MODE_SOFT_HALT (1L<<10)
3687 #define BCE_TXP_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11)
3688 #define BCE_TXP_CPU_MODE_BAD_INST_HALT_ENA (1L<<12)
3689 #define BCE_TXP_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13)
3690 #define BCE_TXP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15)
3692 #define BCE_TXP_CPU_STATE 0x00045004
3693 #define BCE_TXP_CPU_STATE_BREAKPOINT (1L<<0)
3694 #define BCE_TXP_CPU_STATE_BAD_INST_HALTED (1L<<2)
3695 #define BCE_TXP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3)
3696 #define BCE_TXP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4)
3697 #define BCE_TXP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5)
3698 #define BCE_TXP_CPU_STATE_BAD_pc_HALTED (1L<<6)
3699 #define BCE_TXP_CPU_STATE_ALIGN_HALTED (1L<<7)
3700 #define BCE_TXP_CPU_STATE_FIO_ABORT_HALTED (1L<<8)
3701 #define BCE_TXP_CPU_STATE_SOFT_HALTED (1L<<10)
3702 #define BCE_TXP_CPU_STATE_SPAD_UNDERFLOW (1L<<11)
3703 #define BCE_TXP_CPU_STATE_INTERRRUPT (1L<<12)
3704 #define BCE_TXP_CPU_STATE_DATA_ACCESS_STALL (1L<<14)
3705 #define BCE_TXP_CPU_STATE_INST_FETCH_STALL (1L<<15)
3706 #define BCE_TXP_CPU_STATE_BLOCKED_READ (1L<<31)
3708 #define BCE_TXP_CPU_EVENT_MASK 0x00045008
3709 #define BCE_TXP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0)
3710 #define BCE_TXP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2)
3711 #define BCE_TXP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3)
3712 #define BCE_TXP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4)
3713 #define BCE_TXP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5)
3714 #define BCE_TXP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6)
3715 #define BCE_TXP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7)
3716 #define BCE_TXP_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8)
3717 #define BCE_TXP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10)
3718 #define BCE_TXP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11)
3719 #define BCE_TXP_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12)
3721 #define BCE_TXP_CPU_PROGRAM_COUNTER 0x0004501c
3722 #define BCE_TXP_CPU_INSTRUCTION 0x00045020
3723 #define BCE_TXP_CPU_DATA_ACCESS 0x00045024
3724 #define BCE_TXP_CPU_INTERRUPT_ENABLE 0x00045028
3725 #define BCE_TXP_CPU_INTERRUPT_VECTOR 0x0004502c
3726 #define BCE_TXP_CPU_INTERRUPT_SAVED_PC 0x00045030
3727 #define BCE_TXP_CPU_HW_BREAKPOINT 0x00045034
3728 #define BCE_TXP_CPU_HW_BREAKPOINT_DISABLE (1L<<0)
3729 #define BCE_TXP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2)
3731 #define BCE_TXP_CPU_DEBUG_VECT_PEEK 0x00045038
3732 #define BCE_TXP_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
3733 #define BCE_TXP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
3734 #define BCE_TXP_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
3735 #define BCE_TXP_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
3736 #define BCE_TXP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
3737 #define BCE_TXP_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
3739 #define BCE_TXP_CPU_LAST_BRANCH_ADDR 0x00045048
3740 #define BCE_TXP_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1)
3741 #define BCE_TXP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1)
3742 #define BCE_TXP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1)
3743 #define BCE_TXP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2)
3745 #define BCE_TXP_CPU_REG_FILE 0x00045200
3746 #define BCE_TXP_FTQ_DATA 0x000453c0
3747 #define BCE_TXP_FTQ_CMD 0x000453f8
3748 #define BCE_TXP_FTQ_CMD_OFFSET (0x3ffL<<0)
3749 #define BCE_TXP_FTQ_CMD_WR_TOP (1L<<10)
3750 #define BCE_TXP_FTQ_CMD_WR_TOP_0 (0L<<10)
3751 #define BCE_TXP_FTQ_CMD_WR_TOP_1 (1L<<10)
3752 #define BCE_TXP_FTQ_CMD_SFT_RESET (1L<<25)
3753 #define BCE_TXP_FTQ_CMD_RD_DATA (1L<<26)
3754 #define BCE_TXP_FTQ_CMD_ADD_INTERVEN (1L<<27)
3755 #define BCE_TXP_FTQ_CMD_ADD_DATA (1L<<28)
3756 #define BCE_TXP_FTQ_CMD_INTERVENE_CLR (1L<<29)
3757 #define BCE_TXP_FTQ_CMD_POP (1L<<30)
3758 #define BCE_TXP_FTQ_CMD_BUSY (1L<<31)
3760 #define BCE_TXP_FTQ_CTL 0x000453fc
3761 #define BCE_TXP_FTQ_CTL_INTERVENE (1L<<0)
3762 #define BCE_TXP_FTQ_CTL_OVERFLOW (1L<<1)
3763 #define BCE_TXP_FTQ_CTL_FORCE_INTERVENE (1L<<2)
3764 #define BCE_TXP_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
3765 #define BCE_TXP_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
3767 #define BCE_TXP_SCRATCH 0x00060000
3771 * tpat_reg definition
3774 #define BCE_TPAT_CPU_MODE 0x00085000
3775 #define BCE_TPAT_CPU_MODE_LOCAL_RST (1L<<0)
3776 #define BCE_TPAT_CPU_MODE_STEP_ENA (1L<<1)
3777 #define BCE_TPAT_CPU_MODE_PAGE_0_DATA_ENA (1L<<2)
3778 #define BCE_TPAT_CPU_MODE_PAGE_0_INST_ENA (1L<<3)
3779 #define BCE_TPAT_CPU_MODE_MSG_BIT1 (1L<<6)
3780 #define BCE_TPAT_CPU_MODE_INTERRUPT_ENA (1L<<7)
3781 #define BCE_TPAT_CPU_MODE_SOFT_HALT (1L<<10)
3782 #define BCE_TPAT_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11)
3783 #define BCE_TPAT_CPU_MODE_BAD_INST_HALT_ENA (1L<<12)
3784 #define BCE_TPAT_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13)
3785 #define BCE_TPAT_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15)
3787 #define BCE_TPAT_CPU_STATE 0x00085004
3788 #define BCE_TPAT_CPU_STATE_BREAKPOINT (1L<<0)
3789 #define BCE_TPAT_CPU_STATE_BAD_INST_HALTED (1L<<2)
3790 #define BCE_TPAT_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3)
3791 #define BCE_TPAT_CPU_STATE_PAGE_0_INST_HALTED (1L<<4)
3792 #define BCE_TPAT_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5)
3793 #define BCE_TPAT_CPU_STATE_BAD_pc_HALTED (1L<<6)
3794 #define BCE_TPAT_CPU_STATE_ALIGN_HALTED (1L<<7)
3795 #define BCE_TPAT_CPU_STATE_FIO_ABORT_HALTED (1L<<8)
3796 #define BCE_TPAT_CPU_STATE_SOFT_HALTED (1L<<10)
3797 #define BCE_TPAT_CPU_STATE_SPAD_UNDERFLOW (1L<<11)
3798 #define BCE_TPAT_CPU_STATE_INTERRRUPT (1L<<12)
3799 #define BCE_TPAT_CPU_STATE_DATA_ACCESS_STALL (1L<<14)
3800 #define BCE_TPAT_CPU_STATE_INST_FETCH_STALL (1L<<15)
3801 #define BCE_TPAT_CPU_STATE_BLOCKED_READ (1L<<31)
3803 #define BCE_TPAT_CPU_EVENT_MASK 0x00085008
3804 #define BCE_TPAT_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0)
3805 #define BCE_TPAT_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2)
3806 #define BCE_TPAT_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3)
3807 #define BCE_TPAT_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4)
3808 #define BCE_TPAT_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5)
3809 #define BCE_TPAT_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6)
3810 #define BCE_TPAT_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7)
3811 #define BCE_TPAT_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8)
3812 #define BCE_TPAT_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10)
3813 #define BCE_TPAT_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11)
3814 #define BCE_TPAT_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12)
3816 #define BCE_TPAT_CPU_PROGRAM_COUNTER 0x0008501c
3817 #define BCE_TPAT_CPU_INSTRUCTION 0x00085020
3818 #define BCE_TPAT_CPU_DATA_ACCESS 0x00085024
3819 #define BCE_TPAT_CPU_INTERRUPT_ENABLE 0x00085028
3820 #define BCE_TPAT_CPU_INTERRUPT_VECTOR 0x0008502c
3821 #define BCE_TPAT_CPU_INTERRUPT_SAVED_PC 0x00085030
3822 #define BCE_TPAT_CPU_HW_BREAKPOINT 0x00085034
3823 #define BCE_TPAT_CPU_HW_BREAKPOINT_DISABLE (1L<<0)
3824 #define BCE_TPAT_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2)
3826 #define BCE_TPAT_CPU_DEBUG_VECT_PEEK 0x00085038
3827 #define BCE_TPAT_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
3828 #define BCE_TPAT_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
3829 #define BCE_TPAT_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
3830 #define BCE_TPAT_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
3831 #define BCE_TPAT_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
3832 #define BCE_TPAT_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
3834 #define BCE_TPAT_CPU_LAST_BRANCH_ADDR 0x00085048
3835 #define BCE_TPAT_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1)
3836 #define BCE_TPAT_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1)
3837 #define BCE_TPAT_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1)
3838 #define BCE_TPAT_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2)
3840 #define BCE_TPAT_CPU_REG_FILE 0x00085200
3841 #define BCE_TPAT_FTQ_DATA 0x000853c0
3842 #define BCE_TPAT_FTQ_CMD 0x000853f8
3843 #define BCE_TPAT_FTQ_CMD_OFFSET (0x3ffL<<0)
3844 #define BCE_TPAT_FTQ_CMD_WR_TOP (1L<<10)
3845 #define BCE_TPAT_FTQ_CMD_WR_TOP_0 (0L<<10)
3846 #define BCE_TPAT_FTQ_CMD_WR_TOP_1 (1L<<10)
3847 #define BCE_TPAT_FTQ_CMD_SFT_RESET (1L<<25)
3848 #define BCE_TPAT_FTQ_CMD_RD_DATA (1L<<26)
3849 #define BCE_TPAT_FTQ_CMD_ADD_INTERVEN (1L<<27)
3850 #define BCE_TPAT_FTQ_CMD_ADD_DATA (1L<<28)
3851 #define BCE_TPAT_FTQ_CMD_INTERVENE_CLR (1L<<29)
3852 #define BCE_TPAT_FTQ_CMD_POP (1L<<30)
3853 #define BCE_TPAT_FTQ_CMD_BUSY (1L<<31)
3855 #define BCE_TPAT_FTQ_CTL 0x000853fc
3856 #define BCE_TPAT_FTQ_CTL_INTERVENE (1L<<0)
3857 #define BCE_TPAT_FTQ_CTL_OVERFLOW (1L<<1)
3858 #define BCE_TPAT_FTQ_CTL_FORCE_INTERVENE (1L<<2)
3859 #define BCE_TPAT_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
3860 #define BCE_TPAT_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
3862 #define BCE_TPAT_SCRATCH 0x000a0000
3866 * rxp_reg definition
3869 #define BCE_RXP_CPU_MODE 0x000c5000
3870 #define BCE_RXP_CPU_MODE_LOCAL_RST (1L<<0)
3871 #define BCE_RXP_CPU_MODE_STEP_ENA (1L<<1)
3872 #define BCE_RXP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2)
3873 #define BCE_RXP_CPU_MODE_PAGE_0_INST_ENA (1L<<3)
3874 #define BCE_RXP_CPU_MODE_MSG_BIT1 (1L<<6)
3875 #define BCE_RXP_CPU_MODE_INTERRUPT_ENA (1L<<7)
3876 #define BCE_RXP_CPU_MODE_SOFT_HALT (1L<<10)
3877 #define BCE_RXP_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11)
3878 #define BCE_RXP_CPU_MODE_BAD_INST_HALT_ENA (1L<<12)
3879 #define BCE_RXP_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13)
3880 #define BCE_RXP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15)
3882 #define BCE_RXP_CPU_STATE 0x000c5004
3883 #define BCE_RXP_CPU_STATE_BREAKPOINT (1L<<0)
3884 #define BCE_RXP_CPU_STATE_BAD_INST_HALTED (1L<<2)
3885 #define BCE_RXP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3)
3886 #define BCE_RXP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4)
3887 #define BCE_RXP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5)
3888 #define BCE_RXP_CPU_STATE_BAD_pc_HALTED (1L<<6)
3889 #define BCE_RXP_CPU_STATE_ALIGN_HALTED (1L<<7)
3890 #define BCE_RXP_CPU_STATE_FIO_ABORT_HALTED (1L<<8)
3891 #define BCE_RXP_CPU_STATE_SOFT_HALTED (1L<<10)
3892 #define BCE_RXP_CPU_STATE_SPAD_UNDERFLOW (1L<<11)
3893 #define BCE_RXP_CPU_STATE_INTERRRUPT (1L<<12)
3894 #define BCE_RXP_CPU_STATE_DATA_ACCESS_STALL (1L<<14)
3895 #define BCE_RXP_CPU_STATE_INST_FETCH_STALL (1L<<15)
3896 #define BCE_RXP_CPU_STATE_BLOCKED_READ (1L<<31)
3898 #define BCE_RXP_CPU_EVENT_MASK 0x000c5008
3899 #define BCE_RXP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0)
3900 #define BCE_RXP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2)
3901 #define BCE_RXP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3)
3902 #define BCE_RXP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4)
3903 #define BCE_RXP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5)
3904 #define BCE_RXP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6)
3905 #define BCE_RXP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7)
3906 #define BCE_RXP_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8)
3907 #define BCE_RXP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10)
3908 #define BCE_RXP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11)
3909 #define BCE_RXP_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12)
3911 #define BCE_RXP_CPU_PROGRAM_COUNTER 0x000c501c
3912 #define BCE_RXP_CPU_INSTRUCTION 0x000c5020
3913 #define BCE_RXP_CPU_DATA_ACCESS 0x000c5024
3914 #define BCE_RXP_CPU_INTERRUPT_ENABLE 0x000c5028
3915 #define BCE_RXP_CPU_INTERRUPT_VECTOR 0x000c502c
3916 #define BCE_RXP_CPU_INTERRUPT_SAVED_PC 0x000c5030
3917 #define BCE_RXP_CPU_HW_BREAKPOINT 0x000c5034
3918 #define BCE_RXP_CPU_HW_BREAKPOINT_DISABLE (1L<<0)
3919 #define BCE_RXP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2)
3921 #define BCE_RXP_CPU_DEBUG_VECT_PEEK 0x000c5038
3922 #define BCE_RXP_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
3923 #define BCE_RXP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
3924 #define BCE_RXP_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
3925 #define BCE_RXP_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
3926 #define BCE_RXP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
3927 #define BCE_RXP_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
3929 #define BCE_RXP_CPU_LAST_BRANCH_ADDR 0x000c5048
3930 #define BCE_RXP_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1)
3931 #define BCE_RXP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1)
3932 #define BCE_RXP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1)
3933 #define BCE_RXP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2)
3935 #define BCE_RXP_CPU_REG_FILE 0x000c5200
3936 #define BCE_RXP_CFTQ_DATA 0x000c5380
3937 #define BCE_RXP_CFTQ_CMD 0x000c53b8
3938 #define BCE_RXP_CFTQ_CMD_OFFSET (0x3ffL<<0)
3939 #define BCE_RXP_CFTQ_CMD_WR_TOP (1L<<10)
3940 #define BCE_RXP_CFTQ_CMD_WR_TOP_0 (0L<<10)
3941 #define BCE_RXP_CFTQ_CMD_WR_TOP_1 (1L<<10)
3942 #define BCE_RXP_CFTQ_CMD_SFT_RESET (1L<<25)
3943 #define BCE_RXP_CFTQ_CMD_RD_DATA (1L<<26)
3944 #define BCE_RXP_CFTQ_CMD_ADD_INTERVEN (1L<<27)
3945 #define BCE_RXP_CFTQ_CMD_ADD_DATA (1L<<28)
3946 #define BCE_RXP_CFTQ_CMD_INTERVENE_CLR (1L<<29)
3947 #define BCE_RXP_CFTQ_CMD_POP (1L<<30)
3948 #define BCE_RXP_CFTQ_CMD_BUSY (1L<<31)
3950 #define BCE_RXP_CFTQ_CTL 0x000c53bc
3951 #define BCE_RXP_CFTQ_CTL_INTERVENE (1L<<0)
3952 #define BCE_RXP_CFTQ_CTL_OVERFLOW (1L<<1)
3953 #define BCE_RXP_CFTQ_CTL_FORCE_INTERVENE (1L<<2)
3954 #define BCE_RXP_CFTQ_CTL_MAX_DEPTH (0x3ffL<<12)
3955 #define BCE_RXP_CFTQ_CTL_CUR_DEPTH (0x3ffL<<22)
3957 #define BCE_RXP_FTQ_DATA 0x000c53c0
3958 #define BCE_RXP_FTQ_CMD 0x000c53f8
3959 #define BCE_RXP_FTQ_CMD_OFFSET (0x3ffL<<0)
3960 #define BCE_RXP_FTQ_CMD_WR_TOP (1L<<10)
3961 #define BCE_RXP_FTQ_CMD_WR_TOP_0 (0L<<10)
3962 #define BCE_RXP_FTQ_CMD_WR_TOP_1 (1L<<10)
3963 #define BCE_RXP_FTQ_CMD_SFT_RESET (1L<<25)
3964 #define BCE_RXP_FTQ_CMD_RD_DATA (1L<<26)
3965 #define BCE_RXP_FTQ_CMD_ADD_INTERVEN (1L<<27)
3966 #define BCE_RXP_FTQ_CMD_ADD_DATA (1L<<28)
3967 #define BCE_RXP_FTQ_CMD_INTERVENE_CLR (1L<<29)
3968 #define BCE_RXP_FTQ_CMD_POP (1L<<30)
3969 #define BCE_RXP_FTQ_CMD_BUSY (1L<<31)
3971 #define BCE_RXP_FTQ_CTL 0x000c53fc
3972 #define BCE_RXP_FTQ_CTL_INTERVENE (1L<<0)
3973 #define BCE_RXP_FTQ_CTL_OVERFLOW (1L<<1)
3974 #define BCE_RXP_FTQ_CTL_FORCE_INTERVENE (1L<<2)
3975 #define BCE_RXP_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
3976 #define BCE_RXP_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
3978 #define BCE_RXP_SCRATCH 0x000e0000
3982 * com_reg definition
3985 #define BCE_COM_CPU_MODE 0x00105000
3986 #define BCE_COM_CPU_MODE_LOCAL_RST (1L<<0)
3987 #define BCE_COM_CPU_MODE_STEP_ENA (1L<<1)
3988 #define BCE_COM_CPU_MODE_PAGE_0_DATA_ENA (1L<<2)
3989 #define BCE_COM_CPU_MODE_PAGE_0_INST_ENA (1L<<3)
3990 #define BCE_COM_CPU_MODE_MSG_BIT1 (1L<<6)
3991 #define BCE_COM_CPU_MODE_INTERRUPT_ENA (1L<<7)
3992 #define BCE_COM_CPU_MODE_SOFT_HALT (1L<<10)
3993 #define BCE_COM_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11)
3994 #define BCE_COM_CPU_MODE_BAD_INST_HALT_ENA (1L<<12)
3995 #define BCE_COM_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13)
3996 #define BCE_COM_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15)
3998 #define BCE_COM_CPU_STATE 0x00105004
3999 #define BCE_COM_CPU_STATE_BREAKPOINT (1L<<0)
4000 #define BCE_COM_CPU_STATE_BAD_INST_HALTED (1L<<2)
4001 #define BCE_COM_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3)
4002 #define BCE_COM_CPU_STATE_PAGE_0_INST_HALTED (1L<<4)
4003 #define BCE_COM_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5)
4004 #define BCE_COM_CPU_STATE_BAD_pc_HALTED (1L<<6)
4005 #define BCE_COM_CPU_STATE_ALIGN_HALTED (1L<<7)
4006 #define BCE_COM_CPU_STATE_FIO_ABORT_HALTED (1L<<8)
4007 #define BCE_COM_CPU_STATE_SOFT_HALTED (1L<<10)
4008 #define BCE_COM_CPU_STATE_SPAD_UNDERFLOW (1L<<11)
4009 #define BCE_COM_CPU_STATE_INTERRRUPT (1L<<12)
4010 #define BCE_COM_CPU_STATE_DATA_ACCESS_STALL (1L<<14)
4011 #define BCE_COM_CPU_STATE_INST_FETCH_STALL (1L<<15)
4012 #define BCE_COM_CPU_STATE_BLOCKED_READ (1L<<31)
4014 #define BCE_COM_CPU_EVENT_MASK 0x00105008
4015 #define BCE_COM_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0)
4016 #define BCE_COM_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2)
4017 #define BCE_COM_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3)
4018 #define BCE_COM_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4)
4019 #define BCE_COM_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5)
4020 #define BCE_COM_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6)
4021 #define BCE_COM_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7)
4022 #define BCE_COM_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8)
4023 #define BCE_COM_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10)
4024 #define BCE_COM_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11)
4025 #define BCE_COM_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12)
4027 #define BCE_COM_CPU_PROGRAM_COUNTER 0x0010501c
4028 #define BCE_COM_CPU_INSTRUCTION 0x00105020
4029 #define BCE_COM_CPU_DATA_ACCESS 0x00105024
4030 #define BCE_COM_CPU_INTERRUPT_ENABLE 0x00105028
4031 #define BCE_COM_CPU_INTERRUPT_VECTOR 0x0010502c
4032 #define BCE_COM_CPU_INTERRUPT_SAVED_PC 0x00105030
4033 #define BCE_COM_CPU_HW_BREAKPOINT 0x00105034
4034 #define BCE_COM_CPU_HW_BREAKPOINT_DISABLE (1L<<0)
4035 #define BCE_COM_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2)
4037 #define BCE_COM_CPU_DEBUG_VECT_PEEK 0x00105038
4038 #define BCE_COM_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
4039 #define BCE_COM_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
4040 #define BCE_COM_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
4041 #define BCE_COM_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
4042 #define BCE_COM_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
4043 #define BCE_COM_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
4045 #define BCE_COM_CPU_LAST_BRANCH_ADDR 0x00105048
4046 #define BCE_COM_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1)
4047 #define BCE_COM_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1)
4048 #define BCE_COM_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1)
4049 #define BCE_COM_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2)
4051 #define BCE_COM_CPU_REG_FILE 0x00105200
4052 #define BCE_COM_COMXQ_FTQ_DATA 0x00105340
4053 #define BCE_COM_COMXQ_FTQ_CMD 0x00105378
4054 #define BCE_COM_COMXQ_FTQ_CMD_OFFSET (0x3ffL<<0)
4055 #define BCE_COM_COMXQ_FTQ_CMD_WR_TOP (1L<<10)
4056 #define BCE_COM_COMXQ_FTQ_CMD_WR_TOP_0 (0L<<10)
4057 #define BCE_COM_COMXQ_FTQ_CMD_WR_TOP_1 (1L<<10)
4058 #define BCE_COM_COMXQ_FTQ_CMD_SFT_RESET (1L<<25)
4059 #define BCE_COM_COMXQ_FTQ_CMD_RD_DATA (1L<<26)
4060 #define BCE_COM_COMXQ_FTQ_CMD_ADD_INTERVEN (1L<<27)
4061 #define BCE_COM_COMXQ_FTQ_CMD_ADD_DATA (1L<<28)
4062 #define BCE_COM_COMXQ_FTQ_CMD_INTERVENE_CLR (1L<<29)
4063 #define BCE_COM_COMXQ_FTQ_CMD_POP (1L<<30)
4064 #define BCE_COM_COMXQ_FTQ_CMD_BUSY (1L<<31)
4066 #define BCE_COM_COMXQ_FTQ_CTL 0x0010537c
4067 #define BCE_COM_COMXQ_FTQ_CTL_INTERVENE (1L<<0)
4068 #define BCE_COM_COMXQ_FTQ_CTL_OVERFLOW (1L<<1)
4069 #define BCE_COM_COMXQ_FTQ_CTL_FORCE_INTERVENE (1L<<2)
4070 #define BCE_COM_COMXQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
4071 #define BCE_COM_COMXQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
4073 #define BCE_COM_COMTQ_FTQ_DATA 0x00105380
4074 #define BCE_COM_COMTQ_FTQ_CMD 0x001053b8
4075 #define BCE_COM_COMTQ_FTQ_CMD_OFFSET (0x3ffL<<0)
4076 #define BCE_COM_COMTQ_FTQ_CMD_WR_TOP (1L<<10)
4077 #define BCE_COM_COMTQ_FTQ_CMD_WR_TOP_0 (0L<<10)
4078 #define BCE_COM_COMTQ_FTQ_CMD_WR_TOP_1 (1L<<10)
4079 #define BCE_COM_COMTQ_FTQ_CMD_SFT_RESET (1L<<25)
4080 #define BCE_COM_COMTQ_FTQ_CMD_RD_DATA (1L<<26)
4081 #define BCE_COM_COMTQ_FTQ_CMD_ADD_INTERVEN (1L<<27)
4082 #define BCE_COM_COMTQ_FTQ_CMD_ADD_DATA (1L<<28)
4083 #define BCE_COM_COMTQ_FTQ_CMD_INTERVENE_CLR (1L<<29)
4084 #define BCE_COM_COMTQ_FTQ_CMD_POP (1L<<30)
4085 #define BCE_COM_COMTQ_FTQ_CMD_BUSY (1L<<31)
4087 #define BCE_COM_COMTQ_FTQ_CTL 0x001053bc
4088 #define BCE_COM_COMTQ_FTQ_CTL_INTERVENE (1L<<0)
4089 #define BCE_COM_COMTQ_FTQ_CTL_OVERFLOW (1L<<1)
4090 #define BCE_COM_COMTQ_FTQ_CTL_FORCE_INTERVENE (1L<<2)
4091 #define BCE_COM_COMTQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
4092 #define BCE_COM_COMTQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
4094 #define BCE_COM_COMQ_FTQ_DATA 0x001053c0
4095 #define BCE_COM_COMQ_FTQ_CMD 0x001053f8
4096 #define BCE_COM_COMQ_FTQ_CMD_OFFSET (0x3ffL<<0)
4097 #define BCE_COM_COMQ_FTQ_CMD_WR_TOP (1L<<10)
4098 #define BCE_COM_COMQ_FTQ_CMD_WR_TOP_0 (0L<<10)
4099 #define BCE_COM_COMQ_FTQ_CMD_WR_TOP_1 (1L<<10)
4100 #define BCE_COM_COMQ_FTQ_CMD_SFT_RESET (1L<<25)
4101 #define BCE_COM_COMQ_FTQ_CMD_RD_DATA (1L<<26)
4102 #define BCE_COM_COMQ_FTQ_CMD_ADD_INTERVEN (1L<<27)
4103 #define BCE_COM_COMQ_FTQ_CMD_ADD_DATA (1L<<28)
4104 #define BCE_COM_COMQ_FTQ_CMD_INTERVENE_CLR (1L<<29)
4105 #define BCE_COM_COMQ_FTQ_CMD_POP (1L<<30)
4106 #define BCE_COM_COMQ_FTQ_CMD_BUSY (1L<<31)
4108 #define BCE_COM_COMQ_FTQ_CTL 0x001053fc
4109 #define BCE_COM_COMQ_FTQ_CTL_INTERVENE (1L<<0)
4110 #define BCE_COM_COMQ_FTQ_CTL_OVERFLOW (1L<<1)
4111 #define BCE_COM_COMQ_FTQ_CTL_FORCE_INTERVENE (1L<<2)
4112 #define BCE_COM_COMQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
4113 #define BCE_COM_COMQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
4115 #define BCE_COM_SCRATCH 0x00120000
4122 #define BCE_CP_CPU_MODE 0x00185000
4123 #define BCE_CP_CPU_MODE_LOCAL_RST (1L<<0)
4124 #define BCE_CP_CPU_MODE_STEP_ENA (1L<<1)
4125 #define BCE_CP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2)
4126 #define BCE_CP_CPU_MODE_PAGE_0_INST_ENA (1L<<3)
4127 #define BCE_CP_CPU_MODE_MSG_BIT1 (1L<<6)
4128 #define BCE_CP_CPU_MODE_INTERRUPT_ENA (1L<<7)
4129 #define BCE_CP_CPU_MODE_SOFT_HALT (1L<<10)
4130 #define BCE_CP_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11)
4131 #define BCE_CP_CPU_MODE_BAD_INST_HALT_ENA (1L<<12)
4132 #define BCE_CP_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13)
4133 #define BCE_CP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15)
4135 #define BCE_CP_CPU_STATE 0x00185004
4136 #define BCE_CP_CPU_STATE_BREAKPOINT (1L<<0)
4137 #define BCE_CP_CPU_STATE_BAD_INST_HALTED (1L<<2)
4138 #define BCE_CP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3)
4139 #define BCE_CP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4)
4140 #define BCE_CP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5)
4141 #define BCE_CP_CPU_STATE_BAD_pc_HALTED (1L<<6)
4142 #define BCE_CP_CPU_STATE_ALIGN_HALTED (1L<<7)
4143 #define BCE_CP_CPU_STATE_FIO_ABORT_HALTED (1L<<8)
4144 #define BCE_CP_CPU_STATE_SOFT_HALTED (1L<<10)
4145 #define BCE_CP_CPU_STATE_SPAD_UNDERFLOW (1L<<11)
4146 #define BCE_CP_CPU_STATE_INTERRRUPT (1L<<12)
4147 #define BCE_CP_CPU_STATE_DATA_ACCESS_STALL (1L<<14)
4148 #define BCE_CP_CPU_STATE_INST_FETCH_STALL (1L<<15)
4149 #define BCE_CP_CPU_STATE_BLOCKED_READ (1L<<31)
4151 #define BCE_CP_CPU_EVENT_MASK 0x00185008
4152 #define BCE_CP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0)
4153 #define BCE_CP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2)
4154 #define BCE_CP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3)
4155 #define BCE_CP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4)
4156 #define BCE_CP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5)
4157 #define BCE_CP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6)
4158 #define BCE_CP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7)
4159 #define BCE_CP_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8)
4160 #define BCE_CP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10)
4161 #define BCE_CP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11)
4162 #define BCE_CP_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12)
4164 #define BCE_CP_CPU_PROGRAM_COUNTER 0x0018501c
4165 #define BCE_CP_CPU_INSTRUCTION 0x00185020
4166 #define BCE_CP_CPU_DATA_ACCESS 0x00185024
4167 #define BCE_CP_CPU_INTERRUPT_ENABLE 0x00185028
4168 #define BCE_CP_CPU_INTERRUPT_VECTOR 0x0018502c
4169 #define BCE_CP_CPU_INTERRUPT_SAVED_PC 0x00185030
4170 #define BCE_CP_CPU_HW_BREAKPOINT 0x00185034
4171 #define BCE_CP_CPU_HW_BREAKPOINT_DISABLE (1L<<0)
4172 #define BCE_CP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2)
4174 #define BCE_CP_CPU_DEBUG_VECT_PEEK 0x00185038
4175 #define BCE_CP_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
4176 #define BCE_CP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
4177 #define BCE_CP_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
4178 #define BCE_CP_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
4179 #define BCE_CP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
4180 #define BCE_CP_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
4182 #define BCE_CP_CPU_LAST_BRANCH_ADDR 0x00185048
4183 #define BCE_CP_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1)
4184 #define BCE_CP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1)
4185 #define BCE_CP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1)
4186 #define BCE_CP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2)
4188 #define BCE_CP_CPU_REG_FILE 0x00185200
4189 #define BCE_CP_CPQ_FTQ_DATA 0x001853c0
4190 #define BCE_CP_CPQ_FTQ_CMD 0x001853f8
4191 #define BCE_CP_CPQ_FTQ_CMD_OFFSET (0x3ffL<<0)
4192 #define BCE_CP_CPQ_FTQ_CMD_WR_TOP (1L<<10)
4193 #define BCE_CP_CPQ_FTQ_CMD_WR_TOP_0 (0L<<10)
4194 #define BCE_CP_CPQ_FTQ_CMD_WR_TOP_1 (1L<<10)
4195 #define BCE_CP_CPQ_FTQ_CMD_SFT_RESET (1L<<25)
4196 #define BCE_CP_CPQ_FTQ_CMD_RD_DATA (1L<<26)
4197 #define BCE_CP_CPQ_FTQ_CMD_ADD_INTERVEN (1L<<27)
4198 #define BCE_CP_CPQ_FTQ_CMD_ADD_DATA (1L<<28)
4199 #define BCE_CP_CPQ_FTQ_CMD_INTERVENE_CLR (1L<<29)
4200 #define BCE_CP_CPQ_FTQ_CMD_POP (1L<<30)
4201 #define BCE_CP_CPQ_FTQ_CMD_BUSY (1L<<31)
4203 #define BCE_CP_CPQ_FTQ_CTL 0x001853fc
4204 #define BCE_CP_CPQ_FTQ_CTL_INTERVENE (1L<<0)
4205 #define BCE_CP_CPQ_FTQ_CTL_OVERFLOW (1L<<1)
4206 #define BCE_CP_CPQ_FTQ_CTL_FORCE_INTERVENE (1L<<2)
4207 #define BCE_CP_CPQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
4208 #define BCE_CP_CPQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
4210 #define BCE_CP_SCRATCH 0x001a0000
4214 * mcp_reg definition
4217 #define BCE_MCP_CPU_MODE 0x00145000
4218 #define BCE_MCP_CPU_MODE_LOCAL_RST (1L<<0)
4219 #define BCE_MCP_CPU_MODE_STEP_ENA (1L<<1)
4220 #define BCE_MCP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2)
4221 #define BCE_MCP_CPU_MODE_PAGE_0_INST_ENA (1L<<3)
4222 #define BCE_MCP_CPU_MODE_MSG_BIT1 (1L<<6)
4223 #define BCE_MCP_CPU_MODE_INTERRUPT_ENA (1L<<7)
4224 #define BCE_MCP_CPU_MODE_SOFT_HALT (1L<<10)
4225 #define BCE_MCP_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11)
4226 #define BCE_MCP_CPU_MODE_BAD_INST_HALT_ENA (1L<<12)
4227 #define BCE_MCP_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13)
4228 #define BCE_MCP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15)
4230 #define BCE_MCP_CPU_STATE 0x00145004
4231 #define BCE_MCP_CPU_STATE_BREAKPOINT (1L<<0)
4232 #define BCE_MCP_CPU_STATE_BAD_INST_HALTED (1L<<2)
4233 #define BCE_MCP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3)
4234 #define BCE_MCP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4)
4235 #define BCE_MCP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5)
4236 #define BCE_MCP_CPU_STATE_BAD_pc_HALTED (1L<<6)
4237 #define BCE_MCP_CPU_STATE_ALIGN_HALTED (1L<<7)
4238 #define BCE_MCP_CPU_STATE_FIO_ABORT_HALTED (1L<<8)
4239 #define BCE_MCP_CPU_STATE_SOFT_HALTED (1L<<10)
4240 #define BCE_MCP_CPU_STATE_SPAD_UNDERFLOW (1L<<11)
4241 #define BCE_MCP_CPU_STATE_INTERRRUPT (1L<<12)
4242 #define BCE_MCP_CPU_STATE_DATA_ACCESS_STALL (1L<<14)
4243 #define BCE_MCP_CPU_STATE_INST_FETCH_STALL (1L<<15)
4244 #define BCE_MCP_CPU_STATE_BLOCKED_READ (1L<<31)
4246 #define BCE_MCP_CPU_EVENT_MASK 0x00145008
4247 #define BCE_MCP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0)
4248 #define BCE_MCP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2)
4249 #define BCE_MCP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3)
4250 #define BCE_MCP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4)
4251 #define BCE_MCP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5)
4252 #define BCE_MCP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6)
4253 #define BCE_MCP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7)
4254 #define BCE_MCP_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8)
4255 #define BCE_MCP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10)
4256 #define BCE_MCP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11)
4257 #define BCE_MCP_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12)
4259 #define BCE_MCP_CPU_PROGRAM_COUNTER 0x0014501c
4260 #define BCE_MCP_CPU_INSTRUCTION 0x00145020
4261 #define BCE_MCP_CPU_DATA_ACCESS 0x00145024
4262 #define BCE_MCP_CPU_INTERRUPT_ENABLE 0x00145028
4263 #define BCE_MCP_CPU_INTERRUPT_VECTOR 0x0014502c
4264 #define BCE_MCP_CPU_INTERRUPT_SAVED_PC 0x00145030
4265 #define BCE_MCP_CPU_HW_BREAKPOINT 0x00145034
4266 #define BCE_MCP_CPU_HW_BREAKPOINT_DISABLE (1L<<0)
4267 #define BCE_MCP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2)
4269 #define BCE_MCP_CPU_DEBUG_VECT_PEEK 0x00145038
4270 #define BCE_MCP_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
4271 #define BCE_MCP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
4272 #define BCE_MCP_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
4273 #define BCE_MCP_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
4274 #define BCE_MCP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
4275 #define BCE_MCP_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
4277 #define BCE_MCP_CPU_LAST_BRANCH_ADDR 0x00145048
4278 #define BCE_MCP_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1)
4279 #define BCE_MCP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1)
4280 #define BCE_MCP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1)
4281 #define BCE_MCP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2)
4283 #define BCE_MCP_CPU_REG_FILE 0x00145200
4284 #define BCE_MCP_MCPQ_FTQ_DATA 0x001453c0
4285 #define BCE_MCP_MCPQ_FTQ_CMD 0x001453f8
4286 #define BCE_MCP_MCPQ_FTQ_CMD_OFFSET (0x3ffL<<0)
4287 #define BCE_MCP_MCPQ_FTQ_CMD_WR_TOP (1L<<10)
4288 #define BCE_MCP_MCPQ_FTQ_CMD_WR_TOP_0 (0L<<10)
4289 #define BCE_MCP_MCPQ_FTQ_CMD_WR_TOP_1 (1L<<10)
4290 #define BCE_MCP_MCPQ_FTQ_CMD_SFT_RESET (1L<<25)
4291 #define BCE_MCP_MCPQ_FTQ_CMD_RD_DATA (1L<<26)
4292 #define BCE_MCP_MCPQ_FTQ_CMD_ADD_INTERVEN (1L<<27)
4293 #define BCE_MCP_MCPQ_FTQ_CMD_ADD_DATA (1L<<28)
4294 #define BCE_MCP_MCPQ_FTQ_CMD_INTERVENE_CLR (1L<<29)
4295 #define BCE_MCP_MCPQ_FTQ_CMD_POP (1L<<30)
4296 #define BCE_MCP_MCPQ_FTQ_CMD_BUSY (1L<<31)
4298 #define BCE_MCP_MCPQ_FTQ_CTL 0x001453fc
4299 #define BCE_MCP_MCPQ_FTQ_CTL_INTERVENE (1L<<0)
4300 #define BCE_MCP_MCPQ_FTQ_CTL_OVERFLOW (1L<<1)
4301 #define BCE_MCP_MCPQ_FTQ_CTL_FORCE_INTERVENE (1L<<2)
4302 #define BCE_MCP_MCPQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
4303 #define BCE_MCP_MCPQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
4305 #define BCE_MCP_ROM 0x00150000
4306 #define BCE_MCP_SCRATCH 0x00160000
4308 #define BCE_SHM_HDR_SIGNATURE BCE_MCP_SCRATCH
4309 #define BCE_SHM_HDR_SIGNATURE_SIG_MASK 0xffff0000
4310 #define BCE_SHM_HDR_SIGNATURE_SIG 0x53530000
4311 #define BCE_SHM_HDR_SIGNATURE_VER_MASK 0x000000ff
4312 #define BCE_SHM_HDR_SIGNATURE_VER_ONE 0x00000001
4314 #define BCE_SHM_HDR_ADDR_0 BCE_MCP_SCRATCH + 4
4315 #define BCE_SHM_HDR_ADDR_1 BCE_MCP_SCRATCH + 8
4317 /****************************************************************************/
4318 /* End machine generated definitions. */
4319 /****************************************************************************/
4321 #define NUM_MC_HASH_REGISTERS 8
4324 /* PHY_ID1: bits 31-16; PHY_ID2: bits 15-0. */
4325 #define PHY_BCM5706_PHY_ID 0x00206160
4327 #define PHY_ID(id) ((id) & 0xfffffff0)
4328 #define PHY_REV_ID(id) ((id) & 0xf)
4330 /* 5708 Serdes PHY registers */
4332 #define BCM5708S_UP1 0xb
4334 #define BCM5708S_UP1_2G5 0x1
4336 #define BCM5708S_BLK_ADDR 0x1f
4338 #define BCM5708S_BLK_ADDR_DIG 0x0000
4339 #define BCM5708S_BLK_ADDR_DIG3 0x0002
4340 #define BCM5708S_BLK_ADDR_TX_MISC 0x0005
4343 #define BCM5708S_1000X_CTL1 0x10
4345 #define BCM5708S_1000X_CTL1_FIBER_MODE 0x0001
4346 #define BCM5708S_1000X_CTL1_AUTODET_EN 0x0010
4348 #define BCM5708S_1000X_CTL2 0x11
4350 #define BCM5708S_1000X_CTL2_PLLEL_DET_EN 0x0001
4352 #define BCM5708S_1000X_STAT1 0x14
4354 #define BCM5708S_1000X_STAT1_SGMII 0x0001
4355 #define BCM5708S_1000X_STAT1_LINK 0x0002
4356 #define BCM5708S_1000X_STAT1_FD 0x0004
4357 #define BCM5708S_1000X_STAT1_SPEED_MASK 0x0018
4358 #define BCM5708S_1000X_STAT1_SPEED_10 0x0000
4359 #define BCM5708S_1000X_STAT1_SPEED_100 0x0008
4360 #define BCM5708S_1000X_STAT1_SPEED_1G 0x0010
4361 #define BCM5708S_1000X_STAT1_SPEED_2G5 0x0018
4362 #define BCM5708S_1000X_STAT1_TX_PAUSE 0x0020
4363 #define BCM5708S_1000X_STAT1_RX_PAUSE 0x0040
4365 /* Digital3 Block */
4366 #define BCM5708S_DIG_3_0 0x10
4368 #define BCM5708S_DIG_3_0_USE_IEEE 0x0001
4371 #define BCM5708S_TX_ACTL1 0x15
4373 #define BCM5708S_TX_ACTL1_DRIVER_VCM 0x30
4375 #define BCM5708S_TX_ACTL3 0x17
4377 #define RX_COPY_THRESH 92
4379 #define DMA_READ_CHANS 5
4380 #define DMA_WRITE_CHANS 3
4382 /* Use the natural page size of the host CPU. */
4383 /* XXX: This has only been tested on amd64/i386 systems using 4KB pages. */
4384 #define BCM_PAGE_BITS PAGE_SHIFT
4385 #define BCM_PAGE_SIZE (1 << BCM_PAGE_BITS)
4387 #define BCE_TX_BD_SHIFT 4 /* struct tx_bd */
4388 #define BCE_TX_BD_PAGE_SHIFT (BCM_PAGE_BITS - BCE_TX_BD_SHIFT)
4390 #define BCE_RX_BD_SHIFT 4 /* struct rx_bd */
4391 #define BCE_RX_BD_PAGE_SHIFT (BCM_PAGE_BITS - BCE_RX_BD_SHIFT)
4394 #define TOTAL_TX_BD_PER_PAGE (BCM_PAGE_SIZE / sizeof(struct tx_bd))
4395 #define USABLE_TX_BD_PER_PAGE (TOTAL_TX_BD_PER_PAGE - 1)
4396 #define TOTAL_TX_BD (TOTAL_TX_BD_PER_PAGE * TX_PAGES)
4397 #define USABLE_TX_BD (USABLE_TX_BD_PER_PAGE * TX_PAGES)
4398 #define MAX_TX_BD (TOTAL_TX_BD - 1)
4399 #define BCE_TX_SPARE_SPACE 5
4402 #define TOTAL_RX_BD_PER_PAGE (BCM_PAGE_SIZE / sizeof(struct rx_bd))
4403 #define USABLE_RX_BD_PER_PAGE (TOTAL_RX_BD_PER_PAGE - 1)
4404 #define TOTAL_RX_BD (TOTAL_RX_BD_PER_PAGE * RX_PAGES)
4405 #define USABLE_RX_BD (USABLE_RX_BD_PER_PAGE * RX_PAGES)
4406 #define MAX_RX_BD (TOTAL_RX_BD - 1)
4408 #define NEXT_TX_BD(x) \
4409 (((x) & USABLE_TX_BD_PER_PAGE) == (USABLE_TX_BD_PER_PAGE - 1)) ? \
4412 #define TX_CHAIN_IDX(x) ((x) & MAX_TX_BD)
4414 #define TX_PAGE(x) \
4415 (((x) & ~USABLE_TX_BD_PER_PAGE) >> BCE_TX_BD_PAGE_SHIFT)
4416 #define TX_IDX(x) ((x) & USABLE_TX_BD_PER_PAGE)
4418 #define NEXT_RX_BD(x) \
4419 (((x) & USABLE_RX_BD_PER_PAGE) == (USABLE_RX_BD_PER_PAGE - 1)) ? \
4422 #define RX_CHAIN_IDX(x) ((x) & MAX_RX_BD)
4424 #define RX_PAGE(x) \
4425 (((x) & ~USABLE_RX_BD_PER_PAGE) >> BCE_RX_BD_PAGE_SHIFT)
4426 #define RX_IDX(x) ((x) & USABLE_RX_BD_PER_PAGE)
4430 #define CTX_SIZE (1 << CTX_SHIFT)
4431 #define CTX_MASK (CTX_SIZE - 1)
4432 #define GET_CID_ADDR(_cid) ((_cid) << CTX_SHIFT)
4433 #define GET_CID(_cid_addr) ((_cid_addr) >> CTX_SHIFT)
4435 #define PHY_CTX_SHIFT 6
4436 #define PHY_CTX_SIZE (1 << PHY_CTX_SHIFT)
4437 #define PHY_CTX_MASK (PHY_CTX_SIZE - 1)
4438 #define GET_PCID_ADDR(_pcid) ((_pcid) << PHY_CTX_SHIFT)
4439 #define GET_PCID(_pcid_addr) ((_pcid_addr) >> PHY_CTX_SHIFT)
4441 #define MB_KERNEL_CTX_SHIFT 8
4442 #define MB_KERNEL_CTX_SIZE (1 << MB_KERNEL_CTX_SHIFT)
4443 #define MB_KERNEL_CTX_MASK (MB_KERNEL_CTX_SIZE - 1)
4444 #define MB_GET_CID_ADDR(_cid) (0x10000 + ((_cid) << MB_KERNEL_CTX_SHIFT))
4446 #define MAX_CID_CNT 0x4000
4447 #define MAX_CID_ADDR (GET_CID_ADDR(MAX_CID_CNT))
4448 #define INVALID_CID_ADDR 0xffffffff
4453 #define MB_TX_CID_ADDR MB_GET_CID_ADDR(TX_CID)
4454 #define MB_RX_CID_ADDR MB_GET_CID_ADDR(RX_CID)
4456 /****************************************************************************/
4457 /* BCE Processor Firmwware Load Definitions */
4458 /****************************************************************************/
4462 uint32_t mode_value_halt;
4463 uint32_t mode_value_sstep;
4466 uint32_t state_value_clear;
4476 uint32_t mips_view_base;
4484 uint32_t start_addr;
4489 uint32_t text_index;
4495 uint32_t data_index;
4501 uint32_t sbss_index;
4510 /* Read-only section. */
4511 uint32_t rodata_addr;
4512 uint32_t rodata_len;
4513 uint32_t rodata_index;
4517 #define RV2P_PROC1 0
4518 #define RV2P_PROC2 1
4520 #define BCE_MIREG(x) ((x & 0x1F) << 16)
4521 #define BCE_MIPHY(x) ((x & 0x1F) << 21)
4522 #define BCE_PHY_TIMEOUT 50
4524 #define BCE_NVRAM_SIZE 0x200
4525 #define BCE_NVRAM_MAGIC 0x669955aa
4526 #define BCE_CRC32_RESIDUAL 0xdebb20e3
4528 #define BCE_TX_TIMEOUT 5
4530 #define BCE_MAX_SEGMENTS 32
4531 #define BCE_DMA_ALIGN 8
4532 #define BCE_DMA_BOUNDARY 0
4534 /* The BCM5708 has a problem with addresses greater that 40bits. */
4535 /* Handle the sizing issue in an architecture agnostic fashion. */
4536 #if (BUS_SPACE_MAXADDR < 0xFFFFFFFFFF)
4537 #define BCE_BUS_SPACE_MAXADDR BUS_SPACE_MAXADDR
4539 #define BCE_BUS_SPACE_MAXADDR 0xFFFFFFFFFF
4543 * XXX Checksum offload involving IP fragments seems to cause problems on
4544 * transmit. Disable it for now, hopefully there will be a more elegant
4548 #define BCE_IF_HWASSIST (CSUM_IP | CSUM_TCP | CSUM_UDP)
4550 #define BCE_IF_HWASSIST (CSUM_TCP | CSUM_UDP)
4553 /* NOTE: This hardware also can do VLAN csum offload */
4554 #define BCE_IF_CAPABILITIES (IFCAP_VLAN_MTU | \
4555 IFCAP_VLAN_HWTAGGING | \
4559 #define BCE_MIN_MTU 60
4560 #define BCE_MIN_ETHER_MTU 64
4562 #define BCE_MAX_STD_MTU 1500
4563 #define BCE_MAX_STD_ETHER_MTU 1518
4564 #define BCE_MAX_STD_ETHER_MTU_VLAN 1522
4566 #define BCE_MAX_JUMBO_MTU 9000
4567 #define BCE_MAX_JUMBO_ETHER_MTU 9018
4568 #define BCE_MAX_JUMBO_ETHER_MTU_VLAN 9022
4571 #define BCE_MAX_MTU ETHER_MAX_LEN_JUMBO + EVL_ENCAPLEN /* 9022 */
4574 /****************************************************************************/
4575 /* BCE Device State Data Structure */
4576 /****************************************************************************/
4578 #define BCE_STATUS_BLK_SZ sizeof(struct status_block)
4579 #define BCE_STATS_BLK_SZ sizeof(struct statistics_block)
4580 #define BCE_TX_CHAIN_PAGE_SZ BCM_PAGE_SIZE
4581 #define BCE_RX_CHAIN_PAGE_SZ BCM_PAGE_SIZE
4584 struct arpcom arpcom;
4586 struct resource *bce_res_mem; /* Device resource handle */
4587 bus_space_tag_t bce_btag; /* Device bus tag */
4588 bus_space_handle_t bce_bhandle; /* Device bus handle */
4589 struct resource *bce_res_irq; /* IRQ Resource Handle */
4590 void *bce_intrhand; /* Interrupt handler */
4593 uint32_t bce_chipid;
4595 /* General controller flags. */
4597 #define BCE_PCIX_FLAG 0x01
4598 #define BCE_PCI_32BIT_FLAG 0x02
4599 #define BCE_ONE_TDMA_FLAG 0x04 /* Deprecated */
4600 #define BCE_NO_WOL_FLAG 0x08
4601 #define BCE_USING_DAC_FLAG 0x10
4602 #define BCE_USING_MSI_FLAG 0x20
4603 #define BCE_MFW_ENABLE_FLAG 0x40 /* Management F/W is enabled */
4605 /* PHY specific flags. */
4606 uint32_t bce_phy_flags;
4607 #define BCE_PHY_SERDES_FLAG 0x001
4608 #define BCE_PHY_CRC_FIX_FLAG 0x002
4609 #define BCE_PHY_PARALLEL_DETECT_FLAG 0x004
4610 #define BCE_PHY_2_5G_CAPABLE_FLAG 0x008
4611 #define BCE_PHY_INT_MODE_MASK_FLAG 0x300
4612 #define BCE_PHY_INT_MODE_AUTO_POLLING_FLAG 0x100
4613 #define BCE_PHY_INT_MODE_LINK_READY_FLAG 0x200
4615 bus_addr_t max_bus_addr;
4616 uint16_t bus_speed_mhz; /* PCI bus speed */
4617 const struct flash_spec *bce_flash_info;/* Flash NVRAM settings */
4618 uint32_t bce_flash_size; /* Flash NVRAM size */
4619 uint32_t bce_shmem_base; /* Shared Memory base address */
4621 /* Tracks the version of bootcode firmware. */
4622 uint32_t bce_fw_ver;
4625 * Tracks the state of the firmware. 0 = Running while any
4626 * other value indicates that the firmware is not responding.
4628 uint16_t bce_fw_timed_out;
4631 * An incrementing sequence used to coordinate messages passed
4632 * from the driver to the firmware.
4634 uint16_t bce_fw_wr_seq;
4637 * An incrementing sequence used to let the firmware know that
4638 * the driver is still operating. Without the pulse, management
4639 * firmware such as IPMI or UMP will operate in OS absent state.
4641 uint16_t bce_fw_drv_pulse_wr_seq;
4643 u_char eaddr[6]; /* Ethernet MAC address. */
4646 * These setting are used by the host coalescing (HC) block to
4647 * to control how often the status block, statistics block and
4648 * interrupts are generated.
4650 uint32_t bce_tx_quick_cons_trip_int;
4651 uint32_t bce_tx_quick_cons_trip;
4652 uint32_t bce_rx_quick_cons_trip_int;
4653 uint32_t bce_rx_quick_cons_trip;
4654 uint16_t bce_comp_prod_trip_int;
4655 uint16_t bce_comp_prod_trip;
4656 uint32_t bce_tx_ticks_int;
4657 uint32_t bce_tx_ticks;
4658 uint32_t bce_rx_ticks_int;
4659 uint32_t bce_rx_ticks;
4660 uint16_t bce_com_ticks_int;
4661 uint16_t bce_com_ticks;
4662 uint16_t bce_cmd_ticks_int;
4663 uint16_t bce_cmd_ticks;
4664 uint32_t bce_stats_ticks;
4665 uint32_t bce_coalchg_mask; /* BCE_COALMASK_ */
4667 /* The address of the integrated PHY on the MII bus. */
4670 /* The device handle for the MII bus child device. */
4671 device_t bce_miibus;
4673 /* Driver maintained TX chain pointers and byte counter. */
4676 uint32_t rx_prod_bseq; /* Counts the bytes used. */
4679 uint32_t tx_prod_bseq; /* Counts the bytes used. */
4682 struct callout bce_stat_ch;
4684 /* Frame size and mbuf allocation size for RX frames. */
4685 uint32_t max_frame_size;
4686 int mbuf_alloc_size;
4688 /* Receive mode settings (i.e promiscuous, multicast, etc.). */
4691 /* Bus tag for the bce controller. */
4692 bus_dma_tag_t parent_tag;
4694 /* H/W maintained TX buffer descriptor chain structure. */
4695 bus_dma_tag_t tx_bd_chain_tag;
4696 bus_dmamap_t tx_bd_chain_map[TX_PAGES];
4697 struct tx_bd *tx_bd_chain[TX_PAGES];
4698 bus_addr_t tx_bd_chain_paddr[TX_PAGES];
4700 /* H/W maintained RX buffer descriptor chain structure. */
4701 bus_dma_tag_t rx_bd_chain_tag;
4702 bus_dmamap_t rx_bd_chain_map[RX_PAGES];
4703 struct rx_bd *rx_bd_chain[RX_PAGES];
4704 bus_addr_t rx_bd_chain_paddr[RX_PAGES];
4706 /* H/W maintained status block. */
4707 bus_dma_tag_t status_tag;
4708 bus_dmamap_t status_map;
4709 struct status_block *status_block; /* virtual address */
4710 bus_addr_t status_block_paddr; /* Physical address */
4712 /* Driver maintained status block values. */
4713 uint16_t last_status_idx;
4714 uint16_t hw_rx_cons;
4715 uint16_t hw_tx_cons;
4717 /* H/W maintained statistics block. */
4718 bus_dma_tag_t stats_tag;
4719 bus_dmamap_t stats_map;
4720 struct statistics_block *stats_block; /* Virtual address */
4721 bus_addr_t stats_block_paddr; /* Physical address */
4723 /* Bus tag for RX/TX mbufs. */
4724 bus_dma_tag_t rx_mbuf_tag;
4725 bus_dma_tag_t tx_mbuf_tag;
4727 /* S/W maintained mbuf TX chain structure. */
4728 bus_dmamap_t tx_mbuf_map[TOTAL_TX_BD];
4729 struct mbuf *tx_mbuf_ptr[TOTAL_TX_BD];
4731 /* S/W maintained mbuf RX chain structure. */
4732 bus_dmamap_t rx_mbuf_tmpmap;
4733 bus_dmamap_t rx_mbuf_map[TOTAL_RX_BD];
4734 struct mbuf *rx_mbuf_ptr[TOTAL_RX_BD];
4735 bus_addr_t rx_mbuf_paddr[TOTAL_RX_BD];
4737 /* Track the number of rx_bd and tx_bd's in use. */
4738 uint16_t free_rx_bd;
4740 uint16_t used_tx_bd;
4744 struct sysctl_ctx_list bce_sysctl_ctx;
4745 struct sysctl_oid *bce_sysctl_tree;
4747 /* Provides access to hardware statistics through sysctl. */
4748 uint64_t stat_IfHCInOctets;
4749 uint64_t stat_IfHCInBadOctets;
4750 uint64_t stat_IfHCOutOctets;
4751 uint64_t stat_IfHCOutBadOctets;
4752 uint64_t stat_IfHCInUcastPkts;
4753 uint64_t stat_IfHCInMulticastPkts;
4754 uint64_t stat_IfHCInBroadcastPkts;
4755 uint64_t stat_IfHCOutUcastPkts;
4756 uint64_t stat_IfHCOutMulticastPkts;
4757 uint64_t stat_IfHCOutBroadcastPkts;
4759 uint32_t stat_emac_tx_stat_dot3statsinternalmactransmiterrors;
4760 uint32_t stat_Dot3StatsCarrierSenseErrors;
4761 uint32_t stat_Dot3StatsFCSErrors;
4762 uint32_t stat_Dot3StatsAlignmentErrors;
4763 uint32_t stat_Dot3StatsSingleCollisionFrames;
4764 uint32_t stat_Dot3StatsMultipleCollisionFrames;
4765 uint32_t stat_Dot3StatsDeferredTransmissions;
4766 uint32_t stat_Dot3StatsExcessiveCollisions;
4767 uint32_t stat_Dot3StatsLateCollisions;
4768 uint32_t stat_EtherStatsCollisions;
4769 uint32_t stat_EtherStatsFragments;
4770 uint32_t stat_EtherStatsJabbers;
4771 uint32_t stat_EtherStatsUndersizePkts;
4772 uint32_t stat_EtherStatsOverrsizePkts;
4773 uint32_t stat_EtherStatsPktsRx64Octets;
4774 uint32_t stat_EtherStatsPktsRx65Octetsto127Octets;
4775 uint32_t stat_EtherStatsPktsRx128Octetsto255Octets;
4776 uint32_t stat_EtherStatsPktsRx256Octetsto511Octets;
4777 uint32_t stat_EtherStatsPktsRx512Octetsto1023Octets;
4778 uint32_t stat_EtherStatsPktsRx1024Octetsto1522Octets;
4779 uint32_t stat_EtherStatsPktsRx1523Octetsto9022Octets;
4780 uint32_t stat_EtherStatsPktsTx64Octets;
4781 uint32_t stat_EtherStatsPktsTx65Octetsto127Octets;
4782 uint32_t stat_EtherStatsPktsTx128Octetsto255Octets;
4783 uint32_t stat_EtherStatsPktsTx256Octetsto511Octets;
4784 uint32_t stat_EtherStatsPktsTx512Octetsto1023Octets;
4785 uint32_t stat_EtherStatsPktsTx1024Octetsto1522Octets;
4786 uint32_t stat_EtherStatsPktsTx1523Octetsto9022Octets;
4787 uint32_t stat_XonPauseFramesReceived;
4788 uint32_t stat_XoffPauseFramesReceived;
4789 uint32_t stat_OutXonSent;
4790 uint32_t stat_OutXoffSent;
4791 uint32_t stat_FlowControlDone;
4792 uint32_t stat_MacControlFramesReceived;
4793 uint32_t stat_XoffStateEntered;
4794 uint32_t stat_IfInFramesL2FilterDiscards;
4795 uint32_t stat_IfInRuleCheckerDiscards;
4796 uint32_t stat_IfInFTQDiscards;
4797 uint32_t stat_IfInMBUFDiscards;
4798 uint32_t stat_IfInRuleCheckerP4Hit;
4799 uint32_t stat_CatchupInRuleCheckerDiscards;
4800 uint32_t stat_CatchupInFTQDiscards;
4801 uint32_t stat_CatchupInMBUFDiscards;
4802 uint32_t stat_CatchupInRuleCheckerP4Hit;
4804 /* Provides access to certain firmware statistics. */
4805 uint32_t com_no_buffers;
4808 /* Track the number of enqueued mbufs. */
4812 /* Track how many and what type of interrupts are generated. */
4813 uint32_t interrupts_generated;
4814 uint32_t interrupts_handled;
4815 uint32_t rx_interrupts;
4816 uint32_t tx_interrupts;
4818 uint32_t rx_low_watermark; /* Lowest number of rx_bd's free. */
4819 uint32_t rx_empty_count;
4820 uint32_t tx_hi_watermark; /* Greatest number of tx_bd's used. */
4821 uint32_t tx_full_count; /* Number of times the TX chain was full. */
4822 uint32_t mbuf_alloc_failed; /* Mbuf allocation failure counter. */
4823 uint32_t l2fhdr_status_errors;
4824 uint32_t unexpected_attentions;
4825 uint32_t lost_status_block_updates;
4829 #define BCE_COALMASK_TX_BDS_INT 0x01
4830 #define BCE_COALMASK_TX_BDS 0x02
4831 #define BCE_COALMASK_TX_TICKS_INT 0x04
4832 #define BCE_COALMASK_TX_TICKS 0x08
4833 #define BCE_COALMASK_RX_BDS_INT 0x10
4834 #define BCE_COALMASK_RX_BDS 0x20
4835 #define BCE_COALMASK_RX_TICKS_INT 0x40
4836 #define BCE_COALMASK_RX_TICKS 0x80
4838 #endif /* #ifndef _BCE_H_DEFINED */