2 * Copyright (c) 2001 Gary Jennejohn. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. Neither the name of the author nor the names of any co-contributors
14 * may be used to endorse or promote products derived from this software
15 * without specific prior written permission.
16 * 4. Altered versions must be plainly marked as such, and must not be
17 * misrepresented as being the original software and/or documentation.
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 *---------------------------------------------------------------------------
33 * $FreeBSD: src/sys/i4b/layer1/ifpi2/i4b_ifpi2_isacsx.h,v 1.1.2.1 2002/04/25 20:26:50 gj Exp $
34 * $DragonFly: src/sys/net/i4b/layer1/ifpi2/i4b_ifpi2_isacsx.h,v 1.2 2003/06/17 04:28:39 dillon Exp $
36 * last edit-date: [Wed Jan 24 09:10:42 2001]
38 *---------------------------------------------------------------------------*/
43 #define ISACSX_FIFO_LEN 32 /* 32 bytes FIFO on chip */
45 #define ISACSX_V13 0x01
48 * definitions of registers and bits for the ISAC-SX ISDN chip.
51 typedef struct isacsx_reg {
53 /* 32 byte deep FIFO always first */
55 unsigned char isacsx_fifo [ISACSX_FIFO_LEN];
57 /* most registers can be read/written, but have different names */
58 /* so define a union with read/write names to make that clear */
62 unsigned char isacsx_istad;
63 unsigned char isacsx_stard;
64 unsigned char isacsx_moded;
65 unsigned char isacsx_exmd1;
66 unsigned char isacsx_timr1;
67 unsigned char dummy_25;
68 unsigned char isacsx_rbcld;
69 unsigned char isacsx_rbchd;
70 unsigned char isacsx_rstad;
71 unsigned char isacsx_tmd;
72 unsigned char dummy_2a;
73 unsigned char dummy_2b;
74 unsigned char dummy_2c;
75 unsigned char dummy_2d;
76 unsigned char isacsx_cir0;
77 unsigned char isacsx_codr1;
78 unsigned char isacsx_tr_conf0;
79 unsigned char isacsx_tr_conf1;
80 unsigned char isacsx_tr_conf2;
81 unsigned char isacsx_tr_sta;
82 unsigned char dummy_34;
83 unsigned char isacsx_sqrr1;
84 unsigned char isacsx_sqrr2;
85 unsigned char isacsx_sqrr3;
86 unsigned char isacsx_istatr;
87 unsigned char isacsx_masktr;
88 unsigned char dummy_3a;
89 unsigned char dummy_3b;
90 unsigned char isacsx_acgf2;
91 unsigned char dummy_3d;
92 unsigned char dummy_3e;
93 unsigned char dummy_3f;
94 unsigned char isacsx_cda10;
95 unsigned char isacsx_cda11;
96 unsigned char isacsx_cda20;
97 unsigned char isacsx_cda21;
98 unsigned char isacsx_cda_tsdp10;
99 unsigned char isacsx_cda_tsdp11;
100 unsigned char isacsx_cda_tsdp20;
101 unsigned char isacsx_cda_tsdp21;
102 unsigned char dummy_48;
103 unsigned char dummy_49;
104 unsigned char dummy_4a;
105 unsigned char dummy_4b;
106 unsigned char isacsx_tr_tsdp_bc1;
107 unsigned char isacsx_tr_tsdp_bc2;
108 unsigned char isacsx_cda1_cr;
109 unsigned char isacsx_cda2_cr;
110 unsigned char isacsx_tr_cr;
111 unsigned char dummy_51;
112 unsigned char dummy_52;
113 unsigned char isacsx_dci_cr;
114 unsigned char isacsx_mon_cr;
115 unsigned char isacsx_sds_cr;
116 unsigned char dummy_56;
117 unsigned char isacsx_iom_cr;
118 unsigned char isacsx_sti;
119 unsigned char isacsx_msti;
120 unsigned char isacsx_sds_conf;
121 unsigned char isacsx_mcda;
122 unsigned char isacsx_mor;
123 unsigned char isacsx_mosr;
124 unsigned char isacsx_mocr;
125 unsigned char isacsx_msta;
126 unsigned char isacsx_ista;
127 unsigned char isacsx_auxi;
128 unsigned char isacsx_mode1;
129 unsigned char isacsx_mode2;
130 unsigned char isacsx_id;
131 unsigned char isacsx_timr2;
132 unsigned char dummy_66;
133 unsigned char dummy_67;
134 unsigned char dummy_68;
135 unsigned char dummy_69;
136 unsigned char dummy_6a;
137 unsigned char dummy_6b;
138 unsigned char dummy_6c;
139 unsigned char dummy_6d;
140 unsigned char dummy_6e;
141 unsigned char dummy_6f;
144 unsigned char isacsx_maskd;
145 unsigned char isacsx_cmdrd;
146 unsigned char isacsx_moded;
147 unsigned char isacsx_exmd1;
148 unsigned char isacsx_timr1;
149 unsigned char isacsx_sap1;
150 unsigned char isacsx_sap2;
151 unsigned char isacsx_tei1;
152 unsigned char isacsx_tei2;
153 unsigned char isacsx_tmd;
154 unsigned char dummy_2a;
155 unsigned char dummy_2b;
156 unsigned char dummy_2c;
157 unsigned char dummy_2d;
158 unsigned char isacsx_cix0;
159 unsigned char isacsx_codx1;
160 unsigned char isacsx_tr_conf0;
161 unsigned char isacsx_tr_conf1;
162 unsigned char isacsx_tr_conf2;
163 unsigned char dummy_33;
164 unsigned char dummy_34;
165 unsigned char isacsx_sqrx1;
166 unsigned char dummy_36;
167 unsigned char dummy_37;
168 unsigned char dummy_38;
169 unsigned char isacsx_masktr;
170 unsigned char dummy_3a;
171 unsigned char dummy_3b;
172 unsigned char isacsx_acgf2;
173 unsigned char dummy_3d;
174 unsigned char dummy_3e;
175 unsigned char dummy_3f;
176 unsigned char isacsx_cda10;
177 unsigned char isacsx_cda11;
178 unsigned char isacsx_cda20;
179 unsigned char isacsx_cda21;
180 unsigned char isacsx_cda_tsdp10;
181 unsigned char isacsx_cda_tsdp11;
182 unsigned char isacsx_cda_tsdp20;
183 unsigned char isacsx_cda_tsdp21;
184 unsigned char dummy_48;
185 unsigned char dummy_49;
186 unsigned char dummy_4a;
187 unsigned char dummy_4b;
188 unsigned char isacsx_tr_tsdp_bc1;
189 unsigned char isacsx_tr_tsdp_bc2;
190 unsigned char isacsx_cda1_cr;
191 unsigned char isacsx_cda2_cr;
192 unsigned char isacsx_tr_cr;
193 unsigned char dummy_51;
194 unsigned char dummy_52;
195 unsigned char isacsx_dci_cr;
196 unsigned char isacsx_mon_cr;
197 unsigned char isacsx_sds_cr;
198 unsigned char dummy_56;
199 unsigned char isacsx_iom_cr;
200 unsigned char isacsx_asti;
201 unsigned char isacsx_msti;
202 unsigned char isacsx_sds_conf;
203 unsigned char dummy_5b;
204 unsigned char isacsx_mox;
205 unsigned char dummy_5d;
206 unsigned char isacsx_mocr;
207 unsigned char isacsx_mconf;
208 unsigned char isacsx_mask;
209 unsigned char isacsx_auxm;
210 unsigned char isacsx_mode1;
211 unsigned char isacsx_mode2;
212 unsigned char isacsx_sres;
213 unsigned char isacsx_timr2;
214 unsigned char dummy_66;
215 unsigned char dummy_67;
216 unsigned char dummy_68;
217 unsigned char dummy_69;
218 unsigned char dummy_6a;
219 unsigned char dummy_6b;
220 unsigned char dummy_6c;
221 unsigned char dummy_6d;
222 unsigned char dummy_6e;
223 unsigned char dummy_6f;
228 #define REG_OFFSET(type, field) (int)(&(((type *)0)->field))
230 /* ISACSX read registers */
232 #define i_istad isacsx_rw.isacsx_r.isacsx_istad
233 #define I_ISTAD REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_istad)
234 #define i_stard isacsx_rw.isacsx_r.isacsx_stard
235 #define I_STARD REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_stard)
236 #define i_rmoded isacsx_rw.isacsx_r.isacsx_moded
237 #define I_RMODED REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_moded)
238 #define i_rexmd1 isacsx_rw.isacsx_r.isacsx_exmd1
239 #define I_REXMD1 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_exmd1)
240 #define i_rtimr1 isacsx_rw.isacsx_r.isacsx_timr1
241 #define I_RTIMR1 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_timr1)
242 #define i_rbcld isacsx_rw.isacsx_r.isacsx_rbcld
243 #define I_RBCLD REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_rbcld)
244 #define i_rbchd isacsx_rw.isacsx_r.isacsx_rbchd
245 #define I_RBCHD REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_rbchd)
246 #define i_rstad isacsx_rw.isacsx_r.isacsx_rstad
247 #define I_RSTAD REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_rstad)
248 #define i_rtmd isacsx_rw.isacsx_r.isacsx_tmd
249 #define I_RTMD REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_tmd)
250 #define i_cir0 isacsx_rw.isacsx_r.isacsx_cir0
251 #define I_CIR0 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cir0)
252 #define i_codr1 isacsx_rw.isacsx_r.isacsx_codr1
253 #define I_CODR1 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_codr1)
254 #define i_rtr_conf0 isacsx_rw.isacsx_r.isacsx_tr_conf0
255 #define I_RTR_CONF0 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_tr_conf0)
256 #define i_rtr_conf1 isacsx_rw.isacsx_r.isacsx_tr_conf1
257 #define I_RTR_CONF1 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_tr_conf1)
258 #define i_rtr_conf2 isacsx_rw.isacsx_r.isacsx_tr_conf2
259 #define I_RTR_CONF2 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_tr_conf2)
260 #define i_sta isacsx_rw.isacsx_r.isacsx_sta
261 #define I_STA REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_sta)
262 #define i_sqrr1 isacsx_rw.isacsx_r.isacsx_sqrr1
263 #define I_SQRR1 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_sqrr1)
264 #define i_sqrr2 isacsx_rw.isacsx_r.isacsx_sqrr2
265 #define I_SQRR2 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_sqrr2)
266 #define i_sqrr3 isacsx_rw.isacsx_r.isacsx_sqrr3
267 #define I_SQRR3 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_sqrr3)
268 #define i_istatr isacsx_rw.isacsx_r.isacsx_istatr
269 #define I_ISTATR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_istatr)
270 #define i_rmasktr isacsx_rw.isacsx_r.isacsx_masktr
271 #define I_RMASKTR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_masktr)
272 #define i_racgf2 isacsx_rw.isacsx_r.isacsx_acgf2
273 #define I_RACGF2 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_acgf2)
274 #define i_rcda10 isacsx_rw.isacsx_r.isacsx_cda10
275 #define I_RCDA10 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda10)
276 #define i_rcda11 isacsx_rw.isacsx_r.isacsx_cda11
277 #define I_RCDA11 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda11)
278 #define i_rcda20 isacsx_rw.isacsx_r.isacsx_cda20
279 #define I_RCDA20 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda20)
280 #define i_rcda21 isacsx_rw.isacsx_r.isacsx_cda21
281 #define I_RCDA21 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda21)
282 #define i_cda_tsdp10 isacsx_rw.isacsx_r.isacsx_cda_tsdp10
283 #define I_CDA_TSDP10 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda_tsdp10)
284 #define i_cda_tsdp11 isacsx_rw.isacsx_r.isacsx_cda_tsdp11
285 #define I_CDA_TSDP11 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda_tsdp11)
286 #define i_cda_tsdp20 isacsx_rw.isacsx_r.isacsx_cda_tsdp20
287 #define I_CDA_TSDP20 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda_tsdp20)
288 #define i_cda_tsdp21 isacsx_rw.isacsx_r.isacsx_cda_tsdp21
289 #define I_CDA_TSDP21 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda_tsdp21)
290 #define i_tr_tsdp_bc1 isacsx_rw.isacsx_r.isacsx_tr_tsdp_bc1
291 #define I_TR_TSDP_BC1 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_tr_tsdp_bc1)
292 #define i_tr_tsdp_bc2 isacsx_rw.isacsx_r.isacsx_tr_tsdp_bc2
293 #define I_TR_TSDP_BC2 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_tr_tsdp_bc2)
294 #define i_cda1_cr isacsx_rw.isacsx_r.isacsx_cda1_cr
295 #define I_CDA1_CR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda1_cr)
296 #define i_cda2_cr isacsx_rw.isacsx_r.isacsx_cda2_cr
297 #define I_CDA2_CR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda2_cr)
298 #define i_tr_cr isacsx_rw.isacsx_r.isacsx_tr_cr
299 #define I_TR_CR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_tr_cr)
300 #define i_dci_cr isacsx_rw.isacsx_r.isacsx_dci_cr
301 #define I_DCI_CR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_dci_cr)
302 #define i_mon_cr isacsx_rw.isacsx_r.isacsx_mon_cr
303 #define I_MON_CR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_mon_cr)
304 #define i_sds_cr isacsx_rw.isacsx_r.isacsx_sds_cr
305 #define I_SDS_CR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_sds_cr)
306 #define i_iom_cr isacsx_rw.isacsx_r.isacsx_iom_cr
307 #define I_IOM_CR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_iom_cr)
308 #define i_sti isacsx_rw.isacsx_r.isacsx_sti
309 #define I_STI REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_sti)
310 #define i_msti isacsx_rw.isacsx_r.isacsx_msti
311 #define I_MSTI REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_msti)
312 #define i_sds_conf isacsx_rw.isacsx_r.isacsx_sds_conf
313 #define I_SDS_CONF REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_sds_conf)
314 #define i_mcda isacsx_rw.isacsx_r.isacsx_mcda
315 #define I_MCDA REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_mcda)
316 #define i_mor isacsx_rw.isacsx_r.isacsx_mor
317 #define I_MOR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_mor)
318 #define i_mosr isacsx_rw.isacsx_r.isacsx_mosr
319 #define I_MOSR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_mosr)
320 #define i_rmocr isacsx_rw.isacsx_r.isacsx_mocr
321 #define I_RMOCR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_mocr)
322 #define i_msta isacsx_rw.isacsx_r.isacsx_msta
323 #define I_MSTA REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_msta)
324 #define i_ista isacsx_rw.isacsx_r.isacsx_ista
325 #define I_ISTA REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_ista)
326 #define i_auxi isacsx_rw.isacsx_r.isacsx_auxi
327 #define I_AUXI REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_auxi)
328 #define i_rmode1 isacsx_rw.isacsx_r.isacsx_mode1
329 #define I_RMODE1 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_mode1)
330 #define i_rmode2 isacsx_rw.isacsx_r.isacsx_mode2
331 #define I_RMODE2 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_mode2)
332 #define i_id isacsx_rw.isacsx_r.isacsx_id
333 #define I_ID REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_id)
334 #define i_rtimr2 isacsx_rw.isacsx_r.isacsx_timr2
335 #define I_RTIMR2 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_timr2)
337 /* ISAC write registers - isacsx_mode, isacsx_timr, isacsx_star2, isacsx_spcr, */
338 /* isacsx_c1r, isacsx_c2r, isacsx_adf2 see read registers */
340 #define i_maskd isacsx_rw.isacsx_w.isacsx_maskd
341 #define I_MASKD REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_maskd)
342 #define i_cmdrd isacsx_rw.isacsx_w.isacsx_cmdrd
343 #define I_CMDRD REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_cmdrd)
344 #define i_wmoded isacsx_rw.isacsx_w.isacsx_moded
345 #define I_WMODED REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_moded)
346 #define i_wexmd1 isacsx_rw.isacsx_w.isacsx_exmd1
347 #define I_WEXMD1 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_exmd1)
348 #define i_wtimr1 isacsx_rw.isacsx_w.isacsx_timr1
349 #define I_WTIMR1 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_timr1)
350 #define i_sap1 isacsx_rw.isacsx_w.isacsx_sap1
351 #define I_SAP1 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_sap1)
352 #define i_sap2 isacsx_rw.isacsx_w.isacsx_sap2
353 #define I_SAP2 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_sap2)
354 #define i_tei1 isacsx_rw.isacsx_w.isacsx_tei1
355 #define i_tei2 isacsx_rw.isacsx_w.isacsx_tei2
356 #define i_wtmd isacsx_rw.isacsx_w.isacsx_tmd
357 #define I_WTMD REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_tmd)
358 #define i_cix0 isacsx_rw.isacsx_w.isacsx_cix0
359 #define I_CIX0 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_cix0)
360 #define i_codx1 isacsx_rw.isacsx_w.isacsx_codx1
361 #define I_CODX1 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_codx1)
362 #define i_wtr_conf0 isacsx_rw.isacsx_w.isacsx_tr_conf0
363 #define I_WTR_CONF0 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_tr_conf0)
364 #define i_wtr_conf1 isacsx_rw.isacsx_w.isacsx_tr_conf1
365 #define I_WTR_CONF1 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_tr_conf1)
366 #define i_wtr_conf2 isacsx_rw.isacsx_w.isacsx_tr_conf2
367 #define I_WTR_CONF2 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_tr_conf2)
368 #define i_sqrx1 isacsx_rw.isacsx_w.isacsx_sqrx1
369 #define I_SQRX1 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_sqrx1)
370 #define i_wmasktr isacsx_rw.isacsx_w.isacsx_masktr
371 #define I_WMASKTR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_masktr)
372 #define i_wacgf2 isacsx_rw.isacsx_w.isacsx_acgf2
373 #define I_WACGF2 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_acgf2)
374 #define i_wcda10 isacsx_rw.isacsx_w.isacsx_cda10
375 #define I_WCDA10 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_cda10)
376 #define i_wcda11 isacsx_rw.isacsx_r.isacsx_cda11
377 #define I_WCDA11 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda11)
378 #define i_wcda20 isacsx_rw.isacsx_r.isacsx_cda20
379 #define I_WCDA20 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda20)
380 #define i_wcda21 isacsx_rw.isacsx_r.isacsx_cda21
381 #define I_WCDA21 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda21)
382 #define i_cda_tsdp10 isacsx_rw.isacsx_r.isacsx_cda_tsdp10
383 #define I_CDA_TSDP10 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda_tsdp10)
384 #define i_cda_tsdp11 isacsx_rw.isacsx_r.isacsx_cda_tsdp11
385 #define I_CDA_TSDP11 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda_tsdp11)
386 #define i_cda_tsdp20 isacsx_rw.isacsx_r.isacsx_cda_tsdp20
387 #define I_CDA_TSDP20 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda_tsdp20)
388 #define i_cda_tsdp21 isacsx_rw.isacsx_r.isacsx_cda_tsdp21
389 #define I_CDA_TSDP21 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda_tsdp21)
390 #define i_tr_tsdp_bc1 isacsx_rw.isacsx_r.isacsx_tr_tsdp_bc1
391 #define I_TR_TSDP_BC1 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_tr_tsdp_bc1)
392 #define i_tr_tsdp_bc2 isacsx_rw.isacsx_r.isacsx_tr_tsdp_bc2
393 #define I_TR_TSDP_BC2 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_tr_tsdp_bc2)
394 #define i_cda1_cr isacsx_rw.isacsx_r.isacsx_cda1_cr
395 #define I_CDA1_CR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda1_cr)
396 #define i_cda2_cr isacsx_rw.isacsx_r.isacsx_cda2_cr
397 #define I_CDA2_CR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda2_cr)
398 #define i_tr_cr isacsx_rw.isacsx_r.isacsx_tr_cr
399 #define I_TR_CR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_tr_cr)
400 #define i_dci_cr isacsx_rw.isacsx_r.isacsx_dci_cr
401 #define I_DCI_CR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_dci_cr)
402 #define i_mon_cr isacsx_rw.isacsx_r.isacsx_mon_cr
403 #define I_MON_CR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_mon_cr)
404 #define i_sds_cr isacsx_rw.isacsx_r.isacsx_sds_cr
405 #define I_SDS_CR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_sds_cr)
406 #define i_iom_cr isacsx_rw.isacsx_r.isacsx_iom_cr
407 #define I_IOM_CR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_iom_cr)
408 #define i_asti isacsx_rw.isacsx_r.isacsx_asti
409 #define I_ASTI REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_asti)
410 #define i_msti isacsx_rw.isacsx_r.isacsx_msti
411 #define I_MSTI REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_msti)
412 #define i_sds_conf isacsx_rw.isacsx_r.isacsx_sds_conf
413 #define I_SDS_CONF REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_sds_conf)
414 #define i_mox isacsx_rw.isacsx_w.isacsx_mox
415 #define I_MOX REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_mox)
416 #define i_wmocr isacsx_rw.isacsx_w.isacsx_mocr
417 #define I_WMOCR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_mocr)
418 #define i_mconf isacsx_rw.isacsx_w.isacsx_mconf
419 #define I_MCONF REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_mconf)
420 #define i_mask isacsx_rw.isacsx_w.isacsx_mask
421 #define I_MASK REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_mask)
422 #define i_auxm isacsx_rw.isacsx_w.isacsx_auxm
423 #define I_AUXM REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_auxm)
424 #define i_wmode1 isacsx_rw.isacsx_w.isacsx_mode1
425 #define I_WMODE1 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_mode1)
426 #define i_wmode2 isacsx_rw.isacsx_w.isacsx_mode2
427 #define I_WMODE2 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_mode2)
428 #define i_sres isacsx_rw.isacsx_w.isacsx_sres
429 #define I_SRES REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_sres)
430 #define i_wtimr2 isacsx_rw.isacsx_w.isacsx_timr2
431 #define I_WTIMR2 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_timr2)
433 #define ISACSX_ISTAD_RME 0x80
434 #define ISACSX_ISTAD_RPF 0x40
435 #define ISACSX_ISTAD_RFO 0x20
436 #define ISACSX_ISTAD_XPR 0x10
437 #define ISACSX_ISTAD_XMR 0x08
438 #define ISACSX_ISTAD_XDU 0x04
440 #define ISACSX_MASKD_RME 0x80
441 #define ISACSX_MASKD_RPF 0x40
442 #define ISACSX_MASKD_RFO 0x20
443 #define ISACSX_MASKD_XPR 0x10
444 #define ISACSX_MASKD_XMR 0x08
445 #define ISACSX_MASKD_XDU 0x04
446 /* these must always be set */
447 #define ISACSX_MASKD_LOW 0x03
448 #define ISACSX_MASKD_ALL 0xff
450 #define ISACSX_STARD_XDOV 0x80
451 #define ISACSX_STARD_XFW 0x40
452 #define ISACSX_STARD_RAC1 0x08
453 #define ISACSX_STARD_XAC1 0x02
455 #define ISACSX_CMDRD_RMC 0x80
456 #define ISACSX_CMDRD_RRES 0x40
457 #define ISACSX_CMDRD_STI 0x10
458 #define ISACSX_CMDRD_XTF 0x08
459 #define ISACSX_CMDRD_XME 0x02
460 #define ISACSX_CMDRD_XRES 0x01
462 #define ISACSX_MODED_MDS2 0x80
463 #define ISACSX_MODED_MDS1 0x40
464 #define ISACSX_MODED_MDS0 0x20
465 #define ISACSX_MODED_RAC 0x08
466 #define ISACSX_MODED_DIM2 0x04
467 #define ISACSX_MODED_DIM1 0x02
468 #define ISACSX_MODED_DIM0 0x01
471 #define ISACSX_EXMD1_XFBS_32 0x00 /* XFIFO is 32 bytes */
472 #define ISACSX_EXMD1_XFBS_16 0x80 /* XFIFO is 16 bytes */
474 #define ISACSX_EXMD1_RFBS_32 0x00 /* XFIFO is 32 bytes */
475 #define ISACSX_EXMD1_RFBS_16 0x20 /* XFIFO is 16 bytes */
476 #define ISACSX_EXMD1_RFBS_08 0x40 /* XFIFO is 8 bytes */
477 #define ISACSX_EXMD1_RFBS_04 0x60 /* XFIFO is 4 bytes */
478 #define ISACSX_EXMD1_SRA 0x10
479 #define ISACSX_EXMD1_XCRC 0x08
480 #define ISACSX_EXMD1_RCRC 0x04
481 #define ISACSX_EXMD1_ITF 0x01
483 #define ISACSX_RSTAD_VFR 0x80
484 #define ISACSX_RSTAD_RDO 0x40
485 #define ISACSX_RSTAD_CRC 0x20
486 #define ISACSX_RSTAD_RAB 0x10
487 #define ISACSX_RSTAD_SA1 0x08
488 #define ISACSX_RSTAD_SA0 0x04
489 #define ISACSX_RSTAD_CR 0x02
490 #define ISACSX_RSTAD_TA 0x01
492 #define ISACSX_RSTAD_MASK 0xf0 /* the interesting bits */
494 #define ISACSX_RBCHD_OV 0x10
495 /* the other 4 bits are the high bits of the receive byte count */
497 #define ISACSX_CIR0_CIC0 0x08
499 #define ISACSX_CIR0_IPU 0x07
500 #define ISACSX_CIR0_IDR 0x00
501 #define ISACSX_CIR0_ISD 0x02
502 #define ISACSX_CIR0_IDIS 0x03
503 #define ISACSX_CIR0_IEI 0x06
504 #define ISACSX_CIR0_IRSY 0x04
505 #define ISACSX_CIR0_IARD 0x08
506 #define ISACSX_CIR0_ITI 0x0a
507 #define ISACSX_CIR0_IATI 0x0b
508 #define ISACSX_CIR0_IAI8 0x0c
509 #define ISACSX_CIR0_IAI10 0x0d
510 #define ISACSX_CIR0_IDID 0x0f
512 #define ISACSX_IOM_CR_SPU 0x80
513 #define ISACSX_IOM_CR_CI_CS 0x20
514 #define ISACSX_IOM_CR_TIC_DIS 0x10
515 #define ISACSX_IOM_CR_EN_BCL 0x08
516 #define ISACSX_IOM_CR_CLKM 0x04
517 #define ISACSX_IOM_CR_DIS_OD 0x02
518 #define ISACSX_IOM_CR_DIS_IOM 0x01
520 #define ISACSX_CI_MASK 0x0f
522 #define ISACSX_CIX0_BAC 0x01
523 /* in IOM-2 mode the low bits are always 1 */
524 #define ISACSX_CIX0_LOW 0x0e
525 /* C/I codes from bits 7-4 (>> 4 & 0xf) */
527 #define ISACSX_CIX0_CTIM 0
528 #define ISACSX_CIX0_CRS 0x01
530 #define ISACSX_CIX0_CSSSP 0x02
532 #define ISACSX_CIX0_CSSCP 0x03
533 #define ISACSX_CIX0_CAR8 0x08
534 #define ISACSX_CIX0_CAR10 0x09
535 #define ISACSX_CIX0_CARL 0x0a
536 #define ISACSX_CIX0_CDIU 0x0f
538 /* Interrupt, General Configuration Registers */
540 #define ISACSX_ISTA_ST 0x20
541 #define ISACSX_ISTA_CIC 0x10
542 #define ISACSX_ISTA_AUX 0x08
543 #define ISACSX_ISTA_TRAN 0x04
544 #define ISACSX_ISTA_MOS 0x02
545 #define ISACSX_ISTA_ICD 0x01
547 #define ISACSX_MASK_ST 0x20
548 #define ISACSX_MASK_CIC 0x10
549 #define ISACSX_MASK_AUX 0x08
550 #define ISACSX_MASK_TRAN 0x04
551 #define ISACSX_MASK_MOS 0x02
552 #define ISACSX_MASK_ICD 0x01
554 #define ISACSX_AUXI_EAW 0x20
555 #define ISACSX_AUXI_WOV 0x10
556 #define ISACSX_AUXI_TIN2 0x08
557 #define ISACSX_AUXI_TIN1 0x04
559 #define ISACSX_AUXM_EAW 0x20
560 #define ISACSX_AUXM_WOV 0x10
561 #define ISACSX_AUXM_TIN2 0x08
562 #define ISACSX_AUXM_TIN1 0x04
564 #define ISACSX_MODE1_WTC1 0x10
565 #define ISACSX_MODE1_WTC2 0x08
566 #define ISACSX_MODE1_CFS 0x04
567 #define ISACSX_MODE1_RSS2 0x02
568 #define ISACSX_MODE1_RSS1 0x01
570 #define ISACSX_MODE2_INT_POL 0x08
571 #define ISACSX_MODE2_PPSDX 0x01
573 #define ISACSX_ID_MASK 0x2F /* 0x01 = Version 1.3 */
575 #endif /* I4B_ISACSX_H_ */