sys/net/i4b/layer1/isic/i4b_sws.c

   1 /*
   2  *   Copyright (c) 1998, 2000 German Tischler. All rights reserved.
   3  *
   4  *   Redistribution and use in source and binary forms, with or without
   5  *   modification, are permitted provided that the following conditions
   6  *   are met:
   7  *
   8  *   1. Redistributions of source code must retain the above copyright
   9  *      notice, this list of conditions and the following disclaimer.
  10  *   2. Redistributions in binary form must reproduce the above copyright
  11  *      notice, this list of conditions and the following disclaimer in the
  12  *      documentation and/or other materials provided with the distribution.
  13  *   3. Neither the name of the author nor the names of any co-contributors
  14  *      may be used to endorse or promote products derived from this software
  15  *      without specific prior written permission.
  16  *   4. Altered versions must be plainly marked as such, and must not be
  17  *      misrepresented as being the original software and/or documentation.
  18  *
  19  *   THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  20  *   ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  21  *   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  22  *   ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  23  *   FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  24  *   DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  25  *   OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  26  *   HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  27  *   LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  28  *   OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  29  *   SUCH DAMAGE.
  30  *
  31  *---------------------------------------------------------------------------
  32  *
  33  * Card format:
  34  *
  35  * iobase + 0 : reset on  (0x03)
  36  * iobase + 1 : reset off (0x0)
  37  * iobase + 2 : isac read/write
  38  * iobase + 3 : hscx read/write ( offset 0-0x3f    hscx0 ,
  39  *                                offset 0x40-0x7f hscx1 )
  40  * iobase + 4 : offset for indirect adressing
  41  *
  42  *---------------------------------------------------------------------------
  43  *
  44  *      isic - I4B Siemens ISDN Chipset Driver for SWS cards
  45  *      ====================================================
  46  *
  47  * $FreeBSD: src/sys/i4b/layer1/isic/i4b_sws.c,v 1.5.2.1 2001/08/10 14:08:38 obrien Exp $
  48  * $DragonFly: src/sys/net/i4b/layer1/isic/i4b_sws.c,v 1.2 2003/06/17 04:28:40 dillon Exp $
  49  *
  50  *      last edit-date: [Wed Jan 24 08:58:57 2001]
  51  *
  52  *---------------------------------------------------------------------------*/
  53
  54 #include "isic.h"
  55 #include "opt_i4b.h"
  56
  57 #if defined (SEDLBAUER) && NISIC > 0
  58
  59 #define SWS_RESON  0 /* reset on                 */
  60 #define SWS_RESOFF 1 /* reset off                */
  61 #define SWS_ISAC   2 /* ISAC                     */
  62 #define SWS_HSCX0  3 /* HSCX0                    */
  63 #define SWS_RW     4 /* indirect access register */
  64 #define SWS_HSCX1  5 /* this is for fakeing that we mean hscx1, though */
  65                      /* access is done through hscx0                   */
  66
  67 #define SWS_REGS   8 /* we use an area of 8 bytes for io */
  68
  69 #include <sys/param.h>
  70 #include <sys/systm.h>
  71 #include <sys/socket.h>
  72 #include <net/if.h>
  73
  74 #include <machine/i4b_ioctl.h>
  75 #include <machine/i4b_trace.h>
  76 #include <i4b/layer1/i4b_l1.h>
  77 #include <i4b/layer1/isic/i4b_isic.h>
  78 #include <i4b/layer1/isic/i4b_hscx.h>
  79
  80 /*---------------------------------------------------------------------------*
  81  *      SWS P&P ISAC get fifo routine
  82  *---------------------------------------------------------------------------*/
  83 static void
  84 sws_read_fifo(struct l1_softc *sc,int what,void *buf,size_t size) {
  85         bus_space_tag_t    t = rman_get_bustag(sc->sc_resources.io_base[0]);
  86         bus_space_handle_t h = rman_get_bushandle(sc->sc_resources.io_base[0]);
  87
  88         switch ( what ) {
  89                 case ISIC_WHAT_ISAC:
  90                         bus_space_write_1(t,h,SWS_RW,0x0);
  91                         bus_space_read_multi_1(t,h,SWS_ISAC,buf,size);
  92                         break;
  93                 case ISIC_WHAT_HSCXA:
  94                         bus_space_write_1(t,h,SWS_RW,0x0);
  95                         bus_space_read_multi_1(t,h,SWS_HSCX0,buf,size);
  96                         break;
  97                 case ISIC_WHAT_HSCXB:
  98                         bus_space_write_1(t,h,SWS_RW,0x0+0x40);
  99                         bus_space_read_multi_1(t,h,SWS_HSCX0,buf,size);
 100                         break;
 101         }
 102 }
 103
 104 static void
 105 sws_write_fifo(struct l1_softc *sc,int what,void *buf,size_t size) {
 106         bus_space_tag_t    t = rman_get_bustag(sc->sc_resources.io_base[0]);
 107         bus_space_handle_t h = rman_get_bushandle(sc->sc_resources.io_base[0]);
 108
 109         switch ( what ) {
 110                 case ISIC_WHAT_ISAC:
 111                         bus_space_write_1(t,h,SWS_RW,0x0);
 112                         bus_space_write_multi_1(t,h,SWS_ISAC,buf,size);
 113                         break;
 114                 case ISIC_WHAT_HSCXA:
 115                         bus_space_write_1(t,h,SWS_RW,0x0);
 116                         bus_space_write_multi_1(t,h,SWS_HSCX0,buf,size);
 117                         break;
 118                 case ISIC_WHAT_HSCXB:
 119                         bus_space_write_1(t,h,SWS_RW,0x0+0x40);
 120                         bus_space_write_multi_1(t,h,SWS_HSCX0,buf,size);
 121                         break;
 122         }
 123 }
 124
 125 static void
 126 sws_write_reg(struct l1_softc *sc,int what,bus_size_t reg,u_int8_t data) {
 127         bus_space_tag_t    t = rman_get_bustag(sc->sc_resources.io_base[0]);
 128         bus_space_handle_t h = rman_get_bushandle(sc->sc_resources.io_base[0]);
 129
 130         switch ( what ) {
 131                 case ISIC_WHAT_ISAC:
 132                         bus_space_write_1(t,h,SWS_RW,reg);
 133                         bus_space_write_1(t,h,SWS_ISAC,data);
 134                         break;
 135                 case ISIC_WHAT_HSCXA:
 136                         bus_space_write_1(t,h,SWS_RW,reg);
 137                         bus_space_write_1(t,h,SWS_HSCX0,data);
 138                         break;
 139                 case ISIC_WHAT_HSCXB:
 140                         bus_space_write_1(t,h,SWS_RW,reg+0x40);
 141                         bus_space_write_1(t,h,SWS_HSCX0,data);
 142                         break;
 143         }
 144 }
 145
 146 static u_char
 147 sws_read_reg (struct l1_softc *sc,int what,bus_size_t reg) {
 148         bus_space_tag_t    t = rman_get_bustag(sc->sc_resources.io_base[0]);
 149         bus_space_handle_t h = rman_get_bushandle(sc->sc_resources.io_base[0]);
 150
 151         switch ( what ) {
 152                 case ISIC_WHAT_ISAC:
 153                         bus_space_write_1(t,h,SWS_RW,reg);
 154                         return bus_space_read_1(t,h,SWS_ISAC);
 155                 case ISIC_WHAT_HSCXA:
 156                         bus_space_write_1(t,h,SWS_RW,reg);
 157                         return bus_space_read_1(t,h,SWS_HSCX0);
 158                 case ISIC_WHAT_HSCXB:
 159                         bus_space_write_1(t,h,SWS_RW,reg+0x40);
 160                         return bus_space_read_1(t,h,SWS_HSCX0);
 161                 default:
 162                         return 0;
 163         }
 164 }
 165
 166 /* attach callback routine */
 167 int
 168 isic_attach_sws(device_t dev)
 169 {
 170         int unit = device_get_unit(dev);
 171         struct l1_softc *sc = &l1_sc[unit];
 172
 173         struct i4b_info * info = &(sc->sc_resources);
 174         bus_space_tag_t    t = rman_get_bustag(info->io_base[0]);
 175         bus_space_handle_t h = rman_get_bushandle(info->io_base[0]);
 176
 177         /* fill in l1_softc structure */
 178         sc->readreg     = sws_read_reg;
 179         sc->writereg    = sws_write_reg;
 180         sc->readfifo    = sws_read_fifo;
 181         sc->writefifo   = sws_write_fifo;
 182         sc->clearirq    = NULL;
 183         sc->sc_cardtyp  = CARD_TYPEP_SWS;
 184         sc->sc_bustyp   = BUS_TYPE_IOM2;
 185         sc->sc_ipac     = 0;
 186         sc->sc_bfifolen = HSCX_FIFO_LEN;
 187
 188         /*
 189          * Read HSCX A/B VSTR.  Expected value for the SWS PnP card is
 190          * 0x05 ( = version 2.1 ) in the least significant bits.
 191          */
 192
 193         if( ((HSCX_READ(0, H_VSTR) & 0xf) != 0x5) ||
 194             ((HSCX_READ(1, H_VSTR) & 0xf) != 0x5) )
 195         {
 196                 printf("isic%d: HSCX VSTR test failed for SWS PnP\n",
 197                         sc->sc_unit);
 198                 printf("isic%d: HSC0: VSTR: %#x\n",
 199                         sc->sc_unit, HSCX_READ(0, H_VSTR));
 200                 printf("isic%d: HSC1: VSTR: %#x\n",
 201                         sc->sc_unit, HSCX_READ(1, H_VSTR));
 202                 return (ENXIO);
 203         }
 204
 205         /* reset card */
 206         bus_space_write_1(t,h,SWS_RESON,0x3);
 207         DELAY(SEC_DELAY / 5);
 208         bus_space_write_1(t,h,SWS_RESOFF,0x0);
 209         DELAY(SEC_DELAY / 5);
 210
 211         return(0);
 212 }
 213 #endif /* defined(SEDLBAUER) && NISIC > 0 */