2 * Copyright (c) 2003 Peter Wemm.
3 * Copyright (c) 1993 The Regents of the University of California.
4 * Copyright (c) 2008 The DragonFly Project.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by the University of
18 * California, Berkeley and its contributors.
19 * 4. Neither the name of the University nor the names of its contributors
20 * may be used to endorse or promote products derived from this software
21 * without specific prior written permission.
23 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35 * $FreeBSD: src/sys/amd64/include/cpufunc.h,v 1.139 2004/01/28 23:53:04 peter Exp $
39 * Functions to provide access to special i386 instructions.
40 * This in included in sys/systm.h, and that file should be
41 * used in preference to this.
44 #ifndef _CPU_CPUFUNC_H_
45 #define _CPU_CPUFUNC_H_
47 #include <sys/cdefs.h>
48 #include <machine/psl.h>
51 struct region_descriptor;
54 #define readb(va) (*(volatile u_int8_t *) (va))
55 #define readw(va) (*(volatile u_int16_t *) (va))
56 #define readl(va) (*(volatile u_int32_t *) (va))
57 #define readq(va) (*(volatile u_int64_t *) (va))
59 #define writeb(va, d) (*(volatile u_int8_t *) (va) = (d))
60 #define writew(va, d) (*(volatile u_int16_t *) (va) = (d))
61 #define writel(va, d) (*(volatile u_int32_t *) (va) = (d))
62 #define writeq(va, d) (*(volatile u_int64_t *) (va) = (d))
67 #include <machine/lock.h> /* XXX */
73 __asm __volatile("int $3");
79 __asm __volatile("pause");
87 __asm __volatile("bsfl %1,%0" : "=r" (result) : "rm" (mask));
91 static __inline u_long
96 __asm __volatile("bsfq %1,%0" : "=r" (result) : "rm" (mask));
100 static __inline u_long
105 __asm __volatile("bsfq %1,%0" : "=r" (result) : "rm" (mask));
109 static __inline u_int
114 __asm __volatile("bsrl %1,%0" : "=r" (result) : "rm" (mask));
118 static __inline u_long
123 __asm __volatile("bsrq %1,%0" : "=r" (result) : "rm" (mask));
128 do_cpuid(u_int ax, u_int *p)
130 __asm __volatile("cpuid"
131 : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3])
136 cpuid_count(u_int ax, u_int cx, u_int *p)
138 __asm __volatile("cpuid"
139 : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3])
140 : "0" (ax), "c" (cx));
143 #ifndef _CPU_DISABLE_INTR_DEFINED
146 cpu_disable_intr(void)
148 __asm __volatile("cli" : : : "memory");
153 #ifndef _CPU_ENABLE_INTR_DEFINED
156 cpu_enable_intr(void)
158 __asm __volatile("sti");
164 * Cpu and compiler memory ordering fence. mfence ensures strong read and
167 * A serializing or fence instruction is required here. A locked bus
168 * cycle on data for which we already own cache mastership is the most
175 __asm __volatile("mfence" : : : "memory");
177 __asm __volatile("" : : : "memory");
182 * cpu_lfence() ensures strong read ordering for reads issued prior
183 * to the instruction verses reads issued afterwords.
185 * A serializing or fence instruction is required here. A locked bus
186 * cycle on data for which we already own cache mastership is the most
193 __asm __volatile("lfence" : : : "memory");
195 __asm __volatile("" : : : "memory");
200 * cpu_sfence() ensures strong write ordering for writes issued prior
201 * to the instruction verses writes issued afterwords. Writes are
202 * ordered on intel cpus so we do not actually have to do anything.
209 * Don't use 'sfence' here, as it will create a lot of
210 * unnecessary stalls.
212 __asm __volatile("" : : : "memory");
216 * cpu_ccfence() prevents the compiler from reordering instructions, in
217 * particular stores, relative to the current cpu. Use cpu_sfence() if
218 * you need to guarentee ordering by both the compiler and by the cpu.
220 * This also prevents the compiler from caching memory loads into local
221 * variables across the routine.
226 __asm __volatile("" : : : "memory");
231 #define HAVE_INLINE_FFS
238 * Note that gcc-2's builtin ffs would be used if we didn't declare
239 * this inline or turn off the builtin. The builtin is faster but
240 * broken in gcc-2.4.5 and slower but working in gcc-2.5 and later
243 return (mask == 0 ? mask : (int)bsfl((u_int)mask) + 1);
245 /* Actually, the above is way out of date. The builtins use cmov etc */
246 return (__builtin_ffs(mask));
250 #define HAVE_INLINE_FFSL
255 return (mask == 0 ? mask : (int)bsfq((u_long)mask) + 1);
258 #define HAVE_INLINE_FLS
263 return (mask == 0 ? mask : (int)bsrl((u_int)mask) + 1);
266 #define HAVE_INLINE_FLSL
271 return (mask == 0 ? mask : (int)bsrq((u_long)mask) + 1);
279 __asm __volatile("hlt");
283 * The following complications are to get around gcc not having a
284 * constraint letter for the range 0..255. We still put "d" in the
285 * constraint because "i" isn't a valid constraint when the port
286 * isn't constant. This only matters for -O0 because otherwise
287 * the non-working version gets optimized away.
289 * Use an expression-statement instead of a conditional expression
290 * because gcc-2.6.0 would promote the operands of the conditional
291 * and produce poor code for "if ((inb(var) & const1) == const2)".
293 * The unnecessary test `(port) < 0x10000' is to generate a warning if
294 * the `port' has type u_short or smaller. Such types are pessimal.
295 * This actually only works for signed types. The range check is
296 * careful to avoid generating warnings.
298 #define inb(port) __extension__ ({ \
300 if (__builtin_constant_p(port) && ((port) & 0xffff) < 0x100 \
301 && (port) < 0x10000) \
302 _data = inbc(port); \
304 _data = inbv(port); \
307 #define outb(port, data) ( \
308 __builtin_constant_p(port) && ((port) & 0xffff) < 0x100 \
309 && (port) < 0x10000 \
310 ? outbc(port, data) : outbv(port, data))
312 static __inline u_char
317 __asm __volatile("inb %1,%0" : "=a" (data) : "id" ((u_short)(port)));
322 outbc(u_int port, u_char data)
324 __asm __volatile("outb %0,%1" : : "a" (data), "id" ((u_short)(port)));
327 static __inline u_char
332 * We use %%dx and not %1 here because i/o is done at %dx and not at
333 * %edx, while gcc generates inferior code (movw instead of movl)
334 * if we tell it to load (u_short) port.
336 __asm __volatile("inb %%dx,%0" : "=a" (data) : "d" (port));
340 static __inline u_int
345 __asm __volatile("inl %%dx,%0" : "=a" (data) : "d" (port));
350 insb(u_int port, void *addr, size_t cnt)
352 __asm __volatile("cld; rep; insb"
353 : "+D" (addr), "+c" (cnt)
359 insw(u_int port, void *addr, size_t cnt)
361 __asm __volatile("cld; rep; insw"
362 : "+D" (addr), "+c" (cnt)
368 insl(u_int port, void *addr, size_t cnt)
370 __asm __volatile("cld; rep; insl"
371 : "+D" (addr), "+c" (cnt)
379 __asm __volatile("invd");
385 * If we are not a true-SMP box then smp_invltlb() is a NOP. Note that this
386 * will cause the invl*() functions to be equivalent to the cpu_invl*()
390 void smp_invltlb(void);
391 void smp_invltlb_intr(void);
393 #define smp_invltlb()
396 #ifndef _CPU_INVLPG_DEFINED
399 * Invalidate a patricular VA on this cpu only
402 cpu_invlpg(void *addr)
404 __asm __volatile("invlpg %0" : : "m" (*(char *)addr) : "memory");
412 __asm __volatile("rep; nop");
417 static __inline u_short
422 __asm __volatile("inw %%dx,%0" : "=a" (data) : "d" (port));
426 static __inline u_int
427 loadandclear(volatile u_int *addr)
431 __asm __volatile("xorl %0,%0; xchgl %1,%0"
432 : "=&r" (result) : "m" (*addr));
437 outbv(u_int port, u_char data)
441 * Use an unnecessary assignment to help gcc's register allocator.
442 * This make a large difference for gcc-1.40 and a tiny difference
443 * for gcc-2.6.0. For gcc-1.40, al had to be ``asm("ax")'' for
444 * best results. gcc-2.6.0 can't handle this.
447 __asm __volatile("outb %0,%%dx" : : "a" (al), "d" (port));
451 outl(u_int port, u_int data)
454 * outl() and outw() aren't used much so we haven't looked at
455 * possible micro-optimizations such as the unnecessary
456 * assignment for them.
458 __asm __volatile("outl %0,%%dx" : : "a" (data), "d" (port));
462 outsb(u_int port, const void *addr, size_t cnt)
464 __asm __volatile("cld; rep; outsb"
465 : "+S" (addr), "+c" (cnt)
470 outsw(u_int port, const void *addr, size_t cnt)
472 __asm __volatile("cld; rep; outsw"
473 : "+S" (addr), "+c" (cnt)
478 outsl(u_int port, const void *addr, size_t cnt)
480 __asm __volatile("cld; rep; outsl"
481 : "+S" (addr), "+c" (cnt)
486 outw(u_int port, u_short data)
488 __asm __volatile("outw %0,%%dx" : : "a" (data), "d" (port));
494 __asm __volatile("pause");
497 static __inline u_long
502 __asm __volatile("pushfq; popq %0" : "=r" (rf));
506 static __inline u_int64_t
511 __asm __volatile("rdmsr" : "=a" (low), "=d" (high) : "c" (msr));
512 return (low | ((u_int64_t)high << 32));
515 static __inline u_int64_t
520 __asm __volatile("rdpmc" : "=a" (low), "=d" (high) : "c" (pmc));
521 return (low | ((u_int64_t)high << 32));
524 #define _RDTSC_SUPPORTED_
526 static __inline u_int64_t
531 __asm __volatile("rdtsc" : "=a" (low), "=d" (high));
532 return (low | ((u_int64_t)high << 32));
538 __asm __volatile("wbinvd");
542 write_rflags(u_long rf)
544 __asm __volatile("pushq %0; popfq" : : "r" (rf));
548 wrmsr(u_int msr, u_int64_t newval)
554 __asm __volatile("wrmsr" : : "a" (low), "d" (high), "c" (msr));
558 load_cr0(u_long data)
561 __asm __volatile("movq %0,%%cr0" : : "r" (data));
564 static __inline u_long
569 __asm __volatile("movq %%cr0,%0" : "=r" (data));
573 static __inline u_long
578 __asm __volatile("movq %%cr2,%0" : "=r" (data));
583 load_cr3(u_long data)
586 __asm __volatile("movq %0,%%cr3" : : "r" (data) : "memory");
589 static __inline u_long
594 __asm __volatile("movq %%cr3,%0" : "=r" (data));
599 load_cr4(u_long data)
601 __asm __volatile("movq %0,%%cr4" : : "r" (data));
604 static __inline u_long
609 __asm __volatile("movq %%cr4,%0" : "=r" (data));
613 #ifndef _CPU_INVLTLB_DEFINED
616 * Invalidate the TLB on this cpu only
622 #if defined(SWTCH_OPTIM_STATS)
630 * TLB flush for an individual page (even if it has PG_G).
631 * Only works on 486+ CPUs (i386 does not have PG_G).
637 __asm __volatile("invlpg %0" : : "m" (*(char *)addr) : "memory");
640 static __inline u_short
644 __asm __volatile("movw %%fs,%0" : "=rm" (sel));
648 static __inline u_short
652 __asm __volatile("movw %%gs,%0" : "=rm" (sel));
659 __asm __volatile("movw %0,%%ds" : : "rm" (sel));
665 __asm __volatile("movw %0,%%es" : : "rm" (sel));
669 /* This is defined in <machine/specialreg.h> but is too painful to get to */
671 #define MSR_FSBASE 0xc0000100
676 /* Preserve the fsbase value across the selector load */
677 __asm __volatile("rdmsr; movw %0,%%fs; wrmsr"
678 : : "rm" (sel), "c" (MSR_FSBASE) : "eax", "edx");
682 #define MSR_GSBASE 0xc0000101
688 * Preserve the gsbase value across the selector load.
689 * Note that we have to disable interrupts because the gsbase
690 * being trashed happens to be the kernel gsbase at the time.
692 __asm __volatile("pushfq; cli; rdmsr; movw %0,%%gs; wrmsr; popfq"
693 : : "rm" (sel), "c" (MSR_GSBASE) : "eax", "edx");
696 /* Usable by userland */
700 __asm __volatile("movw %0,%%fs" : : "rm" (sel));
706 __asm __volatile("movw %0,%%gs" : : "rm" (sel));
710 /* void lidt(struct region_descriptor *addr); */
712 lidt(struct region_descriptor *addr)
714 __asm __volatile("lidt (%0)" : : "r" (addr));
717 /* void lldt(u_short sel); */
721 __asm __volatile("lldt %0" : : "r" (sel));
724 /* void ltr(u_short sel); */
728 __asm __volatile("ltr %0" : : "r" (sel));
731 static __inline u_int64_t
735 __asm __volatile("movq %%dr0,%0" : "=r" (data));
740 load_dr0(u_int64_t dr0)
742 __asm __volatile("movq %0,%%dr0" : : "r" (dr0));
745 static __inline u_int64_t
749 __asm __volatile("movq %%dr1,%0" : "=r" (data));
754 load_dr1(u_int64_t dr1)
756 __asm __volatile("movq %0,%%dr1" : : "r" (dr1));
759 static __inline u_int64_t
763 __asm __volatile("movq %%dr2,%0" : "=r" (data));
768 load_dr2(u_int64_t dr2)
770 __asm __volatile("movq %0,%%dr2" : : "r" (dr2));
773 static __inline u_int64_t
777 __asm __volatile("movq %%dr3,%0" : "=r" (data));
782 load_dr3(u_int64_t dr3)
784 __asm __volatile("movq %0,%%dr3" : : "r" (dr3));
787 static __inline u_int64_t
791 __asm __volatile("movq %%dr4,%0" : "=r" (data));
796 load_dr4(u_int64_t dr4)
798 __asm __volatile("movq %0,%%dr4" : : "r" (dr4));
801 static __inline u_int64_t
805 __asm __volatile("movq %%dr5,%0" : "=r" (data));
810 load_dr5(u_int64_t dr5)
812 __asm __volatile("movq %0,%%dr5" : : "r" (dr5));
815 static __inline u_int64_t
819 __asm __volatile("movq %%dr6,%0" : "=r" (data));
824 load_dr6(u_int64_t dr6)
826 __asm __volatile("movq %0,%%dr6" : : "r" (dr6));
829 static __inline u_int64_t
833 __asm __volatile("movq %%dr7,%0" : "=r" (data));
838 load_dr7(u_int64_t dr7)
840 __asm __volatile("movq %0,%%dr7" : : "r" (dr7));
843 static __inline register_t
848 rflags = read_rflags();
854 intr_restore(register_t rflags)
856 write_rflags(rflags);
859 #else /* !__GNUC__ */
861 int breakpoint(void);
862 void cpu_pause(void);
863 u_int bsfl(u_int mask);
864 u_int bsrl(u_int mask);
865 void cpu_disable_intr(void);
866 void cpu_enable_intr(void);
867 void cpu_invlpg(u_long addr);
868 void cpu_invlpg_range(u_long start, u_long end);
869 void do_cpuid(u_int ax, u_int *p);
871 u_char inb(u_int port);
872 u_int inl(u_int port);
873 void insb(u_int port, void *addr, size_t cnt);
874 void insl(u_int port, void *addr, size_t cnt);
875 void insw(u_int port, void *addr, size_t cnt);
877 void invlpg(u_int addr);
878 void invlpg_range(u_int start, u_int end);
879 void cpu_invltlb(void);
880 u_short inw(u_int port);
881 void load_cr0(u_int cr0);
882 void load_cr3(u_int cr3);
883 void load_cr4(u_int cr4);
884 void load_fs(u_int sel);
885 void load_gs(u_int sel);
886 struct region_descriptor;
887 void lidt(struct region_descriptor *addr);
888 void lldt(u_short sel);
889 void ltr(u_short sel);
890 void outb(u_int port, u_char data);
891 void outl(u_int port, u_int data);
892 void outsb(u_int port, void *addr, size_t cnt);
893 void outsl(u_int port, void *addr, size_t cnt);
894 void outsw(u_int port, void *addr, size_t cnt);
895 void outw(u_int port, u_short data);
896 void ia32_pause(void);
903 u_int64_t rdmsr(u_int msr);
904 u_int64_t rdpmc(u_int pmc);
905 u_int64_t rdtsc(void);
906 u_int read_rflags(void);
908 void write_rflags(u_int rf);
909 void wrmsr(u_int msr, u_int64_t newval);
910 u_int64_t rdr0(void);
911 void load_dr0(u_int64_t dr0);
912 u_int64_t rdr1(void);
913 void load_dr1(u_int64_t dr1);
914 u_int64_t rdr2(void);
915 void load_dr2(u_int64_t dr2);
916 u_int64_t rdr3(void);
917 void load_dr3(u_int64_t dr3);
918 u_int64_t rdr4(void);
919 void load_dr4(u_int64_t dr4);
920 u_int64_t rdr5(void);
921 void load_dr5(u_int64_t dr5);
922 u_int64_t rdr6(void);
923 void load_dr6(u_int64_t dr6);
924 u_int64_t rdr7(void);
925 void load_dr7(u_int64_t dr7);
926 register_t intr_disable(void);
927 void intr_restore(register_t rf);
929 #endif /* __GNUC__ */
931 int rdmsr_safe(u_int msr, uint64_t *val);
932 void reset_dbregs(void);
936 #endif /* !_CPU_CPUFUNC_H_ */