2 * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 /* local prototypes */
28 static int ata_ahci_ctlr_reset(device_t dev);
29 static int ata_ahci_status(device_t dev);
30 static int ata_ahci_begin_transaction(struct ata_request *request);
31 static int ata_ahci_end_transaction(struct ata_request *request);
32 static u_int32_t ata_ahci_softreset(device_t dev, int port);
33 static void ata_ahci_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error);
34 static int ata_ahci_setup_fis(struct ata_ahci_cmd_tab *ctp, struct ata_request *request);
37 * AHCI v1.x compliant SATA chipset support functions
40 ata_ahci_ident(device_t dev)
42 struct ata_pci_controller *ctlr = device_get_softc(dev);
43 static const struct ata_chip_id id = {0, 0, 0, 0x00, ATA_SA300, "AHCI"};
46 /* is this a possible AHCI candidate ? */
47 if (pci_get_class(dev) != PCIC_STORAGE ||
48 pci_get_subclass(dev) != PCIS_STORAGE_SATA)
51 /* is this PCI device flagged as an AHCI compliant chip ? */
52 if (pci_read_config(dev, PCIR_PROGIF, 1) != PCIP_STORAGE_SATA_AHCI_1_0)
56 ksnprintf(buffer, sizeof(buffer), "%s (ID=%08x) AHCI controller",
57 ata_pcivendor2str(dev), pci_get_devid(dev));
59 ksnprintf(buffer, sizeof(buffer), "%s AHCI controller",
60 ata_pcivendor2str(dev));
61 device_set_desc_copy(dev, buffer);
63 ctlr->chipinit = ata_ahci_chipinit;
68 * AHCI v1.x compliant SATA chipset support functions
71 ata_ahci_chipinit(device_t dev)
73 struct ata_pci_controller *ctlr = device_get_softc(dev);
77 /* if we have a memory BAR(5) we are likely on an AHCI part */
78 ctlr->r_type2 = SYS_RES_MEMORY;
79 ctlr->r_rid2 = PCIR_BAR(5);
80 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
81 &ctlr->r_rid2, RF_ACTIVE)))
84 /* setup interrupt delivery if not done allready by a vendor driver */
86 if (ata_setup_interrupt(dev, ata_generic_intr)) {
87 bus_release_resource(dev, ctlr->r_type2, ctlr->r_rid2, ctlr->r_res2);
92 device_printf(dev, "AHCI called from vendor specific driver\n");
94 /* reset controller */
95 if ((error = ata_ahci_ctlr_reset(dev)) != 0) {
96 bus_release_resource(dev, ctlr->r_type2, ctlr->r_rid2, ctlr->r_res2);
100 /* get the number of HW channels */
102 MAX(flsl(ATA_INL(ctlr->r_res2, ATA_AHCI_PI)),
103 (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_NPMASK) + 1);
105 ctlr->reset = ata_ahci_reset;
106 ctlr->dmainit = ata_ahci_dmainit;
107 ctlr->allocate = ata_ahci_allocate;
108 ctlr->setmode = ata_sata_setmode;
110 /* enable PCI interrupt */
111 pci_write_config(dev, PCIR_COMMAND,
112 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2);
114 /* announce we support the HW */
115 version = ATA_INL(ctlr->r_res2, ATA_AHCI_VS);
117 "AHCI Version %x%x.%x%x controller with %d ports detected\n",
118 (version >> 24) & 0xff, (version >> 16) & 0xff,
119 (version >> 8) & 0xff, version & 0xff,
120 (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_NPMASK) + 1);
125 ata_ahci_ctlr_reset(device_t dev)
127 struct ata_pci_controller *ctlr = device_get_softc(dev);
129 /* enable AHCI mode */
130 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC, ATA_AHCI_GHC_AE);
132 /* reset AHCI controller */
133 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC, ATA_AHCI_GHC_HR);
135 if (ATA_INL(ctlr->r_res2, ATA_AHCI_GHC) & ATA_AHCI_GHC_HR) {
136 device_printf(dev, "AHCI controller reset failure\n");
140 /* reenable AHCI mode */
141 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC, ATA_AHCI_GHC_AE);
143 /* clear interrupts */
144 ATA_OUTL(ctlr->r_res2, ATA_AHCI_IS, ATA_INL(ctlr->r_res2, ATA_AHCI_IS));
146 /* enable AHCI interrupts */
147 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC,
148 ATA_INL(ctlr->r_res2, ATA_AHCI_GHC) | ATA_AHCI_GHC_IE);
154 ata_ahci_allocate(device_t dev)
156 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
157 struct ata_channel *ch = device_get_softc(dev);
158 int offset = ch->unit << 7;
160 /* set the SATA resources */
161 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
162 ch->r_io[ATA_SSTATUS].offset = ATA_AHCI_P_SSTS + offset;
163 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
164 ch->r_io[ATA_SERROR].offset = ATA_AHCI_P_SERR + offset;
165 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
166 ch->r_io[ATA_SCONTROL].offset = ATA_AHCI_P_SCTL + offset;
167 ch->r_io[ATA_SACTIVE].res = ctlr->r_res2;
168 ch->r_io[ATA_SACTIVE].offset = ATA_AHCI_P_SACT + offset;
170 ch->hw.status = ata_ahci_status;
171 ch->hw.begin_transaction = ata_ahci_begin_transaction;
172 ch->hw.end_transaction = ata_ahci_end_transaction;
173 ch->hw.command = NULL; /* not used here */
174 ch->hw.softreset = ata_ahci_softreset;
180 ata_ahci_status(device_t dev)
182 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
183 struct ata_channel *ch = device_get_softc(dev);
184 u_int32_t action = ATA_INL(ctlr->r_res2, ATA_AHCI_IS);
185 int offset = ch->unit << 7;
187 #define ATA_AHCI_STATBITS \
188 (ATA_AHCI_P_IX_IF|ATA_AHCI_P_IX_HBD|ATA_AHCI_P_IX_HBF|ATA_AHCI_P_IX_TFE)
190 if (action & (1 << ch->unit)) {
191 u_int32_t istatus = ATA_INL(ctlr->r_res2, ATA_AHCI_P_IS + offset);
192 u_int32_t cstatus = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CI + offset);
194 /* clear interrupt(s) */
195 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IS + offset, istatus);
196 ATA_OUTL(ctlr->r_res2, ATA_AHCI_IS, action & (1 << ch->unit));
198 /* do we have any PHY events ? */
199 if (istatus & (ATA_AHCI_P_IX_PRC | ATA_AHCI_P_IX_PC))
200 ata_sata_phy_check_events(dev);
202 /* do we have a potentially hanging engine to take care of? */
203 if ((istatus & ATA_AHCI_STATBITS) && (cstatus & 1)) {
205 u_int32_t cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset);
208 /* kill off all activity on this channel */
209 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
210 cmd & ~(ATA_AHCI_P_CMD_FRE | ATA_AHCI_P_CMD_ST));
212 /* XXX SOS this is not entirely wrong */
215 if (timeout++ > 1000) {
216 device_printf(dev, "stopping AHCI engine failed\n");
219 } while (ATA_INL(ctlr->r_res2,
220 ATA_AHCI_P_CMD + offset) & ATA_AHCI_P_CMD_CR);
222 /* start operations on this channel */
223 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
224 cmd | (ATA_AHCI_P_CMD_FRE | ATA_AHCI_P_CMD_ST));
229 return (!(cstatus & 1));
234 /* must be called with ATA channel locked and state_mtx held */
236 ata_ahci_begin_transaction(struct ata_request *request)
238 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev));
239 struct ata_channel *ch = device_get_softc(request->parent);
240 struct ata_device *atadev = device_get_softc(request->dev);
241 struct ata_ahci_cmd_tab *ctp;
242 struct ata_ahci_cmd_list *clp;
243 int offset = ch->unit << 7;
244 int port = atadev->unit & 0x0f;
245 int tag = 0, entries = 0;
248 /* get a piece of the workspace for this request */
249 ctp = (struct ata_ahci_cmd_tab *)
250 (ch->dma->work + ATA_AHCI_CT_OFFSET + (ATA_AHCI_CT_SIZE * tag));
252 /* setup the FIS for this request */
253 if (!(fis_size = ata_ahci_setup_fis(ctp, request))) {
254 device_printf(request->dev, "setting up SATA FIS failed\n");
255 request->result = EIO;
256 return ATA_OP_FINISHED;
259 /* if request moves data setup and load SG list */
260 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) {
261 if (ch->dma->load(ch->dev, request->data, request->bytecount,
262 request->flags & ATA_R_READ,
263 ctp->prd_tab, &entries)) {
264 device_printf(request->dev, "setting up DMA failed\n");
265 request->result = EIO;
266 return ATA_OP_FINISHED;
270 /* setup the command list entry */
271 clp = (struct ata_ahci_cmd_list *)
272 (ch->dma->work + ATA_AHCI_CL_OFFSET + (ATA_AHCI_CL_SIZE * tag));
274 clp->prd_length = entries;
275 clp->cmd_flags = (request->flags & ATA_R_WRITE ? ATA_AHCI_CMD_WRITE : 0) |
276 (request->flags & ATA_R_ATAPI ?
277 (ATA_AHCI_CMD_ATAPI | ATA_AHCI_CMD_PREFETCH) : 0) |
278 (fis_size / sizeof(u_int32_t)) |
281 clp->cmd_table_phys = htole64(ch->dma->work_bus + ATA_AHCI_CT_OFFSET +
282 (ATA_AHCI_CT_SIZE * tag));
284 /* clear eventual ACTIVE bit */
285 ATA_IDX_OUTL(ch, ATA_SACTIVE, ATA_IDX_INL(ch, ATA_SACTIVE) & (1 << tag));
287 /* set command type bit */
288 if (request->flags & ATA_R_ATAPI)
289 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
290 ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset) |
291 ATA_AHCI_P_CMD_ATAPI);
293 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
294 ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset) &
295 ~ATA_AHCI_P_CMD_ATAPI);
297 /* set PM port to address */
298 //ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_FBS + offset, (port << 8) | 0x00000001);
300 /* issue command to controller */
301 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CI + offset, (1 << tag));
303 if (!(request->flags & ATA_R_ATAPI)) {
304 /* device reset doesn't interrupt */
305 if (request->u.ata.command == ATA_DEVICE_RESET) {
307 int timeout = 1000000;
311 tf_data = ATA_INL(ctlr->r_res2, ATA_AHCI_P_TFD + (ch->unit<<7));
312 } while ((tf_data & ATA_S_BUSY) && timeout--);
314 device_printf(ch->dev, "device_reset timeout=%dus\n",
315 (1000000-timeout)*10);
316 request->status = tf_data;
317 if (request->status & ATA_S_ERROR)
318 request->error = tf_data >> 8;
319 return ATA_OP_FINISHED;
323 /* start the timeout */
324 callout_reset(&request->callout, request->timeout * hz,
325 (timeout_t*)ata_timeout, request);
326 return ATA_OP_CONTINUES;
329 /* must be called with ATA channel locked and state_mtx held */
331 ata_ahci_end_transaction(struct ata_request *request)
333 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev));
334 struct ata_channel *ch = device_get_softc(request->parent);
335 struct ata_ahci_cmd_list *clp;
337 int offset = ch->unit << 7;
340 /* kill the timeout */
341 callout_stop_sync(&request->callout);
344 tf_data = ATA_INL(ctlr->r_res2, ATA_AHCI_P_TFD + offset);
345 request->status = tf_data;
347 /* if error status get details */
348 if (request->status & ATA_S_ERROR)
349 request->error = tf_data >> 8;
351 /* record how much data we actually moved */
352 clp = (struct ata_ahci_cmd_list *)
353 (ch->dma->work + ATA_AHCI_CL_OFFSET + (ATA_AHCI_CL_SIZE * tag));
354 request->donecount = clp->bytecount;
356 /* release SG list etc */
357 ch->dma->unload(ch->dev);
359 return ATA_OP_FINISHED;
363 ata_ahci_restart(device_t dev)
365 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
366 struct ata_channel *ch = device_get_softc(dev);
368 int offset = ch->unit << 7;
371 /* kill off all activity on this channel */
372 cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset);
373 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
374 cmd & ~(ATA_AHCI_P_CMD_FRE | ATA_AHCI_P_CMD_ST));
376 /* XXX SOS this is not entirely wrong */
380 if (timeout++ > 1000) {
381 device_printf(dev, "stopping AHCI engine failed\n");
385 while (ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset) & ATA_AHCI_P_CMD_CR);
387 /* issue Command List Override if supported */
388 if (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_CAP_CLO) {
389 cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset);
390 cmd |= ATA_AHCI_P_CMD_CLO;
391 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, cmd);
395 if (timeout++ > 1000) {
396 device_printf(dev, "executing CLO failed\n");
400 while (ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD+offset)&ATA_AHCI_P_CMD_CLO);
403 /* clear SATA error register */
404 ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR));
406 /* clear any interrupts pending on this channel */
407 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IS + offset,
408 ATA_INL(ctlr->r_res2, ATA_AHCI_P_IS + offset));
410 /* start operations on this channel */
411 cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset);
412 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
413 cmd | (ATA_AHCI_P_CMD_FRE | ATA_AHCI_P_CMD_ST));
417 ata_ahci_softreset(device_t dev, int port __unused)
419 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
420 struct ata_channel *ch = device_get_softc(dev);
421 int offset = ch->unit << 7;
427 if (timeout++ > 1000) {
428 device_printf(dev, "still BUSY after softreset\n");
431 } while (ATA_INL(ctlr->r_res2, ATA_AHCI_P_TFD + offset) & ATA_S_BUSY);
433 device_printf(dev, "BUSY wait time=%dms\n", timeout);
435 return ATA_INL(ctlr->r_res2, ATA_AHCI_P_SIG + offset);
439 ata_ahci_reset(device_t dev)
441 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
442 struct ata_channel *ch = device_get_softc(dev);
444 u_int32_t cmd, signature;
445 int offset = ch->unit << 7;
447 /* Disable port interrupts */
448 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IE + offset, 0);
450 if (!(ATA_INL(ctlr->r_res2, ATA_AHCI_PI) & (1 << ch->unit))) {
451 device_printf(dev, "port not implemented\n");
455 /* setup work areas */
456 work = ch->dma->work_bus + ATA_AHCI_CL_OFFSET;
457 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CLB + offset, work & 0xffffffff);
458 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CLBU + offset, work >> 32);
460 work = ch->dma->work_bus + ATA_AHCI_FB_OFFSET;
461 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_FB + offset, work & 0xffffffff);
462 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_FBU + offset, work >> 32);
464 /* enable wanted port interrupts */
465 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IE + offset,
466 (ATA_AHCI_P_IX_CPD | ATA_AHCI_P_IX_TFE | ATA_AHCI_P_IX_HBF |
467 ATA_AHCI_P_IX_HBD | ATA_AHCI_P_IX_IF | ATA_AHCI_P_IX_OF |
468 ATA_AHCI_P_IX_PRC | ATA_AHCI_P_IX_PC | ATA_AHCI_P_IX_DP |
469 ATA_AHCI_P_IX_UF | ATA_AHCI_P_IX_SDB | ATA_AHCI_P_IX_DS |
470 ATA_AHCI_P_IX_PS | ATA_AHCI_P_IX_DHR));
472 /* activate the channel and power/spin up device */
473 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
474 (ATA_AHCI_P_CMD_ACTIVE | ATA_AHCI_P_CMD_POD | ATA_AHCI_P_CMD_SUD));
476 ata_ahci_restart(dev);
478 /* enable FIS based switching */
479 //ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_FBS + offset, 0x00000003);
481 /* reset PHY and decide what is present */
482 if (!ata_sata_phy_reset(dev)) {
484 device_printf(dev, "phy reset found no device\n");
487 /* kill off all activity on this channel */
488 cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset);
489 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
490 cmd & ~(ATA_AHCI_P_CMD_FRE | ATA_AHCI_P_CMD_ST));
494 signature = ata_ahci_softreset(dev, 0);
496 device_printf(ch->dev, "SIGNATURE: %08x\n", signature);
498 switch (signature >> 16) {
500 ch->devices = ATA_ATA_MASTER;
503 ch->devices = ATA_PORTMULTIPLIER;
504 device_printf(ch->dev, "Portmultipliers not supported yet\n");
508 ch->devices = ATA_ATAPI_MASTER;
510 default: /* SOS XXX */
512 device_printf(ch->dev, "Unknown signature, assuming disk device\n");
513 ch->devices = ATA_ATA_MASTER;
516 device_printf(dev, "AHCI reset done: devices=%08x\n", ch->devices);
520 ata_ahci_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error)
522 struct ata_dmasetprd_args *args = xsc;
523 struct ata_ahci_dma_prd *prd = args->dmatab;
526 if (!(args->error = error)) {
527 for (i = 0; i < nsegs; i++) {
528 prd[i].dba = htole64(segs[i].ds_addr);
529 prd[i].dbc = htole32((segs[i].ds_len - 1) & ATA_AHCI_PRD_MASK);
533 KASSERT(nsegs <= ATA_AHCI_DMA_ENTRIES, ("too many DMA segment entries\n"));
538 ata_ahci_dmainit(device_t dev)
540 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
541 struct ata_channel *ch = device_get_softc(dev);
545 /* note start and stop are not used here */
546 ch->dma->setprd = ata_ahci_dmasetprd;
547 ch->dma->max_iosize = (ATA_AHCI_DMA_ENTRIES - 1) * PAGE_SIZE;
548 if (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_CAP_64BIT)
549 ch->dma->max_address = BUS_SPACE_MAXADDR;
554 ata_ahci_setup_fis(struct ata_ahci_cmd_tab *ctp, struct ata_request *request)
556 bzero(ctp->cfis, 64);
557 if (request->flags & ATA_R_ATAPI) {
558 bzero(ctp->acmd, 32);
559 bcopy(request->u.atapi.ccb, ctp->acmd, 16);
561 return ata_request2fis_h2d(request, &ctp->cfis[0]);