2 * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 /* local prototypes */
28 static int ata_cmd_allocate(device_t dev);
29 static int ata_cmd_status(device_t dev);
30 static void ata_cmd_setmode(device_t dev, int mode);
31 static int ata_sii_allocate(device_t dev);
32 static int ata_sii_status(device_t dev);
33 static void ata_sii_reset(device_t dev);
34 static void ata_sii_setmode(device_t dev, int mode);
35 static int ata_siiprb_allocate(device_t dev);
36 static int ata_siiprb_status(device_t dev);
37 static int ata_siiprb_begin_transaction(struct ata_request *request);
38 static int ata_siiprb_end_transaction(struct ata_request *request);
39 static u_int32_t ata_siiprb_softreset(device_t dev, int port);
40 static void ata_siiprb_reset(device_t dev);
41 static void ata_siiprb_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error);
42 static void ata_siiprb_dmainit(device_t dev);
48 #define SII_SETCLK 0x02
53 * Silicon Image Inc. (SiI) (former CMD) chipset support functions
56 ata_sii_ident(device_t dev)
58 struct ata_pci_controller *ctlr = device_get_softc(dev);
59 static const struct ata_chip_id ids[] =
60 {{ ATA_SII3114, 0x00, SII_MEMIO, SII_4CH, ATA_SA150, "SiI 3114" },
61 { ATA_SII3512, 0x02, SII_MEMIO, 0, ATA_SA150, "SiI 3512" },
62 { ATA_SII3112, 0x02, SII_MEMIO, 0, ATA_SA150, "SiI 3112" },
63 { ATA_SII3112_1, 0x02, SII_MEMIO, 0, ATA_SA150, "SiI 3112" },
64 { ATA_SII3512, 0x00, SII_MEMIO, SII_BUG, ATA_SA150, "SiI 3512" },
65 { ATA_SII3112, 0x00, SII_MEMIO, SII_BUG, ATA_SA150, "SiI 3112" },
66 { ATA_SII3112_1, 0x00, SII_MEMIO, SII_BUG, ATA_SA150, "SiI 3112" },
67 { ATA_SII3124, 0x00, SII_PRBIO, SII_4CH, ATA_SA300, "SiI 3124" },
68 { ATA_SII3132, 0x00, SII_PRBIO, 0, ATA_SA300, "SiI 3132" },
69 { ATA_SII0680, 0x00, SII_MEMIO, SII_SETCLK, ATA_UDMA6, "SiI 0680" },
70 { ATA_CMD649, 0x00, 0, SII_INTR, ATA_UDMA5, "CMD 649" },
71 { ATA_CMD648, 0x00, 0, SII_INTR, ATA_UDMA4, "CMD 648" },
72 { ATA_CMD646, 0x07, 0, 0, ATA_UDMA2, "CMD 646U2" },
73 { ATA_CMD646, 0x00, 0, 0, ATA_WDMA2, "CMD 646" },
76 if (pci_get_vendor(dev) != ATA_SILICON_IMAGE_ID)
79 if (!(ctlr->chip = ata_match_chip(dev, ids)))
83 ctlr->chipinit = ata_sii_chipinit;
88 ata_sii_chipinit(device_t dev)
90 struct ata_pci_controller *ctlr = device_get_softc(dev);
92 if (ata_setup_interrupt(dev, ata_generic_intr))
95 switch (ctlr->chip->cfg1) {
97 ctlr->r_type1 = SYS_RES_MEMORY;
98 ctlr->r_rid1 = PCIR_BAR(0);
99 if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1,
100 &ctlr->r_rid1, RF_ACTIVE))){
101 ata_teardown_interrupt(dev);
105 ctlr->r_rid2 = PCIR_BAR(2);
106 ctlr->r_type2 = SYS_RES_MEMORY;
107 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
108 &ctlr->r_rid2, RF_ACTIVE))){
109 bus_release_resource(dev, ctlr->r_type1, ctlr->r_rid1,ctlr->r_res1);
110 ata_teardown_interrupt(dev);
113 ctlr->allocate = ata_siiprb_allocate;
114 ctlr->reset = ata_siiprb_reset;
115 ctlr->dmainit = ata_siiprb_dmainit;
116 ctlr->setmode = ata_sata_setmode;
117 ctlr->channels = (ctlr->chip->cfg2 == SII_4CH) ? 4 : 2;
119 /* reset controller */
120 ATA_OUTL(ctlr->r_res1, 0x0040, 0x80000000);
122 ATA_OUTL(ctlr->r_res1, 0x0040, 0x0000000f);
124 /* enable PCI interrupt */
125 pci_write_config(dev, PCIR_COMMAND,
126 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2);
130 ctlr->r_type2 = SYS_RES_MEMORY;
131 ctlr->r_rid2 = PCIR_BAR(5);
132 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
133 &ctlr->r_rid2, RF_ACTIVE))){
134 if (ctlr->chip->chipid != ATA_SII0680 ||
135 (pci_read_config(dev, 0x8a, 1) & 1)) {
136 ata_teardown_interrupt(dev);
141 if (ctlr->chip->cfg2 & SII_SETCLK) {
142 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10)
143 pci_write_config(dev, 0x8a,
144 (pci_read_config(dev, 0x8a, 1) & 0xcf)|0x10,1);
145 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10)
146 device_printf(dev, "%s could not set ATA133 clock\n",
150 /* if we have 4 channels enable the second set */
151 if (ctlr->chip->cfg2 & SII_4CH) {
152 ATA_OUTL(ctlr->r_res2, 0x0200, 0x00000002);
156 /* dont block interrupts from any channel */
157 pci_write_config(dev, 0x48,
158 (pci_read_config(dev, 0x48, 4) & ~0x03c00000), 4);
160 /* enable PCI interrupt as BIOS might not */
161 pci_write_config(dev, 0x8a, (pci_read_config(dev, 0x8a, 1) & 0x3f), 1);
164 ctlr->allocate = ata_sii_allocate;
166 if (ctlr->chip->max_dma >= ATA_SA150) {
167 ctlr->reset = ata_sii_reset;
168 ctlr->setmode = ata_sata_setmode;
171 ctlr->setmode = ata_sii_setmode;
175 if ((pci_read_config(dev, 0x51, 1) & 0x08) != 0x08) {
176 device_printf(dev, "HW has secondary channel disabled\n");
180 /* enable interrupt as BIOS might not */
181 pci_write_config(dev, 0x71, 0x01, 1);
183 ctlr->allocate = ata_cmd_allocate;
184 ctlr->setmode = ata_cmd_setmode;
191 ata_cmd_allocate(device_t dev)
193 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
194 struct ata_channel *ch = device_get_softc(dev);
196 /* setup the usual register normal pci style */
197 if (ata_pci_allocate(dev))
200 if (ctlr->chip->cfg2 & SII_INTR)
201 ch->hw.status = ata_cmd_status;
207 ata_cmd_status(device_t dev)
209 struct ata_channel *ch = device_get_softc(dev);
212 if (((reg71 = pci_read_config(device_get_parent(ch->dev), 0x71, 1)) &
213 (ch->unit ? 0x08 : 0x04))) {
214 pci_write_config(device_get_parent(ch->dev), 0x71,
215 reg71 & ~(ch->unit ? 0x04 : 0x08), 1);
216 return ata_pci_status(dev);
222 ata_cmd_setmode(device_t dev, int mode)
224 device_t gparent = GRANDPARENT(dev);
225 struct ata_pci_controller *ctlr = device_get_softc(gparent);
226 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
227 struct ata_device *atadev = device_get_softc(dev);
228 int devno = (ch->unit << 1) + atadev->unit;
230 int treg = 0x54 + ((devno < 3) ? (devno << 1) : 7);
231 int ureg = ch->unit ? 0x7b : 0x73;
232 static const uint8_t piotimings[] =
233 { 0xa9, 0x57, 0x44, 0x32, 0x3f };
234 static const uint8_t dmatimings[] = { 0x87, 0x32, 0x3f };
235 static const uint8_t udmatimings[][2] =
236 { { 0x31, 0xc2 }, { 0x21, 0x82 }, { 0x11, 0x42 },
237 { 0x25, 0x8a }, { 0x15, 0x4a }, { 0x05, 0x0a } };
239 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
241 mode = ata_check_80pin(dev, mode);
243 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
246 device_printf(dev, "%ssetting %s on %s chip\n",
247 (error) ? "FAILURE " : "",
248 ata_mode2str(mode), ctlr->chip->text);
250 if (mode >= ATA_UDMA0) {
251 u_int8_t umode = pci_read_config(gparent, ureg, 1);
253 umode &= ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca);
254 umode |= udmatimings[mode & ATA_MODE_MASK][atadev->unit];
255 pci_write_config(gparent, ureg, umode, 1);
257 else if (mode >= ATA_WDMA0) {
258 pci_write_config(gparent, treg, dmatimings[mode & ATA_MODE_MASK],1);
259 pci_write_config(gparent, ureg,
260 pci_read_config(gparent, ureg, 1) &
261 ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca), 1);
264 pci_write_config(gparent, treg,
265 piotimings[(mode & ATA_MODE_MASK) - ATA_PIO0], 1);
266 pci_write_config(gparent, ureg,
267 pci_read_config(gparent, ureg, 1) &
268 ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca), 1);
275 ata_sii_allocate(device_t dev)
277 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
278 struct ata_channel *ch = device_get_softc(dev);
279 int unit01 = (ch->unit & 1), unit10 = (ch->unit & 2);
282 for (i = ATA_DATA; i <= ATA_COMMAND; i++) {
283 ch->r_io[i].res = ctlr->r_res2;
284 ch->r_io[i].offset = 0x80 + i + (unit01 << 6) + (unit10 << 8);
286 ch->r_io[ATA_CONTROL].res = ctlr->r_res2;
287 ch->r_io[ATA_CONTROL].offset = 0x8a + (unit01 << 6) + (unit10 << 8);
288 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2;
289 ata_default_registers(dev);
291 ch->r_io[ATA_BMCMD_PORT].res = ctlr->r_res2;
292 ch->r_io[ATA_BMCMD_PORT].offset = 0x00 + (unit01 << 3) + (unit10 << 8);
293 ch->r_io[ATA_BMSTAT_PORT].res = ctlr->r_res2;
294 ch->r_io[ATA_BMSTAT_PORT].offset = 0x02 + (unit01 << 3) + (unit10 << 8);
295 ch->r_io[ATA_BMDTP_PORT].res = ctlr->r_res2;
296 ch->r_io[ATA_BMDTP_PORT].offset = 0x04 + (unit01 << 3) + (unit10 << 8);
298 if (ctlr->chip->max_dma >= ATA_SA150) {
299 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
300 ch->r_io[ATA_SSTATUS].offset = 0x104 + (unit01 << 7) + (unit10 << 8);
301 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
302 ch->r_io[ATA_SERROR].offset = 0x108 + (unit01 << 7) + (unit10 << 8);
303 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
304 ch->r_io[ATA_SCONTROL].offset = 0x100 + (unit01 << 7) + (unit10 << 8);
305 ch->flags |= ATA_NO_SLAVE;
307 /* enable PHY state change interrupt */
308 ATA_OUTL(ctlr->r_res2, 0x148 + (unit01 << 7) + (unit10 << 8),(1 << 16));
311 if ((ctlr->chip->cfg2 & SII_BUG) && ch->dma) {
312 /* work around errata in early chips */
313 ch->dma->boundary = 8192;
314 ch->dma->segsize = 15 * DEV_BSIZE;
318 ch->hw.status = ata_sii_status;
323 ata_sii_status(device_t dev)
325 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
326 struct ata_channel *ch = device_get_softc(dev);
327 int offset0 = ((ch->unit & 1) << 3) + ((ch->unit & 2) << 8);
328 int offset1 = ((ch->unit & 1) << 6) + ((ch->unit & 2) << 8);
330 /* do we have any PHY events ? */
331 if (ctlr->chip->max_dma >= ATA_SA150 &&
332 (ATA_INL(ctlr->r_res2, 0x10 + offset0) & 0x00000010))
333 ata_sata_phy_check_events(dev);
335 if (ATA_INL(ctlr->r_res2, 0xa0 + offset1) & 0x00000800)
336 return ata_pci_status(dev);
342 ata_sii_reset(device_t dev)
344 if (ata_sata_phy_reset(dev))
345 ata_generic_reset(dev);
349 ata_sii_setmode(device_t dev, int mode)
351 device_t gparent = GRANDPARENT(dev);
352 struct ata_pci_controller *ctlr = device_get_softc(gparent);
353 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
354 struct ata_device *atadev = device_get_softc(dev);
355 int rego = (ch->unit << 4) + (atadev->unit << 1);
356 int mreg = ch->unit ? 0x84 : 0x80;
357 int mask = 0x03 << (atadev->unit << 2);
358 int mval = pci_read_config(gparent, mreg, 1) & ~mask;
360 u_int8_t preg = 0xa4 + rego;
361 u_int8_t dreg = 0xa8 + rego;
362 u_int8_t ureg = 0xac + rego;
363 static const uint16_t piotimings[] =
364 { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 };
365 static const uint16_t dmatimings[] = { 0x2208, 0x10c2, 0x10c1 };
366 static const uint8_t udmatimings[] =
367 { 0xf, 0xb, 0x7, 0x5, 0x3, 0x2, 0x1 };
369 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
371 if (ctlr->chip->cfg2 & SII_SETCLK) {
372 if (mode > ATA_UDMA2 && (pci_read_config(gparent, 0x79, 1) &
373 (ch->unit ? 0x02 : 0x01))) {
374 ata_print_cable(dev, "controller");
379 mode = ata_check_80pin(dev, mode);
381 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
384 device_printf(dev, "%ssetting %s on %s chip\n",
385 (error) ? "FAILURE " : "",
386 ata_mode2str(mode), ctlr->chip->text);
390 if (mode >= ATA_UDMA0) {
391 pci_write_config(gparent, mreg,
392 mval | (0x03 << (atadev->unit << 2)), 1);
393 pci_write_config(gparent, ureg,
394 (pci_read_config(gparent, ureg, 1) & ~0x3f) |
395 udmatimings[mode & ATA_MODE_MASK], 1);
398 else if (mode >= ATA_WDMA0) {
399 pci_write_config(gparent, mreg,
400 mval | (0x02 << (atadev->unit << 2)), 1);
401 pci_write_config(gparent, dreg, dmatimings[mode & ATA_MODE_MASK], 2);
405 pci_write_config(gparent, mreg,
406 mval | (0x01 << (atadev->unit << 2)), 1);
407 pci_write_config(gparent, preg, piotimings[mode & ATA_MODE_MASK], 2);
412 struct ata_siiprb_dma_prdentry {
418 #define ATA_SIIPRB_DMA_ENTRIES 125
419 struct ata_siiprb_ata_command {
420 struct ata_siiprb_dma_prdentry prd[ATA_SIIPRB_DMA_ENTRIES];
423 struct ata_siiprb_atapi_command {
425 struct ata_siiprb_dma_prdentry prd[ATA_SIIPRB_DMA_ENTRIES];
428 struct ata_siiprb_command {
430 u_int16_t protocol_override;
431 u_int32_t transfer_count;
434 struct ata_siiprb_ata_command ata;
435 struct ata_siiprb_atapi_command atapi;
440 ata_siiprb_allocate(device_t dev)
442 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
443 struct ata_channel *ch = device_get_softc(dev);
444 int offset = ch->unit * 0x2000;
446 /* set the SATA resources */
447 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
448 ch->r_io[ATA_SSTATUS].offset = 0x1f04 + offset;
449 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
450 ch->r_io[ATA_SERROR].offset = 0x1f08 + offset;
451 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
452 ch->r_io[ATA_SCONTROL].offset = 0x1f00 + offset;
453 ch->r_io[ATA_SACTIVE].res = ctlr->r_res2;
454 ch->r_io[ATA_SACTIVE].offset = 0x1f0c + offset;
456 ch->hw.status = ata_siiprb_status;
457 ch->hw.begin_transaction = ata_siiprb_begin_transaction;
458 ch->hw.end_transaction = ata_siiprb_end_transaction;
459 ch->hw.command = NULL; /* not used here */
460 ch->hw.softreset = ata_siiprb_softreset;
465 ata_siiprb_status(device_t dev)
467 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
468 struct ata_channel *ch = device_get_softc(dev);
469 u_int32_t action = ATA_INL(ctlr->r_res1, 0x0044);
470 int offset = ch->unit * 0x2000;
472 if (action & (1 << ch->unit)) {
473 u_int32_t istatus = ATA_INL(ctlr->r_res2, 0x1008 + offset);
475 /* do we have any PHY events ? */
476 ata_sata_phy_check_events(dev);
478 /* clear interrupt(s) */
479 ATA_OUTL(ctlr->r_res2, 0x1008 + offset, istatus);
481 /* do we have any device action ? */
482 return (istatus & 0x00000003);
488 ata_siiprb_begin_transaction(struct ata_request *request)
490 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev));
491 struct ata_channel *ch = device_get_softc(request->parent);
492 struct ata_siiprb_command *prb;
493 struct ata_siiprb_dma_prdentry *prd;
494 int offset = ch->unit * 0x2000;
499 if (request->u.ata.command == ATA_DEVICE_RESET) {
501 return ATA_OP_FINISHED;
504 /* check for 48 bit access and convert if needed */
505 ata_modify_if_48bit(request);
507 /* get a piece of the workspace for this request */
508 prb = (struct ata_siiprb_command *)ch->dma->work;
510 /* set basic prd options ata/atapi etc etc */
511 bzero(prb, sizeof(struct ata_siiprb_command));
513 /* setup the FIS for this request */
514 if (!ata_request2fis_h2d(request, &prb->fis[0])) {
515 device_printf(request->dev, "setting up SATA FIS failed\n");
516 request->result = EIO;
517 return ATA_OP_FINISHED;
520 /* setup transfer type */
521 if (request->flags & ATA_R_ATAPI) {
522 struct ata_device *atadev = device_get_softc(request->dev);
524 bcopy(request->u.atapi.ccb, prb->u.atapi.ccb, 16);
525 if ((atadev->param.config & ATA_PROTO_MASK) == ATA_PROTO_ATAPI_12)
526 ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000020);
528 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000020);
529 if (request->flags & ATA_R_READ)
530 prb->control = htole16(0x0010);
531 if (request->flags & ATA_R_WRITE)
532 prb->control = htole16(0x0020);
533 prd = &prb->u.atapi.prd[0];
536 prd = &prb->u.ata.prd[0];
538 /* if request moves data setup and load SG list */
539 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) {
540 if (ch->dma->load(ch->dev, request->data, request->bytecount,
541 request->flags & ATA_R_READ, prd, &dummy)) {
542 device_printf(request->dev, "setting up DMA failed\n");
543 request->result = EIO;
544 return ATA_OP_FINISHED;
548 /* activate the prb */
549 prb_bus = ch->dma->work_bus;
550 ATA_OUTL(ctlr->r_res2, 0x1c00 + offset, prb_bus);
551 ATA_OUTL(ctlr->r_res2, 0x1c04 + offset, prb_bus>>32);
553 /* start the timeout */
554 callout_reset(&request->callout, request->timeout * hz,
555 (timeout_t*)ata_timeout, request);
556 return ATA_OP_CONTINUES;
560 ata_siiprb_end_transaction(struct ata_request *request)
562 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev));
563 struct ata_channel *ch = device_get_softc(request->parent);
564 struct ata_siiprb_command *prb;
565 int offset = ch->unit * 0x2000;
568 /* kill the timeout */
569 callout_stop_sync(&request->callout);
571 prb = (struct ata_siiprb_command *)
572 ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + offset);
574 /* any controller errors flagged ? */
575 if ((error = ATA_INL(ctlr->r_res2, 0x1024 + offset))) {
577 kprintf("ata_siiprb_end_transaction %s error=%08x\n",
578 ata_cmd2str(request), error);
580 /* if device error status get details */
581 if (error == 1 || error == 2) {
582 request->status = prb->fis[2];
583 if (request->status & ATA_S_ERROR)
584 request->error = prb->fis[3];
587 /* SOS XXX handle other controller errors here */
589 /* initialize port */
590 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000004);
592 /* poll for port ready */
593 for (timeout = 0; timeout < 1000; timeout++) {
595 if (ATA_INL(ctlr->r_res2, 0x1008 + offset) & 0x00040000)
600 device_printf(ch->dev, "port initialize timeout\n");
602 device_printf(ch->dev, "port initialize time=%dms\n", timeout);
606 /* update progress */
607 if (!(request->status & ATA_S_ERROR) && !(request->flags & ATA_R_TIMEOUT)) {
608 if (request->flags & ATA_R_READ)
609 request->donecount = prb->transfer_count;
611 request->donecount = request->bytecount;
614 /* release SG list etc */
615 ch->dma->unload(ch->dev);
617 return ATA_OP_FINISHED;
621 ata_siiprb_issue_cmd(device_t dev)
623 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
624 struct ata_channel *ch = device_get_softc(dev);
625 u_int64_t prb_bus = ch->dma->work_bus;
627 int offset = ch->unit * 0x2000;
630 /* issue command to chip */
631 ATA_OUTL(ctlr->r_res2, 0x1c00 + offset, prb_bus);
632 ATA_OUTL(ctlr->r_res2, 0x1c04 + offset, prb_bus >> 32);
634 /* poll for command finished */
635 for (timeout = 0; timeout < 10000; timeout++) {
637 if ((status = ATA_INL(ctlr->r_res2, 0x1008 + offset)) & 0x00010000)
644 device_printf(ch->dev, "ata_siiprb_issue_cmd time=%dms status=%08x\n",
650 ata_siiprb_softreset(device_t dev, int port)
652 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
653 struct ata_channel *ch = device_get_softc(dev);
654 struct ata_siiprb_command *prb = (struct ata_siiprb_command *)ch->dma->work;
656 int offset = ch->unit * 0x2000;
658 /* setup the workspace for a soft reset command */
659 bzero(prb, sizeof(struct ata_siiprb_command));
660 prb->control = htole16(0x0080);
661 prb->fis[1] = port & 0x0f;
663 /* issue soft reset */
664 if (ata_siiprb_issue_cmd(dev))
669 /* get possible signature */
670 prb = (struct ata_siiprb_command *)
671 ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + offset);
672 signature=prb->fis[12]|(prb->fis[4]<<8)|(prb->fis[5]<<16)|(prb->fis[6]<<24);
678 ata_siiprb_reset(device_t dev)
680 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
681 struct ata_channel *ch = device_get_softc(dev);
682 int offset = ch->unit * 0x2000;
683 u_int32_t status, signature;
686 /* reset channel HW */
687 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000001);
689 ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000001);
692 /* poll for channel ready */
693 for (timeout = 0; timeout < 1000; timeout++) {
694 if ((status = ATA_INL(ctlr->r_res2, 0x1008 + offset)) & 0x00040000)
701 device_printf(ch->dev, "channel HW reset timeout\n");
703 device_printf(ch->dev, "channel HW reset time=%dms\n", timeout);
707 if (!ata_sata_phy_reset(dev)) {
709 device_printf(ch->dev, "phy reset found no device\n");
714 /* issue soft reset */
715 signature = ata_siiprb_softreset(dev, ATA_PM);
717 device_printf(ch->dev, "SIGNATURE: %08x\n", signature);
719 /* figure out whats there */
720 switch (signature >> 16) {
722 ch->devices = ATA_ATA_MASTER;
725 ch->devices = ATA_PORTMULTIPLIER;
726 device_printf(ch->dev, "Portmultipliers not supported yet\n");
730 ch->devices = ATA_ATAPI_MASTER;
736 device_printf(dev, "siiprb_reset devices=%08x\n", ch->devices);
739 /* clear interrupt(s) */
740 ATA_OUTL(ctlr->r_res2, 0x1008 + offset, 0x000008ff);
742 /* require explicit interrupt ack */
743 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000008);
746 ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000400);
748 /* enable interrupts wanted */
749 ATA_OUTL(ctlr->r_res2, 0x1010 + offset, 0x000000ff);
753 ata_siiprb_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error)
755 struct ata_dmasetprd_args *args = xsc;
756 struct ata_siiprb_dma_prdentry *prd = args->dmatab;
759 if ((args->error = error))
762 for (i = 0; i < nsegs; i++) {
763 prd[i].addr = htole64(segs[i].ds_addr);
764 prd[i].count = htole32(segs[i].ds_len);
766 prd[i - 1].control = htole32(ATA_DMA_EOT);
767 KASSERT(nsegs <= ATA_SIIPRB_DMA_ENTRIES,("too many DMA segment entries\n"));
772 ata_siiprb_dmainit(device_t dev)
774 struct ata_channel *ch = device_get_softc(dev);
778 /* note start and stop are not used here */
779 ch->dma->setprd = ata_siiprb_dmasetprd;
780 ch->dma->max_address = BUS_SPACE_MAXADDR;