2 * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 /* local prototypes */
28 static int ata_via_chipinit(device_t dev);
29 static int ata_via_allocate(device_t dev);
30 static void ata_via_reset(device_t dev);
31 static void ata_via_old_setmode(device_t dev, int mode);
32 static void ata_via_southbridge_fixup(device_t dev);
33 static void ata_via_new_setmode(device_t dev, int mode);
47 * VIA Technologies Inc. chipset support functions
50 ata_via_ident(device_t dev)
52 struct ata_pci_controller *ctlr = device_get_softc(dev);
53 static const struct ata_chip_id ids[] =
54 {{ ATA_VIA82C586, 0x02, VIA33, 0x00, ATA_UDMA2, "82C586B" },
55 { ATA_VIA82C586, 0x00, VIA33, 0x00, ATA_WDMA2, "82C586" },
56 { ATA_VIA82C596, 0x12, VIA66, VIACLK, ATA_UDMA4, "82C596B" },
57 { ATA_VIA82C596, 0x00, VIA33, 0x00, ATA_UDMA2, "82C596" },
58 { ATA_VIA82C686, 0x40, VIA100, VIABUG, ATA_UDMA5, "82C686B"},
59 { ATA_VIA82C686, 0x10, VIA66, VIACLK, ATA_UDMA4, "82C686A" },
60 { ATA_VIA82C686, 0x00, VIA33, 0x00, ATA_UDMA2, "82C686" },
61 { ATA_VIA8231, 0x00, VIA100, VIABUG, ATA_UDMA5, "8231" },
62 { ATA_VIA8233, 0x00, VIA100, 0x00, ATA_UDMA5, "8233" },
63 { ATA_VIA8233C, 0x00, VIA100, 0x00, ATA_UDMA5, "8233C" },
64 { ATA_VIA8233A, 0x00, VIA133, 0x00, ATA_UDMA6, "8233A" },
65 { ATA_VIA8235, 0x00, VIA133, 0x00, ATA_UDMA6, "8235" },
66 { ATA_VIA8237, 0x00, VIA133, 0x00, ATA_UDMA6, "8237" },
67 { ATA_VIA8237A, 0x00, VIA133, 0x00, ATA_UDMA6, "8237A" },
68 { ATA_VIA8251, 0x00, VIA133, 0x00, ATA_UDMA6, "8251" },
69 { 0, 0, 0, 0, 0, 0 }};
70 static const struct ata_chip_id new_ids[] =
71 {{ ATA_VIA6410, 0x00, 0, 0x00, ATA_UDMA6, "6410" },
72 { ATA_VIA6420, 0x00, 7, 0x00, ATA_SA150, "6420" },
73 { ATA_VIA6421, 0x00, 6, VIABAR, ATA_SA150, "6421" },
74 { ATA_VIA8237A, 0x00, 7, 0x00, ATA_SA150, "8237A" },
75 { ATA_VIA8237S, 0x00, 7, 0x00, ATA_SA150, "8237S" },
76 { ATA_VIA8251, 0x00, 0, VIAAHCI, ATA_SA300, "8251" },
77 { 0, 0, 0, 0, 0, 0 }};
79 if (pci_get_vendor(dev) != ATA_VIA_ID)
82 if (pci_get_devid(dev) == ATA_VIA82C571) {
83 if (!(ctlr->chip = ata_find_chip(dev, ids, -99)))
87 if (!(ctlr->chip = ata_match_chip(dev, new_ids)))
92 ctlr->chipinit = ata_via_chipinit;
97 ata_via_chipinit(device_t dev)
99 struct ata_pci_controller *ctlr = device_get_softc(dev);
101 if (ata_setup_interrupt(dev, ata_generic_intr))
104 if (ctlr->chip->max_dma >= ATA_SA150) {
105 /* do we have AHCI capability ? */
106 if ((ctlr->chip->cfg2 == VIAAHCI) && ata_ahci_chipinit(dev) != ENXIO)
109 ctlr->r_type2 = SYS_RES_IOPORT;
110 ctlr->r_rid2 = PCIR_BAR(5);
111 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
112 &ctlr->r_rid2, RF_ACTIVE))) {
113 ctlr->allocate = ata_via_allocate;
114 ctlr->reset = ata_via_reset;
116 /* enable PCI interrupt */
117 pci_write_config(dev, PCIR_COMMAND,
118 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400,2);
121 if (ctlr->chip->cfg2 & VIABAR) {
123 ctlr->setmode = ata_via_new_setmode;
126 ctlr->setmode = ata_sata_setmode;
130 /* prepare for ATA-66 on the 82C686a and 82C596b */
131 if (ctlr->chip->cfg2 & VIACLK)
132 pci_write_config(dev, 0x50, 0x030b030b, 4);
134 /* the southbridge might need the data corruption fix */
135 if (ctlr->chip->cfg2 & VIABUG)
136 ata_via_southbridge_fixup(dev);
138 /* set fifo configuration half'n'half */
139 pci_write_config(dev, 0x43,
140 (pci_read_config(dev, 0x43, 1) & 0x90) | 0x2a, 1);
142 /* set status register read retry */
143 pci_write_config(dev, 0x44, pci_read_config(dev, 0x44, 1) | 0x08, 1);
145 /* set DMA read & end-of-sector fifo flush */
146 pci_write_config(dev, 0x46,
147 (pci_read_config(dev, 0x46, 1) & 0x0c) | 0xf0, 1);
149 /* set sector size */
150 pci_write_config(dev, 0x60, DEV_BSIZE, 2);
151 pci_write_config(dev, 0x68, DEV_BSIZE, 2);
153 ctlr->setmode = ata_via_old_setmode;
158 ata_via_allocate(device_t dev)
160 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
161 struct ata_channel *ch = device_get_softc(dev);
163 /* newer SATA chips has resources in one BAR for each channel */
164 if (ctlr->chip->cfg2 & VIABAR) {
165 struct resource *r_io;
168 rid = PCIR_BAR(ch->unit);
169 if (!(r_io = bus_alloc_resource_any(device_get_parent(dev),
174 for (i = ATA_DATA; i <= ATA_COMMAND; i ++) {
175 ch->r_io[i].res = r_io;
176 ch->r_io[i].offset = i;
178 ch->r_io[ATA_CONTROL].res = r_io;
179 ch->r_io[ATA_CONTROL].offset = 2 + ATA_IOSIZE;
180 ch->r_io[ATA_IDX_ADDR].res = r_io;
181 ata_default_registers(dev);
182 for (i = ATA_BMCMD_PORT; i <= ATA_BMDTP_PORT; i++) {
183 ch->r_io[i].res = ctlr->r_res1;
184 ch->r_io[i].offset = (i - ATA_BMCMD_PORT)+(ch->unit * ATA_BMIOSIZE);
191 /* setup the usual register normal pci style */
192 if (ata_pci_allocate(dev))
196 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
197 ch->r_io[ATA_SSTATUS].offset = (ch->unit << ctlr->chip->cfg1);
198 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
199 ch->r_io[ATA_SERROR].offset = 0x04 + (ch->unit << ctlr->chip->cfg1);
200 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
201 ch->r_io[ATA_SCONTROL].offset = 0x08 + (ch->unit << ctlr->chip->cfg1);
202 ch->flags |= ATA_NO_SLAVE;
204 /* XXX SOS PHY hotplug handling missing in VIA chip ?? */
205 /* XXX SOS unknown how to enable PHY state change interrupt */
210 ata_via_reset(device_t dev)
212 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
213 struct ata_channel *ch = device_get_softc(dev);
215 if ((ctlr->chip->cfg2 & VIABAR) && (ch->unit > 1))
216 ata_generic_reset(dev);
218 if (ata_sata_phy_reset(dev))
219 ata_generic_reset(dev);
223 ata_via_new_setmode(device_t dev, int mode)
225 device_t gparent = GRANDPARENT(dev);
226 struct ata_pci_controller *ctlr = device_get_softc(gparent);
227 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
228 struct ata_device *atadev = device_get_softc(dev);
231 if ((ctlr->chip->cfg2 & VIABAR) && (ch->unit > 1)) {
232 static const uint8_t pio_timings[] = { 0xa8, 0x65, 0x65, 0x32, 0x20,
234 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 };
235 static const uint8_t dma_timings[] = { 0xee, 0xe8, 0xe6, 0xe4, 0xe2, 0xe1, 0xe0 };
237 mode = ata_check_80pin(dev, ata_limit_mode(dev, mode, ATA_UDMA6));
238 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
240 device_printf(dev, "%ssetting %s on %s chip\n",
241 (error) ? "FAILURE " : "", ata_mode2str(mode),
244 pci_write_config(gparent, 0xab, pio_timings[ata_mode2idx(mode)], 1);
245 if (mode >= ATA_UDMA0)
246 pci_write_config(gparent, 0xb3,
247 dma_timings[mode & ATA_MODE_MASK], 1);
252 ata_sata_setmode(dev, mode);
256 ata_via_old_setmode(device_t dev, int mode)
258 device_t gparent = GRANDPARENT(dev);
259 struct ata_pci_controller *ctlr = device_get_softc(gparent);
260 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
261 struct ata_device *atadev = device_get_softc(dev);
262 int devno = (ch->unit << 1) + atadev->unit;
263 int reg = 0x53 - devno;
265 static const uint8_t timings[] =
266 { 0xa8, 0x65, 0x42, 0x22, 0x20, 0x42, 0x22, 0x20,
267 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 };
268 static const uint8_t modes[][7] = {
269 { 0xc2, 0xc1, 0xc0, 0x00, 0x00, 0x00, 0x00 }, /* VIA ATA33 */
270 { 0xee, 0xec, 0xea, 0xe9, 0xe8, 0x00, 0x00 }, /* VIA ATA66 */
271 { 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0, 0x00 }, /* VIA ATA100 */
272 { 0xf7, 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0 } }; /* VIA ATA133 */
274 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
275 mode = ata_check_80pin(dev, mode);
277 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
279 device_printf(dev, "%ssetting %s on %s chip\n",
280 (error) ? "FAILURE " : "", ata_mode2str(mode),
283 if (ctlr->chip->cfg1 != VIA133)
284 pci_write_config(gparent, reg - 0x08,timings[ata_mode2idx(mode)],1);
285 if (mode >= ATA_UDMA0)
286 pci_write_config(gparent, reg,
287 modes[ctlr->chip->cfg1][mode & ATA_MODE_MASK], 1);
289 pci_write_config(gparent, reg, 0x8b, 1);
295 ata_via_southbridge_fixup(device_t dev)
300 if (device_get_children(device_get_parent(dev), &children, &nchildren))
303 for (i = 0; i < nchildren; i++) {
304 if (pci_get_devid(children[i]) == ATA_VIA8363 ||
305 pci_get_devid(children[i]) == ATA_VIA8371 ||
306 pci_get_devid(children[i]) == ATA_VIA8662 ||
307 pci_get_devid(children[i]) == ATA_VIA8361) {
308 u_int8_t reg76 = pci_read_config(children[i], 0x76, 1);
310 if ((reg76 & 0xf0) != 0xd0) {
312 "Correcting VIA config for southbridge data corruption bug\n");
313 pci_write_config(children[i], 0x75, 0x80, 1);
314 pci_write_config(children[i], 0x76, (reg76 & 0x0f) | 0xd0, 1);
319 kfree(children, M_TEMP);