sys/dev/drm/i915/intel_dsi_panel_vbt.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Author: Shobhit Kumar <shobhit.kumar@intel.com>
  24  *
  25  */
  26
  27 #include <drm/drmP.h>
  28 #include <drm/drm_crtc.h>
  29 #include <drm/drm_edid.h>
  30 #include <drm/i915_drm.h>
  31 #include <linux/slab.h>
  32 #include <video/mipi_display.h>
  33 #include <video/mipi_display.h>
  34 #include "i915_drv.h"
  35 #include "intel_drv.h"
  36 #include "intel_dsi.h"
  37 #include "intel_dsi_cmd.h"
  38
  39 #define MIPI_TRANSFER_MODE_SHIFT        0
  40 #define MIPI_VIRTUAL_CHANNEL_SHIFT      1
  41 #define MIPI_PORT_SHIFT                 3
  42
  43 #define PREPARE_CNT_MAX         0x3F
  44 #define EXIT_ZERO_CNT_MAX       0x3F
  45 #define CLK_ZERO_CNT_MAX        0xFF
  46 #define TRAIL_CNT_MAX           0x1F
  47
  48 #define NS_KHZ_RATIO 1000000
  49
  50 #define GPI0_NC_0_HV_DDI0_HPD           0x4130
  51 #define GPIO_NC_0_HV_DDI0_PAD           0x4138
  52 #define GPIO_NC_1_HV_DDI0_DDC_SDA       0x4120
  53 #define GPIO_NC_1_HV_DDI0_DDC_SDA_PAD   0x4128
  54 #define GPIO_NC_2_HV_DDI0_DDC_SCL       0x4110
  55 #define GPIO_NC_2_HV_DDI0_DDC_SCL_PAD   0x4118
  56 #define GPIO_NC_3_PANEL0_VDDEN          0x4140
  57 #define GPIO_NC_3_PANEL0_VDDEN_PAD      0x4148
  58 #define GPIO_NC_4_PANEL0_BLKEN          0x4150
  59 #define GPIO_NC_4_PANEL0_BLKEN_PAD      0x4158
  60 #define GPIO_NC_5_PANEL0_BLKCTL         0x4160
  61 #define GPIO_NC_5_PANEL0_BLKCTL_PAD     0x4168
  62 #define GPIO_NC_6_PCONF0                0x4180
  63 #define GPIO_NC_6_PAD                   0x4188
  64 #define GPIO_NC_7_PCONF0                0x4190
  65 #define GPIO_NC_7_PAD                   0x4198
  66 #define GPIO_NC_8_PCONF0                0x4170
  67 #define GPIO_NC_8_PAD                   0x4178
  68 #define GPIO_NC_9_PCONF0                0x4100
  69 #define GPIO_NC_9_PAD                   0x4108
  70 #define GPIO_NC_10_PCONF0               0x40E0
  71 #define GPIO_NC_10_PAD                  0x40E8
  72 #define GPIO_NC_11_PCONF0               0x40F0
  73 #define GPIO_NC_11_PAD                  0x40F8
  74
  75 struct gpio_table {
  76         u16 function_reg;
  77         u16 pad_reg;
  78         u8 init;
  79 };
  80
  81 static struct gpio_table gtable[] = {
  82         { GPI0_NC_0_HV_DDI0_HPD, GPIO_NC_0_HV_DDI0_PAD, 0 },
  83         { GPIO_NC_1_HV_DDI0_DDC_SDA, GPIO_NC_1_HV_DDI0_DDC_SDA_PAD, 0 },
  84         { GPIO_NC_2_HV_DDI0_DDC_SCL, GPIO_NC_2_HV_DDI0_DDC_SCL_PAD, 0 },
  85         { GPIO_NC_3_PANEL0_VDDEN, GPIO_NC_3_PANEL0_VDDEN_PAD, 0 },
  86         { GPIO_NC_4_PANEL0_BLKEN, GPIO_NC_4_PANEL0_BLKEN_PAD, 0 },
  87         { GPIO_NC_5_PANEL0_BLKCTL, GPIO_NC_5_PANEL0_BLKCTL_PAD, 0 },
  88         { GPIO_NC_6_PCONF0, GPIO_NC_6_PAD, 0 },
  89         { GPIO_NC_7_PCONF0, GPIO_NC_7_PAD, 0 },
  90         { GPIO_NC_8_PCONF0, GPIO_NC_8_PAD, 0 },
  91         { GPIO_NC_9_PCONF0, GPIO_NC_9_PAD, 0 },
  92         { GPIO_NC_10_PCONF0, GPIO_NC_10_PAD, 0},
  93         { GPIO_NC_11_PCONF0, GPIO_NC_11_PAD, 0}
  94 };
  95
  96 static u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi, u8 *data)
  97 {
  98         u8 type, byte, mode, vc, port;
  99         u16 len;
 100
 101         byte = *data++;
 102         mode = (byte >> MIPI_TRANSFER_MODE_SHIFT) & 0x1;
 103         vc = (byte >> MIPI_VIRTUAL_CHANNEL_SHIFT) & 0x3;
 104         port = (byte >> MIPI_PORT_SHIFT) & 0x3;
 105
 106         /* LP or HS mode */
 107         intel_dsi->hs = mode;
 108
 109         /* get packet type and increment the pointer */
 110         type = *data++;
 111
 112         len = *((u16 *) data);
 113         data += 2;
 114
 115         switch (type) {
 116         case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM:
 117                 dsi_vc_generic_write_0(intel_dsi, vc);
 118                 break;
 119         case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM:
 120                 dsi_vc_generic_write_1(intel_dsi, vc, *data);
 121                 break;
 122         case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM:
 123                 dsi_vc_generic_write_2(intel_dsi, vc, *data, *(data + 1));
 124                 break;
 125         case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM:
 126         case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM:
 127         case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM:
 128                 DRM_DEBUG_DRIVER("Generic Read not yet implemented or used\n");
 129                 break;
 130         case MIPI_DSI_GENERIC_LONG_WRITE:
 131                 dsi_vc_generic_write(intel_dsi, vc, data, len);
 132                 break;
 133         case MIPI_DSI_DCS_SHORT_WRITE:
 134                 dsi_vc_dcs_write_0(intel_dsi, vc, *data);
 135                 break;
 136         case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
 137                 dsi_vc_dcs_write_1(intel_dsi, vc, *data, *(data + 1));
 138                 break;
 139         case MIPI_DSI_DCS_READ:
 140                 DRM_DEBUG_DRIVER("DCS Read not yet implemented or used\n");
 141                 break;
 142         case MIPI_DSI_DCS_LONG_WRITE:
 143                 dsi_vc_dcs_write(intel_dsi, vc, data, len);
 144                 break;
 145         }
 146
 147         data += len;
 148
 149         return data;
 150 }
 151
 152 static u8 *mipi_exec_delay(struct intel_dsi *intel_dsi, u8 *data)
 153 {
 154         u32 delay = *((u32 *) data);
 155
 156         usleep_range(delay, delay + 10);
 157         data += 4;
 158
 159         return data;
 160 }
 161
 162 static u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, u8 *data)
 163 {
 164         u8 gpio, action;
 165         u16 function, pad;
 166         u32 val;
 167         struct drm_device *dev = intel_dsi->base.base.dev;
 168         struct drm_i915_private *dev_priv = dev->dev_private;
 169
 170         gpio = *data++;
 171
 172         /* pull up/down */
 173         action = *data++;
 174
 175         function = gtable[gpio].function_reg;
 176         pad = gtable[gpio].pad_reg;
 177
 178         mutex_lock(&dev_priv->dpio_lock);
 179         if (!gtable[gpio].init) {
 180                 /* program the function */
 181                 /* FIXME: remove constant below */
 182                 vlv_gpio_nc_write(dev_priv, function, 0x2000CC00);
 183                 gtable[gpio].init = 1;
 184         }
 185
 186         val = 0x4 | action;
 187
 188         /* pull up/down */
 189         vlv_gpio_nc_write(dev_priv, pad, val);
 190         mutex_unlock(&dev_priv->dpio_lock);
 191
 192         return data;
 193 }
 194
 195 typedef u8 * (*fn_mipi_elem_exec)(struct intel_dsi *intel_dsi, u8 *data);
 196 static const fn_mipi_elem_exec exec_elem[] = {
 197         NULL, /* reserved */
 198         mipi_exec_send_packet,
 199         mipi_exec_delay,
 200         mipi_exec_gpio,
 201         NULL, /* status read; later */
 202 };
 203
 204 /*
 205  * MIPI Sequence from VBT #53 parsing logic
 206  * We have already separated each seqence during bios parsing
 207  * Following is generic execution function for any sequence
 208  */
 209
 210 static const char * const seq_name[] = {
 211         "UNDEFINED",
 212         "MIPI_SEQ_ASSERT_RESET",
 213         "MIPI_SEQ_INIT_OTP",
 214         "MIPI_SEQ_DISPLAY_ON",
 215         "MIPI_SEQ_DISPLAY_OFF",
 216         "MIPI_SEQ_DEASSERT_RESET"
 217 };
 218
 219 static void generic_exec_sequence(struct intel_dsi *intel_dsi, char *sequence)
 220 {
 221         u8 *data = sequence;
 222         fn_mipi_elem_exec mipi_elem_exec;
 223         int index;
 224
 225         if (!sequence)
 226                 return;
 227
 228         DRM_DEBUG_DRIVER("Starting MIPI sequence - %s\n", seq_name[*data]);
 229
 230         /* go to the first element of the sequence */
 231         data++;
 232
 233         /* parse each byte till we reach end of sequence byte - 0x00 */
 234         while (1) {
 235                 index = *data;
 236                 mipi_elem_exec = exec_elem[index];
 237                 if (!mipi_elem_exec) {
 238                         DRM_ERROR("Unsupported MIPI element, skipping sequence execution\n");
 239                         return;
 240                 }
 241
 242                 /* goto element payload */
 243                 data++;
 244
 245                 /* execute the element specific rotines */
 246                 data = mipi_elem_exec(intel_dsi, data);
 247
 248                 /*
 249                  * After processing the element, data should point to
 250                  * next element or end of sequence
 251                  * check if have we reached end of sequence
 252                  */
 253                 if (*data == 0x00)
 254                         break;
 255         }
 256 }
 257
 258 static bool generic_init(struct intel_dsi_device *dsi)
 259 {
 260         struct intel_dsi *intel_dsi = container_of(dsi, struct intel_dsi, dev);
 261         struct drm_device *dev = intel_dsi->base.base.dev;
 262         struct drm_i915_private *dev_priv = dev->dev_private;
 263         struct mipi_config *mipi_config = dev_priv->vbt.dsi.config;
 264         struct mipi_pps_data *pps = dev_priv->vbt.dsi.pps;
 265         struct drm_display_mode *mode = dev_priv->vbt.lfp_lvds_vbt_mode;
 266         u32 bits_per_pixel = 24;
 267         u32 tlpx_ns, extra_byte_count, bitrate, tlpx_ui;
 268         u32 ui_num, ui_den;
 269         u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt;
 270         u32 ths_prepare_ns, tclk_trail_ns;
 271         u32 tclk_prepare_clkzero, ths_prepare_hszero;
 272         u32 lp_to_hs_switch, hs_to_lp_switch;
 273
 274         DRM_DEBUG_KMS("\n");
 275
 276         intel_dsi->eotp_pkt = mipi_config->eot_pkt_disabled ? 0 : 1;
 277         intel_dsi->clock_stop = mipi_config->enable_clk_stop ? 1 : 0;
 278         intel_dsi->lane_count = mipi_config->lane_cnt + 1;
 279         intel_dsi->pixel_format = mipi_config->videomode_color_format << 7;
 280
 281         if (intel_dsi->pixel_format == VID_MODE_FORMAT_RGB666)
 282                 bits_per_pixel = 18;
 283         else if (intel_dsi->pixel_format == VID_MODE_FORMAT_RGB565)
 284                 bits_per_pixel = 16;
 285
 286         bitrate = (mode->clock * bits_per_pixel) / intel_dsi->lane_count;
 287
 288         intel_dsi->operation_mode = mipi_config->is_cmd_mode;
 289         intel_dsi->video_mode_format = mipi_config->video_transfer_mode;
 290         intel_dsi->escape_clk_div = mipi_config->byte_clk_sel;
 291         intel_dsi->lp_rx_timeout = mipi_config->lp_rx_timeout;
 292         intel_dsi->turn_arnd_val = mipi_config->turn_around_timeout;
 293         intel_dsi->rst_timer_val = mipi_config->device_reset_timer;
 294         intel_dsi->init_count = mipi_config->master_init_timer;
 295         intel_dsi->bw_timer = mipi_config->dbi_bw_timer;
 296         intel_dsi->video_frmt_cfg_bits =
 297                 mipi_config->bta_enabled ? DISABLE_VIDEO_BTA : 0;
 298
 299         switch (intel_dsi->escape_clk_div) {
 300         case 0:
 301                 tlpx_ns = 50;
 302                 break;
 303         case 1:
 304                 tlpx_ns = 100;
 305                 break;
 306
 307         case 2:
 308                 tlpx_ns = 200;
 309                 break;
 310         default:
 311                 tlpx_ns = 50;
 312                 break;
 313         }
 314
 315         switch (intel_dsi->lane_count) {
 316         case 1:
 317         case 2:
 318                 extra_byte_count = 2;
 319                 break;
 320         case 3:
 321                 extra_byte_count = 4;
 322                 break;
 323         case 4:
 324         default:
 325                 extra_byte_count = 3;
 326                 break;
 327         }
 328
 329         /*
 330          * ui(s) = 1/f [f in hz]
 331          * ui(ns) = 10^9 / (f*10^6) [f in Mhz] -> 10^3/f(Mhz)
 332          */
 333
 334         /* in Kbps */
 335         ui_num = NS_KHZ_RATIO;
 336         ui_den = bitrate;
 337
 338         tclk_prepare_clkzero = mipi_config->tclk_prepare_clkzero;
 339         ths_prepare_hszero = mipi_config->ths_prepare_hszero;
 340
 341         /*
 342          * B060
 343          * LP byte clock = TLPX/ (8UI)
 344          */
 345         intel_dsi->lp_byte_clk = DIV_ROUND_UP(tlpx_ns * ui_den, 8 * ui_num);
 346
 347         /* count values in UI = (ns value) * (bitrate / (2 * 10^6))
 348          *
 349          * Since txddrclkhs_i is 2xUI, all the count values programmed in
 350          * DPHY param register are divided by 2
 351          *
 352          * prepare count
 353          */
 354         ths_prepare_ns = max(mipi_config->ths_prepare,
 355                              mipi_config->tclk_prepare);
 356         prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den, ui_num * 2);
 357
 358         /* exit zero count */
 359         exit_zero_cnt = DIV_ROUND_UP(
 360                                 (ths_prepare_hszero - ths_prepare_ns) * ui_den,
 361                                 ui_num * 2
 362                                 );
 363
 364         /*
 365          * Exit zero  is unified val ths_zero and ths_exit
 366          * minimum value for ths_exit = 110ns
 367          * min (exit_zero_cnt * 2) = 110/UI
 368          * exit_zero_cnt = 55/UI
 369          */
 370          if (exit_zero_cnt < (55 * ui_den / ui_num))
 371                 if ((55 * ui_den) % ui_num)
 372                         exit_zero_cnt += 1;
 373
 374         /* clk zero count */
 375         clk_zero_cnt = DIV_ROUND_UP(
 376                         (tclk_prepare_clkzero - ths_prepare_ns)
 377                         * ui_den, 2 * ui_num);
 378
 379         /* trail count */
 380         tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail);
 381         trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, 2 * ui_num);
 382
 383         if (prepare_cnt > PREPARE_CNT_MAX ||
 384                 exit_zero_cnt > EXIT_ZERO_CNT_MAX ||
 385                 clk_zero_cnt > CLK_ZERO_CNT_MAX ||
 386                 trail_cnt > TRAIL_CNT_MAX)
 387                 DRM_DEBUG_DRIVER("Values crossing maximum limits, restricting to max values\n");
 388
 389         if (prepare_cnt > PREPARE_CNT_MAX)
 390                 prepare_cnt = PREPARE_CNT_MAX;
 391
 392         if (exit_zero_cnt > EXIT_ZERO_CNT_MAX)
 393                 exit_zero_cnt = EXIT_ZERO_CNT_MAX;
 394
 395         if (clk_zero_cnt > CLK_ZERO_CNT_MAX)
 396                 clk_zero_cnt = CLK_ZERO_CNT_MAX;
 397
 398         if (trail_cnt > TRAIL_CNT_MAX)
 399                 trail_cnt = TRAIL_CNT_MAX;
 400
 401         /* B080 */
 402         intel_dsi->dphy_reg = exit_zero_cnt << 24 | trail_cnt << 16 |
 403                                                 clk_zero_cnt << 8 | prepare_cnt;
 404
 405         /*
 406          * LP to HS switch count = 4TLPX + PREP_COUNT * 2 + EXIT_ZERO_COUNT * 2
 407          *                                      + 10UI + Extra Byte Count
 408          *
 409          * HS to LP switch count = THS-TRAIL + 2TLPX + Extra Byte Count
 410          * Extra Byte Count is calculated according to number of lanes.
 411          * High Low Switch Count is the Max of LP to HS and
 412          * HS to LP switch count
 413          *
 414          */
 415         tlpx_ui = DIV_ROUND_UP(tlpx_ns * ui_den, ui_num);
 416
 417         /* B044 */
 418         /* FIXME:
 419          * The comment above does not match with the code */
 420         lp_to_hs_switch = DIV_ROUND_UP(4 * tlpx_ui + prepare_cnt * 2 +
 421                                                 exit_zero_cnt * 2 + 10, 8);
 422
 423         hs_to_lp_switch = DIV_ROUND_UP(mipi_config->ths_trail + 2 * tlpx_ui, 8);
 424
 425         intel_dsi->hs_to_lp_count = max(lp_to_hs_switch, hs_to_lp_switch);
 426         intel_dsi->hs_to_lp_count += extra_byte_count;
 427
 428         /* B088 */
 429         /* LP -> HS for clock lanes
 430          * LP clk sync + LP11 + LP01 + tclk_prepare + tclk_zero +
 431          *                                              extra byte count
 432          * 2TPLX + 1TLPX + 1 TPLX(in ns) + prepare_cnt * 2 + clk_zero_cnt *
 433          *                                      2(in UI) + extra byte count
 434          * In byteclks = (4TLPX + prepare_cnt * 2 + clk_zero_cnt *2 (in UI)) /
 435          *                                      8 + extra byte count
 436          */
 437         intel_dsi->clk_lp_to_hs_count =
 438                 DIV_ROUND_UP(
 439                         4 * tlpx_ui + prepare_cnt * 2 +
 440                         clk_zero_cnt * 2,
 441                         8);
 442
 443         intel_dsi->clk_lp_to_hs_count += extra_byte_count;
 444
 445         /* HS->LP for Clock Lanes
 446          * Low Power clock synchronisations + 1Tx byteclk + tclk_trail +
 447          *                                              Extra byte count
 448          * 2TLPX + 8UI + (trail_count*2)(in UI) + Extra byte count
 449          * In byteclks = (2*TLpx(in UI) + trail_count*2 +8)(in UI)/8 +
 450          *                                              Extra byte count
 451          */
 452         intel_dsi->clk_hs_to_lp_count =
 453                 DIV_ROUND_UP(2 * tlpx_ui + trail_cnt * 2 + 8,
 454                         8);
 455         intel_dsi->clk_hs_to_lp_count += extra_byte_count;
 456
 457         DRM_DEBUG_KMS("Eot %s\n", intel_dsi->eotp_pkt ? "enabled" : "disabled");
 458         DRM_DEBUG_KMS("Clockstop %s\n", intel_dsi->clock_stop ?
 459                                                 "disabled" : "enabled");
 460         DRM_DEBUG_KMS("Mode %s\n", intel_dsi->operation_mode ? "command" : "video");
 461         DRM_DEBUG_KMS("Pixel Format %d\n", intel_dsi->pixel_format);
 462         DRM_DEBUG_KMS("TLPX %d\n", intel_dsi->escape_clk_div);
 463         DRM_DEBUG_KMS("LP RX Timeout 0x%x\n", intel_dsi->lp_rx_timeout);
 464         DRM_DEBUG_KMS("Turnaround Timeout 0x%x\n", intel_dsi->turn_arnd_val);
 465         DRM_DEBUG_KMS("Init Count 0x%x\n", intel_dsi->init_count);
 466         DRM_DEBUG_KMS("HS to LP Count 0x%x\n", intel_dsi->hs_to_lp_count);
 467         DRM_DEBUG_KMS("LP Byte Clock %d\n", intel_dsi->lp_byte_clk);
 468         DRM_DEBUG_KMS("DBI BW Timer 0x%x\n", intel_dsi->bw_timer);
 469         DRM_DEBUG_KMS("LP to HS Clock Count 0x%x\n", intel_dsi->clk_lp_to_hs_count);
 470         DRM_DEBUG_KMS("HS to LP Clock Count 0x%x\n", intel_dsi->clk_hs_to_lp_count);
 471         DRM_DEBUG_KMS("BTA %s\n",
 472                         intel_dsi->video_frmt_cfg_bits & DISABLE_VIDEO_BTA ?
 473                         "disabled" : "enabled");
 474
 475         /* delays in VBT are in unit of 100us, so need to convert
 476          * here in ms
 477          * Delay (100us) * 100 /1000 = Delay / 10 (ms) */
 478         intel_dsi->backlight_off_delay = pps->bl_disable_delay / 10;
 479         intel_dsi->backlight_on_delay = pps->bl_enable_delay / 10;
 480         intel_dsi->panel_on_delay = pps->panel_on_delay / 10;
 481         intel_dsi->panel_off_delay = pps->panel_off_delay / 10;
 482         intel_dsi->panel_pwr_cycle_delay = pps->panel_power_cycle_delay / 10;
 483
 484         return true;
 485 }
 486
 487 static int generic_mode_valid(struct intel_dsi_device *dsi,
 488                    struct drm_display_mode *mode)
 489 {
 490         return MODE_OK;
 491 }
 492
 493 static bool generic_mode_fixup(struct intel_dsi_device *dsi,
 494                     const struct drm_display_mode *mode,
 495                     struct drm_display_mode *adjusted_mode) {
 496         return true;
 497 }
 498
 499 static void generic_panel_reset(struct intel_dsi_device *dsi)
 500 {
 501         struct intel_dsi *intel_dsi = container_of(dsi, struct intel_dsi, dev);
 502         struct drm_device *dev = intel_dsi->base.base.dev;
 503         struct drm_i915_private *dev_priv = dev->dev_private;
 504
 505         char *sequence = dev_priv->vbt.dsi.sequence[MIPI_SEQ_ASSERT_RESET];
 506
 507         generic_exec_sequence(intel_dsi, sequence);
 508 }
 509
 510 static void generic_disable_panel_power(struct intel_dsi_device *dsi)
 511 {
 512         struct intel_dsi *intel_dsi = container_of(dsi, struct intel_dsi, dev);
 513         struct drm_device *dev = intel_dsi->base.base.dev;
 514         struct drm_i915_private *dev_priv = dev->dev_private;
 515
 516         char *sequence = dev_priv->vbt.dsi.sequence[MIPI_SEQ_DEASSERT_RESET];
 517
 518         generic_exec_sequence(intel_dsi, sequence);
 519 }
 520
 521 static void generic_send_otp_cmds(struct intel_dsi_device *dsi)
 522 {
 523         struct intel_dsi *intel_dsi = container_of(dsi, struct intel_dsi, dev);
 524         struct drm_device *dev = intel_dsi->base.base.dev;
 525         struct drm_i915_private *dev_priv = dev->dev_private;
 526
 527         char *sequence = dev_priv->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP];
 528
 529         generic_exec_sequence(intel_dsi, sequence);
 530 }
 531
 532 static void generic_enable(struct intel_dsi_device *dsi)
 533 {
 534         struct intel_dsi *intel_dsi = container_of(dsi, struct intel_dsi, dev);
 535         struct drm_device *dev = intel_dsi->base.base.dev;
 536         struct drm_i915_private *dev_priv = dev->dev_private;
 537
 538         char *sequence = dev_priv->vbt.dsi.sequence[MIPI_SEQ_DISPLAY_ON];
 539
 540         generic_exec_sequence(intel_dsi, sequence);
 541 }
 542
 543 static void generic_disable(struct intel_dsi_device *dsi)
 544 {
 545         struct intel_dsi *intel_dsi = container_of(dsi, struct intel_dsi, dev);
 546         struct drm_device *dev = intel_dsi->base.base.dev;
 547         struct drm_i915_private *dev_priv = dev->dev_private;
 548
 549         char *sequence = dev_priv->vbt.dsi.sequence[MIPI_SEQ_DISPLAY_OFF];
 550
 551         generic_exec_sequence(intel_dsi, sequence);
 552 }
 553
 554 static enum drm_connector_status generic_detect(struct intel_dsi_device *dsi)
 555 {
 556         return connector_status_connected;
 557 }
 558
 559 static bool generic_get_hw_state(struct intel_dsi_device *dev)
 560 {
 561         return true;
 562 }
 563
 564 static struct drm_display_mode *generic_get_modes(struct intel_dsi_device *dsi)
 565 {
 566         struct intel_dsi *intel_dsi = container_of(dsi, struct intel_dsi, dev);
 567         struct drm_device *dev = intel_dsi->base.base.dev;
 568         struct drm_i915_private *dev_priv = dev->dev_private;
 569
 570         dev_priv->vbt.lfp_lvds_vbt_mode->type |= DRM_MODE_TYPE_PREFERRED;
 571         return dev_priv->vbt.lfp_lvds_vbt_mode;
 572 }
 573
 574 static void generic_destroy(struct intel_dsi_device *dsi) { }
 575
 576 /* Callbacks. We might not need them all. */
 577 struct intel_dsi_dev_ops vbt_generic_dsi_display_ops = {
 578         .init = generic_init,
 579         .mode_valid = generic_mode_valid,
 580         .mode_fixup = generic_mode_fixup,
 581         .panel_reset = generic_panel_reset,
 582         .disable_panel_power = generic_disable_panel_power,
 583         .send_otp_cmds = generic_send_otp_cmds,
 584         .enable = generic_enable,
 585         .disable = generic_disable,
 586         .detect = generic_detect,
 587         .get_hw_state = generic_get_hw_state,
 588         .get_modes = generic_get_modes,
 589         .destroy = generic_destroy,
 590 };