sys/dev/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <drm/drmP.h>
  31 #include <drm/i915_drm.h>
  32 #include "i915_drv.h"
  33 #include <drm/drm_pciids.h>
  34 #include "intel_drv.h"
  35
  36 #include <linux/module.h>
  37 #include <drm/drm_crtc_helper.h>
  38
  39 static struct drm_driver driver;
  40
  41 #define GEN_DEFAULT_PIPEOFFSETS \
  42         .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
  43                           PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \
  44         .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
  45                            TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \
  46         .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET }
  47
  48 #define GEN_CHV_PIPEOFFSETS \
  49         .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
  50                           CHV_PIPE_C_OFFSET }, \
  51         .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
  52                            CHV_TRANSCODER_C_OFFSET, }, \
  53         .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \
  54                              CHV_PALETTE_C_OFFSET }
  55
  56 #define CURSOR_OFFSETS \
  57         .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }
  58
  59 #define IVB_CURSOR_OFFSETS \
  60         .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET }
  61
  62 static const struct intel_device_info intel_i830_info = {
  63         .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
  64         .has_overlay = 1, .overlay_needs_physical = 1,
  65         .ring_mask = RENDER_RING,
  66         GEN_DEFAULT_PIPEOFFSETS,
  67         CURSOR_OFFSETS,
  68 };
  69
  70 static const struct intel_device_info intel_845g_info = {
  71         .gen = 2, .num_pipes = 1,
  72         .has_overlay = 1, .overlay_needs_physical = 1,
  73         .ring_mask = RENDER_RING,
  74         GEN_DEFAULT_PIPEOFFSETS,
  75         CURSOR_OFFSETS,
  76 };
  77
  78 static const struct intel_device_info intel_i85x_info = {
  79         .gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2,
  80         .cursor_needs_physical = 1,
  81         .has_overlay = 1, .overlay_needs_physical = 1,
  82         .has_fbc = 1,
  83         .ring_mask = RENDER_RING,
  84         GEN_DEFAULT_PIPEOFFSETS,
  85         CURSOR_OFFSETS,
  86 };
  87
  88 static const struct intel_device_info intel_i865g_info = {
  89         .gen = 2, .num_pipes = 1,
  90         .has_overlay = 1, .overlay_needs_physical = 1,
  91         .ring_mask = RENDER_RING,
  92         GEN_DEFAULT_PIPEOFFSETS,
  93         CURSOR_OFFSETS,
  94 };
  95
  96 static const struct intel_device_info intel_i915g_info = {
  97         .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2,
  98         .has_overlay = 1, .overlay_needs_physical = 1,
  99         .ring_mask = RENDER_RING,
 100         GEN_DEFAULT_PIPEOFFSETS,
 101         CURSOR_OFFSETS,
 102 };
 103 static const struct intel_device_info intel_i915gm_info = {
 104         .gen = 3, .is_mobile = 1, .num_pipes = 2,
 105         .cursor_needs_physical = 1,
 106         .has_overlay = 1, .overlay_needs_physical = 1,
 107         .supports_tv = 1,
 108         .has_fbc = 1,
 109         .ring_mask = RENDER_RING,
 110         GEN_DEFAULT_PIPEOFFSETS,
 111         CURSOR_OFFSETS,
 112 };
 113 static const struct intel_device_info intel_i945g_info = {
 114         .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2,
 115         .has_overlay = 1, .overlay_needs_physical = 1,
 116         .ring_mask = RENDER_RING,
 117         GEN_DEFAULT_PIPEOFFSETS,
 118         CURSOR_OFFSETS,
 119 };
 120 static const struct intel_device_info intel_i945gm_info = {
 121         .gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2,
 122         .has_hotplug = 1, .cursor_needs_physical = 1,
 123         .has_overlay = 1, .overlay_needs_physical = 1,
 124         .supports_tv = 1,
 125         .has_fbc = 1,
 126         .ring_mask = RENDER_RING,
 127         GEN_DEFAULT_PIPEOFFSETS,
 128         CURSOR_OFFSETS,
 129 };
 130
 131 static const struct intel_device_info intel_i965g_info = {
 132         .gen = 4, .is_broadwater = 1, .num_pipes = 2,
 133         .has_hotplug = 1,
 134         .has_overlay = 1,
 135         .ring_mask = RENDER_RING,
 136         GEN_DEFAULT_PIPEOFFSETS,
 137         CURSOR_OFFSETS,
 138 };
 139
 140 static const struct intel_device_info intel_i965gm_info = {
 141         .gen = 4, .is_crestline = 1, .num_pipes = 2,
 142         .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
 143         .has_overlay = 1,
 144         .supports_tv = 1,
 145         .ring_mask = RENDER_RING,
 146         GEN_DEFAULT_PIPEOFFSETS,
 147         CURSOR_OFFSETS,
 148 };
 149
 150 static const struct intel_device_info intel_g33_info = {
 151         .gen = 3, .is_g33 = 1, .num_pipes = 2,
 152         .need_gfx_hws = 1, .has_hotplug = 1,
 153         .has_overlay = 1,
 154         .ring_mask = RENDER_RING,
 155         GEN_DEFAULT_PIPEOFFSETS,
 156         CURSOR_OFFSETS,
 157 };
 158
 159 static const struct intel_device_info intel_g45_info = {
 160         .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2,
 161         .has_pipe_cxsr = 1, .has_hotplug = 1,
 162         .ring_mask = RENDER_RING | BSD_RING,
 163         GEN_DEFAULT_PIPEOFFSETS,
 164         CURSOR_OFFSETS,
 165 };
 166
 167 static const struct intel_device_info intel_gm45_info = {
 168         .gen = 4, .is_g4x = 1, .num_pipes = 2,
 169         .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
 170         .has_pipe_cxsr = 1, .has_hotplug = 1,
 171         .supports_tv = 1,
 172         .ring_mask = RENDER_RING | BSD_RING,
 173         GEN_DEFAULT_PIPEOFFSETS,
 174         CURSOR_OFFSETS,
 175 };
 176
 177 static const struct intel_device_info intel_pineview_info = {
 178         .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2,
 179         .need_gfx_hws = 1, .has_hotplug = 1,
 180         .has_overlay = 1,
 181         GEN_DEFAULT_PIPEOFFSETS,
 182         CURSOR_OFFSETS,
 183 };
 184
 185 static const struct intel_device_info intel_ironlake_d_info = {
 186         .gen = 5, .num_pipes = 2,
 187         .need_gfx_hws = 1, .has_hotplug = 1,
 188         .ring_mask = RENDER_RING | BSD_RING,
 189         GEN_DEFAULT_PIPEOFFSETS,
 190         CURSOR_OFFSETS,
 191 };
 192
 193 static const struct intel_device_info intel_ironlake_m_info = {
 194         .gen = 5, .is_mobile = 1, .num_pipes = 2,
 195         .need_gfx_hws = 1, .has_hotplug = 1,
 196         .has_fbc = 1,
 197         .ring_mask = RENDER_RING | BSD_RING,
 198         GEN_DEFAULT_PIPEOFFSETS,
 199         CURSOR_OFFSETS,
 200 };
 201
 202 static const struct intel_device_info intel_sandybridge_d_info = {
 203         .gen = 6, .num_pipes = 2,
 204         .need_gfx_hws = 1, .has_hotplug = 1,
 205         .has_fbc = 1,
 206         .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
 207         .has_llc = 1,
 208         GEN_DEFAULT_PIPEOFFSETS,
 209         CURSOR_OFFSETS,
 210 };
 211
 212 static const struct intel_device_info intel_sandybridge_m_info = {
 213         .gen = 6, .is_mobile = 1, .num_pipes = 2,
 214         .need_gfx_hws = 1, .has_hotplug = 1,
 215         .has_fbc = 1,
 216         .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
 217         .has_llc = 1,
 218         GEN_DEFAULT_PIPEOFFSETS,
 219         CURSOR_OFFSETS,
 220 };
 221
 222 #define GEN7_FEATURES  \
 223         .gen = 7, .num_pipes = 3, \
 224         .need_gfx_hws = 1, .has_hotplug = 1, \
 225         .has_fbc = 1, \
 226         .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
 227         .has_llc = 1
 228
 229 static const struct intel_device_info intel_ivybridge_d_info = {
 230         GEN7_FEATURES,
 231         .is_ivybridge = 1,
 232         GEN_DEFAULT_PIPEOFFSETS,
 233         IVB_CURSOR_OFFSETS,
 234 };
 235
 236 static const struct intel_device_info intel_ivybridge_m_info = {
 237         GEN7_FEATURES,
 238         .is_ivybridge = 1,
 239         .is_mobile = 1,
 240         GEN_DEFAULT_PIPEOFFSETS,
 241         IVB_CURSOR_OFFSETS,
 242 };
 243
 244 static const struct intel_device_info intel_ivybridge_q_info = {
 245         GEN7_FEATURES,
 246         .is_ivybridge = 1,
 247         .num_pipes = 0, /* legal, last one wins */
 248         GEN_DEFAULT_PIPEOFFSETS,
 249         IVB_CURSOR_OFFSETS,
 250 };
 251
 252 static const struct intel_device_info intel_valleyview_m_info = {
 253         GEN7_FEATURES,
 254         .is_mobile = 1,
 255         .num_pipes = 2,
 256         .is_valleyview = 1,
 257         .display_mmio_offset = VLV_DISPLAY_BASE,
 258         .has_fbc = 0, /* legal, last one wins */
 259         .has_llc = 0, /* legal, last one wins */
 260         GEN_DEFAULT_PIPEOFFSETS,
 261         CURSOR_OFFSETS,
 262 };
 263
 264 static const struct intel_device_info intel_valleyview_d_info = {
 265         GEN7_FEATURES,
 266         .num_pipes = 2,
 267         .is_valleyview = 1,
 268         .display_mmio_offset = VLV_DISPLAY_BASE,
 269         .has_fbc = 0, /* legal, last one wins */
 270         .has_llc = 0, /* legal, last one wins */
 271         GEN_DEFAULT_PIPEOFFSETS,
 272         CURSOR_OFFSETS,
 273 };
 274
 275 static const struct intel_device_info intel_haswell_d_info = {
 276         GEN7_FEATURES,
 277         .is_haswell = 1,
 278         .has_ddi = 1,
 279         .has_fpga_dbg = 1,
 280         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 281         GEN_DEFAULT_PIPEOFFSETS,
 282         IVB_CURSOR_OFFSETS,
 283 };
 284
 285 static const struct intel_device_info intel_haswell_m_info = {
 286         GEN7_FEATURES,
 287         .is_haswell = 1,
 288         .is_mobile = 1,
 289         .has_ddi = 1,
 290         .has_fpga_dbg = 1,
 291         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 292         GEN_DEFAULT_PIPEOFFSETS,
 293         IVB_CURSOR_OFFSETS,
 294 };
 295
 296 static const struct intel_device_info intel_broadwell_d_info = {
 297         .gen = 8, .num_pipes = 3,
 298         .need_gfx_hws = 1, .has_hotplug = 1,
 299         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 300         .has_llc = 1,
 301         .has_ddi = 1,
 302         .has_fpga_dbg = 1,
 303         .has_fbc = 1,
 304         GEN_DEFAULT_PIPEOFFSETS,
 305         IVB_CURSOR_OFFSETS,
 306 };
 307
 308 static const struct intel_device_info intel_broadwell_m_info = {
 309         .gen = 8, .is_mobile = 1, .num_pipes = 3,
 310         .need_gfx_hws = 1, .has_hotplug = 1,
 311         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 312         .has_llc = 1,
 313         .has_ddi = 1,
 314         .has_fpga_dbg = 1,
 315         .has_fbc = 1,
 316         GEN_DEFAULT_PIPEOFFSETS,
 317         IVB_CURSOR_OFFSETS,
 318 };
 319
 320 static const struct intel_device_info intel_broadwell_gt3d_info = {
 321         .gen = 8, .num_pipes = 3,
 322         .need_gfx_hws = 1, .has_hotplug = 1,
 323         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 324         .has_llc = 1,
 325         .has_ddi = 1,
 326         .has_fpga_dbg = 1,
 327         .has_fbc = 1,
 328         GEN_DEFAULT_PIPEOFFSETS,
 329         IVB_CURSOR_OFFSETS,
 330 };
 331
 332 static const struct intel_device_info intel_broadwell_gt3m_info = {
 333         .gen = 8, .is_mobile = 1, .num_pipes = 3,
 334         .need_gfx_hws = 1, .has_hotplug = 1,
 335         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 336         .has_llc = 1,
 337         .has_ddi = 1,
 338         .has_fpga_dbg = 1,
 339         .has_fbc = 1,
 340         GEN_DEFAULT_PIPEOFFSETS,
 341         IVB_CURSOR_OFFSETS,
 342 };
 343
 344 static const struct intel_device_info intel_cherryview_info = {
 345         .is_preliminary = 1,
 346         .gen = 8, .num_pipes = 3,
 347         .need_gfx_hws = 1, .has_hotplug = 1,
 348         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 349         .is_valleyview = 1,
 350         .display_mmio_offset = VLV_DISPLAY_BASE,
 351         GEN_CHV_PIPEOFFSETS,
 352         CURSOR_OFFSETS,
 353 };
 354
 355 static const struct intel_device_info intel_skylake_info = {
 356         .is_preliminary = 1,
 357         .is_skylake = 1,
 358         .gen = 9, .num_pipes = 3,
 359         .need_gfx_hws = 1, .has_hotplug = 1,
 360         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 361         .has_llc = 1,
 362         .has_ddi = 1,
 363         .has_fbc = 1,
 364         GEN_DEFAULT_PIPEOFFSETS,
 365         IVB_CURSOR_OFFSETS,
 366 };
 367
 368 /*
 369  * Make sure any device matches here are from most specific to most
 370  * general.  For example, since the Quanta match is based on the subsystem
 371  * and subvendor IDs, we need it to come before the more general IVB
 372  * PCI ID matches, otherwise we'll use the wrong info struct above.
 373  */
 374 #define INTEL_PCI_IDS \
 375         INTEL_I830_IDS(&intel_i830_info),       \
 376         INTEL_I845G_IDS(&intel_845g_info),      \
 377         INTEL_I85X_IDS(&intel_i85x_info),       \
 378         INTEL_I865G_IDS(&intel_i865g_info),     \
 379         INTEL_I915G_IDS(&intel_i915g_info),     \
 380         INTEL_I915GM_IDS(&intel_i915gm_info),   \
 381         INTEL_I945G_IDS(&intel_i945g_info),     \
 382         INTEL_I945GM_IDS(&intel_i945gm_info),   \
 383         INTEL_I965G_IDS(&intel_i965g_info),     \
 384         INTEL_G33_IDS(&intel_g33_info),         \
 385         INTEL_I965GM_IDS(&intel_i965gm_info),   \
 386         INTEL_GM45_IDS(&intel_gm45_info),       \
 387         INTEL_G45_IDS(&intel_g45_info),         \
 388         INTEL_PINEVIEW_IDS(&intel_pineview_info),       \
 389         INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),   \
 390         INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),   \
 391         INTEL_SNB_D_IDS(&intel_sandybridge_d_info),     \
 392         INTEL_SNB_M_IDS(&intel_sandybridge_m_info),     \
 393         INTEL_IVB_M_IDS(&intel_ivybridge_m_info),       \
 394         INTEL_IVB_D_IDS(&intel_ivybridge_d_info),       \
 395         INTEL_HSW_D_IDS(&intel_haswell_d_info), \
 396         INTEL_HSW_M_IDS(&intel_haswell_m_info), \
 397         INTEL_VLV_M_IDS(&intel_valleyview_m_info),      \
 398         INTEL_VLV_D_IDS(&intel_valleyview_d_info),      \
 399         INTEL_BDW_GT12M_IDS(&intel_broadwell_m_info),   \
 400         INTEL_BDW_GT12D_IDS(&intel_broadwell_d_info),   \
 401         INTEL_BDW_GT3M_IDS(&intel_broadwell_gt3m_info), \
 402         INTEL_BDW_GT3D_IDS(&intel_broadwell_gt3d_info), \
 403         INTEL_CHV_IDS(&intel_cherryview_info),  \
 404         INTEL_SKL_IDS(&intel_skylake_info)
 405
 406 static const struct pci_device_id pciidlist[] = {               /* aka */
 407         INTEL_PCI_IDS,
 408         {0, 0}
 409 };
 410
 411 #define PCI_VENDOR_INTEL        0x8086
 412
 413 void intel_detect_pch(struct drm_device *dev)
 414 {
 415         struct drm_i915_private *dev_priv = dev->dev_private;
 416         struct device *pch = NULL;
 417         struct pci_devinfo *di;
 418
 419         /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
 420          * (which really amounts to a PCH but no South Display).
 421          */
 422         if (INTEL_INFO(dev)->num_pipes == 0) {
 423                 dev_priv->pch_type = PCH_NOP;
 424                 return;
 425         }
 426
 427         /* XXX The ISA bridge probe causes some old Core2 machines to hang */
 428         if (INTEL_INFO(dev)->gen < 5)
 429                 return;
 430
 431         /*
 432          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
 433          * make graphics device passthrough work easy for VMM, that only
 434          * need to expose ISA bridge to let driver know the real hardware
 435          * underneath. This is a requirement from virtualization team.
 436          *
 437          * In some virtualized environments (e.g. XEN), there is irrelevant
 438          * ISA bridge in the system. To work reliably, we should scan trhough
 439          * all the ISA bridge devices and check for the first match, instead
 440          * of only checking the first one.
 441          */
 442         di = NULL;
 443
 444         while ((pch = pci_iterate_class(&di, PCIC_BRIDGE, PCIS_BRIDGE_ISA))) {
 445                 if (pci_get_vendor(pch) == PCI_VENDOR_INTEL) {
 446                         unsigned short id = pci_get_device(pch) & INTEL_PCH_DEVICE_ID_MASK;
 447                         dev_priv->pch_id = id;
 448
 449                         if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
 450                                 dev_priv->pch_type = PCH_IBX;
 451                                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
 452                                 WARN_ON(!IS_GEN5(dev));
 453                         } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
 454                                 dev_priv->pch_type = PCH_CPT;
 455                                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 456                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
 457                         } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
 458                                 /* PantherPoint is CPT compatible */
 459                                 dev_priv->pch_type = PCH_CPT;
 460                                 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
 461                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
 462                         } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 463                                 dev_priv->pch_type = PCH_LPT;
 464                                 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
 465                                 WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));
 466                                 WARN_ON(IS_HSW_ULT(dev) || IS_BDW_ULT(dev));
 467                         } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
 468                                 dev_priv->pch_type = PCH_LPT;
 469                                 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
 470                                 WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));
 471                                 WARN_ON(!IS_HSW_ULT(dev) && !IS_BDW_ULT(dev));
 472                         } else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) {
 473                                 dev_priv->pch_type = PCH_SPT;
 474                                 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
 475                                 WARN_ON(!IS_SKYLAKE(dev));
 476                         } else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {
 477                                 dev_priv->pch_type = PCH_SPT;
 478                                 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
 479                                 WARN_ON(!IS_SKYLAKE(dev));
 480                         } else
 481                                 continue;
 482
 483                         break;
 484                 }
 485         }
 486         if (!pch)
 487                 DRM_DEBUG_KMS("No PCH found.\n");
 488
 489 #if 0
 490         pci_dev_put(pch);
 491 #endif
 492 }
 493
 494 bool i915_semaphore_is_enabled(struct drm_device *dev)
 495 {
 496         if (INTEL_INFO(dev)->gen < 6)
 497                 return false;
 498
 499         if (i915.semaphores >= 0)
 500                 return i915.semaphores;
 501
 502         /* TODO: make semaphores and Execlists play nicely together */
 503         if (i915.enable_execlists)
 504                 return false;
 505
 506         /* Until we get further testing... */
 507         if (IS_GEN8(dev))
 508                 return false;
 509
 510 #ifdef CONFIG_INTEL_IOMMU
 511         /* Enable semaphores on SNB when IO remapping is off */
 512         if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
 513                 return false;
 514 #endif
 515
 516         return true;
 517 }
 518
 519 void intel_hpd_cancel_work(struct drm_i915_private *dev_priv)
 520 {
 521         lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
 522
 523         dev_priv->long_hpd_port_mask = 0;
 524         dev_priv->short_hpd_port_mask = 0;
 525         dev_priv->hpd_event_bits = 0;
 526
 527         lockmgr(&dev_priv->irq_lock, LK_RELEASE);
 528
 529         cancel_work_sync(&dev_priv->dig_port_work);
 530         cancel_work_sync(&dev_priv->hotplug_work);
 531         cancel_delayed_work_sync(&dev_priv->hotplug_reenable_work);
 532 }
 533
 534 static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
 535 {
 536         struct drm_device *dev = dev_priv->dev;
 537         struct drm_encoder *encoder;
 538
 539         drm_modeset_lock_all(dev);
 540         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 541                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
 542
 543                 if (intel_encoder->suspend)
 544                         intel_encoder->suspend(intel_encoder);
 545         }
 546         drm_modeset_unlock_all(dev);
 547 }
 548
 549
 550 static int intel_suspend_complete(struct drm_i915_private *dev_priv);
 551 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
 552                               bool rpm_resume);
 553
 554 static int i915_drm_suspend(struct drm_device *dev)
 555 {
 556         struct drm_i915_private *dev_priv = dev->dev_private;
 557         struct drm_crtc *crtc;
 558         pci_power_t opregion_target_state;
 559
 560         /* ignore lid events during suspend */
 561         mutex_lock(&dev_priv->modeset_restore_lock);
 562         dev_priv->modeset_restore = MODESET_SUSPENDED;
 563         mutex_unlock(&dev_priv->modeset_restore_lock);
 564
 565         /* We do a lot of poking in a lot of registers, make sure they work
 566          * properly. */
 567         intel_display_set_init_power(dev_priv, true);
 568
 569         drm_kms_helper_poll_disable(dev);
 570
 571 #if 0
 572         pci_save_state(dev->pdev);
 573 #endif
 574
 575         /* If KMS is active, we do the leavevt stuff here */
 576         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 577                 int error;
 578
 579                 error = i915_gem_suspend(dev);
 580                 if (error) {
 581                         dev_err(dev->pdev->dev,
 582                                 "GEM idle failed, resume might fail\n");
 583                         return error;
 584                 }
 585
 586                 intel_suspend_gt_powersave(dev);
 587
 588                 /*
 589                  * Disable CRTCs directly since we want to preserve sw state
 590                  * for _thaw. Also, power gate the CRTC power wells.
 591                  */
 592                 drm_modeset_lock_all(dev);
 593                 for_each_crtc(dev, crtc)
 594                         intel_crtc_control(crtc, false);
 595                 drm_modeset_unlock_all(dev);
 596
 597 #if 0
 598                 intel_dp_mst_suspend(dev);
 599 #endif
 600
 601                 intel_runtime_pm_disable_interrupts(dev_priv);
 602                 intel_hpd_cancel_work(dev_priv);
 603
 604                 intel_suspend_encoders(dev_priv);
 605
 606                 intel_suspend_hw(dev);
 607         }
 608
 609         i915_gem_suspend_gtt_mappings(dev);
 610
 611         i915_save_state(dev);
 612
 613         opregion_target_state = PCI_D3cold;
 614 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
 615         if (acpi_target_system_state() < ACPI_STATE_S3)
 616                 opregion_target_state = PCI_D1;
 617 #endif
 618         intel_opregion_notify_adapter(dev, opregion_target_state);
 619
 620 #if 0
 621         intel_uncore_forcewake_reset(dev, false);
 622 #endif
 623         intel_opregion_fini(dev);
 624
 625 #if 0
 626         intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED);
 627 #endif
 628
 629         dev_priv->suspend_count++;
 630
 631         intel_display_set_init_power(dev_priv, false);
 632
 633         return 0;
 634 }
 635
 636 static int i915_drm_suspend_late(struct drm_device *drm_dev, bool hibernation)
 637 {
 638         struct drm_i915_private *dev_priv = drm_dev->dev_private;
 639         int ret;
 640
 641         ret = intel_suspend_complete(dev_priv);
 642
 643         if (ret) {
 644                 DRM_ERROR("Suspend complete failed: %d\n", ret);
 645
 646                 return ret;
 647         }
 648
 649 #if 0
 650         pci_disable_device(drm_dev->pdev);
 651         /*
 652          * During hibernation on some GEN4 platforms the BIOS may try to access
 653          * the device even though it's already in D3 and hang the machine. So
 654          * leave the device in D0 on those platforms and hope the BIOS will
 655          * power down the device properly. Platforms where this was seen:
 656          * Lenovo Thinkpad X301, X61s
 657          */
 658         if (!(hibernation &&
 659               drm_dev->pdev->subsystem_vendor == PCI_VENDOR_ID_LENOVO &&
 660               INTEL_INFO(dev_priv)->gen == 4))
 661                 pci_set_power_state(drm_dev->pdev, PCI_D3hot);
 662 #endif
 663
 664         return 0;
 665 }
 666
 667 int i915_suspend_legacy(device_t kdev)
 668 {
 669         struct drm_device *dev = device_get_softc(kdev);
 670         int error;
 671
 672         if (!dev || !dev->dev_private) {
 673                 DRM_ERROR("dev: %p\n", dev);
 674                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
 675                 return -ENODEV;
 676         }
 677
 678 #if 0
 679         if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND &&
 680                          state.event != PM_EVENT_FREEZE))
 681                 return -EINVAL;
 682 #endif
 683
 684         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 685                 return 0;
 686
 687         error = i915_drm_suspend(dev);
 688         if (error)
 689                 return error;
 690
 691         return i915_drm_suspend_late(dev, false);
 692 }
 693
 694 static int i915_drm_resume(struct drm_device *dev)
 695 {
 696         struct drm_i915_private *dev_priv = dev->dev_private;
 697
 698         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 699                 mutex_lock(&dev->struct_mutex);
 700                 i915_gem_restore_gtt_mappings(dev);
 701                 mutex_unlock(&dev->struct_mutex);
 702         }
 703
 704         i915_restore_state(dev);
 705         intel_opregion_setup(dev);
 706
 707         /* KMS EnterVT equivalent */
 708         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 709                 intel_init_pch_refclk(dev);
 710                 drm_mode_config_reset(dev);
 711
 712                 mutex_lock(&dev->struct_mutex);
 713                 if (i915_gem_init_hw(dev)) {
 714                         DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
 715                         atomic_set_mask(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
 716                 }
 717                 mutex_unlock(&dev->struct_mutex);
 718
 719                 /* We need working interrupts for modeset enabling ... */
 720                 intel_runtime_pm_enable_interrupts(dev_priv);
 721
 722                 intel_modeset_init_hw(dev);
 723
 724                 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
 725                 if (dev_priv->display.hpd_irq_setup)
 726                         dev_priv->display.hpd_irq_setup(dev);
 727                 lockmgr(&dev_priv->irq_lock, LK_RELEASE);
 728
 729                 drm_modeset_lock_all(dev);
 730                 intel_modeset_setup_hw_state(dev, true);
 731                 drm_modeset_unlock_all(dev);
 732
 733                 intel_dp_mst_resume(dev);
 734
 735                 /*
 736                  * ... but also need to make sure that hotplug processing
 737                  * doesn't cause havoc. Like in the driver load code we don't
 738                  * bother with the tiny race here where we might loose hotplug
 739                  * notifications.
 740                  * */
 741                 intel_hpd_init(dev_priv);
 742                 /* Config may have changed between suspend and resume */
 743                 drm_helper_hpd_irq_event(dev);
 744         }
 745
 746         intel_opregion_init(dev);
 747
 748         intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
 749
 750         mutex_lock(&dev_priv->modeset_restore_lock);
 751         dev_priv->modeset_restore = MODESET_DONE;
 752         mutex_unlock(&dev_priv->modeset_restore_lock);
 753
 754 #if 0
 755         intel_opregion_notify_adapter(dev, PCI_D0);
 756 #endif
 757
 758         drm_kms_helper_poll_enable(dev);
 759
 760         return 0;
 761 }
 762
 763 static int i915_drm_resume_early(struct drm_device *dev)
 764 {
 765         struct drm_i915_private *dev_priv = dev->dev_private;
 766         int ret = 0;
 767
 768         /*
 769          * We have a resume ordering issue with the snd-hda driver also
 770          * requiring our device to be power up. Due to the lack of a
 771          * parent/child relationship we currently solve this with an early
 772          * resume hook.
 773          *
 774          * FIXME: This should be solved with a special hdmi sink device or
 775          * similar so that power domains can be employed.
 776          */
 777 #if 0
 778         if (pci_enable_device(dev->pdev))
 779                 return -EIO;
 780
 781         pci_set_master(dev->pdev);
 782 #endif
 783
 784         if (IS_VALLEYVIEW(dev_priv))
 785                 ret = vlv_resume_prepare(dev_priv, false);
 786         if (ret)
 787                 DRM_ERROR("Resume prepare failed: %d,Continuing resume\n", ret);
 788
 789         intel_uncore_early_sanitize(dev, true);
 790
 791         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 792                 hsw_disable_pc8(dev_priv);
 793
 794         intel_uncore_sanitize(dev);
 795         intel_power_domains_init_hw(dev_priv);
 796
 797         return ret;
 798 }
 799
 800 int i915_resume_legacy(struct drm_device *dev)
 801 {
 802         int ret;
 803
 804         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 805                 return 0;
 806
 807         ret = i915_drm_resume_early(dev);
 808         if (ret)
 809                 return ret;
 810
 811         return i915_drm_resume(dev);
 812 }
 813
 814 /* XXX Hack for the old *BSD drm code base
 815  * The device id field is set at probe time */
 816 static drm_pci_id_list_t i915_attach_list[] = {
 817         {0x8086, 0, 0, "Intel i915 GPU"},
 818         {0, 0, 0, NULL}
 819 };
 820
 821 struct intel_device_info *
 822 i915_get_device_id(int device)
 823 {
 824         const struct pci_device_id *did;
 825
 826         for (did = &pciidlist[0]; did->device != 0; did++) {
 827                 if (did->device != device)
 828                         continue;
 829                 return (struct intel_device_info *)did->driver_data;
 830         }
 831         return (NULL);
 832 }
 833
 834 extern devclass_t drm_devclass;
 835
 836 /**
 837  * i915_reset - reset chip after a hang
 838  * @dev: drm device to reset
 839  *
 840  * Reset the chip.  Useful if a hang is detected. Returns zero on successful
 841  * reset or otherwise an error code.
 842  *
 843  * Procedure is fairly simple:
 844  *   - reset the chip using the reset reg
 845  *   - re-init context state
 846  *   - re-init hardware status page
 847  *   - re-init ring buffer
 848  *   - re-init interrupt state
 849  *   - re-init display
 850  */
 851 int i915_reset(struct drm_device *dev)
 852 {
 853         struct drm_i915_private *dev_priv = dev->dev_private;
 854         bool simulated;
 855         int ret;
 856
 857         if (!i915.reset)
 858                 return 0;
 859
 860         intel_reset_gt_powersave(dev);
 861
 862         mutex_lock(&dev->struct_mutex);
 863
 864         i915_gem_reset(dev);
 865
 866         simulated = dev_priv->gpu_error.stop_rings != 0;
 867
 868         ret = intel_gpu_reset(dev);
 869
 870         /* Also reset the gpu hangman. */
 871         if (simulated) {
 872                 DRM_INFO("Simulated gpu hang, resetting stop_rings\n");
 873                 dev_priv->gpu_error.stop_rings = 0;
 874                 if (ret == -ENODEV) {
 875                         DRM_INFO("Reset not implemented, but ignoring "
 876                                  "error for simulated gpu hangs\n");
 877                         ret = 0;
 878                 }
 879         }
 880
 881         if (i915_stop_ring_allow_warn(dev_priv))
 882                 pr_notice("drm/i915: Resetting chip after gpu hang\n");
 883
 884         if (ret) {
 885                 DRM_ERROR("Failed to reset chip: %i\n", ret);
 886                 mutex_unlock(&dev->struct_mutex);
 887                 return ret;
 888         }
 889
 890         intel_overlay_reset(dev_priv);
 891
 892         /* Ok, now get things going again... */
 893
 894         /*
 895          * Everything depends on having the GTT running, so we need to start
 896          * there.  Fortunately we don't need to do this unless we reset the
 897          * chip at a PCI level.
 898          *
 899          * Next we need to restore the context, but we don't use those
 900          * yet either...
 901          *
 902          * Ring buffer needs to be re-initialized in the KMS case, or if X
 903          * was running at the time of the reset (i.e. we weren't VT
 904          * switched away).
 905          */
 906         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 907                 /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
 908                 dev_priv->gpu_error.reload_in_reset = true;
 909
 910                 ret = i915_gem_init_hw(dev);
 911
 912                 dev_priv->gpu_error.reload_in_reset = false;
 913
 914                 mutex_unlock(&dev->struct_mutex);
 915                 if (ret) {
 916                         DRM_ERROR("Failed hw init on reset %d\n", ret);
 917                         return ret;
 918                 }
 919
 920                 /*
 921                  * FIXME: This races pretty badly against concurrent holders of
 922                  * ring interrupts. This is possible since we've started to drop
 923                  * dev->struct_mutex in select places when waiting for the gpu.
 924                  */
 925
 926                 /*
 927                  * rps/rc6 re-init is necessary to restore state lost after the
 928                  * reset and the re-install of gt irqs. Skip for ironlake per
 929                  * previous concerns that it doesn't respond well to some forms
 930                  * of re-init after reset.
 931                  */
 932                 if (INTEL_INFO(dev)->gen > 5)
 933                         intel_enable_gt_powersave(dev);
 934         } else {
 935                 mutex_unlock(&dev->struct_mutex);
 936         }
 937
 938         return 0;
 939 }
 940
 941 static int i915_pci_probe(device_t kdev)
 942 {
 943         int device, i = 0;
 944
 945         if (pci_get_class(kdev) != PCIC_DISPLAY)
 946                 return ENXIO;
 947
 948         if (pci_get_vendor(kdev) != PCI_VENDOR_INTEL)
 949                 return ENXIO;
 950
 951         device = pci_get_device(kdev);
 952
 953         driver.driver_features &= ~(DRIVER_USE_AGP);
 954
 955         for (i = 0; pciidlist[i].device != 0; i++) {
 956                 if (pciidlist[i].device == device) {
 957                         i915_attach_list[0].device = device;
 958                         return 0;
 959                 }
 960         }
 961
 962         return ENXIO;
 963 }
 964
 965 #if 0
 966 static void
 967 i915_pci_remove(struct pci_dev *pdev)
 968 {
 969         struct drm_device *dev = pci_get_drvdata(pdev);
 970
 971         drm_put_dev(dev);
 972 }
 973
 974 static int i915_pm_suspend(struct device *dev)
 975 {
 976         struct pci_dev *pdev = to_pci_dev(dev);
 977         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 978
 979         if (!drm_dev || !drm_dev->dev_private) {
 980                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
 981                 return -ENODEV;
 982         }
 983
 984         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 985                 return 0;
 986
 987         return i915_drm_suspend(drm_dev);
 988 }
 989
 990 static int i915_pm_suspend_late(struct device *dev)
 991 {
 992         struct drm_device *drm_dev = dev_to_i915(dev)->dev;
 993
 994         /*
 995          * We have a suspedn ordering issue with the snd-hda driver also
 996          * requiring our device to be power up. Due to the lack of a
 997          * parent/child relationship we currently solve this with an late
 998          * suspend hook.
 999          *
1000          * FIXME: This should be solved with a special hdmi sink device or
1001          * similar so that power domains can be employed.
1002          */
1003         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1004                 return 0;
1005
1006         return i915_drm_suspend_late(drm_dev, false);
1007 }
1008
1009 static int i915_pm_poweroff_late(struct device *dev)
1010 {
1011         struct drm_device *drm_dev = dev_to_i915(dev)->dev;
1012
1013         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1014                 return 0;
1015
1016         return i915_drm_suspend_late(drm_dev, true);
1017 }
1018
1019 static int i915_pm_resume_early(struct device *dev)
1020 {
1021         struct drm_device *drm_dev = dev_to_i915(dev)->dev;
1022
1023         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1024                 return 0;
1025
1026         return i915_drm_resume_early(drm_dev);
1027 }
1028
1029 static int i915_pm_resume(struct device *dev)
1030 {
1031         struct drm_device *drm_dev = dev_to_i915(dev)->dev;
1032
1033         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1034                 return 0;
1035
1036         return i915_drm_resume(drm_dev);
1037 }
1038 #endif
1039
1040 static int hsw_suspend_complete(struct drm_i915_private *dev_priv)
1041 {
1042         hsw_enable_pc8(dev_priv);
1043
1044         return 0;
1045 }
1046
1047 /*
1048  * Save all Gunit registers that may be lost after a D3 and a subsequent
1049  * S0i[R123] transition. The list of registers needing a save/restore is
1050  * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
1051  * registers in the following way:
1052  * - Driver: saved/restored by the driver
1053  * - Punit : saved/restored by the Punit firmware
1054  * - No, w/o marking: no need to save/restore, since the register is R/O or
1055  *                    used internally by the HW in a way that doesn't depend
1056  *                    keeping the content across a suspend/resume.
1057  * - Debug : used for debugging
1058  *
1059  * We save/restore all registers marked with 'Driver', with the following
1060  * exceptions:
1061  * - Registers out of use, including also registers marked with 'Debug'.
1062  *   These have no effect on the driver's operation, so we don't save/restore
1063  *   them to reduce the overhead.
1064  * - Registers that are fully setup by an initialization function called from
1065  *   the resume path. For example many clock gating and RPS/RC6 registers.
1066  * - Registers that provide the right functionality with their reset defaults.
1067  *
1068  * TODO: Except for registers that based on the above 3 criteria can be safely
1069  * ignored, we save/restore all others, practically treating the HW context as
1070  * a black-box for the driver. Further investigation is needed to reduce the
1071  * saved/restored registers even further, by following the same 3 criteria.
1072  */
1073 static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
1074 {
1075         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
1076         int i;
1077
1078         /* GAM 0x4000-0x4770 */
1079         s->wr_watermark         = I915_READ(GEN7_WR_WATERMARK);
1080         s->gfx_prio_ctrl        = I915_READ(GEN7_GFX_PRIO_CTRL);
1081         s->arb_mode             = I915_READ(ARB_MODE);
1082         s->gfx_pend_tlb0        = I915_READ(GEN7_GFX_PEND_TLB0);
1083         s->gfx_pend_tlb1        = I915_READ(GEN7_GFX_PEND_TLB1);
1084
1085         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
1086                 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS_BASE + i * 4);
1087
1088         s->media_max_req_count  = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
1089         s->gfx_max_req_count    = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
1090
1091         s->render_hwsp          = I915_READ(RENDER_HWS_PGA_GEN7);
1092         s->ecochk               = I915_READ(GAM_ECOCHK);
1093         s->bsd_hwsp             = I915_READ(BSD_HWS_PGA_GEN7);
1094         s->blt_hwsp             = I915_READ(BLT_HWS_PGA_GEN7);
1095
1096         s->tlb_rd_addr          = I915_READ(GEN7_TLB_RD_ADDR);
1097
1098         /* MBC 0x9024-0x91D0, 0x8500 */
1099         s->g3dctl               = I915_READ(VLV_G3DCTL);
1100         s->gsckgctl             = I915_READ(VLV_GSCKGCTL);
1101         s->mbctl                = I915_READ(GEN6_MBCTL);
1102
1103         /* GCP 0x9400-0x9424, 0x8100-0x810C */
1104         s->ucgctl1              = I915_READ(GEN6_UCGCTL1);
1105         s->ucgctl3              = I915_READ(GEN6_UCGCTL3);
1106         s->rcgctl1              = I915_READ(GEN6_RCGCTL1);
1107         s->rcgctl2              = I915_READ(GEN6_RCGCTL2);
1108         s->rstctl               = I915_READ(GEN6_RSTCTL);
1109         s->misccpctl            = I915_READ(GEN7_MISCCPCTL);
1110
1111         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1112         s->gfxpause             = I915_READ(GEN6_GFXPAUSE);
1113         s->rpdeuhwtc            = I915_READ(GEN6_RPDEUHWTC);
1114         s->rpdeuc               = I915_READ(GEN6_RPDEUC);
1115         s->ecobus               = I915_READ(ECOBUS);
1116         s->pwrdwnupctl          = I915_READ(VLV_PWRDWNUPCTL);
1117         s->rp_down_timeout      = I915_READ(GEN6_RP_DOWN_TIMEOUT);
1118         s->rp_deucsw            = I915_READ(GEN6_RPDEUCSW);
1119         s->rcubmabdtmr          = I915_READ(GEN6_RCUBMABDTMR);
1120         s->rcedata              = I915_READ(VLV_RCEDATA);
1121         s->spare2gh             = I915_READ(VLV_SPAREG2H);
1122
1123         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
1124         s->gt_imr               = I915_READ(GTIMR);
1125         s->gt_ier               = I915_READ(GTIER);
1126         s->pm_imr               = I915_READ(GEN6_PMIMR);
1127         s->pm_ier               = I915_READ(GEN6_PMIER);
1128
1129         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
1130                 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH_BASE + i * 4);
1131
1132         /* GT SA CZ domain, 0x100000-0x138124 */
1133         s->tilectl              = I915_READ(TILECTL);
1134         s->gt_fifoctl           = I915_READ(GTFIFOCTL);
1135         s->gtlc_wake_ctrl       = I915_READ(VLV_GTLC_WAKE_CTRL);
1136         s->gtlc_survive         = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1137         s->pmwgicz              = I915_READ(VLV_PMWGICZ);
1138
1139         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
1140         s->gu_ctl0              = I915_READ(VLV_GU_CTL0);
1141         s->gu_ctl1              = I915_READ(VLV_GU_CTL1);
1142         s->pcbr                 = I915_READ(VLV_PCBR);
1143         s->clock_gate_dis2      = I915_READ(VLV_GUNIT_CLOCK_GATE2);
1144
1145         /*
1146          * Not saving any of:
1147          * DFT,         0x9800-0x9EC0
1148          * SARB,        0xB000-0xB1FC
1149          * GAC,         0x5208-0x524C, 0x14000-0x14C000
1150          * PCI CFG
1151          */
1152 }
1153
1154 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
1155 {
1156         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
1157         u32 val;
1158         int i;
1159
1160         /* GAM 0x4000-0x4770 */
1161         I915_WRITE(GEN7_WR_WATERMARK,   s->wr_watermark);
1162         I915_WRITE(GEN7_GFX_PRIO_CTRL,  s->gfx_prio_ctrl);
1163         I915_WRITE(ARB_MODE,            s->arb_mode | (0xffff << 16));
1164         I915_WRITE(GEN7_GFX_PEND_TLB0,  s->gfx_pend_tlb0);
1165         I915_WRITE(GEN7_GFX_PEND_TLB1,  s->gfx_pend_tlb1);
1166
1167         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
1168                 I915_WRITE(GEN7_LRA_LIMITS_BASE + i * 4, s->lra_limits[i]);
1169
1170         I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
1171         I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->gfx_max_req_count);
1172
1173         I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
1174         I915_WRITE(GAM_ECOCHK,          s->ecochk);
1175         I915_WRITE(BSD_HWS_PGA_GEN7,    s->bsd_hwsp);
1176         I915_WRITE(BLT_HWS_PGA_GEN7,    s->blt_hwsp);
1177
1178         I915_WRITE(GEN7_TLB_RD_ADDR,    s->tlb_rd_addr);
1179
1180         /* MBC 0x9024-0x91D0, 0x8500 */
1181         I915_WRITE(VLV_G3DCTL,          s->g3dctl);
1182         I915_WRITE(VLV_GSCKGCTL,        s->gsckgctl);
1183         I915_WRITE(GEN6_MBCTL,          s->mbctl);
1184
1185         /* GCP 0x9400-0x9424, 0x8100-0x810C */
1186         I915_WRITE(GEN6_UCGCTL1,        s->ucgctl1);
1187         I915_WRITE(GEN6_UCGCTL3,        s->ucgctl3);
1188         I915_WRITE(GEN6_RCGCTL1,        s->rcgctl1);
1189         I915_WRITE(GEN6_RCGCTL2,        s->rcgctl2);
1190         I915_WRITE(GEN6_RSTCTL,         s->rstctl);
1191         I915_WRITE(GEN7_MISCCPCTL,      s->misccpctl);
1192
1193         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1194         I915_WRITE(GEN6_GFXPAUSE,       s->gfxpause);
1195         I915_WRITE(GEN6_RPDEUHWTC,      s->rpdeuhwtc);
1196         I915_WRITE(GEN6_RPDEUC,         s->rpdeuc);
1197         I915_WRITE(ECOBUS,              s->ecobus);
1198         I915_WRITE(VLV_PWRDWNUPCTL,     s->pwrdwnupctl);
1199         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
1200         I915_WRITE(GEN6_RPDEUCSW,       s->rp_deucsw);
1201         I915_WRITE(GEN6_RCUBMABDTMR,    s->rcubmabdtmr);
1202         I915_WRITE(VLV_RCEDATA,         s->rcedata);
1203         I915_WRITE(VLV_SPAREG2H,        s->spare2gh);
1204
1205         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
1206         I915_WRITE(GTIMR,               s->gt_imr);
1207         I915_WRITE(GTIER,               s->gt_ier);
1208         I915_WRITE(GEN6_PMIMR,          s->pm_imr);
1209         I915_WRITE(GEN6_PMIER,          s->pm_ier);
1210
1211         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
1212                 I915_WRITE(GEN7_GT_SCRATCH_BASE + i * 4, s->gt_scratch[i]);
1213
1214         /* GT SA CZ domain, 0x100000-0x138124 */
1215         I915_WRITE(TILECTL,                     s->tilectl);
1216         I915_WRITE(GTFIFOCTL,                   s->gt_fifoctl);
1217         /*
1218          * Preserve the GT allow wake and GFX force clock bit, they are not
1219          * be restored, as they are used to control the s0ix suspend/resume
1220          * sequence by the caller.
1221          */
1222         val = I915_READ(VLV_GTLC_WAKE_CTRL);
1223         val &= VLV_GTLC_ALLOWWAKEREQ;
1224         val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
1225         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
1226
1227         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1228         val &= VLV_GFX_CLK_FORCE_ON_BIT;
1229         val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
1230         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
1231
1232         I915_WRITE(VLV_PMWGICZ,                 s->pmwgicz);
1233
1234         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
1235         I915_WRITE(VLV_GU_CTL0,                 s->gu_ctl0);
1236         I915_WRITE(VLV_GU_CTL1,                 s->gu_ctl1);
1237         I915_WRITE(VLV_PCBR,                    s->pcbr);
1238         I915_WRITE(VLV_GUNIT_CLOCK_GATE2,       s->clock_gate_dis2);
1239 }
1240
1241 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
1242 {
1243         u32 val;
1244         int err;
1245
1246 #define COND (I915_READ(VLV_GTLC_SURVIVABILITY_REG) & VLV_GFX_CLK_STATUS_BIT)
1247
1248         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1249         val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
1250         if (force_on)
1251                 val |= VLV_GFX_CLK_FORCE_ON_BIT;
1252         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
1253
1254         if (!force_on)
1255                 return 0;
1256
1257         err = wait_for(COND, 20);
1258         if (err)
1259                 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
1260                           I915_READ(VLV_GTLC_SURVIVABILITY_REG));
1261
1262         return err;
1263 #undef COND
1264 }
1265
1266 static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
1267 {
1268         u32 val;
1269         int err = 0;
1270
1271         val = I915_READ(VLV_GTLC_WAKE_CTRL);
1272         val &= ~VLV_GTLC_ALLOWWAKEREQ;
1273         if (allow)
1274                 val |= VLV_GTLC_ALLOWWAKEREQ;
1275         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
1276         POSTING_READ(VLV_GTLC_WAKE_CTRL);
1277
1278 #define COND (!!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEACK) == \
1279               allow)
1280         err = wait_for(COND, 1);
1281         if (err)
1282                 DRM_ERROR("timeout disabling GT waking\n");
1283         return err;
1284 #undef COND
1285 }
1286
1287 static int vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
1288                                  bool wait_for_on)
1289 {
1290         u32 mask;
1291         u32 val;
1292         int err;
1293
1294         mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
1295         val = wait_for_on ? mask : 0;
1296 #define COND ((I915_READ(VLV_GTLC_PW_STATUS) & mask) == val)
1297         if (COND)
1298                 return 0;
1299
1300         DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n",
1301                         wait_for_on ? "on" : "off",
1302                         I915_READ(VLV_GTLC_PW_STATUS));
1303
1304         /*
1305          * RC6 transitioning can be delayed up to 2 msec (see
1306          * valleyview_enable_rps), use 3 msec for safety.
1307          */
1308         err = wait_for(COND, 3);
1309         if (err)
1310                 DRM_ERROR("timeout waiting for GT wells to go %s\n",
1311                           wait_for_on ? "on" : "off");
1312
1313         return err;
1314 #undef COND
1315 }
1316
1317 static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
1318 {
1319         if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
1320                 return;
1321
1322         DRM_ERROR("GT register access while GT waking disabled\n");
1323         I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
1324 }
1325
1326 static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
1327 {
1328         u32 mask;
1329         int err;
1330
1331         /*
1332          * Bspec defines the following GT well on flags as debug only, so
1333          * don't treat them as hard failures.
1334          */
1335         (void)vlv_wait_for_gt_wells(dev_priv, false);
1336
1337         mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
1338         WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
1339
1340         vlv_check_no_gt_access(dev_priv);
1341
1342         err = vlv_force_gfx_clock(dev_priv, true);
1343         if (err)
1344                 goto err1;
1345
1346         err = vlv_allow_gt_wake(dev_priv, false);
1347         if (err)
1348                 goto err2;
1349
1350         if (!IS_CHERRYVIEW(dev_priv->dev))
1351                 vlv_save_gunit_s0ix_state(dev_priv);
1352
1353         err = vlv_force_gfx_clock(dev_priv, false);
1354         if (err)
1355                 goto err2;
1356
1357         return 0;
1358
1359 err2:
1360         /* For safety always re-enable waking and disable gfx clock forcing */
1361         vlv_allow_gt_wake(dev_priv, true);
1362 err1:
1363         vlv_force_gfx_clock(dev_priv, false);
1364
1365         return err;
1366 }
1367
1368 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
1369                                 bool rpm_resume)
1370 {
1371         struct drm_device *dev = dev_priv->dev;
1372         int err;
1373         int ret;
1374
1375         /*
1376          * If any of the steps fail just try to continue, that's the best we
1377          * can do at this point. Return the first error code (which will also
1378          * leave RPM permanently disabled).
1379          */
1380         ret = vlv_force_gfx_clock(dev_priv, true);
1381
1382         if (!IS_CHERRYVIEW(dev_priv->dev))
1383                 vlv_restore_gunit_s0ix_state(dev_priv);
1384
1385         err = vlv_allow_gt_wake(dev_priv, true);
1386         if (!ret)
1387                 ret = err;
1388
1389         err = vlv_force_gfx_clock(dev_priv, false);
1390         if (!ret)
1391                 ret = err;
1392
1393         vlv_check_no_gt_access(dev_priv);
1394
1395         if (rpm_resume) {
1396                 intel_init_clock_gating(dev);
1397                 i915_gem_restore_fences(dev);
1398         }
1399
1400         return ret;
1401 }
1402
1403 #if 0
1404 static int intel_runtime_suspend(struct device *device)
1405 {
1406         struct pci_dev *pdev = to_pci_dev(device);
1407         struct drm_device *dev = pci_get_drvdata(pdev);
1408         struct drm_i915_private *dev_priv = dev->dev_private;
1409         int ret;
1410
1411         if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6(dev))))
1412                 return -ENODEV;
1413
1414         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
1415                 return -ENODEV;
1416
1417         DRM_DEBUG_KMS("Suspending device\n");
1418
1419         /*
1420          * We could deadlock here in case another thread holding struct_mutex
1421          * calls RPM suspend concurrently, since the RPM suspend will wait
1422          * first for this RPM suspend to finish. In this case the concurrent
1423          * RPM resume will be followed by its RPM suspend counterpart. Still
1424          * for consistency return -EAGAIN, which will reschedule this suspend.
1425          */
1426         if (!mutex_trylock(&dev->struct_mutex)) {
1427                 DRM_DEBUG_KMS("device lock contention, deffering suspend\n");
1428                 /*
1429                  * Bump the expiration timestamp, otherwise the suspend won't
1430                  * be rescheduled.
1431                  */
1432                 pm_runtime_mark_last_busy(device);
1433
1434                 return -EAGAIN;
1435         }
1436         /*
1437          * We are safe here against re-faults, since the fault handler takes
1438          * an RPM reference.
1439          */
1440         i915_gem_release_all_mmaps(dev_priv);
1441         mutex_unlock(&dev->struct_mutex);
1442
1443         intel_suspend_gt_powersave(dev);
1444         intel_runtime_pm_disable_interrupts(dev_priv);
1445
1446         ret = intel_suspend_complete(dev_priv);
1447         if (ret) {
1448                 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
1449                 intel_runtime_pm_enable_interrupts(dev_priv);
1450
1451                 return ret;
1452         }
1453
1454         cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
1455         intel_uncore_forcewake_reset(dev, false);
1456         dev_priv->pm.suspended = true;
1457
1458         /*
1459          * FIXME: We really should find a document that references the arguments
1460          * used below!
1461          */
1462         if (IS_HASWELL(dev)) {
1463                 /*
1464                  * current versions of firmware which depend on this opregion
1465                  * notification have repurposed the D1 definition to mean
1466                  * "runtime suspended" vs. what you would normally expect (D3)
1467                  * to distinguish it from notifications that might be sent via
1468                  * the suspend path.
1469                  */
1470                 intel_opregion_notify_adapter(dev, PCI_D1);
1471         } else {
1472                 /*
1473                  * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
1474                  * being detected, and the call we do at intel_runtime_resume()
1475                  * won't be able to restore them. Since PCI_D3hot matches the
1476                  * actual specification and appears to be working, use it. Let's
1477                  * assume the other non-Haswell platforms will stay the same as
1478                  * Broadwell.
1479                  */
1480                 intel_opregion_notify_adapter(dev, PCI_D3hot);
1481         }
1482
1483         assert_forcewakes_inactive(dev_priv);
1484
1485         DRM_DEBUG_KMS("Device suspended\n");
1486         return 0;
1487 }
1488
1489 static int intel_runtime_resume(struct device *device)
1490 {
1491         struct pci_dev *pdev = to_pci_dev(device);
1492         struct drm_device *dev = pci_get_drvdata(pdev);
1493         struct drm_i915_private *dev_priv = dev->dev_private;
1494         int ret = 0;
1495
1496         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
1497                 return -ENODEV;
1498
1499         DRM_DEBUG_KMS("Resuming device\n");
1500
1501         intel_opregion_notify_adapter(dev, PCI_D0);
1502         dev_priv->pm.suspended = false;
1503
1504         if (IS_GEN6(dev_priv))
1505                 intel_init_pch_refclk(dev);
1506         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1507                 hsw_disable_pc8(dev_priv);
1508         else if (IS_VALLEYVIEW(dev_priv))
1509                 ret = vlv_resume_prepare(dev_priv, true);
1510
1511         /*
1512          * No point of rolling back things in case of an error, as the best
1513          * we can do is to hope that things will still work (and disable RPM).
1514          */
1515         i915_gem_init_swizzling(dev);
1516         gen6_update_ring_freq(dev);
1517
1518         intel_runtime_pm_enable_interrupts(dev_priv);
1519         intel_enable_gt_powersave(dev);
1520
1521         if (ret)
1522                 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
1523         else
1524                 DRM_DEBUG_KMS("Device resumed\n");
1525
1526         return ret;
1527 }
1528 #endif
1529
1530 /*
1531  * This function implements common functionality of runtime and system
1532  * suspend sequence.
1533  */
1534 static int intel_suspend_complete(struct drm_i915_private *dev_priv)
1535 {
1536         struct drm_device *dev = dev_priv->dev;
1537         int ret;
1538
1539         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1540                 ret = hsw_suspend_complete(dev_priv);
1541         else if (IS_VALLEYVIEW(dev))
1542                 ret = vlv_suspend_complete(dev_priv);
1543         else
1544                 ret = 0;
1545
1546         return ret;
1547 }
1548
1549 #if 0
1550 static const struct dev_pm_ops i915_pm_ops = {
1551         /*
1552          * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
1553          * PMSG_RESUME]
1554          */
1555         .suspend = i915_pm_suspend,
1556         .suspend_late = i915_pm_suspend_late,
1557         .resume_early = i915_pm_resume_early,
1558         .resume = i915_pm_resume,
1559
1560         /*
1561          * S4 event handlers
1562          * @freeze, @freeze_late    : called (1) before creating the
1563          *                            hibernation image [PMSG_FREEZE] and
1564          *                            (2) after rebooting, before restoring
1565          *                            the image [PMSG_QUIESCE]
1566          * @thaw, @thaw_early       : called (1) after creating the hibernation
1567          *                            image, before writing it [PMSG_THAW]
1568          *                            and (2) after failing to create or
1569          *                            restore the image [PMSG_RECOVER]
1570          * @poweroff, @poweroff_late: called after writing the hibernation
1571          *                            image, before rebooting [PMSG_HIBERNATE]
1572          * @restore, @restore_early : called after rebooting and restoring the
1573          *                            hibernation image [PMSG_RESTORE]
1574          */
1575         .freeze = i915_pm_suspend,
1576         .freeze_late = i915_pm_suspend_late,
1577         .thaw_early = i915_pm_resume_early,
1578         .thaw = i915_pm_resume,
1579         .poweroff = i915_pm_suspend,
1580         .poweroff_late = i915_pm_poweroff_late,
1581         .restore_early = i915_pm_resume_early,
1582         .restore = i915_pm_resume,
1583
1584         /* S0ix (via runtime suspend) event handlers */
1585         .runtime_suspend = intel_runtime_suspend,
1586         .runtime_resume = intel_runtime_resume,
1587 };
1588
1589 static const struct vm_operations_struct i915_gem_vm_ops = {
1590         .fault = i915_gem_fault,
1591         .open = drm_gem_vm_open,
1592         .close = drm_gem_vm_close,
1593 };
1594
1595 static const struct file_operations i915_driver_fops = {
1596         .owner = THIS_MODULE,
1597         .open = drm_open,
1598         .release = drm_release,
1599         .unlocked_ioctl = drm_ioctl,
1600         .mmap = drm_gem_mmap,
1601         .poll = drm_poll,
1602         .read = drm_read,
1603 #ifdef CONFIG_COMPAT
1604         .compat_ioctl = i915_compat_ioctl,
1605 #endif
1606         .llseek = noop_llseek,
1607 };
1608 #endif
1609
1610 static struct cdev_pager_ops i915_gem_vm_ops = {
1611         .cdev_pg_fault  = i915_gem_fault,
1612         .cdev_pg_ctor   = i915_gem_pager_ctor,
1613         .cdev_pg_dtor   = i915_gem_pager_dtor
1614 };
1615
1616 static struct drm_driver driver = {
1617         /* Don't use MTRRs here; the Xserver or userspace app should
1618          * deal with them for Intel hardware.
1619          */
1620         .driver_features =
1621             DRIVER_USE_AGP |
1622             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM |
1623             DRIVER_RENDER,
1624         .load = i915_driver_load,
1625         .unload = i915_driver_unload,
1626         .open = i915_driver_open,
1627         .lastclose = i915_driver_lastclose,
1628         .preclose = i915_driver_preclose,
1629         .postclose = i915_driver_postclose,
1630
1631         /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
1632
1633         .device_is_agp = i915_driver_device_is_agp,
1634
1635 #if defined(CONFIG_DEBUG_FS)
1636         .debugfs_init = i915_debugfs_init,
1637         .debugfs_cleanup = i915_debugfs_cleanup,
1638 #endif
1639         .gem_free_object = i915_gem_free_object,
1640         .gem_pager_ops = &i915_gem_vm_ops,
1641
1642         .dumb_create = i915_gem_dumb_create,
1643         .dumb_map_offset = i915_gem_mmap_gtt,
1644         .dumb_destroy = drm_gem_dumb_destroy,
1645         .ioctls = i915_ioctls,
1646         .name = DRIVER_NAME,
1647         .desc = DRIVER_DESC,
1648         .date = DRIVER_DATE,
1649         .major = DRIVER_MAJOR,
1650         .minor = DRIVER_MINOR,
1651         .patchlevel = DRIVER_PATCHLEVEL,
1652 };
1653
1654 static int __init i915_init(void);
1655
1656 static int
1657 i915_attach(device_t kdev)
1658 {
1659         struct drm_device *dev = device_get_softc(kdev);
1660         int error;
1661         int dummy;
1662
1663         i915_init();
1664
1665         dev->driver = &driver;
1666         error = drm_attach(kdev, i915_attach_list);
1667
1668         /*
1669          * XXX hack - give the kvm_console time to come up before X starts
1670          * messing with everything, avoiding at least one deadlock.
1671          */
1672         tsleep(&dummy, 0, "i915_attach", hz*2);
1673
1674         return error;
1675 }
1676
1677 static device_method_t i915_methods[] = {
1678         /* Device interface */
1679         DEVMETHOD(device_probe,         i915_pci_probe),
1680         DEVMETHOD(device_attach,        i915_attach),
1681         DEVMETHOD(device_suspend,       i915_suspend_legacy),
1682         DEVMETHOD(device_resume,        i915_resume_legacy),
1683         DEVMETHOD(device_detach,        drm_release),
1684         DEVMETHOD_END
1685 };
1686
1687 static driver_t i915_driver = {
1688         "drm",
1689         i915_methods,
1690         sizeof(struct drm_device)
1691 };
1692
1693 static int __init i915_init(void)
1694 {
1695         driver.num_ioctls = i915_max_ioctl;
1696
1697         /*
1698          * If CONFIG_DRM_I915_KMS is set, default to KMS unless
1699          * explicitly disabled with the module pararmeter.
1700          *
1701          * Otherwise, just follow the parameter (defaulting to off).
1702          *
1703          * Allow optional vga_text_mode_force boot option to override
1704          * the default behavior.
1705          */
1706 #if defined(CONFIG_DRM_I915_KMS)
1707         if (i915.modeset != 0)
1708                 driver.driver_features |= DRIVER_MODESET;
1709 #endif
1710         if (i915.modeset == 1)
1711                 driver.driver_features |= DRIVER_MODESET;
1712
1713 #ifdef CONFIG_VGA_CONSOLE
1714         if (vgacon_text_force() && i915.modeset == -1)
1715                 driver.driver_features &= ~DRIVER_MODESET;
1716 #endif
1717
1718         if (!(driver.driver_features & DRIVER_MODESET)) {
1719                 driver.get_vblank_timestamp = NULL;
1720 #ifndef CONFIG_DRM_I915_UMS
1721                 /* Silently fail loading to not upset userspace. */
1722                 DRM_DEBUG_DRIVER("KMS and UMS disabled.\n");
1723                 return 0;
1724 #endif
1725         }
1726
1727         /*
1728          * FIXME: Note that we're lying to the DRM core here so that we can get access
1729          * to the atomic ioctl and the atomic properties.  Only plane operations on
1730          * a single CRTC will actually work.
1731          */
1732         if (i915.nuclear_pageflip)
1733                 driver.driver_features |= DRIVER_ATOMIC;
1734
1735 #if 0
1736         return drm_pci_init(&driver, &i915_pci_driver);
1737 #else
1738         return 1;
1739 #endif
1740 }
1741
1742 DRIVER_MODULE_ORDERED(i915, vgapci, i915_driver, drm_devclass, NULL, NULL, SI_ORDER_ANY);
1743 MODULE_DEPEND(i915, drm, 1, 1, 1);
1744 MODULE_DEPEND(i915, iicbus, 1, 1, 1);
1745 MODULE_DEPEND(i915, iic, 1, 1, 1);
1746 MODULE_DEPEND(i915, iicbb, 1, 1, 1);