sys/net/i4b/layer1/ifpnp/i4b_ifpnp_avm.c

   1 /*
   2  *   Copyright (c) 1999, 2000 Udo Schweigert. All rights reserved.
   3  *
   4  *   Redistribution and use in source and binary forms, with or without
   5  *   modification, are permitted provided that the following conditions
   6  *   are met:
   7  *
   8  *   1. Redistributions of source code must retain the above copyright
   9  *      notice, this list of conditions and the following disclaimer.
  10  *   2. Redistributions in binary form must reproduce the above copyright
  11  *      notice, this list of conditions and the following disclaimer in the
  12  *      documentation and/or other materials provided with the distribution.
  13  *   3. Neither the name of the author nor the names of any co-contributors
  14  *      may be used to endorse or promote products derived from this software
  15  *      without specific prior written permission.
  16  *   4. Altered versions must be plainly marked as such, and must not be
  17  *      misrepresented as being the original software and/or documentation.
  18  *
  19  *   THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  20  *   ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  21  *   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  22  *   ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  23  *   FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  24  *   DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  25  *   OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  26  *   HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  27  *   LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  28  *   OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  29  *   SUCH DAMAGE.
  30  *
  31  *---------------------------------------------------------------------------
  32  *
  33  *      i4b_ifpnp_avm.c: AVM Fritz!Card PnP hardware driver
  34  *      ---------------------------------------------------
  35  *
  36  * $FreeBSD: src/sys/i4b/layer1/ifpnp/i4b_ifpnp_avm.c,v 1.5.2.1 2001/08/10 14:08:37 obrien Exp $
  37  * $DragonFly: src/sys/net/i4b/layer1/ifpnp/i4b_ifpnp_avm.c,v 1.7 2005/06/03 16:50:03 dillon Exp $
  38  *
  39  *      last edit-date: [Fri Jan 12 17:05:28 2001]
  40  *
  41  *---------------------------------------------------------------------------*/
  42
  43 #include "use_ifpnp.h"
  44 #include "opt_i4b.h"
  45
  46 #if (NIFPNP > 0)
  47
  48 #include <sys/param.h>
  49 #include <sys/kernel.h>
  50 #include <sys/systm.h>
  51 #include <sys/mbuf.h>
  52
  53 #include <machine/bus.h>
  54 #include <sys/bus.h>
  55 #include <sys/rman.h>
  56
  57 #include <bus/isa/isavar.h>
  58
  59 #include <sys/socket.h>
  60 #include <sys/thread2.h>
  61 #include <net/if.h>
  62
  63 #include <net/i4b/include/machine/i4b_debug.h>
  64 #include <net/i4b/include/machine/i4b_ioctl.h>
  65 #include <net/i4b/include/machine/i4b_trace.h>
  66
  67 #include "../../include/i4b_global.h"
  68 #include "../../include/i4b_mbuf.h"
  69
  70 #include "../i4b_l1.h"
  71 #include "../isic/i4b_isic.h"
  72 #include "../isic/i4b_isac.h"
  73 #include "../isic/i4b_hscx.h"
  74
  75 #include "i4b_ifpnp_ext.h"
  76
  77 /* prototypes */
  78 static void avm_pnp_intr(void *);
  79 static void hscx_write_reg(int, u_int, struct l1_softc *, u_int);
  80 static void hscx_write_reg_val(int, u_int, u_int8_t, struct l1_softc *);
  81 static u_int hscx_read_reg(int, u_int, struct l1_softc *);
  82 static void hscx_read_fifo(int, void *, size_t, struct l1_softc *);
  83 static void hscx_write_fifo(int, void *, size_t, struct l1_softc *);
  84 static void avm_pnp_hscx_int_handler(struct l1_softc *);
  85 static void avm_pnp_hscx_intr(int, u_int, u_int, struct l1_softc *);
  86 static void avm_pnp_init_linktab(struct l1_softc *);
  87 static void avm_pnp_bchannel_setup(int, int, int, int);
  88 static void avm_pnp_bchannel_start(int, int);
  89 static void avm_pnp_hscx_init(struct l1_softc *, int, int);
  90 static void avm_pnp_bchannel_stat(int, int, bchan_statistics_t *);
  91 static void avm_pnp_set_linktab(int, int, drvr_link_t *);
  92 static isdn_link_t * avm_pnp_ret_linktab(int, int);
  93 static int avm_pnp_probe(device_t);
  94 static int avm_pnp_hscx_fifo(l1_bchan_state_t *, struct l1_softc *);
  95 int avm_pnp_attach(device_t);
  96 static void ifpnp_isac_intr(struct l1_softc *sc);
  97
  98 static device_method_t avm_pnp_methods[] = {
  99         /* Device interface */
 100         DEVMETHOD(device_probe,         avm_pnp_probe),
 101         DEVMETHOD(device_attach,        avm_pnp_attach),
 102         { 0, 0 }
 103 };
 104
 105 static driver_t avm_pnp_driver = {
 106         "ifpnp",
 107         avm_pnp_methods,
 108         sizeof(struct l1_softc)
 109 };
 110
 111 static devclass_t avm_pnp_devclass;
 112
 113 DRIVER_MODULE(avm_pnp, isa, avm_pnp_driver, avm_pnp_devclass, 0, 0);
 114
 115 /* jump table for multiplex routines */
 116
 117 struct i4b_l1mux_func avm_pnp_l1mux_func = {
 118         avm_pnp_ret_linktab,
 119         avm_pnp_set_linktab,
 120         ifpnp_mph_command_req,
 121         ifpnp_ph_data_req,
 122         ifpnp_ph_activate_req,
 123 };
 124
 125 struct l1_softc *ifpnp_scp[IFPNP_MAXUNIT];
 126
 127 /*---------------------------------------------------------------------------*
 128  *      AVM PnP Fritz!Card special registers
 129  *---------------------------------------------------------------------------*/
 130
 131 /*
 132  *      register offsets from i/o base
 133  */
 134 #define CLASS_OFFSET            0x00
 135 #define REVISION_OFFSET         0x01
 136 #define STAT0_OFFSET            0x02
 137 #define STAT1_OFFSET            0x03
 138 #define ADDR_REG_OFFSET         0x04
 139 /*#define MODREG_OFFSET         0x06
 140 #define VERREG_OFFSET           0x07*/
 141
 142 /* these 2 are used to select an ISAC register set */
 143 #define ISAC_LO_REG_OFFSET      0x04
 144 #define ISAC_HI_REG_OFFSET      0x06
 145
 146 /* offset higher than this goes to the HI register set */
 147 #define MAX_LO_REG_OFFSET       0x2f
 148
 149 /* mask for the offset */
 150 #define ISAC_REGSET_MASK        0x0f
 151
 152 /* the offset from the base to the ISAC registers */
 153 #define ISAC_REG_OFFSET         0x10
 154
 155 /* the offset from the base to the ISAC FIFO */
 156 #define ISAC_FIFO               0x02
 157
 158 /* not really the HSCX, but sort of */
 159 #define HSCX_FIFO               0x00
 160 #define HSCX_STAT               0x04
 161
 162 /*
 163  *      AVM PnP Status Latch 0 read only bits
 164  */
 165 #define ASL_IRQ_ISAC            0x01    /* ISAC  interrupt, active low */
 166 #define ASL_IRQ_HSCX            0x02    /* HSX   interrupt, active low */
 167 #define ASL_IRQ_TIMER           0x04    /* Timer interrupt, active low */
 168 #define ASL_IRQ_BCHAN           ASL_IRQ_HSCX
 169 /* actually active LOW */
 170 #define ASL_IRQ_Pending         (ASL_IRQ_ISAC | ASL_IRQ_HSCX | ASL_IRQ_TIMER)
 171
 172 /*
 173  *      AVM Status Latch 0 write only bits
 174  */
 175 #define ASL_RESET_ALL           0x01  /* reset siemens IC's, active 1 */
 176 #define ASL_TIMERDISABLE        0x02  /* active high */
 177 #define ASL_TIMERRESET          0x04  /* active high */
 178 #define ASL_ENABLE_INT          0x08  /* active high */
 179 #define ASL_TESTBIT             0x10  /* active high */
 180
 181 /*
 182  *      AVM Status Latch 1 write only bits
 183  */
 184 #define ASL1_INTSEL              0x0f  /* active high */
 185 #define ASL1_ENABLE_IOM          0x80  /* active high */
 186
 187 /*
 188  * "HSCX" mode bits
 189  */
 190 #define  HSCX_MODE_ITF_FLG      0x01
 191 #define  HSCX_MODE_TRANS        0x02
 192 #define  HSCX_MODE_CCR_7        0x04
 193 #define  HSCX_MODE_CCR_16       0x08
 194 #define  HSCX_MODE_TESTLOOP     0x80
 195
 196 /*
 197  * "HSCX" status bits
 198  */
 199 #define  HSCX_STAT_RME          0x01
 200 #define  HSCX_STAT_RDO          0x10
 201 #define  HSCX_STAT_CRCVFRRAB    0x0E
 202 #define  HSCX_STAT_CRCVFR       0x06
 203 #define  HSCX_STAT_RML_MASK     0x3f00
 204
 205 /*
 206  * "HSCX" interrupt bits
 207  */
 208 #define  HSCX_INT_XPR           0x80
 209 #define  HSCX_INT_XDU           0x40
 210 #define  HSCX_INT_RPR           0x20
 211 #define  HSCX_INT_MASK          0xE0
 212
 213 /*
 214  * "HSCX" command bits
 215  */
 216 #define  HSCX_CMD_XRS           0x80
 217 #define  HSCX_CMD_XME           0x01
 218 #define  HSCX_CMD_RRS           0x20
 219 #define  HSCX_CMD_XML_MASK      0x3f00
 220
 221 /*
 222  * to prevent deactivating the "HSCX" when both channels are active we
 223  * define an HSCX_ACTIVE flag which is or'd into the channel's state
 224  * flag in avm_pnp_bchannel_setup upon active and cleared upon deactivation.
 225  * It is set high to allow room for new flags.
 226  */
 227 #define HSCX_AVMA1PP_ACTIVE     0x1000
 228
 229 /*---------------------------------------------------------------------------*
 230  *      AVM read fifo routines
 231  *---------------------------------------------------------------------------*/
 232
 233 static void
 234 avm_pnp_read_fifo(struct l1_softc *sc, int what, void *buf, size_t size)
 235 {
 236         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 237         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 238
 239         switch (what) {
 240                 case ISIC_WHAT_ISAC:
 241                         bus_space_write_1(btag, bhandle,  ADDR_REG_OFFSET, ISAC_FIFO);
 242                         bus_space_read_multi_1(btag, bhandle,  ISAC_REG_OFFSET, buf, size);
 243                         break;
 244                 case ISIC_WHAT_HSCXA:
 245                         hscx_read_fifo(0, buf, size, sc);
 246                         break;
 247                 case ISIC_WHAT_HSCXB:
 248                         hscx_read_fifo(1, buf, size, sc);
 249                         break;
 250         }
 251 }
 252
 253 static void
 254 hscx_read_fifo(int chan, void *buf, size_t len, struct l1_softc *sc)
 255 {
 256         u_int8_t *ip;
 257         size_t cnt;
 258         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 259         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 260
 261         bus_space_write_1(btag, bhandle, ADDR_REG_OFFSET, chan);
 262         ip = (u_int8_t *)buf;
 263         cnt = 0;
 264         while (cnt++ < len)
 265         {
 266                 *ip++ = bus_space_read_1(btag, bhandle, ISAC_REG_OFFSET);
 267         }
 268 }
 269
 270 /*---------------------------------------------------------------------------*
 271  *      AVM write fifo routines
 272  *---------------------------------------------------------------------------*/
 273 static void
 274 avm_pnp_write_fifo(struct l1_softc *sc, int what, void *buf, size_t size)
 275 {
 276         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 277         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 278
 279         switch (what) {
 280                 case ISIC_WHAT_ISAC:
 281                         bus_space_write_1(btag, bhandle,  ADDR_REG_OFFSET, ISAC_FIFO);
 282                         bus_space_write_multi_1(btag, bhandle,  ISAC_REG_OFFSET, (u_int8_t*)buf, size);
 283                         break;
 284                 case ISIC_WHAT_HSCXA:
 285                         hscx_write_fifo(0, buf, size, sc);
 286                         break;
 287                 case ISIC_WHAT_HSCXB:
 288                         hscx_write_fifo(1, buf, size, sc);
 289                         break;
 290         }
 291 }
 292
 293 static void
 294 hscx_write_fifo(int chan, void *buf, size_t len, struct l1_softc *sc)
 295 {
 296         u_int8_t *ip;
 297         size_t cnt;
 298         l1_bchan_state_t *Bchan = &sc->sc_chan[chan];
 299         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 300         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 301
 302         sc->avma1pp_cmd &= ~HSCX_CMD_XME;
 303         sc->avma1pp_txl = 0;
 304
 305         if (Bchan->out_mbuf_cur == NULL)
 306         {
 307           if (Bchan->bprot != BPROT_NONE)
 308                  sc->avma1pp_cmd |= HSCX_CMD_XME;
 309         }
 310         if (len != sc->sc_bfifolen)
 311                 sc->avma1pp_txl = len;
 312
 313         hscx_write_reg(chan, HSCX_STAT, sc, 3);
 314
 315         ip = (u_int8_t *)buf;
 316         cnt = 0;
 317         while (cnt++ < len)
 318         {
 319                 bus_space_write_1(btag, bhandle, ISAC_REG_OFFSET, *ip++);
 320         }
 321 }
 322
 323 /*---------------------------------------------------------------------------*
 324  *      AVM write register routines
 325  *---------------------------------------------------------------------------*/
 326
 327 static void
 328 avm_pnp_write_reg(struct l1_softc *sc, int what, bus_size_t offs, u_int8_t data)
 329 {
 330         u_char reg_bank;
 331         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 332         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 333
 334         switch (what) {
 335                 case ISIC_WHAT_ISAC:
 336                         reg_bank = (offs > MAX_LO_REG_OFFSET) ? ISAC_HI_REG_OFFSET:ISAC_LO_REG_OFFSET;
 337                         /* set the register bank */
 338                         bus_space_write_1(btag, bhandle, ADDR_REG_OFFSET, reg_bank);
 339                         bus_space_write_1(btag, bhandle, ISAC_REG_OFFSET + (offs & ISAC_REGSET_MASK), data);
 340                         break;
 341                 case ISIC_WHAT_HSCXA:
 342                         hscx_write_reg_val(0, offs, data, sc);
 343                         break;
 344                 case ISIC_WHAT_HSCXB:
 345                         hscx_write_reg_val(1, offs, data, sc);
 346                         break;
 347         }
 348 }
 349
 350 static void
 351 hscx_write_reg(int chan, u_int off, struct l1_softc *sc, u_int which)
 352 {
 353         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 354         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 355
 356         /* point at the correct channel */
 357         bus_space_write_1(btag, bhandle, ADDR_REG_OFFSET, chan);
 358         if (which & 4)
 359                 bus_space_write_1(btag, bhandle, ISAC_REG_OFFSET + off + 2, sc->avma1pp_prot);
 360         if (which & 2)
 361                 bus_space_write_1(btag, bhandle, ISAC_REG_OFFSET + off + 1, sc->avma1pp_txl);
 362         if (which & 1)
 363                 bus_space_write_1(btag, bhandle, ISAC_REG_OFFSET + off, sc->avma1pp_cmd);
 364 }
 365
 366 static void
 367 hscx_write_reg_val(int chan, u_int off, u_int8_t val, struct l1_softc *sc)
 368 {
 369         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 370         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 371
 372         /* point at the correct channel */
 373         bus_space_write_1(btag, bhandle, ADDR_REG_OFFSET, chan);
 374         bus_space_write_1(btag, bhandle, ISAC_REG_OFFSET + off, val);
 375 }
 376
 377 /*---------------------------------------------------------------------------*
 378  *      AVM read register routines
 379  *---------------------------------------------------------------------------*/
 380 static u_int8_t
 381 avm_pnp_read_reg(struct l1_softc *sc, int what, bus_size_t offs)
 382 {
 383         u_char reg_bank;
 384         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 385         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 386
 387         switch (what) {
 388                 case ISIC_WHAT_ISAC:
 389                         reg_bank = (offs > MAX_LO_REG_OFFSET) ? ISAC_HI_REG_OFFSET:ISAC_LO_REG_OFFSET;
 390                         /* set the register bank */
 391                         bus_space_write_1(btag, bhandle, ADDR_REG_OFFSET, reg_bank);
 392                         return(bus_space_read_1(btag, bhandle, ISAC_REG_OFFSET +
 393                                 (offs & ISAC_REGSET_MASK)));
 394                 case ISIC_WHAT_HSCXA:
 395                         return hscx_read_reg(0, offs, sc);
 396                 case ISIC_WHAT_HSCXB:
 397                         return hscx_read_reg(1, offs, sc);
 398         }
 399         return 0;
 400 }
 401
 402 static u_int
 403 hscx_read_reg(int chan, u_int off, struct l1_softc *sc)
 404 {
 405         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 406         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 407
 408         /* point at the correct channel */
 409         bus_space_write_1(btag, bhandle, ADDR_REG_OFFSET, chan);
 410         return(bus_space_read_1(btag, bhandle, ISAC_REG_OFFSET + off));
 411 }
 412
 413
 414 static struct ifpnp_ids {
 415         u_long vend_id;
 416         char *id_str;
 417 } ifpnp_ids[] = {
 418         { 0x0009cd06,           "AVM Fritz!Card PnP"            },
 419         { 0, 0 }
 420 };
 421
 422 /*---------------------------------------------------------------------------*
 423  *      avm_pnp_probe - probe for a card
 424  *---------------------------------------------------------------------------*/
 425 static int
 426 avm_pnp_probe(dev)
 427         device_t                dev;
 428 {
 429         struct ifpnp_ids *ids;                  /* pnp id's */
 430         char *string = NULL;                            /* the name */
 431         u_int32_t vend_id = isa_get_vendorid(dev);      /* vendor id */
 432
 433         /* search table of knowd id's */
 434
 435         for(ids = ifpnp_ids; ids->vend_id != 0; ids++)
 436         {
 437                 if(vend_id == ids->vend_id)
 438                 {
 439                         string = ids->id_str;
 440                         break;
 441                 }
 442         }
 443
 444         if(string)              /* set name if we have one */
 445         {
 446                 device_set_desc(dev, string);   /* set description */
 447                 return 0;
 448         }
 449         else
 450         {
 451                 return ENXIO;
 452         }
 453 }
 454
 455 /*---------------------------------------------------------------------------*
 456  *      avm_pnp_attach - attach Fritz!Card PnP
 457  *---------------------------------------------------------------------------*/
 458 int
 459 avm_pnp_attach(device_t dev)
 460 {
 461         struct l1_softc *sc;
 462         u_int v;
 463         int unit, error = 0;
 464         u_int16_t vid;
 465         void *ih = 0;
 466         bus_space_handle_t bhandle;
 467         bus_space_tag_t btag;
 468
 469         crit_enter();
 470
 471         vid = isa_get_vendorid(dev);
 472         sc = device_get_softc(dev);
 473         unit = device_get_unit(dev);
 474         bzero(sc, sizeof(struct l1_softc));
 475
 476         /* probably not really required */
 477         if(unit > IFPNP_MAXUNIT) {
 478                 printf("avm_pnp%d: Error, unit > IFPNP_MAXUNIT!\n", unit);
 479                 crit_exit();
 480                 return(ENXIO);
 481         }
 482
 483         ifpnp_scp[unit] = sc;
 484
 485
 486         /* get io_base */
 487         if(!(sc->sc_resources.io_base[0] =
 488                         bus_alloc_resource(dev, SYS_RES_IOPORT,
 489                                                 &sc->sc_resources.io_rid[0],
 490                                                 0UL, ~0UL, 1, RF_ACTIVE ) ))
 491         {
 492                 printf("avm_pnp_attach: Couldn't get my io_base.\n");
 493                 return ENXIO;
 494         }
 495         if (sc->sc_resources.io_base[0] == NULL) {
 496                 printf("avm_pnp%d: couldn't map IO port\n", unit);
 497                 error = ENXIO;
 498                 goto fail;
 499         }
 500
 501         bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 502         btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 503
 504         /* will not be used for pnp devices */
 505         sc->sc_port = rman_get_start(sc->sc_resources.io_base[0]);
 506
 507         /* get irq, release io_base if we don't get it */
 508
 509         if(!(sc->sc_resources.irq =
 510                         bus_alloc_resource(dev, SYS_RES_IRQ,
 511                                            &sc->sc_resources.irq_rid,
 512                                            0UL, ~0UL, 1, RF_ACTIVE)))
 513         {
 514                 printf("avm_pnp%d: Could not get irq.\n",unit);
 515                 error = ENXIO;
 516                 goto fail;
 517         }
 518
 519         /* not needed */
 520         sc->sc_irq = rman_get_start(sc->sc_resources.irq);
 521         bus_setup_intr(dev, sc->sc_resources.irq, INTR_TYPE_NET,
 522                        (void(*)(void*))avm_pnp_intr, sc,
 523                        &ih, NULL);
 524         sc->sc_unit = unit;
 525
 526         /* end of new-bus stuff */
 527
 528         ISAC_BASE = (caddr_t)ISIC_WHAT_ISAC;
 529
 530         HSCX_A_BASE = (caddr_t)ISIC_WHAT_HSCXA;
 531         HSCX_B_BASE = (caddr_t)ISIC_WHAT_HSCXB;
 532
 533         /* setup access routines */
 534
 535         sc->clearirq = NULL;
 536         sc->readreg = avm_pnp_read_reg;
 537         sc->writereg = avm_pnp_write_reg;
 538
 539         sc->readfifo = avm_pnp_read_fifo;
 540         sc->writefifo = avm_pnp_write_fifo;
 541
 542         /* setup card type */
 543
 544         sc->sc_cardtyp = CARD_TYPEP_AVM_PNP;
 545
 546         /* setup IOM bus type */
 547
 548         sc->sc_bustyp = BUS_TYPE_IOM2;
 549
 550         /* set up some other miscellaneous things */
 551         sc->sc_ipac = 0;
 552         sc->sc_bfifolen = HSCX_FIFO_LEN;
 553
 554         /* reset the card */
 555         /* the Linux driver does this to clear any pending ISAC interrupts */
 556         v = 0;
 557         v = ISAC_READ(I_STAR);
 558         v = ISAC_READ(I_MODE);
 559         v = ISAC_READ(I_ADF2);
 560         v = ISAC_READ(I_ISTA);
 561         if (v & ISAC_ISTA_EXI)
 562         {
 563                  v = ISAC_READ(I_EXIR);
 564         }
 565         v = ISAC_READ(I_CIRR);
 566         ISAC_WRITE(I_MASK, 0xff);
 567         /* the Linux driver does this to clear any pending HSCX interrupts */
 568         v = hscx_read_reg(0, HSCX_STAT, sc);
 569         v = hscx_read_reg(1, HSCX_STAT, sc);
 570
 571         bus_space_write_1(btag, bhandle, STAT0_OFFSET, ASL_RESET_ALL|ASL_TIMERDISABLE);
 572         DELAY(SEC_DELAY/100); /* 10 ms */
 573         bus_space_write_1(btag, bhandle, STAT1_OFFSET, ASL1_ENABLE_IOM|sc->sc_irq);
 574         DELAY(SEC_DELAY/100); /* 10 ms */
 575         bus_space_write_1(btag, bhandle, STAT0_OFFSET, ASL_TIMERRESET|ASL_ENABLE_INT|ASL_TIMERDISABLE);
 576         DELAY(SEC_DELAY/100); /* 10 ms */
 577
 578          printf("ifpnp%d: AVM Fritz!Card PnP Class %#x Revision %d \n", unit,
 579                         bus_space_read_1(btag, bhandle, CLASS_OFFSET),
 580                         bus_space_read_1(btag, bhandle, REVISION_OFFSET));
 581
 582          printf("ifpnp%d: ISAC %s (IOM-%c)\n", unit,
 583                 "2085 Version A1/A2 or 2086/2186 Version 1.1",
 584                  sc->sc_bustyp == BUS_TYPE_IOM1 ? '1' : '2');
 585
 586
 587         /* init the ISAC */
 588         ifpnp_isac_init(sc);
 589
 590         /* init the "HSCX" */
 591         avm_pnp_bchannel_setup(sc->sc_unit, HSCX_CH_A, BPROT_NONE, 0);
 592
 593         avm_pnp_bchannel_setup(sc->sc_unit, HSCX_CH_B, BPROT_NONE, 0);
 594
 595         /* can't use the normal B-Channel stuff */
 596         avm_pnp_init_linktab(sc);
 597
 598         /* set trace level */
 599
 600         sc->sc_trace = TRACE_OFF;
 601
 602         sc->sc_state = ISAC_IDLE;
 603
 604         sc->sc_ibuf = NULL;
 605         sc->sc_ib = NULL;
 606         sc->sc_ilen = 0;
 607
 608         sc->sc_obuf = NULL;
 609         sc->sc_op = NULL;
 610         sc->sc_ol = 0;
 611         sc->sc_freeflag = 0;
 612
 613         sc->sc_obuf2 = NULL;
 614         sc->sc_freeflag2 = 0;
 615
 616         callout_init(&sc->sc_T3_timeout);
 617         callout_init(&sc->sc_T4_timeout);
 618
 619         /* init higher protocol layers */
 620
 621         i4b_l1_mph_status_ind(L0IFPNPUNIT(sc->sc_unit), STI_ATTACH, sc->sc_cardtyp, &avm_pnp_l1mux_func);
 622
 623   fail:
 624         crit_exit();
 625         return(error);
 626 }
 627
 628 /*
 629  * this is the real interrupt routine
 630  */
 631 static void
 632 avm_pnp_hscx_intr(int h_chan, u_int stat, u_int cnt, struct l1_softc *sc)
 633 {
 634         l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
 635         int activity = -1;
 636
 637         NDBGL1(L1_H_IRQ, "%#x", stat);
 638
 639         if((stat & HSCX_INT_XDU) && (chan->bprot != BPROT_NONE))/* xmit data underrun */
 640         {
 641                 chan->stat_XDU++;
 642                 NDBGL1(L1_H_XFRERR, "xmit data underrun");
 643                 /* abort the transmission */
 644                 sc->avma1pp_txl = 0;
 645                 sc->avma1pp_cmd |= HSCX_CMD_XRS;
 646                 hscx_write_reg(h_chan, HSCX_STAT, sc, 1);
 647                 sc->avma1pp_cmd &= ~HSCX_CMD_XRS;
 648                 hscx_write_reg(h_chan, HSCX_STAT, sc, 1);
 649
 650                 if (chan->out_mbuf_head != NULL)  /* don't continue to transmit this buffer */
 651                 {
 652                         i4b_Bfreembuf(chan->out_mbuf_head);
 653                         chan->out_mbuf_cur = chan->out_mbuf_head = NULL;
 654                 }
 655         }
 656
 657         /*
 658          * The following is based on examination of the Linux driver.
 659          *
 660          * The logic here is different than with a "real" HSCX; all kinds
 661          * of information (interrupt/status bits) are in stat.
 662          *              HSCX_INT_RPR indicates a receive interrupt
 663          *                      HSCX_STAT_RDO indicates an overrun condition, abort -
 664          *                      otherwise read the bytes ((stat & HSCX_STZT_RML_MASK) >> 8)
 665          *                      HSCX_STAT_RME indicates end-of-frame and apparently any
 666          *                      CRC/framing errors are only reported in this state.
 667          *                              if ((stat & HSCX_STAT_CRCVFRRAB) != HSCX_STAT_CRCVFR)
 668          *                                      CRC/framing error
 669          */
 670
 671         if(stat & HSCX_INT_RPR)
 672         {
 673                 int fifo_data_len;
 674                 int error = 0;
 675                 /* always have to read the FIFO, so use a scratch buffer */
 676                 u_char scrbuf[HSCX_FIFO_LEN];
 677
 678                 if(stat & HSCX_STAT_RDO)
 679                 {
 680                         chan->stat_RDO++;
 681                         NDBGL1(L1_H_XFRERR, "receive data overflow");
 682                         error++;
 683                 }
 684
 685                 /*
 686                  * check whether we're receiving data for an inactive B-channel
 687                  * and discard it. This appears to happen for telephony when
 688                  * both B-channels are active and one is deactivated. Since
 689                  * it is not really possible to deactivate the channel in that
 690                  * case (the ASIC seems to deactivate _both_ channels), the
 691                  * "deactivated" channel keeps receiving data which can lead
 692                  * to exhaustion of mbufs and a kernel panic.
 693                  *
 694                  * This is a hack, but it's the only solution I can think of
 695                  * without having the documentation for the ASIC.
 696                  * GJ - 28 Nov 1999
 697                  */
 698                  if (chan->state == HSCX_IDLE)
 699                  {
 700                         NDBGL1(L1_H_XFRERR, "toss data from %d", h_chan);
 701                         error++;
 702                  }
 703
 704                 fifo_data_len = cnt;
 705
 706                 if(fifo_data_len == 0)
 707                         fifo_data_len = sc->sc_bfifolen;
 708
 709                 /* ALWAYS read data from HSCX fifo */
 710
 711                 HSCX_RDFIFO(h_chan, scrbuf, fifo_data_len);
 712                 chan->rxcount += fifo_data_len;
 713
 714                 /* all error conditions checked, now decide and take action */
 715
 716                 if(error == 0)
 717                 {
 718                         if(chan->in_mbuf == NULL)
 719                         {
 720                                 if((chan->in_mbuf = i4b_Bgetmbuf(BCH_MAX_DATALEN)) == NULL)
 721                                         panic("L1 avm_pnp_hscx_intr: RME, cannot allocate mbuf!\n");
 722                                 chan->in_cbptr = chan->in_mbuf->m_data;
 723                                 chan->in_len = 0;
 724                         }
 725
 726                         if((chan->in_len + fifo_data_len) <= BCH_MAX_DATALEN)
 727                         {
 728                                 /* OK to copy the data */
 729                                 bcopy(scrbuf, chan->in_cbptr, fifo_data_len);
 730                                 chan->in_cbptr += fifo_data_len;
 731                                 chan->in_len += fifo_data_len;
 732
 733                                 /* setup mbuf data length */
 734
 735                                 chan->in_mbuf->m_len = chan->in_len;
 736                                 chan->in_mbuf->m_pkthdr.len = chan->in_len;
 737
 738                                 if(sc->sc_trace & TRACE_B_RX)
 739                                 {
 740                                         i4b_trace_hdr_t hdr;
 741                                         hdr.unit = L0IFPNPUNIT(sc->sc_unit);
 742                                         hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
 743                                         hdr.dir = FROM_NT;
 744                                         hdr.count = ++sc->sc_trace_bcount;
 745                                         MICROTIME(hdr.time);
 746                                         i4b_l1_trace_ind(&hdr, chan->in_mbuf->m_len, chan->in_mbuf->m_data);
 747                                 }
 748
 749                                 if (stat & HSCX_STAT_RME)
 750                                 {
 751                                   if((stat & HSCX_STAT_CRCVFRRAB) == HSCX_STAT_CRCVFR)
 752                                   {
 753                                          (*chan->isic_drvr_linktab->bch_rx_data_ready)(chan->isic_drvr_linktab->unit);
 754                                          activity = ACT_RX;
 755
 756                                          /* mark buffer ptr as unused */
 757
 758                                          chan->in_mbuf = NULL;
 759                                          chan->in_cbptr = NULL;
 760                                          chan->in_len = 0;
 761                                   }
 762                                   else
 763                                   {
 764                                                 chan->stat_CRC++;
 765                                                 NDBGL1(L1_H_XFRERR, "CRC/RAB");
 766                                           if (chan->in_mbuf != NULL)
 767                                           {
 768                                                   i4b_Bfreembuf(chan->in_mbuf);
 769                                                   chan->in_mbuf = NULL;
 770                                                   chan->in_cbptr = NULL;
 771                                                   chan->in_len = 0;
 772                                           }
 773                                   }
 774                                 }
 775                         } /* END enough space in mbuf */
 776                         else
 777                         {
 778                                  if(chan->bprot == BPROT_NONE)
 779                                  {
 780                                           /* setup mbuf data length */
 781
 782                                           chan->in_mbuf->m_len = chan->in_len;
 783                                           chan->in_mbuf->m_pkthdr.len = chan->in_len;
 784
 785                                           if(sc->sc_trace & TRACE_B_RX)
 786                                           {
 787                                                         i4b_trace_hdr_t hdr;
 788                                                         hdr.unit = L0IFPNPUNIT(sc->sc_unit);
 789                                                         hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
 790                                                         hdr.dir = FROM_NT;
 791                                                         hdr.count = ++sc->sc_trace_bcount;
 792                                                         MICROTIME(hdr.time);
 793                                                         i4b_l1_trace_ind(&hdr, chan->in_mbuf->m_len, chan->in_mbuf->m_data);
 794                                                 }
 795
 796                                           if(!(i4b_l1_bchan_tel_silence(chan->in_mbuf->m_data, chan->in_mbuf->m_len)))
 797                                                  activity = ACT_RX;
 798
 799                                           /* move rx'd data to rx queue */
 800 #if defined (__FreeBSD__) && __FreeBSD__ > 4
 801                                           (void) IF_HANDOFF(&chan->rx_queue, chan->in_mbuf, NULL);
 802 #else
 803                                           if(!(IF_QFULL(&chan->rx_queue)))
 804                                           {
 805                                                 IF_ENQUEUE(&chan->rx_queue, chan->in_mbuf);
 806                                           }
 807                                           else
 808                                           {
 809                                                 i4b_Bfreembuf(chan->in_mbuf);
 810                                           }
 811 #endif
 812                                           /* signal upper layer that data are available */
 813                                           (*chan->isic_drvr_linktab->bch_rx_data_ready)(chan->isic_drvr_linktab->unit);
 814
 815                                           /* alloc new buffer */
 816
 817                                           if((chan->in_mbuf = i4b_Bgetmbuf(BCH_MAX_DATALEN)) == NULL)
 818                                                  panic("L1 avm_pnp_hscx_intr: RPF, cannot allocate new mbuf!\n");
 819
 820                                           /* setup new data ptr */
 821
 822                                           chan->in_cbptr = chan->in_mbuf->m_data;
 823
 824                                           /* OK to copy the data */
 825                                           bcopy(scrbuf, chan->in_cbptr, fifo_data_len);
 826
 827                                           chan->in_cbptr += fifo_data_len;
 828                                           chan->in_len = fifo_data_len;
 829
 830                                           chan->rxcount += fifo_data_len;
 831                                         }
 832                                  else
 833                                         {
 834                                           NDBGL1(L1_H_XFRERR, "RAWHDLC rx buffer overflow in RPF, in_len=%d", chan->in_len);
 835                                           chan->in_cbptr = chan->in_mbuf->m_data;
 836                                           chan->in_len = 0;
 837                                         }
 838                           }
 839                 } /* if(error == 0) */
 840                 else
 841                 {
 842                         /* land here for RDO */
 843                         if (chan->in_mbuf != NULL)
 844                         {
 845                                 i4b_Bfreembuf(chan->in_mbuf);
 846                                 chan->in_mbuf = NULL;
 847                                 chan->in_cbptr = NULL;
 848                                 chan->in_len = 0;
 849                         }
 850                         sc->avma1pp_txl = 0;
 851                         sc->avma1pp_cmd |= HSCX_CMD_RRS;
 852                         hscx_write_reg(h_chan, HSCX_STAT, sc, 1);
 853                         sc->avma1pp_cmd &= ~HSCX_CMD_RRS;
 854                         hscx_write_reg(h_chan, HSCX_STAT, sc, 1);
 855                 }
 856         }
 857
 858
 859         /* transmit fifo empty, new data can be written to fifo */
 860
 861         if(stat & HSCX_INT_XPR)
 862         {
 863                 /*
 864                  * for a description what is going on here, please have
 865                  * a look at isic_bchannel_start() in i4b_bchan.c !
 866                  */
 867
 868                 NDBGL1(L1_H_IRQ, "unit %d, chan %d - XPR, Tx Fifo Empty!", sc->sc_unit, h_chan);
 869
 870                 if(chan->out_mbuf_cur == NULL)  /* last frame is transmitted */
 871                 {
 872                         IF_DEQUEUE(&chan->tx_queue, chan->out_mbuf_head);
 873
 874                         if(chan->out_mbuf_head == NULL)
 875                         {
 876                                 chan->state &= ~HSCX_TX_ACTIVE;
 877                                 (*chan->isic_drvr_linktab->bch_tx_queue_empty)(chan->isic_drvr_linktab->unit);
 878                         }
 879                         else
 880                         {
 881                                 chan->state |= HSCX_TX_ACTIVE;
 882                                 chan->out_mbuf_cur = chan->out_mbuf_head;
 883                                 chan->out_mbuf_cur_ptr = chan->out_mbuf_cur->m_data;
 884                                 chan->out_mbuf_cur_len = chan->out_mbuf_cur->m_len;
 885
 886                                 if(sc->sc_trace & TRACE_B_TX)
 887                                 {
 888                                         i4b_trace_hdr_t hdr;
 889                                         hdr.unit = L0IFPNPUNIT(sc->sc_unit);
 890                                         hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
 891                                         hdr.dir = FROM_TE;
 892                                         hdr.count = ++sc->sc_trace_bcount;
 893                                         MICROTIME(hdr.time);
 894                                         i4b_l1_trace_ind(&hdr, chan->out_mbuf_cur->m_len, chan->out_mbuf_cur->m_data);
 895                                 }
 896
 897                                 if(chan->bprot == BPROT_NONE)
 898                                 {
 899                                         if(!(i4b_l1_bchan_tel_silence(chan->out_mbuf_cur->m_data, chan->out_mbuf_cur->m_len)))
 900                                                 activity = ACT_TX;
 901                                 }
 902                                 else
 903                                 {
 904                                         activity = ACT_TX;
 905                                 }
 906                         }
 907                 }
 908
 909                 avm_pnp_hscx_fifo(chan, sc);
 910         }
 911
 912         /* call timeout handling routine */
 913
 914         if(activity == ACT_RX || activity == ACT_TX)
 915                 (*chan->isic_drvr_linktab->bch_activity)(chan->isic_drvr_linktab->unit, activity);
 916 }
 917
 918 /*
 919  * this is the main routine which checks each channel and then calls
 920  * the real interrupt routine as appropriate
 921  */
 922 static void
 923 avm_pnp_hscx_int_handler(struct l1_softc *sc)
 924 {
 925         u_char stat = 0;
 926         u_char cnt = 0;
 927
 928         stat = hscx_read_reg(0, HSCX_STAT, sc);
 929         if (stat & HSCX_INT_RPR)
 930           cnt = hscx_read_reg(0, HSCX_STAT+1, sc);
 931         if (stat & HSCX_INT_MASK)
 932           avm_pnp_hscx_intr(0, stat, cnt, sc);
 933
 934         cnt = 0;
 935         stat = hscx_read_reg(1, HSCX_STAT, sc);
 936         if (stat & HSCX_INT_RPR)
 937           cnt = hscx_read_reg(1, HSCX_STAT+1, sc);
 938         if (stat & HSCX_INT_MASK)
 939           avm_pnp_hscx_intr(1, stat, cnt, sc);
 940 }
 941
 942 static void
 943 avm_pnp_intr(void *xsc)
 944 {
 945         u_char stat;
 946         struct l1_softc *sc;
 947         bus_space_handle_t bhandle;
 948         bus_space_tag_t btag;
 949
 950         sc = xsc;
 951         bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 952         btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 953
 954         stat = bus_space_read_1(btag, bhandle, STAT0_OFFSET);
 955         NDBGL1(L1_H_IRQ, "stat %x", stat);
 956         /* was there an interrupt from this card ? */
 957         if ((stat & ASL_IRQ_Pending) == ASL_IRQ_Pending)
 958                 return; /* no */
 959         /* interrupts are low active */
 960         if (!(stat & ASL_IRQ_TIMER))
 961           NDBGL1(L1_H_IRQ, "timer interrupt ???");
 962         if (!(stat & ASL_IRQ_HSCX))
 963         {
 964           NDBGL1(L1_H_IRQ, "HSCX");
 965                 avm_pnp_hscx_int_handler(sc);
 966         }
 967         if (!(stat & ASL_IRQ_ISAC))
 968         {
 969           NDBGL1(L1_H_IRQ, "ISAC");
 970                 ifpnp_isac_intr(sc);
 971         }
 972 }
 973
 974 static void
 975 avm_pnp_hscx_init(struct l1_softc *sc, int h_chan, int activate)
 976 {
 977         l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
 978
 979         NDBGL1(L1_BCHAN, "unit=%d, channel=%d, %s",
 980                 sc->sc_unit, h_chan, activate ? "activate" : "deactivate");
 981
 982         if (activate == 0)
 983         {
 984                 /* only deactivate if both channels are idle */
 985                 if (sc->sc_chan[HSCX_CH_A].state != HSCX_IDLE ||
 986                         sc->sc_chan[HSCX_CH_B].state != HSCX_IDLE)
 987                 {
 988                         return;
 989                 }
 990                 sc->avma1pp_cmd = HSCX_CMD_XRS|HSCX_CMD_RRS;
 991                 sc->avma1pp_prot = HSCX_MODE_TRANS;
 992                 hscx_write_reg(h_chan, HSCX_STAT, sc, 5);
 993                 return;
 994         }
 995         if(chan->bprot == BPROT_RHDLC)
 996         {
 997                   NDBGL1(L1_BCHAN, "BPROT_RHDLC");
 998
 999                 /* HDLC Frames, transparent mode 0 */
1000                 sc->avma1pp_cmd = HSCX_CMD_XRS|HSCX_CMD_RRS;
1001                 sc->avma1pp_prot = HSCX_MODE_ITF_FLG;
1002                 hscx_write_reg(h_chan, HSCX_STAT, sc, 5);
1003                 sc->avma1pp_cmd = HSCX_CMD_XRS;
1004                 hscx_write_reg(h_chan, HSCX_STAT, sc, 1);
1005                 sc->avma1pp_cmd = 0;
1006         }
1007         else
1008         {
1009                   NDBGL1(L1_BCHAN, "BPROT_NONE??");
1010
1011                 /* Raw Telephony, extended transparent mode 1 */
1012                 sc->avma1pp_cmd = HSCX_CMD_XRS|HSCX_CMD_RRS;
1013                 sc->avma1pp_prot = HSCX_MODE_TRANS;
1014                 hscx_write_reg(h_chan, HSCX_STAT, sc, 5);
1015                 sc->avma1pp_cmd = HSCX_CMD_XRS;
1016                 hscx_write_reg(h_chan, HSCX_STAT, sc, 1);
1017                 sc->avma1pp_cmd = 0;
1018         }
1019 }
1020
1021 static void
1022 avm_pnp_bchannel_setup(int unit, int h_chan, int bprot, int activate)
1023 {
1024         struct l1_softc *sc = ifpnp_scp[unit];
1025         l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
1026
1027         crit_enter();
1028
1029         if(activate == 0)
1030         {
1031                 /* deactivation */
1032                 chan->state = HSCX_IDLE;
1033                 avm_pnp_hscx_init(sc, h_chan, activate);
1034         }
1035
1036         NDBGL1(L1_BCHAN, "unit=%d, channel=%d, %s",
1037                 sc->sc_unit, h_chan, activate ? "activate" : "deactivate");
1038
1039         /* general part */
1040
1041         chan->unit = sc->sc_unit;       /* unit number */
1042         chan->channel = h_chan;         /* B channel */
1043         chan->bprot = bprot;            /* B channel protocol */
1044         chan->state = HSCX_IDLE;        /* B channel state */
1045
1046         /* receiver part */
1047
1048         chan->rx_queue.ifq_maxlen = IFQ_MAXLEN;
1049
1050 #if defined (__FreeBSD__) && __FreeBSD__ > 4
1051         mtx_init(&chan->rx_queue.ifq_mtx, "i4b_avm_pnp_rx", MTX_DEF);
1052 #endif
1053
1054         i4b_Bcleanifq(&chan->rx_queue); /* clean rx queue */
1055
1056         chan->rxcount = 0;              /* reset rx counter */
1057
1058         i4b_Bfreembuf(chan->in_mbuf);   /* clean rx mbuf */
1059
1060         chan->in_mbuf = NULL;           /* reset mbuf ptr */
1061         chan->in_cbptr = NULL;          /* reset mbuf curr ptr */
1062         chan->in_len = 0;               /* reset mbuf data len */
1063
1064         /* transmitter part */
1065
1066         chan->tx_queue.ifq_maxlen = IFQ_MAXLEN;
1067
1068 #if defined (__FreeBSD__) && __FreeBSD__ > 4
1069         mtx_init(&chan->tx_queue.ifq_mtx, "i4b_avm_pnp_tx", MTX_DEF);
1070 #endif
1071         i4b_Bcleanifq(&chan->tx_queue); /* clean tx queue */
1072
1073         chan->txcount = 0;              /* reset tx counter */
1074
1075         i4b_Bfreembuf(chan->out_mbuf_head);     /* clean tx mbuf */
1076
1077         chan->out_mbuf_head = NULL;     /* reset head mbuf ptr */
1078         chan->out_mbuf_cur = NULL;      /* reset current mbuf ptr */
1079         chan->out_mbuf_cur_ptr = NULL;  /* reset current mbuf data ptr */
1080         chan->out_mbuf_cur_len = 0;     /* reset current mbuf data cnt */
1081
1082         if(activate != 0)
1083         {
1084                 /* activation */
1085                 avm_pnp_hscx_init(sc, h_chan, activate);
1086                 chan->state |= HSCX_AVMA1PP_ACTIVE;
1087         }
1088
1089         crit_exit();
1090 }
1091
1092 static void
1093 avm_pnp_bchannel_start(int unit, int h_chan)
1094 {
1095         struct l1_softc *sc = ifpnp_scp[unit];
1096         l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
1097         int activity = -1;
1098
1099         crit_enter();
1100         if(chan->state & HSCX_TX_ACTIVE)        /* already running ? */
1101         {
1102                 crit_exit();
1103                 return;                         /* yes, leave */
1104         }
1105
1106         /* get next mbuf from queue */
1107
1108         IF_DEQUEUE(&chan->tx_queue, chan->out_mbuf_head);
1109
1110         if(chan->out_mbuf_head == NULL)         /* queue empty ? */
1111         {
1112                 crit_exit();
1113                 return;                         /* yes, exit */
1114         }
1115
1116         /* init current mbuf values */
1117
1118         chan->out_mbuf_cur = chan->out_mbuf_head;
1119         chan->out_mbuf_cur_len = chan->out_mbuf_cur->m_len;
1120         chan->out_mbuf_cur_ptr = chan->out_mbuf_cur->m_data;
1121
1122         /* activity indicator for timeout handling */
1123
1124         if(chan->bprot == BPROT_NONE)
1125         {
1126                 if(!(i4b_l1_bchan_tel_silence(chan->out_mbuf_cur->m_data, chan->out_mbuf_cur->m_len)))
1127                         activity = ACT_TX;
1128         }
1129         else
1130         {
1131                 activity = ACT_TX;
1132         }
1133
1134         chan->state |= HSCX_TX_ACTIVE;          /* we start transmitting */
1135
1136         if(sc->sc_trace & TRACE_B_TX)   /* if trace, send mbuf to trace dev */
1137         {
1138                 i4b_trace_hdr_t hdr;
1139                 hdr.unit = L0IFPNPUNIT(sc->sc_unit);
1140                 hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
1141                 hdr.dir = FROM_TE;
1142                 hdr.count = ++sc->sc_trace_bcount;
1143                 MICROTIME(hdr.time);
1144                 i4b_l1_trace_ind(&hdr, chan->out_mbuf_cur->m_len, chan->out_mbuf_cur->m_data);
1145         }
1146
1147         avm_pnp_hscx_fifo(chan, sc);
1148
1149         /* call timeout handling routine */
1150
1151         if(activity == ACT_RX || activity == ACT_TX)
1152                 (*chan->isic_drvr_linktab->bch_activity)(chan->isic_drvr_linktab->unit, activity);
1153
1154         crit_exit();
1155 }
1156
1157 /*---------------------------------------------------------------------------*
1158  *      return the address of isic drivers linktab
1159  *---------------------------------------------------------------------------*/
1160 static isdn_link_t *
1161 avm_pnp_ret_linktab(int unit, int channel)
1162 {
1163         struct l1_softc *sc = ifpnp_scp[unit];
1164         l1_bchan_state_t *chan = &sc->sc_chan[channel];
1165
1166         return(&chan->isic_isdn_linktab);
1167 }
1168
1169 /*---------------------------------------------------------------------------*
1170  *      set the driver linktab in the b channel softc
1171  *---------------------------------------------------------------------------*/
1172 static void
1173 avm_pnp_set_linktab(int unit, int channel, drvr_link_t *dlt)
1174 {
1175         struct l1_softc *sc = ifpnp_scp[unit];
1176         l1_bchan_state_t *chan = &sc->sc_chan[channel];
1177
1178         chan->isic_drvr_linktab = dlt;
1179 }
1180
1181
1182 /*---------------------------------------------------------------------------*
1183  *      initialize our local linktab
1184  *---------------------------------------------------------------------------*/
1185 static void
1186 avm_pnp_init_linktab(struct l1_softc *sc)
1187 {
1188         l1_bchan_state_t *chan = &sc->sc_chan[HSCX_CH_A];
1189         isdn_link_t *lt = &chan->isic_isdn_linktab;
1190
1191         /* make sure the hardware driver is known to layer 4 */
1192         /* avoid overwriting if already set */
1193         if (ctrl_types[CTRL_PASSIVE].set_linktab == NULL)
1194         {
1195                 ctrl_types[CTRL_PASSIVE].set_linktab = avm_pnp_set_linktab;
1196                 ctrl_types[CTRL_PASSIVE].get_linktab = avm_pnp_ret_linktab;
1197         }
1198
1199         /* local setup */
1200         lt->unit = sc->sc_unit;
1201         lt->channel = HSCX_CH_A;
1202         lt->bch_config = avm_pnp_bchannel_setup;
1203         lt->bch_tx_start = avm_pnp_bchannel_start;
1204         lt->bch_stat = avm_pnp_bchannel_stat;
1205         lt->tx_queue = &chan->tx_queue;
1206
1207         /* used by non-HDLC data transfers, i.e. telephony drivers */
1208         lt->rx_queue = &chan->rx_queue;
1209
1210         /* used by HDLC data transfers, i.e. ipr and isp drivers */
1211         lt->rx_mbuf = &chan->in_mbuf;
1212
1213         chan = &sc->sc_chan[HSCX_CH_B];
1214         lt = &chan->isic_isdn_linktab;
1215
1216         lt->unit = sc->sc_unit;
1217         lt->channel = HSCX_CH_B;
1218         lt->bch_config = avm_pnp_bchannel_setup;
1219         lt->bch_tx_start = avm_pnp_bchannel_start;
1220         lt->bch_stat = avm_pnp_bchannel_stat;
1221         lt->tx_queue = &chan->tx_queue;
1222
1223         /* used by non-HDLC data transfers, i.e. telephony drivers */
1224         lt->rx_queue = &chan->rx_queue;
1225
1226         /* used by HDLC data transfers, i.e. ipr and isp drivers */
1227         lt->rx_mbuf = &chan->in_mbuf;
1228 }
1229
1230 /*
1231  * use this instead of isic_bchannel_stat in i4b_bchan.c because it's static
1232  */
1233 static void
1234 avm_pnp_bchannel_stat(int unit, int h_chan, bchan_statistics_t *bsp)
1235 {
1236         struct l1_softc *sc = ifpnp_scp[unit];
1237         l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
1238
1239         crit_enter();
1240
1241         bsp->outbytes = chan->txcount;
1242         bsp->inbytes = chan->rxcount;
1243
1244         chan->txcount = 0;
1245         chan->rxcount = 0;
1246
1247         crit_exit();
1248 }
1249
1250 /*---------------------------------------------------------------------------*
1251  *      fill HSCX fifo with data from the current mbuf
1252  *      Put this here until it can go into i4b_hscx.c
1253  *---------------------------------------------------------------------------*/
1254 static int
1255 avm_pnp_hscx_fifo(l1_bchan_state_t *chan, struct l1_softc *sc)
1256 {
1257         int len;
1258         int nextlen;
1259         int i;
1260         int cmd = 0;
1261         /* using a scratch buffer simplifies writing to the FIFO */
1262         u_char scrbuf[HSCX_FIFO_LEN];
1263
1264         len = 0;
1265
1266         /*
1267          * fill the HSCX tx fifo with data from the current mbuf. if
1268          * current mbuf holds less data than HSCX fifo length, try to
1269          * get the next mbuf from (a possible) mbuf chain. if there is
1270          * not enough data in a single mbuf or in a chain, then this
1271          * is the last mbuf and we tell the HSCX that it has to send
1272          * CRC and closing flag
1273          */
1274
1275         while(chan->out_mbuf_cur && len != sc->sc_bfifolen)
1276         {
1277                 nextlen = min(chan->out_mbuf_cur_len, sc->sc_bfifolen - len);
1278
1279 #ifdef NOTDEF
1280                 printf("i:mh=%p, mc=%p, mcp=%p, mcl=%d l=%d nl=%d # ",
1281                         chan->out_mbuf_head,
1282                         chan->out_mbuf_cur,
1283                         chan->out_mbuf_cur_ptr,
1284                         chan->out_mbuf_cur_len,
1285                         len,
1286                         nextlen);
1287 #endif
1288
1289                 cmd |= HSCX_CMDR_XTF;
1290                 /* collect the data in the scratch buffer */
1291                 for (i = 0; i < nextlen; i++)
1292                         scrbuf[i + len] = chan->out_mbuf_cur_ptr[i];
1293
1294                 len += nextlen;
1295                 chan->txcount += nextlen;
1296
1297                 chan->out_mbuf_cur_ptr += nextlen;
1298                 chan->out_mbuf_cur_len -= nextlen;
1299
1300                 if(chan->out_mbuf_cur_len == 0)
1301                 {
1302                         if((chan->out_mbuf_cur = chan->out_mbuf_cur->m_next) != NULL)
1303                         {
1304                                 chan->out_mbuf_cur_ptr = chan->out_mbuf_cur->m_data;
1305                                 chan->out_mbuf_cur_len = chan->out_mbuf_cur->m_len;
1306
1307                                 if(sc->sc_trace & TRACE_B_TX)
1308                                 {
1309                                         i4b_trace_hdr_t hdr;
1310                                         hdr.unit = L0IFPNPUNIT(sc->sc_unit);
1311                                         hdr.type = (chan->channel == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
1312                                         hdr.dir = FROM_TE;
1313                                         hdr.count = ++sc->sc_trace_bcount;
1314                                         MICROTIME(hdr.time);
1315                                         i4b_l1_trace_ind(&hdr, chan->out_mbuf_cur->m_len, chan->out_mbuf_cur->m_data);
1316                                 }
1317                         }
1318                         else
1319                         {
1320                                 if (chan->bprot != BPROT_NONE)
1321                                         cmd |= HSCX_CMDR_XME;
1322                                 i4b_Bfreembuf(chan->out_mbuf_head);
1323                                 chan->out_mbuf_head = NULL;
1324                         }
1325                 }
1326         }
1327         /* write what we have from the scratch buf to the HSCX fifo */
1328         if (len != 0)
1329                 HSCX_WRFIFO(chan->channel, scrbuf, len);
1330         return(cmd);
1331 }
1332
1333 /*---------------------------------------------------------------------------*
1334  *      ifpnp - ISAC interrupt routine
1335  *---------------------------------------------------------------------------*/
1336 static void
1337 ifpnp_isac_intr(struct l1_softc *sc)
1338 {
1339         u_char isac_irq_stat;
1340
1341         for(;;)
1342         {
1343                 /* get isac irq status */
1344                 isac_irq_stat = ISAC_READ(I_ISTA);
1345
1346                 if(isac_irq_stat)
1347                         ifpnp_isac_irq(sc, isac_irq_stat); /* isac handler */
1348                 else
1349                         break;
1350         }
1351
1352         ISAC_WRITE(I_MASK, 0xff);
1353
1354         DELAY(100);
1355
1356         ISAC_WRITE(I_MASK, ISAC_IMASK);
1357 }
1358
1359 /*---------------------------------------------------------------------------*
1360  *      ifpnp_recover - try to recover from irq lockup
1361  *---------------------------------------------------------------------------*/
1362 void
1363 ifpnp_recover(struct l1_softc *sc)
1364 {
1365         u_char byte;
1366
1367         /* get isac irq status */
1368
1369         byte = ISAC_READ(I_ISTA);
1370
1371         NDBGL1(L1_ERROR, "  ISAC: ISTA = 0x%x", byte);
1372
1373         if(byte & ISAC_ISTA_EXI)
1374                 NDBGL1(L1_ERROR, "  ISAC: EXIR = 0x%x", (u_char)ISAC_READ(I_EXIR));
1375
1376         if(byte & ISAC_ISTA_CISQ)
1377         {
1378                 byte = ISAC_READ(I_CIRR);
1379
1380                 NDBGL1(L1_ERROR, "  ISAC: CISQ = 0x%x", byte);
1381
1382                 if(byte & ISAC_CIRR_SQC)
1383                         NDBGL1(L1_ERROR, "  ISAC: SQRR = 0x%x", (u_char)ISAC_READ(I_SQRR));
1384         }
1385
1386         NDBGL1(L1_ERROR, "  ISAC: IMASK = 0x%x", ISAC_IMASK);
1387
1388         ISAC_WRITE(I_MASK, 0xff);
1389         DELAY(100);
1390         ISAC_WRITE(I_MASK, ISAC_IMASK);
1391 }
1392
1393 #endif /* NIFPNP > 0 */