sys/dev/drm/r600_cp.c

   1 /*-
   2  * Copyright 2008-2009 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *     Dave Airlie <airlied@redhat.com>
  26  *     Alex Deucher <alexander.deucher@amd.com>
  27  */
  28
  29 #include "dev/drm/drmP.h"
  30 #include "dev/drm/drm.h"
  31 #include "dev/drm/radeon_drm.h"
  32 #include "dev/drm/radeon_drv.h"
  33
  34 #include "dev/drm/r600_microcode.h"
  35
  36 # define ATI_PCIGART_PAGE_SIZE          4096    /**< PCI GART page size */
  37 # define ATI_PCIGART_PAGE_MASK          (~(ATI_PCIGART_PAGE_SIZE-1))
  38
  39 #define R600_PTE_VALID     (1 << 0)
  40 #define R600_PTE_SYSTEM    (1 << 1)
  41 #define R600_PTE_SNOOPED   (1 << 2)
  42 #define R600_PTE_READABLE  (1 << 5)
  43 #define R600_PTE_WRITEABLE (1 << 6)
  44
  45 /* MAX values used for gfx init */
  46 #define R6XX_MAX_SH_GPRS           256
  47 #define R6XX_MAX_TEMP_GPRS         16
  48 #define R6XX_MAX_SH_THREADS        256
  49 #define R6XX_MAX_SH_STACK_ENTRIES  4096
  50 #define R6XX_MAX_BACKENDS          8
  51 #define R6XX_MAX_BACKENDS_MASK     0xff
  52 #define R6XX_MAX_SIMDS             8
  53 #define R6XX_MAX_SIMDS_MASK        0xff
  54 #define R6XX_MAX_PIPES             8
  55 #define R6XX_MAX_PIPES_MASK        0xff
  56
  57 #define R7XX_MAX_SH_GPRS           256
  58 #define R7XX_MAX_TEMP_GPRS         16
  59 #define R7XX_MAX_SH_THREADS        256
  60 #define R7XX_MAX_SH_STACK_ENTRIES  4096
  61 #define R7XX_MAX_BACKENDS          8
  62 #define R7XX_MAX_BACKENDS_MASK     0xff
  63 #define R7XX_MAX_SIMDS             16
  64 #define R7XX_MAX_SIMDS_MASK        0xffff
  65 #define R7XX_MAX_PIPES             8
  66 #define R7XX_MAX_PIPES_MASK        0xff
  67
  68 static int r600_do_wait_for_fifo(drm_radeon_private_t *dev_priv, int entries)
  69 {
  70         int i;
  71
  72         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
  73
  74         for (i = 0; i < dev_priv->usec_timeout; i++) {
  75                 int slots;
  76                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
  77                         slots = (RADEON_READ(R600_GRBM_STATUS)
  78                                  & R700_CMDFIFO_AVAIL_MASK);
  79                 else
  80                         slots = (RADEON_READ(R600_GRBM_STATUS)
  81                                  & R600_CMDFIFO_AVAIL_MASK);
  82                 if (slots >= entries)
  83                         return 0;
  84                 DRM_UDELAY(1);
  85         }
  86         DRM_INFO("wait for fifo failed status : 0x%08X 0x%08X\n",
  87                  RADEON_READ(R600_GRBM_STATUS),
  88                  RADEON_READ(R600_GRBM_STATUS2));
  89
  90         return -EBUSY;
  91 }
  92
  93 static int r600_do_wait_for_idle(drm_radeon_private_t *dev_priv)
  94 {
  95         int i, ret;
  96
  97         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
  98
  99         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
 100                 ret = r600_do_wait_for_fifo(dev_priv, 8);
 101         else
 102                 ret = r600_do_wait_for_fifo(dev_priv, 16);
 103         if (ret)
 104                 return ret;
 105         for (i = 0; i < dev_priv->usec_timeout; i++) {
 106                 if (!(RADEON_READ(R600_GRBM_STATUS) & R600_GUI_ACTIVE))
 107                         return 0;
 108                 DRM_UDELAY(1);
 109         }
 110         DRM_INFO("wait idle failed status : 0x%08X 0x%08X\n",
 111                  RADEON_READ(R600_GRBM_STATUS),
 112                  RADEON_READ(R600_GRBM_STATUS2));
 113
 114         return -EBUSY;
 115 }
 116
 117 void r600_page_table_cleanup(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info)
 118 {
 119 #ifdef __linux__
 120         struct drm_sg_mem *entry = dev->sg;
 121         int max_pages;
 122         int pages;
 123         int i;
 124 #endif
 125         if (gart_info->bus_addr) {
 126 #ifdef __linux__
 127                 max_pages = (gart_info->table_size / sizeof(u32));
 128                 pages = (entry->pages <= max_pages)
 129                   ? entry->pages : max_pages;
 130
 131                 for (i = 0; i < pages; i++) {
 132                         if (!entry->busaddr[i])
 133                                 break;
 134                         pci_unmap_single(dev->pdev, entry->busaddr[i],
 135                                          PAGE_SIZE, PCI_DMA_TODEVICE);
 136                 }
 137 #endif
 138                 if (gart_info->gart_table_location == DRM_ATI_GART_MAIN)
 139                         gart_info->bus_addr = 0;
 140         }
 141 }
 142
 143 /* R600 has page table setup */
 144 int r600_page_table_init(struct drm_device *dev)
 145 {
 146         drm_radeon_private_t *dev_priv = dev->dev_private;
 147         struct drm_ati_pcigart_info *gart_info = &dev_priv->gart_info;
 148         struct drm_sg_mem *entry = dev->sg;
 149         int ret = 0;
 150         int i, j;
 151         int max_pages, pages;
 152         u64 *pci_gart, page_base;
 153         dma_addr_t entry_addr;
 154
 155         /* okay page table is available - lets rock */
 156
 157         /* PTEs are 64-bits */
 158         pci_gart = (u64 *)gart_info->addr;
 159
 160         max_pages = (gart_info->table_size / sizeof(u64));
 161         pages = (entry->pages <= max_pages) ? entry->pages : max_pages;
 162
 163         memset(pci_gart, 0, max_pages * sizeof(u64));
 164
 165         for (i = 0; i < pages; i++) {
 166 #ifdef __linux__
 167                 entry->busaddr[i] = pci_map_single(dev->pdev,
 168                                                    page_address(entry->
 169                                                                 pagelist[i]),
 170                                                    PAGE_SIZE, PCI_DMA_TODEVICE);
 171                 if (entry->busaddr[i] == 0) {
 172                         DRM_ERROR("unable to map PCIGART pages!\n");
 173                         r600_page_table_cleanup(dev, gart_info);
 174                         goto done;
 175                 }
 176 #endif
 177                 entry_addr = entry->busaddr[i];
 178                 for (j = 0; j < (PAGE_SIZE / ATI_PCIGART_PAGE_SIZE); j++) {
 179                         page_base = (u64) entry_addr & ATI_PCIGART_PAGE_MASK;
 180                         page_base |= R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED;
 181                         page_base |= R600_PTE_READABLE | R600_PTE_WRITEABLE;
 182
 183                         *pci_gart = page_base;
 184
 185                         if ((i % 128) == 0)
 186                                 DRM_DEBUG("page entry %d: 0x%016llx\n",
 187                                     i, (unsigned long long)page_base);
 188                         pci_gart++;
 189                         entry_addr += ATI_PCIGART_PAGE_SIZE;
 190                 }
 191         }
 192         ret = 1;
 193 #ifdef __linux__
 194 done:
 195 #endif
 196         return ret;
 197 }
 198
 199 static void r600_vm_flush_gart_range(struct drm_device *dev)
 200 {
 201         drm_radeon_private_t *dev_priv = dev->dev_private;
 202         u32 resp, countdown = 1000;
 203         RADEON_WRITE(R600_VM_CONTEXT0_INVALIDATION_LOW_ADDR, dev_priv->gart_vm_start >> 12);
 204         RADEON_WRITE(R600_VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
 205         RADEON_WRITE(R600_VM_CONTEXT0_REQUEST_RESPONSE, 2);
 206
 207         do {
 208                 resp = RADEON_READ(R600_VM_CONTEXT0_REQUEST_RESPONSE);
 209                 countdown--;
 210                 DRM_UDELAY(1);
 211         } while (((resp & 0xf0) == 0) && countdown);
 212 }
 213
 214 static void r600_vm_init(struct drm_device *dev)
 215 {
 216         drm_radeon_private_t *dev_priv = dev->dev_private;
 217         /* initialise the VM to use the page table we constructed up there */
 218         u32 vm_c0, i;
 219         u32 mc_rd_a;
 220         u32 vm_l2_cntl, vm_l2_cntl3;
 221         /* okay set up the PCIE aperture type thingo */
 222         RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR, dev_priv->gart_vm_start >> 12);
 223         RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
 224         RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
 225
 226         /* setup MC RD a */
 227         mc_rd_a = R600_MCD_L1_TLB | R600_MCD_L1_FRAG_PROC | R600_MCD_SYSTEM_ACCESS_MODE_IN_SYS |
 228                 R600_MCD_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU | R600_MCD_EFFECTIVE_L1_TLB_SIZE(5) |
 229                 R600_MCD_EFFECTIVE_L1_QUEUE_SIZE(5) | R600_MCD_WAIT_L2_QUERY;
 230
 231         RADEON_WRITE(R600_MCD_RD_A_CNTL, mc_rd_a);
 232         RADEON_WRITE(R600_MCD_RD_B_CNTL, mc_rd_a);
 233
 234         RADEON_WRITE(R600_MCD_WR_A_CNTL, mc_rd_a);
 235         RADEON_WRITE(R600_MCD_WR_B_CNTL, mc_rd_a);
 236
 237         RADEON_WRITE(R600_MCD_RD_GFX_CNTL, mc_rd_a);
 238         RADEON_WRITE(R600_MCD_WR_GFX_CNTL, mc_rd_a);
 239
 240         RADEON_WRITE(R600_MCD_RD_SYS_CNTL, mc_rd_a);
 241         RADEON_WRITE(R600_MCD_WR_SYS_CNTL, mc_rd_a);
 242
 243         RADEON_WRITE(R600_MCD_RD_HDP_CNTL, mc_rd_a | R600_MCD_L1_STRICT_ORDERING);
 244         RADEON_WRITE(R600_MCD_WR_HDP_CNTL, mc_rd_a /*| R600_MCD_L1_STRICT_ORDERING*/);
 245
 246         RADEON_WRITE(R600_MCD_RD_PDMA_CNTL, mc_rd_a);
 247         RADEON_WRITE(R600_MCD_WR_PDMA_CNTL, mc_rd_a);
 248
 249         RADEON_WRITE(R600_MCD_RD_SEM_CNTL, mc_rd_a | R600_MCD_SEMAPHORE_MODE);
 250         RADEON_WRITE(R600_MCD_WR_SEM_CNTL, mc_rd_a);
 251
 252         vm_l2_cntl = R600_VM_L2_CACHE_EN | R600_VM_L2_FRAG_PROC | R600_VM_ENABLE_PTE_CACHE_LRU_W;
 253         vm_l2_cntl |= R600_VM_L2_CNTL_QUEUE_SIZE(7);
 254         RADEON_WRITE(R600_VM_L2_CNTL, vm_l2_cntl);
 255
 256         RADEON_WRITE(R600_VM_L2_CNTL2, 0);
 257         vm_l2_cntl3 = (R600_VM_L2_CNTL3_BANK_SELECT_0(0) |
 258                        R600_VM_L2_CNTL3_BANK_SELECT_1(1) |
 259                        R600_VM_L2_CNTL3_CACHE_UPDATE_MODE(2));
 260         RADEON_WRITE(R600_VM_L2_CNTL3, vm_l2_cntl3);
 261
 262         vm_c0 = R600_VM_ENABLE_CONTEXT | R600_VM_PAGE_TABLE_DEPTH_FLAT;
 263
 264         RADEON_WRITE(R600_VM_CONTEXT0_CNTL, vm_c0);
 265
 266         vm_c0 &= ~R600_VM_ENABLE_CONTEXT;
 267
 268         /* disable all other contexts */
 269         for (i = 1; i < 8; i++)
 270                 RADEON_WRITE(R600_VM_CONTEXT0_CNTL + (i * 4), vm_c0);
 271
 272         RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, dev_priv->gart_info.bus_addr >> 12);
 273         RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_START_ADDR, dev_priv->gart_vm_start >> 12);
 274         RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_END_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
 275
 276         r600_vm_flush_gart_range(dev);
 277 }
 278
 279 /* load r600 microcode */
 280 static void r600_cp_load_microcode(drm_radeon_private_t *dev_priv)
 281 {
 282         const u32 (*cp)[3];
 283         const u32 *pfp;
 284         int i;
 285
 286         r600_do_cp_stop(dev_priv);
 287
 288         RADEON_WRITE(R600_CP_RB_CNTL,
 289                      R600_RB_NO_UPDATE |
 290                      R600_RB_BLKSZ(15) |
 291                      R600_RB_BUFSZ(3));
 292
 293         RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP);
 294         RADEON_READ(R600_GRBM_SOFT_RESET);
 295         DRM_UDELAY(15000);
 296         RADEON_WRITE(R600_GRBM_SOFT_RESET, 0);
 297
 298         RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
 299
 300         switch (dev_priv->flags & RADEON_FAMILY_MASK) {
 301         case CHIP_R600:
 302                 DRM_INFO("Loading R600 Microcode\n");
 303                 cp  = R600_cp_microcode;
 304                 pfp = R600_pfp_microcode;
 305                 break;
 306         case CHIP_RV610:
 307                 DRM_INFO("Loading RV610 Microcode\n");
 308                 cp  = RV610_cp_microcode;
 309                 pfp = RV610_pfp_microcode;
 310                 break;
 311         case CHIP_RV630:
 312                 DRM_INFO("Loading RV630 Microcode\n");
 313                 cp  = RV630_cp_microcode;
 314                 pfp = RV630_pfp_microcode;
 315                 break;
 316         case CHIP_RV620:
 317                 DRM_INFO("Loading RV620 Microcode\n");
 318                 cp  = RV620_cp_microcode;
 319                 pfp = RV620_pfp_microcode;
 320                 break;
 321         case CHIP_RV635:
 322                 DRM_INFO("Loading RV635 Microcode\n");
 323                 cp  = RV635_cp_microcode;
 324                 pfp = RV635_pfp_microcode;
 325                 break;
 326         case CHIP_RV670:
 327                 DRM_INFO("Loading RV670 Microcode\n");
 328                 cp  = RV670_cp_microcode;
 329                 pfp = RV670_pfp_microcode;
 330                 break;
 331         case CHIP_RS780:
 332                 DRM_INFO("Loading RS780 Microcode\n");
 333                 cp  = RS780_cp_microcode;
 334                 pfp = RS780_pfp_microcode;
 335                 break;
 336         default:
 337                 goto no_microcode;
 338         }
 339
 340         for (i = 0; i != PM4_UCODE_SIZE; i++) {
 341                 RADEON_WRITE(R600_CP_ME_RAM_DATA, cp[i][0]);
 342                 RADEON_WRITE(R600_CP_ME_RAM_DATA, cp[i][1]);
 343                 RADEON_WRITE(R600_CP_ME_RAM_DATA, cp[i][2]);
 344         }
 345
 346         RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
 347         for (i = 0; i != PFP_UCODE_SIZE; i++)
 348                 RADEON_WRITE(R600_CP_PFP_UCODE_DATA, pfp[i]);
 349 no_microcode:;
 350
 351         RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
 352         RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
 353         RADEON_WRITE(R600_CP_ME_RAM_RADDR, 0);
 354 }
 355
 356 static void r700_vm_init(struct drm_device *dev)
 357 {
 358         drm_radeon_private_t *dev_priv = dev->dev_private;
 359         /* initialise the VM to use the page table we constructed up there */
 360         u32 vm_c0, i;
 361         u32 mc_vm_md_l1;
 362         u32 vm_l2_cntl, vm_l2_cntl3;
 363         /* okay set up the PCIE aperture type thingo */
 364         RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR, dev_priv->gart_vm_start >> 12);
 365         RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
 366         RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
 367
 368         mc_vm_md_l1 = R700_ENABLE_L1_TLB |
 369             R700_ENABLE_L1_FRAGMENT_PROCESSING |
 370             R700_SYSTEM_ACCESS_MODE_IN_SYS |
 371             R700_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
 372             R700_EFFECTIVE_L1_TLB_SIZE(5) |
 373             R700_EFFECTIVE_L1_QUEUE_SIZE(5);
 374
 375         RADEON_WRITE(R700_MC_VM_MD_L1_TLB0_CNTL, mc_vm_md_l1);
 376         RADEON_WRITE(R700_MC_VM_MD_L1_TLB1_CNTL, mc_vm_md_l1);
 377         RADEON_WRITE(R700_MC_VM_MD_L1_TLB2_CNTL, mc_vm_md_l1);
 378         RADEON_WRITE(R700_MC_VM_MB_L1_TLB0_CNTL, mc_vm_md_l1);
 379         RADEON_WRITE(R700_MC_VM_MB_L1_TLB1_CNTL, mc_vm_md_l1);
 380         RADEON_WRITE(R700_MC_VM_MB_L1_TLB2_CNTL, mc_vm_md_l1);
 381         RADEON_WRITE(R700_MC_VM_MB_L1_TLB3_CNTL, mc_vm_md_l1);
 382
 383         vm_l2_cntl = R600_VM_L2_CACHE_EN | R600_VM_L2_FRAG_PROC | R600_VM_ENABLE_PTE_CACHE_LRU_W;
 384         vm_l2_cntl |= R700_VM_L2_CNTL_QUEUE_SIZE(7);
 385         RADEON_WRITE(R600_VM_L2_CNTL, vm_l2_cntl);
 386
 387         RADEON_WRITE(R600_VM_L2_CNTL2, 0);
 388         vm_l2_cntl3 = R700_VM_L2_CNTL3_BANK_SELECT(0) | R700_VM_L2_CNTL3_CACHE_UPDATE_MODE(2);
 389         RADEON_WRITE(R600_VM_L2_CNTL3, vm_l2_cntl3);
 390
 391         vm_c0 = R600_VM_ENABLE_CONTEXT | R600_VM_PAGE_TABLE_DEPTH_FLAT;
 392
 393         RADEON_WRITE(R600_VM_CONTEXT0_CNTL, vm_c0);
 394
 395         vm_c0 &= ~R600_VM_ENABLE_CONTEXT;
 396
 397         /* disable all other contexts */
 398         for (i = 1; i < 8; i++)
 399                 RADEON_WRITE(R600_VM_CONTEXT0_CNTL + (i * 4), vm_c0);
 400
 401         RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, dev_priv->gart_info.bus_addr >> 12);
 402         RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_START_ADDR, dev_priv->gart_vm_start >> 12);
 403         RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_END_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
 404
 405         r600_vm_flush_gart_range(dev);
 406 }
 407
 408 /* load r600 microcode */
 409 static void r700_cp_load_microcode(drm_radeon_private_t *dev_priv)
 410 {
 411         const u32 *pfp;
 412         const u32 *cp;
 413         int i;
 414
 415         r600_do_cp_stop(dev_priv);
 416
 417         RADEON_WRITE(R600_CP_RB_CNTL,
 418                      R600_RB_NO_UPDATE |
 419                      (15 << 8) |
 420                      (3 << 0));
 421
 422         RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP);
 423         RADEON_READ(R600_GRBM_SOFT_RESET);
 424         DRM_UDELAY(15000);
 425         RADEON_WRITE(R600_GRBM_SOFT_RESET, 0);
 426
 427         switch (dev_priv->flags & RADEON_FAMILY_MASK) {
 428         case CHIP_RV770:
 429                 DRM_INFO("Loading RV770 Microcode\n");
 430                 pfp = RV770_pfp_microcode;
 431                 cp  = RV770_cp_microcode;
 432                 break;
 433         case CHIP_RV730:
 434                 DRM_INFO("Loading RV730 Microcode\n");
 435                 pfp = RV730_pfp_microcode;
 436                 cp  = RV730_cp_microcode;
 437                 break;
 438         case CHIP_RV710:
 439                 DRM_INFO("Loading RV710 Microcode\n");
 440                 pfp = RV710_pfp_microcode;
 441                 cp  = RV710_cp_microcode;
 442                 break;
 443         default:
 444                 goto no_microcode;
 445         }
 446
 447         RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
 448         for (i = 0; i != R700_PFP_UCODE_SIZE; i++)
 449                 RADEON_WRITE(R600_CP_PFP_UCODE_DATA, pfp[i]);
 450         RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
 451
 452         RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
 453         for (i = 0; i != R700_PM4_UCODE_SIZE; i++)
 454                 RADEON_WRITE(R600_CP_ME_RAM_DATA, cp[i]);
 455         RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
 456 no_microcode:;
 457
 458         RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
 459         RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
 460         RADEON_WRITE(R600_CP_ME_RAM_RADDR, 0);
 461 }
 462
 463 static void r600_test_writeback(drm_radeon_private_t *dev_priv)
 464 {
 465         u32 tmp;
 466
 467         /* Start with assuming that writeback doesn't work */
 468         dev_priv->writeback_works = 0;
 469
 470         /* Writeback doesn't seem to work everywhere, test it here and possibly
 471          * enable it if it appears to work
 472          */
 473         radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(1), 0);
 474
 475         RADEON_WRITE(R600_SCRATCH_REG1, 0xdeadbeef);
 476
 477         for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
 478                 u32 val;
 479
 480                 val = radeon_read_ring_rptr(dev_priv, R600_SCRATCHOFF(1));
 481                 if (val == 0xdeadbeef)
 482                         break;
 483                 DRM_UDELAY(1);
 484         }
 485
 486         if (tmp < dev_priv->usec_timeout) {
 487                 dev_priv->writeback_works = 1;
 488                 DRM_INFO("writeback test succeeded in %d usecs\n", tmp);
 489         } else {
 490                 dev_priv->writeback_works = 0;
 491                 DRM_INFO("writeback test failed\n");
 492         }
 493         if (radeon_no_wb == 1) {
 494                 dev_priv->writeback_works = 0;
 495                 DRM_INFO("writeback forced off\n");
 496         }
 497
 498         if (!dev_priv->writeback_works) {
 499                 /* Disable writeback to avoid unnecessary bus master transfer */
 500                 RADEON_WRITE(R600_CP_RB_CNTL, RADEON_READ(R600_CP_RB_CNTL) |
 501                              RADEON_RB_NO_UPDATE);
 502                 RADEON_WRITE(R600_SCRATCH_UMSK, 0);
 503         }
 504 }
 505
 506 int r600_do_engine_reset(struct drm_device *dev)
 507 {
 508         drm_radeon_private_t *dev_priv = dev->dev_private;
 509         u32 cp_ptr, cp_me_cntl, cp_rb_cntl;
 510
 511         DRM_INFO("Resetting GPU\n");
 512
 513         cp_ptr = RADEON_READ(R600_CP_RB_WPTR);
 514         cp_me_cntl = RADEON_READ(R600_CP_ME_CNTL);
 515         RADEON_WRITE(R600_CP_ME_CNTL, R600_CP_ME_HALT);
 516
 517         RADEON_WRITE(R600_GRBM_SOFT_RESET, 0x7fff);
 518         RADEON_READ(R600_GRBM_SOFT_RESET);
 519         DRM_UDELAY(50);
 520         RADEON_WRITE(R600_GRBM_SOFT_RESET, 0);
 521         RADEON_READ(R600_GRBM_SOFT_RESET);
 522
 523         RADEON_WRITE(R600_CP_RB_WPTR_DELAY, 0);
 524         cp_rb_cntl = RADEON_READ(R600_CP_RB_CNTL);
 525         RADEON_WRITE(R600_CP_RB_CNTL, R600_RB_RPTR_WR_ENA);
 526
 527         RADEON_WRITE(R600_CP_RB_RPTR_WR, cp_ptr);
 528         RADEON_WRITE(R600_CP_RB_WPTR, cp_ptr);
 529         RADEON_WRITE(R600_CP_RB_CNTL, cp_rb_cntl);
 530         RADEON_WRITE(R600_CP_ME_CNTL, cp_me_cntl);
 531
 532         /* Reset the CP ring */
 533         r600_do_cp_reset(dev_priv);
 534
 535         /* The CP is no longer running after an engine reset */
 536         dev_priv->cp_running = 0;
 537
 538         /* Reset any pending vertex, indirect buffers */
 539         radeon_freelist_reset(dev);
 540
 541         return 0;
 542
 543 }
 544
 545 static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
 546                                              u32 num_backends,
 547                                              u32 backend_disable_mask)
 548 {
 549         u32 backend_map = 0;
 550         u32 enabled_backends_mask;
 551         u32 enabled_backends_count;
 552         u32 cur_pipe;
 553         u32 swizzle_pipe[R6XX_MAX_PIPES];
 554         u32 cur_backend;
 555         u32 i;
 556
 557         if (num_tile_pipes > R6XX_MAX_PIPES)
 558                 num_tile_pipes = R6XX_MAX_PIPES;
 559         if (num_tile_pipes < 1)
 560                 num_tile_pipes = 1;
 561         if (num_backends > R6XX_MAX_BACKENDS)
 562                 num_backends = R6XX_MAX_BACKENDS;
 563         if (num_backends < 1)
 564                 num_backends = 1;
 565
 566         enabled_backends_mask = 0;
 567         enabled_backends_count = 0;
 568         for (i = 0; i < R6XX_MAX_BACKENDS; ++i) {
 569                 if (((backend_disable_mask >> i) & 1) == 0) {
 570                         enabled_backends_mask |= (1 << i);
 571                         ++enabled_backends_count;
 572                 }
 573                 if (enabled_backends_count == num_backends)
 574                         break;
 575         }
 576
 577         if (enabled_backends_count == 0) {
 578                 enabled_backends_mask = 1;
 579                 enabled_backends_count = 1;
 580         }
 581
 582         if (enabled_backends_count != num_backends)
 583                 num_backends = enabled_backends_count;
 584
 585         memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES);
 586         switch (num_tile_pipes) {
 587         case 1:
 588                 swizzle_pipe[0] = 0;
 589                 break;
 590         case 2:
 591                 swizzle_pipe[0] = 0;
 592                 swizzle_pipe[1] = 1;
 593                 break;
 594         case 3:
 595                 swizzle_pipe[0] = 0;
 596                 swizzle_pipe[1] = 1;
 597                 swizzle_pipe[2] = 2;
 598                 break;
 599         case 4:
 600                 swizzle_pipe[0] = 0;
 601                 swizzle_pipe[1] = 1;
 602                 swizzle_pipe[2] = 2;
 603                 swizzle_pipe[3] = 3;
 604                 break;
 605         case 5:
 606                 swizzle_pipe[0] = 0;
 607                 swizzle_pipe[1] = 1;
 608                 swizzle_pipe[2] = 2;
 609                 swizzle_pipe[3] = 3;
 610                 swizzle_pipe[4] = 4;
 611                 break;
 612         case 6:
 613                 swizzle_pipe[0] = 0;
 614                 swizzle_pipe[1] = 2;
 615                 swizzle_pipe[2] = 4;
 616                 swizzle_pipe[3] = 5;
 617                 swizzle_pipe[4] = 1;
 618                 swizzle_pipe[5] = 3;
 619                 break;
 620         case 7:
 621                 swizzle_pipe[0] = 0;
 622                 swizzle_pipe[1] = 2;
 623                 swizzle_pipe[2] = 4;
 624                 swizzle_pipe[3] = 6;
 625                 swizzle_pipe[4] = 1;
 626                 swizzle_pipe[5] = 3;
 627                 swizzle_pipe[6] = 5;
 628                 break;
 629         case 8:
 630                 swizzle_pipe[0] = 0;
 631                 swizzle_pipe[1] = 2;
 632                 swizzle_pipe[2] = 4;
 633                 swizzle_pipe[3] = 6;
 634                 swizzle_pipe[4] = 1;
 635                 swizzle_pipe[5] = 3;
 636                 swizzle_pipe[6] = 5;
 637                 swizzle_pipe[7] = 7;
 638                 break;
 639         }
 640
 641         cur_backend = 0;
 642         for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
 643                 while (((1 << cur_backend) & enabled_backends_mask) == 0)
 644                         cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
 645
 646                 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
 647
 648                 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
 649         }
 650
 651         return backend_map;
 652 }
 653
 654 static int r600_count_pipe_bits(uint32_t val)
 655 {
 656         int i, ret = 0;
 657         for (i = 0; i < 32; i++) {
 658                 ret += val & 1;
 659                 val >>= 1;
 660         }
 661         return ret;
 662 }
 663
 664 static void r600_gfx_init(struct drm_device *dev,
 665                           drm_radeon_private_t *dev_priv)
 666 {
 667         int i, j, num_qd_pipes;
 668         u32 sx_debug_1;
 669         u32 tc_cntl;
 670         u32 arb_pop;
 671         u32 num_gs_verts_per_thread;
 672         u32 vgt_gs_per_es;
 673         u32 gs_prim_buffer_depth = 0;
 674         u32 sq_ms_fifo_sizes;
 675         u32 sq_config;
 676         u32 sq_gpr_resource_mgmt_1 = 0;
 677         u32 sq_gpr_resource_mgmt_2 = 0;
 678         u32 sq_thread_resource_mgmt = 0;
 679         u32 sq_stack_resource_mgmt_1 = 0;
 680         u32 sq_stack_resource_mgmt_2 = 0;
 681         u32 hdp_host_path_cntl;
 682         u32 backend_map;
 683         u32 gb_tiling_config = 0;
 684         u32 cc_rb_backend_disable = 0;
 685         u32 cc_gc_shader_pipe_config = 0;
 686         u32 ramcfg;
 687
 688         /* setup chip specs */
 689         switch (dev_priv->flags & RADEON_FAMILY_MASK) {
 690         case CHIP_R600:
 691                 dev_priv->r600_max_pipes = 4;
 692                 dev_priv->r600_max_tile_pipes = 8;
 693                 dev_priv->r600_max_simds = 4;
 694                 dev_priv->r600_max_backends = 4;
 695                 dev_priv->r600_max_gprs = 256;
 696                 dev_priv->r600_max_threads = 192;
 697                 dev_priv->r600_max_stack_entries = 256;
 698                 dev_priv->r600_max_hw_contexts = 8;
 699                 dev_priv->r600_max_gs_threads = 16;
 700                 dev_priv->r600_sx_max_export_size = 128;
 701                 dev_priv->r600_sx_max_export_pos_size = 16;
 702                 dev_priv->r600_sx_max_export_smx_size = 128;
 703                 dev_priv->r600_sq_num_cf_insts = 2;
 704                 break;
 705         case CHIP_RV630:
 706         case CHIP_RV635:
 707                 dev_priv->r600_max_pipes = 2;
 708                 dev_priv->r600_max_tile_pipes = 2;
 709                 dev_priv->r600_max_simds = 3;
 710                 dev_priv->r600_max_backends = 1;
 711                 dev_priv->r600_max_gprs = 128;
 712                 dev_priv->r600_max_threads = 192;
 713                 dev_priv->r600_max_stack_entries = 128;
 714                 dev_priv->r600_max_hw_contexts = 8;
 715                 dev_priv->r600_max_gs_threads = 4;
 716                 dev_priv->r600_sx_max_export_size = 128;
 717                 dev_priv->r600_sx_max_export_pos_size = 16;
 718                 dev_priv->r600_sx_max_export_smx_size = 128;
 719                 dev_priv->r600_sq_num_cf_insts = 2;
 720                 break;
 721         case CHIP_RV610:
 722         case CHIP_RS780:
 723         case CHIP_RV620:
 724                 dev_priv->r600_max_pipes = 1;
 725                 dev_priv->r600_max_tile_pipes = 1;
 726                 dev_priv->r600_max_simds = 2;
 727                 dev_priv->r600_max_backends = 1;
 728                 dev_priv->r600_max_gprs = 128;
 729                 dev_priv->r600_max_threads = 192;
 730                 dev_priv->r600_max_stack_entries = 128;
 731                 dev_priv->r600_max_hw_contexts = 4;
 732                 dev_priv->r600_max_gs_threads = 4;
 733                 dev_priv->r600_sx_max_export_size = 128;
 734                 dev_priv->r600_sx_max_export_pos_size = 16;
 735                 dev_priv->r600_sx_max_export_smx_size = 128;
 736                 dev_priv->r600_sq_num_cf_insts = 1;
 737                 break;
 738         case CHIP_RV670:
 739                 dev_priv->r600_max_pipes = 4;
 740                 dev_priv->r600_max_tile_pipes = 4;
 741                 dev_priv->r600_max_simds = 4;
 742                 dev_priv->r600_max_backends = 4;
 743                 dev_priv->r600_max_gprs = 192;
 744                 dev_priv->r600_max_threads = 192;
 745                 dev_priv->r600_max_stack_entries = 256;
 746                 dev_priv->r600_max_hw_contexts = 8;
 747                 dev_priv->r600_max_gs_threads = 16;
 748                 dev_priv->r600_sx_max_export_size = 128;
 749                 dev_priv->r600_sx_max_export_pos_size = 16;
 750                 dev_priv->r600_sx_max_export_smx_size = 128;
 751                 dev_priv->r600_sq_num_cf_insts = 2;
 752                 break;
 753         default:
 754                 break;
 755         }
 756
 757         /* Initialize HDP */
 758         j = 0;
 759         for (i = 0; i < 32; i++) {
 760                 RADEON_WRITE((0x2c14 + j), 0x00000000);
 761                 RADEON_WRITE((0x2c18 + j), 0x00000000);
 762                 RADEON_WRITE((0x2c1c + j), 0x00000000);
 763                 RADEON_WRITE((0x2c20 + j), 0x00000000);
 764                 RADEON_WRITE((0x2c24 + j), 0x00000000);
 765                 j += 0x18;
 766         }
 767
 768         RADEON_WRITE(R600_GRBM_CNTL, R600_GRBM_READ_TIMEOUT(0xff));
 769
 770         /* setup tiling, simd, pipe config */
 771         ramcfg = RADEON_READ(R600_RAMCFG);
 772
 773         switch (dev_priv->r600_max_tile_pipes) {
 774         case 1:
 775                 gb_tiling_config |= R600_PIPE_TILING(0);
 776                 break;
 777         case 2:
 778                 gb_tiling_config |= R600_PIPE_TILING(1);
 779                 break;
 780         case 4:
 781                 gb_tiling_config |= R600_PIPE_TILING(2);
 782                 break;
 783         case 8:
 784                 gb_tiling_config |= R600_PIPE_TILING(3);
 785                 break;
 786         default:
 787                 break;
 788         }
 789
 790         gb_tiling_config |= R600_BANK_TILING((ramcfg >> R600_NOOFBANK_SHIFT) & R600_NOOFBANK_MASK);
 791
 792         gb_tiling_config |= R600_GROUP_SIZE(0);
 793
 794         if (((ramcfg >> R600_NOOFROWS_SHIFT) & R600_NOOFROWS_MASK) > 3) {
 795                 gb_tiling_config |= R600_ROW_TILING(3);
 796                 gb_tiling_config |= R600_SAMPLE_SPLIT(3);
 797         } else {
 798                 gb_tiling_config |=
 799                         R600_ROW_TILING(((ramcfg >> R600_NOOFROWS_SHIFT) & R600_NOOFROWS_MASK));
 800                 gb_tiling_config |=
 801                         R600_SAMPLE_SPLIT(((ramcfg >> R600_NOOFROWS_SHIFT) & R600_NOOFROWS_MASK));
 802         }
 803
 804         gb_tiling_config |= R600_BANK_SWAPS(1);
 805
 806         backend_map = r600_get_tile_pipe_to_backend_map(dev_priv->r600_max_tile_pipes,
 807                                                         dev_priv->r600_max_backends,
 808                                                         (0xff << dev_priv->r600_max_backends) & 0xff);
 809         gb_tiling_config |= R600_BACKEND_MAP(backend_map);
 810
 811         cc_gc_shader_pipe_config =
 812                 R600_INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << dev_priv->r600_max_pipes) & R6XX_MAX_PIPES_MASK);
 813         cc_gc_shader_pipe_config |=
 814                 R600_INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << dev_priv->r600_max_simds) & R6XX_MAX_SIMDS_MASK);
 815
 816         cc_rb_backend_disable =
 817                 R600_BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << dev_priv->r600_max_backends) & R6XX_MAX_BACKENDS_MASK);
 818
 819         RADEON_WRITE(R600_GB_TILING_CONFIG,      gb_tiling_config);
 820         RADEON_WRITE(R600_DCP_TILING_CONFIG,    (gb_tiling_config & 0xffff));
 821         RADEON_WRITE(R600_HDP_TILING_CONFIG,    (gb_tiling_config & 0xffff));
 822
 823         RADEON_WRITE(R600_CC_RB_BACKEND_DISABLE,      cc_rb_backend_disable);
 824         RADEON_WRITE(R600_CC_GC_SHADER_PIPE_CONFIG,   cc_gc_shader_pipe_config);
 825         RADEON_WRITE(R600_GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
 826
 827         num_qd_pipes =
 828                 R6XX_MAX_BACKENDS - r600_count_pipe_bits(cc_gc_shader_pipe_config & R600_INACTIVE_QD_PIPES_MASK);
 829         RADEON_WRITE(R600_VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & R600_DEALLOC_DIST_MASK);
 830         RADEON_WRITE(R600_VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & R600_VTX_REUSE_DEPTH_MASK);
 831
 832         /* set HW defaults for 3D engine */
 833         RADEON_WRITE(R600_CP_QUEUE_THRESHOLDS, (R600_ROQ_IB1_START(0x16) |
 834                                                 R600_ROQ_IB2_START(0x2b)));
 835
 836         RADEON_WRITE(R600_CP_MEQ_THRESHOLDS, (R600_MEQ_END(0x40) |
 837                                               R600_ROQ_END(0x40)));
 838
 839         RADEON_WRITE(R600_TA_CNTL_AUX, (R600_DISABLE_CUBE_ANISO |
 840                                         R600_SYNC_GRADIENT |
 841                                         R600_SYNC_WALKER |
 842                                         R600_SYNC_ALIGNER));
 843
 844         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV670)
 845                 RADEON_WRITE(R600_ARB_GDEC_RD_CNTL, 0x00000021);
 846
 847         sx_debug_1 = RADEON_READ(R600_SX_DEBUG_1);
 848         sx_debug_1 |= R600_SMX_EVENT_RELEASE;
 849         if (((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_R600))
 850                 sx_debug_1 |= R600_ENABLE_NEW_SMX_ADDRESS;
 851         RADEON_WRITE(R600_SX_DEBUG_1, sx_debug_1);
 852
 853         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) ||
 854             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630) ||
 855             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
 856             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
 857             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780))
 858                 RADEON_WRITE(R600_DB_DEBUG, R600_PREZ_MUST_WAIT_FOR_POSTZ_DONE);
 859         else
 860                 RADEON_WRITE(R600_DB_DEBUG, 0);
 861
 862         RADEON_WRITE(R600_DB_WATERMARKS, (R600_DEPTH_FREE(4) |
 863                                           R600_DEPTH_FLUSH(16) |
 864                                           R600_DEPTH_PENDING_FREE(4) |
 865                                           R600_DEPTH_CACHELINE_FREE(16)));
 866         RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0);
 867         RADEON_WRITE(R600_VGT_NUM_INSTANCES, 0);
 868
 869         RADEON_WRITE(R600_SPI_CONFIG_CNTL, R600_GPR_WRITE_PRIORITY(0));
 870         RADEON_WRITE(R600_SPI_CONFIG_CNTL_1, R600_VTX_DONE_DELAY(0));
 871
 872         sq_ms_fifo_sizes = RADEON_READ(R600_SQ_MS_FIFO_SIZES);
 873         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
 874             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
 875             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780)) {
 876                 sq_ms_fifo_sizes = (R600_CACHE_FIFO_SIZE(0xa) |
 877                                     R600_FETCH_FIFO_HIWATER(0xa) |
 878                                     R600_DONE_FIFO_HIWATER(0xe0) |
 879                                     R600_ALU_UPDATE_FIFO_HIWATER(0x8));
 880         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) ||
 881                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630)) {
 882                 sq_ms_fifo_sizes &= ~R600_DONE_FIFO_HIWATER(0xff);
 883                 sq_ms_fifo_sizes |= R600_DONE_FIFO_HIWATER(0x4);
 884         }
 885         RADEON_WRITE(R600_SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes);
 886
 887         /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
 888          * should be adjusted as needed by the 2D/3D drivers.  This just sets default values
 889          */
 890         sq_config = RADEON_READ(R600_SQ_CONFIG);
 891         sq_config &= ~(R600_PS_PRIO(3) |
 892                        R600_VS_PRIO(3) |
 893                        R600_GS_PRIO(3) |
 894                        R600_ES_PRIO(3));
 895         sq_config |= (R600_DX9_CONSTS |
 896                       R600_VC_ENABLE |
 897                       R600_PS_PRIO(0) |
 898                       R600_VS_PRIO(1) |
 899                       R600_GS_PRIO(2) |
 900                       R600_ES_PRIO(3));
 901
 902         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) {
 903                 sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(124) |
 904                                           R600_NUM_VS_GPRS(124) |
 905                                           R600_NUM_CLAUSE_TEMP_GPRS(4));
 906                 sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(0) |
 907                                           R600_NUM_ES_GPRS(0));
 908                 sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(136) |
 909                                            R600_NUM_VS_THREADS(48) |
 910                                            R600_NUM_GS_THREADS(4) |
 911                                            R600_NUM_ES_THREADS(4));
 912                 sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(128) |
 913                                             R600_NUM_VS_STACK_ENTRIES(128));
 914                 sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(0) |
 915                                             R600_NUM_ES_STACK_ENTRIES(0));
 916         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
 917                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
 918                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780)) {
 919                 /* no vertex cache */
 920                 sq_config &= ~R600_VC_ENABLE;
 921
 922                 sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(44) |
 923                                           R600_NUM_VS_GPRS(44) |
 924                                           R600_NUM_CLAUSE_TEMP_GPRS(2));
 925                 sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(17) |
 926                                           R600_NUM_ES_GPRS(17));
 927                 sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(79) |
 928                                            R600_NUM_VS_THREADS(78) |
 929                                            R600_NUM_GS_THREADS(4) |
 930                                            R600_NUM_ES_THREADS(31));
 931                 sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(40) |
 932                                             R600_NUM_VS_STACK_ENTRIES(40));
 933                 sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(32) |
 934                                             R600_NUM_ES_STACK_ENTRIES(16));
 935         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630) ||
 936                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV635)) {
 937                 sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(44) |
 938                                           R600_NUM_VS_GPRS(44) |
 939                                           R600_NUM_CLAUSE_TEMP_GPRS(2));
 940                 sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(18) |
 941                                           R600_NUM_ES_GPRS(18));
 942                 sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(79) |
 943                                            R600_NUM_VS_THREADS(78) |
 944                                            R600_NUM_GS_THREADS(4) |
 945                                            R600_NUM_ES_THREADS(31));
 946                 sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(40) |
 947                                             R600_NUM_VS_STACK_ENTRIES(40));
 948                 sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(32) |
 949                                             R600_NUM_ES_STACK_ENTRIES(16));
 950         } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV670) {
 951                 sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(44) |
 952                                           R600_NUM_VS_GPRS(44) |
 953                                           R600_NUM_CLAUSE_TEMP_GPRS(2));
 954                 sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(17) |
 955                                           R600_NUM_ES_GPRS(17));
 956                 sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(79) |
 957                                            R600_NUM_VS_THREADS(78) |
 958                                            R600_NUM_GS_THREADS(4) |
 959                                            R600_NUM_ES_THREADS(31));
 960                 sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(64) |
 961                                             R600_NUM_VS_STACK_ENTRIES(64));
 962                 sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(64) |
 963                                             R600_NUM_ES_STACK_ENTRIES(64));
 964         }
 965
 966         RADEON_WRITE(R600_SQ_CONFIG, sq_config);
 967         RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_1,  sq_gpr_resource_mgmt_1);
 968         RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_2,  sq_gpr_resource_mgmt_2);
 969         RADEON_WRITE(R600_SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
 970         RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
 971         RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
 972
 973         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
 974             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
 975             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780))
 976                 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, R600_CACHE_INVALIDATION(R600_TC_ONLY));
 977         else
 978                 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, R600_CACHE_INVALIDATION(R600_VC_AND_TC));
 979
 980         RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_2S, (R600_S0_X(0xc) |
 981                                                     R600_S0_Y(0x4) |
 982                                                     R600_S1_X(0x4) |
 983                                                     R600_S1_Y(0xc)));
 984         RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_4S, (R600_S0_X(0xe) |
 985                                                     R600_S0_Y(0xe) |
 986                                                     R600_S1_X(0x2) |
 987                                                     R600_S1_Y(0x2) |
 988                                                     R600_S2_X(0xa) |
 989                                                     R600_S2_Y(0x6) |
 990                                                     R600_S3_X(0x6) |
 991                                                     R600_S3_Y(0xa)));
 992         RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_8S_WD0, (R600_S0_X(0xe) |
 993                                                         R600_S0_Y(0xb) |
 994                                                         R600_S1_X(0x4) |
 995                                                         R600_S1_Y(0xc) |
 996                                                         R600_S2_X(0x1) |
 997                                                         R600_S2_Y(0x6) |
 998                                                         R600_S3_X(0xa) |
 999                                                         R600_S3_Y(0xe)));
1000         RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_8S_WD1, (R600_S4_X(0x6) |
1001                                                         R600_S4_Y(0x1) |
1002                                                         R600_S5_X(0x0) |
1003                                                         R600_S5_Y(0x0) |
1004                                                         R600_S6_X(0xb) |
1005                                                         R600_S6_Y(0x4) |
1006                                                         R600_S7_X(0x7) |
1007                                                         R600_S7_Y(0x8)));
1008
1009
1010         switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1011         case CHIP_R600:
1012         case CHIP_RV630:
1013         case CHIP_RV635:
1014                 gs_prim_buffer_depth = 0;
1015                 break;
1016         case CHIP_RV610:
1017         case CHIP_RS780:
1018         case CHIP_RV620:
1019                 gs_prim_buffer_depth = 32;
1020                 break;
1021         case CHIP_RV670:
1022                 gs_prim_buffer_depth = 128;
1023                 break;
1024         default:
1025                 break;
1026         }
1027
1028         num_gs_verts_per_thread = dev_priv->r600_max_pipes * 16;
1029         vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread;
1030         /* Max value for this is 256 */
1031         if (vgt_gs_per_es > 256)
1032                 vgt_gs_per_es = 256;
1033
1034         RADEON_WRITE(R600_VGT_ES_PER_GS, 128);
1035         RADEON_WRITE(R600_VGT_GS_PER_ES, vgt_gs_per_es);
1036         RADEON_WRITE(R600_VGT_GS_PER_VS, 2);
1037         RADEON_WRITE(R600_VGT_GS_VERTEX_REUSE, 16);
1038
1039         /* more default values. 2D/3D driver should adjust as needed */
1040         RADEON_WRITE(R600_PA_SC_LINE_STIPPLE_STATE, 0);
1041         RADEON_WRITE(R600_VGT_STRMOUT_EN, 0);
1042         RADEON_WRITE(R600_SX_MISC, 0);
1043         RADEON_WRITE(R600_PA_SC_MODE_CNTL, 0);
1044         RADEON_WRITE(R600_PA_SC_AA_CONFIG, 0);
1045         RADEON_WRITE(R600_PA_SC_LINE_STIPPLE, 0);
1046         RADEON_WRITE(R600_SPI_INPUT_Z, 0);
1047         RADEON_WRITE(R600_SPI_PS_IN_CONTROL_0, R600_NUM_INTERP(2));
1048         RADEON_WRITE(R600_CB_COLOR7_FRAG, 0);
1049
1050         /* clear render buffer base addresses */
1051         RADEON_WRITE(R600_CB_COLOR0_BASE, 0);
1052         RADEON_WRITE(R600_CB_COLOR1_BASE, 0);
1053         RADEON_WRITE(R600_CB_COLOR2_BASE, 0);
1054         RADEON_WRITE(R600_CB_COLOR3_BASE, 0);
1055         RADEON_WRITE(R600_CB_COLOR4_BASE, 0);
1056         RADEON_WRITE(R600_CB_COLOR5_BASE, 0);
1057         RADEON_WRITE(R600_CB_COLOR6_BASE, 0);
1058         RADEON_WRITE(R600_CB_COLOR7_BASE, 0);
1059
1060         switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1061         case CHIP_RV610:
1062         case CHIP_RS780:
1063         case CHIP_RV620:
1064                 tc_cntl = R600_TC_L2_SIZE(8);
1065                 break;
1066         case CHIP_RV630:
1067         case CHIP_RV635:
1068                 tc_cntl = R600_TC_L2_SIZE(4);
1069                 break;
1070         case CHIP_R600:
1071                 tc_cntl = R600_TC_L2_SIZE(0) | R600_L2_DISABLE_LATE_HIT;
1072                 break;
1073         default:
1074                 tc_cntl = R600_TC_L2_SIZE(0);
1075                 break;
1076         }
1077
1078         RADEON_WRITE(R600_TC_CNTL, tc_cntl);
1079
1080         hdp_host_path_cntl = RADEON_READ(R600_HDP_HOST_PATH_CNTL);
1081         RADEON_WRITE(R600_HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1082
1083         arb_pop = RADEON_READ(R600_ARB_POP);
1084         arb_pop |= R600_ENABLE_TC128;
1085         RADEON_WRITE(R600_ARB_POP, arb_pop);
1086
1087         RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0);
1088         RADEON_WRITE(R600_PA_CL_ENHANCE, (R600_CLIP_VTX_REORDER_ENA |
1089                                           R600_NUM_CLIP_SEQ(3)));
1090         RADEON_WRITE(R600_PA_SC_ENHANCE, R600_FORCE_EOV_MAX_CLK_CNT(4095));
1091
1092 }
1093
1094 static u32 r700_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
1095                                              u32 num_backends,
1096                                              u32 backend_disable_mask)
1097 {
1098         u32 backend_map = 0;
1099         u32 enabled_backends_mask;
1100         u32 enabled_backends_count;
1101         u32 cur_pipe;
1102         u32 swizzle_pipe[R7XX_MAX_PIPES];
1103         u32 cur_backend;
1104         u32 i;
1105
1106         if (num_tile_pipes > R7XX_MAX_PIPES)
1107                 num_tile_pipes = R7XX_MAX_PIPES;
1108         if (num_tile_pipes < 1)
1109                 num_tile_pipes = 1;
1110         if (num_backends > R7XX_MAX_BACKENDS)
1111                 num_backends = R7XX_MAX_BACKENDS;
1112         if (num_backends < 1)
1113                 num_backends = 1;
1114
1115         enabled_backends_mask = 0;
1116         enabled_backends_count = 0;
1117         for (i = 0; i < R7XX_MAX_BACKENDS; ++i) {
1118                 if (((backend_disable_mask >> i) & 1) == 0) {
1119                         enabled_backends_mask |= (1 << i);
1120                         ++enabled_backends_count;
1121                 }
1122                 if (enabled_backends_count == num_backends)
1123                         break;
1124         }
1125
1126         if (enabled_backends_count == 0) {
1127                 enabled_backends_mask = 1;
1128                 enabled_backends_count = 1;
1129         }
1130
1131         if (enabled_backends_count != num_backends)
1132                 num_backends = enabled_backends_count;
1133
1134         memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R7XX_MAX_PIPES);
1135         switch (num_tile_pipes) {
1136         case 1:
1137                 swizzle_pipe[0] = 0;
1138                 break;
1139         case 2:
1140                 swizzle_pipe[0] = 0;
1141                 swizzle_pipe[1] = 1;
1142                 break;
1143         case 3:
1144                 swizzle_pipe[0] = 0;
1145                 swizzle_pipe[1] = 2;
1146                 swizzle_pipe[2] = 1;
1147                 break;
1148         case 4:
1149                 swizzle_pipe[0] = 0;
1150                 swizzle_pipe[1] = 2;
1151                 swizzle_pipe[2] = 3;
1152                 swizzle_pipe[3] = 1;
1153                 break;
1154         case 5:
1155                 swizzle_pipe[0] = 0;
1156                 swizzle_pipe[1] = 2;
1157                 swizzle_pipe[2] = 4;
1158                 swizzle_pipe[3] = 1;
1159                 swizzle_pipe[4] = 3;
1160                 break;
1161         case 6:
1162                 swizzle_pipe[0] = 0;
1163                 swizzle_pipe[1] = 2;
1164                 swizzle_pipe[2] = 4;
1165                 swizzle_pipe[3] = 5;
1166                 swizzle_pipe[4] = 3;
1167                 swizzle_pipe[5] = 1;
1168                 break;
1169         case 7:
1170                 swizzle_pipe[0] = 0;
1171                 swizzle_pipe[1] = 2;
1172                 swizzle_pipe[2] = 4;
1173                 swizzle_pipe[3] = 6;
1174                 swizzle_pipe[4] = 3;
1175                 swizzle_pipe[5] = 1;
1176                 swizzle_pipe[6] = 5;
1177                 break;
1178         case 8:
1179                 swizzle_pipe[0] = 0;
1180                 swizzle_pipe[1] = 2;
1181                 swizzle_pipe[2] = 4;
1182                 swizzle_pipe[3] = 6;
1183                 swizzle_pipe[4] = 3;
1184                 swizzle_pipe[5] = 1;
1185                 swizzle_pipe[6] = 7;
1186                 swizzle_pipe[7] = 5;
1187                 break;
1188         }
1189
1190         cur_backend = 0;
1191         for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
1192                 while (((1 << cur_backend) & enabled_backends_mask) == 0)
1193                         cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
1194
1195                 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
1196
1197                 cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
1198         }
1199
1200         return backend_map;
1201 }
1202
1203 static void r700_gfx_init(struct drm_device *dev,
1204                           drm_radeon_private_t *dev_priv)
1205 {
1206         int i, j, num_qd_pipes;
1207         u32 sx_debug_1;
1208         u32 smx_dc_ctl0;
1209         u32 num_gs_verts_per_thread;
1210         u32 vgt_gs_per_es;
1211         u32 gs_prim_buffer_depth = 0;
1212         u32 sq_ms_fifo_sizes;
1213         u32 sq_config;
1214         u32 sq_thread_resource_mgmt;
1215         u32 hdp_host_path_cntl;
1216         u32 sq_dyn_gpr_size_simd_ab_0;
1217         u32 backend_map;
1218         u32 gb_tiling_config = 0;
1219         u32 cc_rb_backend_disable = 0;
1220         u32 cc_gc_shader_pipe_config = 0;
1221         u32 mc_arb_ramcfg;
1222         u32 db_debug4;
1223
1224         /* setup chip specs */
1225         switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1226         case CHIP_RV770:
1227                 dev_priv->r600_max_pipes = 4;
1228                 dev_priv->r600_max_tile_pipes = 8;
1229                 dev_priv->r600_max_simds = 10;
1230                 dev_priv->r600_max_backends = 4;
1231                 dev_priv->r600_max_gprs = 256;
1232                 dev_priv->r600_max_threads = 248;
1233                 dev_priv->r600_max_stack_entries = 512;
1234                 dev_priv->r600_max_hw_contexts = 8;
1235                 dev_priv->r600_max_gs_threads = 16 * 2;
1236                 dev_priv->r600_sx_max_export_size = 128;
1237                 dev_priv->r600_sx_max_export_pos_size = 16;
1238                 dev_priv->r600_sx_max_export_smx_size = 112;
1239                 dev_priv->r600_sq_num_cf_insts = 2;
1240
1241                 dev_priv->r700_sx_num_of_sets = 7;
1242                 dev_priv->r700_sc_prim_fifo_size = 0xF9;
1243                 dev_priv->r700_sc_hiz_tile_fifo_size = 0x30;
1244                 dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130;
1245                 break;
1246         case CHIP_RV730:
1247                 dev_priv->r600_max_pipes = 2;
1248                 dev_priv->r600_max_tile_pipes = 4;
1249                 dev_priv->r600_max_simds = 8;
1250                 dev_priv->r600_max_backends = 2;
1251                 dev_priv->r600_max_gprs = 128;
1252                 dev_priv->r600_max_threads = 248;
1253                 dev_priv->r600_max_stack_entries = 256;
1254                 dev_priv->r600_max_hw_contexts = 8;
1255                 dev_priv->r600_max_gs_threads = 16 * 2;
1256                 dev_priv->r600_sx_max_export_size = 256;
1257                 dev_priv->r600_sx_max_export_pos_size = 32;
1258                 dev_priv->r600_sx_max_export_smx_size = 224;
1259                 dev_priv->r600_sq_num_cf_insts = 2;
1260
1261                 dev_priv->r700_sx_num_of_sets = 7;
1262                 dev_priv->r700_sc_prim_fifo_size = 0xf9;
1263                 dev_priv->r700_sc_hiz_tile_fifo_size = 0x30;
1264                 dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130;
1265                 break;
1266         case CHIP_RV710:
1267                 dev_priv->r600_max_pipes = 2;
1268                 dev_priv->r600_max_tile_pipes = 2;
1269                 dev_priv->r600_max_simds = 2;
1270                 dev_priv->r600_max_backends = 1;
1271                 dev_priv->r600_max_gprs = 256;
1272                 dev_priv->r600_max_threads = 192;
1273                 dev_priv->r600_max_stack_entries = 256;
1274                 dev_priv->r600_max_hw_contexts = 4;
1275                 dev_priv->r600_max_gs_threads = 8 * 2;
1276                 dev_priv->r600_sx_max_export_size = 128;
1277                 dev_priv->r600_sx_max_export_pos_size = 16;
1278                 dev_priv->r600_sx_max_export_smx_size = 112;
1279                 dev_priv->r600_sq_num_cf_insts = 1;
1280
1281                 dev_priv->r700_sx_num_of_sets = 7;
1282                 dev_priv->r700_sc_prim_fifo_size = 0x40;
1283                 dev_priv->r700_sc_hiz_tile_fifo_size = 0x30;
1284                 dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130;
1285                 break;
1286         default:
1287                 break;
1288         }
1289
1290         /* Initialize HDP */
1291         j = 0;
1292         for (i = 0; i < 32; i++) {
1293                 RADEON_WRITE((0x2c14 + j), 0x00000000);
1294                 RADEON_WRITE((0x2c18 + j), 0x00000000);
1295                 RADEON_WRITE((0x2c1c + j), 0x00000000);
1296                 RADEON_WRITE((0x2c20 + j), 0x00000000);
1297                 RADEON_WRITE((0x2c24 + j), 0x00000000);
1298                 j += 0x18;
1299         }
1300
1301         RADEON_WRITE(R600_GRBM_CNTL, R600_GRBM_READ_TIMEOUT(0xff));
1302
1303         /* setup tiling, simd, pipe config */
1304         mc_arb_ramcfg = RADEON_READ(R700_MC_ARB_RAMCFG);
1305
1306         switch (dev_priv->r600_max_tile_pipes) {
1307         case 1:
1308                 gb_tiling_config |= R600_PIPE_TILING(0);
1309                 break;
1310         case 2:
1311                 gb_tiling_config |= R600_PIPE_TILING(1);
1312                 break;
1313         case 4:
1314                 gb_tiling_config |= R600_PIPE_TILING(2);
1315                 break;
1316         case 8:
1317                 gb_tiling_config |= R600_PIPE_TILING(3);
1318                 break;
1319         default:
1320                 break;
1321         }
1322
1323         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV770)
1324                 gb_tiling_config |= R600_BANK_TILING(1);
1325         else
1326                 gb_tiling_config |= R600_BANK_TILING((mc_arb_ramcfg >> R700_NOOFBANK_SHIFT) & R700_NOOFBANK_MASK);
1327
1328         gb_tiling_config |= R600_GROUP_SIZE(0);
1329
1330         if (((mc_arb_ramcfg >> R700_NOOFROWS_SHIFT) & R700_NOOFROWS_MASK) > 3) {
1331                 gb_tiling_config |= R600_ROW_TILING(3);
1332                 gb_tiling_config |= R600_SAMPLE_SPLIT(3);
1333         } else {
1334                 gb_tiling_config |=
1335                         R600_ROW_TILING(((mc_arb_ramcfg >> R700_NOOFROWS_SHIFT) & R700_NOOFROWS_MASK));
1336                 gb_tiling_config |=
1337                         R600_SAMPLE_SPLIT(((mc_arb_ramcfg >> R700_NOOFROWS_SHIFT) & R700_NOOFROWS_MASK));
1338         }
1339
1340         gb_tiling_config |= R600_BANK_SWAPS(1);
1341
1342         backend_map = r700_get_tile_pipe_to_backend_map(dev_priv->r600_max_tile_pipes,
1343                                                         dev_priv->r600_max_backends,
1344                                                         (0xff << dev_priv->r600_max_backends) & 0xff);
1345         gb_tiling_config |= R600_BACKEND_MAP(backend_map);
1346
1347         cc_gc_shader_pipe_config =
1348                 R600_INACTIVE_QD_PIPES((R7XX_MAX_PIPES_MASK << dev_priv->r600_max_pipes) & R7XX_MAX_PIPES_MASK);
1349         cc_gc_shader_pipe_config |=
1350                 R600_INACTIVE_SIMDS((R7XX_MAX_SIMDS_MASK << dev_priv->r600_max_simds) & R7XX_MAX_SIMDS_MASK);
1351
1352         cc_rb_backend_disable =
1353                 R600_BACKEND_DISABLE((R7XX_MAX_BACKENDS_MASK << dev_priv->r600_max_backends) & R7XX_MAX_BACKENDS_MASK);
1354
1355         RADEON_WRITE(R600_GB_TILING_CONFIG,      gb_tiling_config);
1356         RADEON_WRITE(R600_DCP_TILING_CONFIG,    (gb_tiling_config & 0xffff));
1357         RADEON_WRITE(R600_HDP_TILING_CONFIG,    (gb_tiling_config & 0xffff));
1358
1359         RADEON_WRITE(R600_CC_RB_BACKEND_DISABLE,      cc_rb_backend_disable);
1360         RADEON_WRITE(R600_CC_GC_SHADER_PIPE_CONFIG,   cc_gc_shader_pipe_config);
1361         RADEON_WRITE(R600_GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
1362
1363         RADEON_WRITE(R700_CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable);
1364         RADEON_WRITE(R700_CGTS_SYS_TCC_DISABLE, 0);
1365         RADEON_WRITE(R700_CGTS_TCC_DISABLE, 0);
1366         RADEON_WRITE(R700_CGTS_USER_SYS_TCC_DISABLE, 0);
1367         RADEON_WRITE(R700_CGTS_USER_TCC_DISABLE, 0);
1368
1369         num_qd_pipes =
1370                 R7XX_MAX_BACKENDS - r600_count_pipe_bits(cc_gc_shader_pipe_config & R600_INACTIVE_QD_PIPES_MASK);
1371         RADEON_WRITE(R600_VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & R600_DEALLOC_DIST_MASK);
1372         RADEON_WRITE(R600_VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & R600_VTX_REUSE_DEPTH_MASK);
1373
1374         /* set HW defaults for 3D engine */
1375         RADEON_WRITE(R600_CP_QUEUE_THRESHOLDS, (R600_ROQ_IB1_START(0x16) |
1376                                                 R600_ROQ_IB2_START(0x2b)));
1377
1378         RADEON_WRITE(R600_CP_MEQ_THRESHOLDS, R700_STQ_SPLIT(0x30));
1379
1380         RADEON_WRITE(R600_TA_CNTL_AUX, (R600_DISABLE_CUBE_ANISO |
1381                                         R600_SYNC_GRADIENT |
1382                                         R600_SYNC_WALKER |
1383                                         R600_SYNC_ALIGNER));
1384
1385         sx_debug_1 = RADEON_READ(R700_SX_DEBUG_1);
1386         sx_debug_1 |= R700_ENABLE_NEW_SMX_ADDRESS;
1387         RADEON_WRITE(R700_SX_DEBUG_1, sx_debug_1);
1388
1389         smx_dc_ctl0 = RADEON_READ(R600_SMX_DC_CTL0);
1390         smx_dc_ctl0 &= ~R700_CACHE_DEPTH(0x1ff);
1391         smx_dc_ctl0 |= R700_CACHE_DEPTH((dev_priv->r700_sx_num_of_sets * 64) - 1);
1392         RADEON_WRITE(R600_SMX_DC_CTL0, smx_dc_ctl0);
1393
1394         RADEON_WRITE(R700_SMX_EVENT_CTL, (R700_ES_FLUSH_CTL(4) |
1395                                           R700_GS_FLUSH_CTL(4) |
1396                                           R700_ACK_FLUSH_CTL(3) |
1397                                           R700_SYNC_FLUSH_CTL));
1398
1399         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV770)
1400                 RADEON_WRITE(R700_DB_DEBUG3, R700_DB_CLK_OFF_DELAY(0x1f));
1401         else {
1402                 db_debug4 = RADEON_READ(RV700_DB_DEBUG4);
1403                 db_debug4 |= RV700_DISABLE_TILE_COVERED_FOR_PS_ITER;
1404                 RADEON_WRITE(RV700_DB_DEBUG4, db_debug4);
1405         }
1406
1407         RADEON_WRITE(R600_SX_EXPORT_BUFFER_SIZES, (R600_COLOR_BUFFER_SIZE((dev_priv->r600_sx_max_export_size / 4) - 1) |
1408                                                    R600_POSITION_BUFFER_SIZE((dev_priv->r600_sx_max_export_pos_size / 4) - 1) |
1409                                                    R600_SMX_BUFFER_SIZE((dev_priv->r600_sx_max_export_smx_size / 4) - 1)));
1410
1411         RADEON_WRITE(R700_PA_SC_FIFO_SIZE_R7XX, (R700_SC_PRIM_FIFO_SIZE(dev_priv->r700_sc_prim_fifo_size) |
1412                                                  R700_SC_HIZ_TILE_FIFO_SIZE(dev_priv->r700_sc_hiz_tile_fifo_size) |
1413                                                  R700_SC_EARLYZ_TILE_FIFO_SIZE(dev_priv->r700_sc_earlyz_tile_fifo_fize)));
1414
1415         RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0);
1416
1417         RADEON_WRITE(R600_VGT_NUM_INSTANCES, 1);
1418
1419         RADEON_WRITE(R600_SPI_CONFIG_CNTL, R600_GPR_WRITE_PRIORITY(0));
1420
1421         RADEON_WRITE(R600_SPI_CONFIG_CNTL_1, R600_VTX_DONE_DELAY(4));
1422
1423         RADEON_WRITE(R600_CP_PERFMON_CNTL, 0);
1424
1425         sq_ms_fifo_sizes = (R600_CACHE_FIFO_SIZE(16 * dev_priv->r600_sq_num_cf_insts) |
1426                             R600_DONE_FIFO_HIWATER(0xe0) |
1427                             R600_ALU_UPDATE_FIFO_HIWATER(0x8));
1428         switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1429         case CHIP_RV770:
1430                 sq_ms_fifo_sizes |= R600_FETCH_FIFO_HIWATER(0x1);
1431                 break;
1432         case CHIP_RV730:
1433         case CHIP_RV710:
1434         default:
1435                 sq_ms_fifo_sizes |= R600_FETCH_FIFO_HIWATER(0x4);
1436                 break;
1437         }
1438         RADEON_WRITE(R600_SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes);
1439
1440         /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
1441          * should be adjusted as needed by the 2D/3D drivers.  This just sets default values
1442          */
1443         sq_config = RADEON_READ(R600_SQ_CONFIG);
1444         sq_config &= ~(R600_PS_PRIO(3) |
1445                        R600_VS_PRIO(3) |
1446                        R600_GS_PRIO(3) |
1447                        R600_ES_PRIO(3));
1448         sq_config |= (R600_DX9_CONSTS |
1449                       R600_VC_ENABLE |
1450                       R600_EXPORT_SRC_C |
1451                       R600_PS_PRIO(0) |
1452                       R600_VS_PRIO(1) |
1453                       R600_GS_PRIO(2) |
1454                       R600_ES_PRIO(3));
1455         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710)
1456                 /* no vertex cache */
1457                 sq_config &= ~R600_VC_ENABLE;
1458
1459         RADEON_WRITE(R600_SQ_CONFIG, sq_config);
1460
1461         RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_1,  (R600_NUM_PS_GPRS((dev_priv->r600_max_gprs * 24)/64) |
1462                                                     R600_NUM_VS_GPRS((dev_priv->r600_max_gprs * 24)/64) |
1463                                                     R600_NUM_CLAUSE_TEMP_GPRS(((dev_priv->r600_max_gprs * 24)/64)/2)));
1464
1465         RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_2,  (R600_NUM_GS_GPRS((dev_priv->r600_max_gprs * 7)/64) |
1466                                                     R600_NUM_ES_GPRS((dev_priv->r600_max_gprs * 7)/64)));
1467
1468         sq_thread_resource_mgmt = (R600_NUM_PS_THREADS((dev_priv->r600_max_threads * 4)/8) |
1469                                    R600_NUM_VS_THREADS((dev_priv->r600_max_threads * 2)/8) |
1470                                    R600_NUM_ES_THREADS((dev_priv->r600_max_threads * 1)/8));
1471         if (((dev_priv->r600_max_threads * 1) / 8) > dev_priv->r600_max_gs_threads)
1472                 sq_thread_resource_mgmt |= R600_NUM_GS_THREADS(dev_priv->r600_max_gs_threads);
1473         else
1474                 sq_thread_resource_mgmt |= R600_NUM_GS_THREADS((dev_priv->r600_max_gs_threads * 1)/8);
1475         RADEON_WRITE(R600_SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1476
1477         RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_1, (R600_NUM_PS_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4) |
1478                                                      R600_NUM_VS_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4)));
1479
1480         RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_2, (R600_NUM_GS_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4) |
1481                                                      R600_NUM_ES_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4)));
1482
1483         sq_dyn_gpr_size_simd_ab_0 = (R700_SIMDA_RING0((dev_priv->r600_max_gprs * 38)/64) |
1484                                      R700_SIMDA_RING1((dev_priv->r600_max_gprs * 38)/64) |
1485                                      R700_SIMDB_RING0((dev_priv->r600_max_gprs * 38)/64) |
1486                                      R700_SIMDB_RING1((dev_priv->r600_max_gprs * 38)/64));
1487
1488         RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0);
1489         RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0);
1490         RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0);
1491         RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0);
1492         RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0);
1493         RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0);
1494         RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0);
1495         RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0);
1496
1497         RADEON_WRITE(R700_PA_SC_FORCE_EOV_MAX_CNTS, (R700_FORCE_EOV_MAX_CLK_CNT(4095) |
1498                                                      R700_FORCE_EOV_MAX_REZ_CNT(255)));
1499
1500         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710)
1501                 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, (R600_CACHE_INVALIDATION(R600_TC_ONLY) |
1502                                                            R700_AUTO_INVLD_EN(R700_ES_AND_GS_AUTO)));
1503         else
1504                 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, (R600_CACHE_INVALIDATION(R600_VC_AND_TC) |
1505                                                            R700_AUTO_INVLD_EN(R700_ES_AND_GS_AUTO)));
1506
1507         switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1508         case CHIP_RV770:
1509         case CHIP_RV730:
1510                 gs_prim_buffer_depth = 384;
1511                 break;
1512         case CHIP_RV710:
1513                 gs_prim_buffer_depth = 128;
1514                 break;
1515         default:
1516                 break;
1517         }
1518
1519         num_gs_verts_per_thread = dev_priv->r600_max_pipes * 16;
1520         vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread;
1521         /* Max value for this is 256 */
1522         if (vgt_gs_per_es > 256)
1523                 vgt_gs_per_es = 256;
1524
1525         RADEON_WRITE(R600_VGT_ES_PER_GS, 128);
1526         RADEON_WRITE(R600_VGT_GS_PER_ES, vgt_gs_per_es);
1527         RADEON_WRITE(R600_VGT_GS_PER_VS, 2);
1528
1529         /* more default values. 2D/3D driver should adjust as needed */
1530         RADEON_WRITE(R600_VGT_GS_VERTEX_REUSE, 16);
1531         RADEON_WRITE(R600_PA_SC_LINE_STIPPLE_STATE, 0);
1532         RADEON_WRITE(R600_VGT_STRMOUT_EN, 0);
1533         RADEON_WRITE(R600_SX_MISC, 0);
1534         RADEON_WRITE(R600_PA_SC_MODE_CNTL, 0);
1535         RADEON_WRITE(R700_PA_SC_EDGERULE, 0xaaaaaaaa);
1536         RADEON_WRITE(R600_PA_SC_AA_CONFIG, 0);
1537         RADEON_WRITE(R600_PA_SC_CLIPRECT_RULE, 0xffff);
1538         RADEON_WRITE(R600_PA_SC_LINE_STIPPLE, 0);
1539         RADEON_WRITE(R600_SPI_INPUT_Z, 0);
1540         RADEON_WRITE(R600_SPI_PS_IN_CONTROL_0, R600_NUM_INTERP(2));
1541         RADEON_WRITE(R600_CB_COLOR7_FRAG, 0);
1542
1543         /* clear render buffer base addresses */
1544         RADEON_WRITE(R600_CB_COLOR0_BASE, 0);
1545         RADEON_WRITE(R600_CB_COLOR1_BASE, 0);
1546         RADEON_WRITE(R600_CB_COLOR2_BASE, 0);
1547         RADEON_WRITE(R600_CB_COLOR3_BASE, 0);
1548         RADEON_WRITE(R600_CB_COLOR4_BASE, 0);
1549         RADEON_WRITE(R600_CB_COLOR5_BASE, 0);
1550         RADEON_WRITE(R600_CB_COLOR6_BASE, 0);
1551         RADEON_WRITE(R600_CB_COLOR7_BASE, 0);
1552
1553         RADEON_WRITE(R700_TCP_CNTL, 0);
1554
1555         hdp_host_path_cntl = RADEON_READ(R600_HDP_HOST_PATH_CNTL);
1556         RADEON_WRITE(R600_HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1557
1558         RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0);
1559
1560         RADEON_WRITE(R600_PA_CL_ENHANCE, (R600_CLIP_VTX_REORDER_ENA |
1561                                           R600_NUM_CLIP_SEQ(3)));
1562
1563 }
1564
1565 static void r600_cp_init_ring_buffer(struct drm_device *dev,
1566                                        drm_radeon_private_t *dev_priv,
1567                                        struct drm_file *file_priv)
1568 {
1569         u32 ring_start;
1570         u64 rptr_addr;
1571
1572         if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770))
1573                 r700_gfx_init(dev, dev_priv);
1574         else
1575                 r600_gfx_init(dev, dev_priv);
1576
1577         RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP);
1578         RADEON_READ(R600_GRBM_SOFT_RESET);
1579         DRM_UDELAY(15000);
1580         RADEON_WRITE(R600_GRBM_SOFT_RESET, 0);
1581
1582
1583         /* Set ring buffer size */
1584 #ifdef __BIG_ENDIAN
1585         RADEON_WRITE(R600_CP_RB_CNTL,
1586                      RADEON_BUF_SWAP_32BIT |
1587                      RADEON_RB_NO_UPDATE |
1588                      (dev_priv->ring.rptr_update_l2qw << 8) |
1589                      dev_priv->ring.size_l2qw);
1590 #else
1591         RADEON_WRITE(R600_CP_RB_CNTL,
1592                      RADEON_RB_NO_UPDATE |
1593                      (dev_priv->ring.rptr_update_l2qw << 8) |
1594                      dev_priv->ring.size_l2qw);
1595 #endif
1596
1597         RADEON_WRITE(R600_CP_SEM_WAIT_TIMER, 0x4);
1598
1599         /* Set the write pointer delay */
1600         RADEON_WRITE(R600_CP_RB_WPTR_DELAY, 0);
1601
1602 #ifdef __BIG_ENDIAN
1603         RADEON_WRITE(R600_CP_RB_CNTL,
1604                      RADEON_BUF_SWAP_32BIT |
1605                      RADEON_RB_NO_UPDATE |
1606                      RADEON_RB_RPTR_WR_ENA |
1607                      (dev_priv->ring.rptr_update_l2qw << 8) |
1608                      dev_priv->ring.size_l2qw);
1609 #else
1610         RADEON_WRITE(R600_CP_RB_CNTL,
1611                      RADEON_RB_NO_UPDATE |
1612                      RADEON_RB_RPTR_WR_ENA |
1613                      (dev_priv->ring.rptr_update_l2qw << 8) |
1614                      dev_priv->ring.size_l2qw);
1615 #endif
1616
1617         /* Initialize the ring buffer's read and write pointers */
1618         RADEON_WRITE(R600_CP_RB_RPTR_WR, 0);
1619         RADEON_WRITE(R600_CP_RB_WPTR, 0);
1620         SET_RING_HEAD(dev_priv, 0);
1621         dev_priv->ring.tail = 0;
1622
1623 #if __OS_HAS_AGP
1624         if (dev_priv->flags & RADEON_IS_AGP) {
1625                 rptr_addr = dev_priv->ring_rptr->offset
1626                         - dev->agp->base +
1627                         dev_priv->gart_vm_start;
1628         } else
1629 #endif
1630         {
1631                 rptr_addr = dev_priv->ring_rptr->offset
1632                         - ((unsigned long) dev->sg->virtual)
1633                         + dev_priv->gart_vm_start;
1634         }
1635         RADEON_WRITE(R600_CP_RB_RPTR_ADDR,
1636                      rptr_addr & 0xffffffff);
1637         RADEON_WRITE(R600_CP_RB_RPTR_ADDR_HI,
1638                      upper_32_bits(rptr_addr));
1639
1640 #ifdef __BIG_ENDIAN
1641         RADEON_WRITE(R600_CP_RB_CNTL,
1642                      RADEON_BUF_SWAP_32BIT |
1643                      (dev_priv->ring.rptr_update_l2qw << 8) |
1644                      dev_priv->ring.size_l2qw);
1645 #else
1646         RADEON_WRITE(R600_CP_RB_CNTL,
1647                      (dev_priv->ring.rptr_update_l2qw << 8) |
1648                      dev_priv->ring.size_l2qw);
1649 #endif
1650
1651 #if __OS_HAS_AGP
1652         if (dev_priv->flags & RADEON_IS_AGP) {
1653                 /* XXX */
1654                 radeon_write_agp_base(dev_priv, dev->agp->base);
1655
1656                 /* XXX */
1657                 radeon_write_agp_location(dev_priv,
1658                              (((dev_priv->gart_vm_start - 1 +
1659                                 dev_priv->gart_size) & 0xffff0000) |
1660                               (dev_priv->gart_vm_start >> 16)));
1661
1662                 ring_start = (dev_priv->cp_ring->offset
1663                               - dev->agp->base
1664                               + dev_priv->gart_vm_start);
1665         } else
1666 #endif
1667                 ring_start = (dev_priv->cp_ring->offset
1668                               - (unsigned long)dev->sg->virtual
1669                               + dev_priv->gart_vm_start);
1670
1671         RADEON_WRITE(R600_CP_RB_BASE, ring_start >> 8);
1672
1673         RADEON_WRITE(R600_CP_ME_CNTL, 0xff);
1674
1675         RADEON_WRITE(R600_CP_DEBUG, (1 << 27) | (1 << 28));
1676
1677         /* Initialize the scratch register pointer.  This will cause
1678          * the scratch register values to be written out to memory
1679          * whenever they are updated.
1680          *
1681          * We simply put this behind the ring read pointer, this works
1682          * with PCI GART as well as (whatever kind of) AGP GART
1683          */
1684         {
1685                 u64 scratch_addr;
1686
1687                 scratch_addr = RADEON_READ(R600_CP_RB_RPTR_ADDR);
1688                 scratch_addr |= ((u64)RADEON_READ(R600_CP_RB_RPTR_ADDR_HI)) << 32;
1689                 scratch_addr += R600_SCRATCH_REG_OFFSET;
1690                 scratch_addr >>= 8;
1691                 scratch_addr &= 0xffffffff;
1692
1693                 RADEON_WRITE(R600_SCRATCH_ADDR, (uint32_t)scratch_addr);
1694         }
1695
1696         RADEON_WRITE(R600_SCRATCH_UMSK, 0x7);
1697
1698         /* Turn on bus mastering */
1699         radeon_enable_bm(dev_priv);
1700
1701         radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(0), 0);
1702         RADEON_WRITE(R600_LAST_FRAME_REG, 0);
1703
1704         radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(1), 0);
1705         RADEON_WRITE(R600_LAST_DISPATCH_REG, 0);
1706
1707         radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(2), 0);
1708         RADEON_WRITE(R600_LAST_CLEAR_REG, 0);
1709
1710         /* reset sarea copies of these */
1711         if (dev_priv->sarea_priv) {
1712                 dev_priv->sarea_priv->last_frame = 0;
1713                 dev_priv->sarea_priv->last_dispatch = 0;
1714                 dev_priv->sarea_priv->last_clear = 0;
1715         }
1716
1717         r600_do_wait_for_idle(dev_priv);
1718
1719 }
1720
1721 int r600_do_cleanup_cp(struct drm_device *dev)
1722 {
1723         drm_radeon_private_t *dev_priv = dev->dev_private;
1724         DRM_DEBUG("\n");
1725
1726         /* Make sure interrupts are disabled here because the uninstall ioctl
1727          * may not have been called from userspace and after dev_private
1728          * is freed, it's too late.
1729          */
1730         if (dev->irq_enabled)
1731                 drm_irq_uninstall(dev);
1732
1733 #if __OS_HAS_AGP
1734         if (dev_priv->flags & RADEON_IS_AGP) {
1735                 if (dev_priv->cp_ring != NULL) {
1736                         drm_core_ioremapfree(dev_priv->cp_ring, dev);
1737                         dev_priv->cp_ring = NULL;
1738                 }
1739                 if (dev_priv->ring_rptr != NULL) {
1740                         drm_core_ioremapfree(dev_priv->ring_rptr, dev);
1741                         dev_priv->ring_rptr = NULL;
1742                 }
1743                 if (dev->agp_buffer_map != NULL) {
1744                         drm_core_ioremapfree(dev->agp_buffer_map, dev);
1745                         dev->agp_buffer_map = NULL;
1746                 }
1747         } else
1748 #endif
1749         {
1750
1751                 if (dev_priv->gart_info.bus_addr)
1752                         r600_page_table_cleanup(dev, &dev_priv->gart_info);
1753
1754                 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB) {
1755                         drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev);
1756                         dev_priv->gart_info.addr = 0;
1757                 }
1758         }
1759         /* only clear to the start of flags */
1760         memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
1761
1762         return 0;
1763 }
1764
1765 int r600_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init,
1766                     struct drm_file *file_priv)
1767 {
1768         drm_radeon_private_t *dev_priv = dev->dev_private;
1769
1770         DRM_DEBUG("\n");
1771
1772         /* if we require new memory map but we don't have it fail */
1773         if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) {
1774                 DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n");
1775                 r600_do_cleanup_cp(dev);
1776                 return -EINVAL;
1777         }
1778
1779         if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) {
1780                 DRM_DEBUG("Forcing AGP card to PCI mode\n");
1781                 dev_priv->flags &= ~RADEON_IS_AGP;
1782                 /* The writeback test succeeds, but when writeback is enabled,
1783                  * the ring buffer read ptr update fails after first 128 bytes.
1784                  */
1785                 radeon_no_wb = 1;
1786         } else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE))
1787                  && !init->is_pci) {
1788                 DRM_DEBUG("Restoring AGP flag\n");
1789                 dev_priv->flags |= RADEON_IS_AGP;
1790         }
1791
1792         dev_priv->usec_timeout = init->usec_timeout;
1793         if (dev_priv->usec_timeout < 1 ||
1794             dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) {
1795                 DRM_DEBUG("TIMEOUT problem!\n");
1796                 r600_do_cleanup_cp(dev);
1797                 return -EINVAL;
1798         }
1799
1800         /* Enable vblank on CRTC1 for older X servers
1801          */
1802         dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1;
1803
1804         dev_priv->cp_mode = init->cp_mode;
1805
1806         /* We don't support anything other than bus-mastering ring mode,
1807          * but the ring can be in either AGP or PCI space for the ring
1808          * read pointer.
1809          */
1810         if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) &&
1811             (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) {
1812                 DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode);
1813                 r600_do_cleanup_cp(dev);
1814                 return -EINVAL;
1815         }
1816
1817         switch (init->fb_bpp) {
1818         case 16:
1819                 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
1820                 break;
1821         case 32:
1822         default:
1823                 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
1824                 break;
1825         }
1826         dev_priv->front_offset = init->front_offset;
1827         dev_priv->front_pitch = init->front_pitch;
1828         dev_priv->back_offset = init->back_offset;
1829         dev_priv->back_pitch = init->back_pitch;
1830
1831         dev_priv->ring_offset = init->ring_offset;
1832         dev_priv->ring_rptr_offset = init->ring_rptr_offset;
1833         dev_priv->buffers_offset = init->buffers_offset;
1834         dev_priv->gart_textures_offset = init->gart_textures_offset;
1835
1836         dev_priv->sarea = drm_getsarea(dev);
1837         if (!dev_priv->sarea) {
1838                 DRM_ERROR("could not find sarea!\n");
1839                 r600_do_cleanup_cp(dev);
1840                 return -EINVAL;
1841         }
1842
1843         dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset);
1844         if (!dev_priv->cp_ring) {
1845                 DRM_ERROR("could not find cp ring region!\n");
1846                 r600_do_cleanup_cp(dev);
1847                 return -EINVAL;
1848         }
1849         dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
1850         if (!dev_priv->ring_rptr) {
1851                 DRM_ERROR("could not find ring read pointer!\n");
1852                 r600_do_cleanup_cp(dev);
1853                 return -EINVAL;
1854         }
1855         dev->agp_buffer_token = init->buffers_offset;
1856         dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
1857         if (!dev->agp_buffer_map) {
1858                 DRM_ERROR("could not find dma buffer region!\n");
1859                 r600_do_cleanup_cp(dev);
1860                 return -EINVAL;
1861         }
1862
1863         if (init->gart_textures_offset) {
1864                 dev_priv->gart_textures =
1865                     drm_core_findmap(dev, init->gart_textures_offset);
1866                 if (!dev_priv->gart_textures) {
1867                         DRM_ERROR("could not find GART texture region!\n");
1868                         r600_do_cleanup_cp(dev);
1869                         return -EINVAL;
1870                 }
1871         }
1872
1873         dev_priv->sarea_priv =
1874             (drm_radeon_sarea_t *) ((u8 *) dev_priv->sarea->handle +
1875                                     init->sarea_priv_offset);
1876
1877 #if __OS_HAS_AGP
1878         /* XXX */
1879         if (dev_priv->flags & RADEON_IS_AGP) {
1880                 drm_core_ioremap_wc(dev_priv->cp_ring, dev);
1881                 drm_core_ioremap_wc(dev_priv->ring_rptr, dev);
1882                 drm_core_ioremap_wc(dev->agp_buffer_map, dev);
1883                 if (!dev_priv->cp_ring->handle ||
1884                     !dev_priv->ring_rptr->handle ||
1885                     !dev->agp_buffer_map->handle) {
1886                         DRM_ERROR("could not find ioremap agp regions!\n");
1887                         r600_do_cleanup_cp(dev);
1888                         return -EINVAL;
1889                 }
1890         } else
1891 #endif
1892         {
1893                 dev_priv->cp_ring->handle = (void *)dev_priv->cp_ring->offset;
1894                 dev_priv->ring_rptr->handle =
1895                     (void *)dev_priv->ring_rptr->offset;
1896                 dev->agp_buffer_map->handle =
1897                     (void *)dev->agp_buffer_map->offset;
1898
1899                 DRM_DEBUG("dev_priv->cp_ring->handle %p\n",
1900                           dev_priv->cp_ring->handle);
1901                 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n",
1902                           dev_priv->ring_rptr->handle);
1903                 DRM_DEBUG("dev->agp_buffer_map->handle %p\n",
1904                           dev->agp_buffer_map->handle);
1905         }
1906
1907         dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 24;
1908         dev_priv->fb_size =
1909                 (((radeon_read_fb_location(dev_priv) & 0xffff0000u) << 8) + 0x1000000)
1910                 - dev_priv->fb_location;
1911
1912         dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) |
1913                                         ((dev_priv->front_offset
1914                                           + dev_priv->fb_location) >> 10));
1915
1916         dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) |
1917                                        ((dev_priv->back_offset
1918                                          + dev_priv->fb_location) >> 10));
1919
1920         dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) |
1921                                         ((dev_priv->depth_offset
1922                                           + dev_priv->fb_location) >> 10));
1923
1924         dev_priv->gart_size = init->gart_size;
1925
1926         /* New let's set the memory map ... */
1927         if (dev_priv->new_memmap) {
1928                 u32 base = 0;
1929
1930                 DRM_INFO("Setting GART location based on new memory map\n");
1931
1932                 /* If using AGP, try to locate the AGP aperture at the same
1933                  * location in the card and on the bus, though we have to
1934                  * align it down.
1935                  */
1936 #if __OS_HAS_AGP
1937                 /* XXX */
1938                 if (dev_priv->flags & RADEON_IS_AGP) {
1939                         base = dev->agp->base;
1940                         /* Check if valid */
1941                         if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location &&
1942                             base < (dev_priv->fb_location + dev_priv->fb_size - 1)) {
1943                                 DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n",
1944                                          dev->agp->base);
1945                                 base = 0;
1946                         }
1947                 }
1948 #endif
1949                 /* If not or if AGP is at 0 (Macs), try to put it elsewhere */
1950                 if (base == 0) {
1951                         base = dev_priv->fb_location + dev_priv->fb_size;
1952                         if (base < dev_priv->fb_location ||
1953                             ((base + dev_priv->gart_size) & 0xfffffffful) < base)
1954                                 base = dev_priv->fb_location
1955                                         - dev_priv->gart_size;
1956                 }
1957                 dev_priv->gart_vm_start = base & 0xffc00000u;
1958                 if (dev_priv->gart_vm_start != base)
1959                         DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n",
1960                                  base, dev_priv->gart_vm_start);
1961         }
1962
1963 #if __OS_HAS_AGP
1964         /* XXX */
1965         if (dev_priv->flags & RADEON_IS_AGP)
1966                 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1967                                                  - dev->agp->base
1968                                                  + dev_priv->gart_vm_start);
1969         else
1970 #endif
1971                 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1972                                                  - (unsigned long)dev->sg->virtual
1973                                                  + dev_priv->gart_vm_start);
1974
1975         DRM_DEBUG("fb 0x%08x size %d\n",
1976                   (unsigned int) dev_priv->fb_location,
1977                   (unsigned int) dev_priv->fb_size);
1978         DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size);
1979         DRM_DEBUG("dev_priv->gart_vm_start 0x%08x\n",
1980                   (unsigned int) dev_priv->gart_vm_start);
1981         DRM_DEBUG("dev_priv->gart_buffers_offset 0x%08lx\n",
1982                   dev_priv->gart_buffers_offset);
1983
1984         dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle;
1985         dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle
1986                               + init->ring_size / sizeof(u32));
1987         dev_priv->ring.size = init->ring_size;
1988         dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
1989
1990         dev_priv->ring.rptr_update = /* init->rptr_update */ 4096;
1991         dev_priv->ring.rptr_update_l2qw = drm_order(/* init->rptr_update */ 4096 / 8);
1992
1993         dev_priv->ring.fetch_size = /* init->fetch_size */ 32;
1994         dev_priv->ring.fetch_size_l2ow = drm_order(/* init->fetch_size */ 32 / 16);
1995
1996         dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
1997
1998         dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
1999
2000 #if __OS_HAS_AGP
2001         if (dev_priv->flags & RADEON_IS_AGP) {
2002                 /* XXX turn off pcie gart */
2003         } else
2004 #endif
2005         {
2006                 dev_priv->gart_info.table_mask = DMA_BIT_MASK(32);
2007                 /* if we have an offset set from userspace */
2008                 if (!dev_priv->pcigart_offset_set) {
2009                         DRM_ERROR("Need gart offset from userspace\n");
2010                         r600_do_cleanup_cp(dev);
2011                         return -EINVAL;
2012                 }
2013
2014                 DRM_DEBUG("Using gart offset 0x%08lx\n", dev_priv->pcigart_offset);
2015
2016                 dev_priv->gart_info.bus_addr =
2017                         dev_priv->pcigart_offset + dev_priv->fb_location;
2018                 dev_priv->gart_info.mapping.offset =
2019                         dev_priv->pcigart_offset + dev_priv->fb_aper_offset;
2020                 dev_priv->gart_info.mapping.size =
2021                         dev_priv->gart_info.table_size;
2022
2023                 drm_core_ioremap_wc(&dev_priv->gart_info.mapping, dev);
2024                 if (!dev_priv->gart_info.mapping.handle) {
2025                         DRM_ERROR("ioremap failed.\n");
2026                         r600_do_cleanup_cp(dev);
2027                         return -EINVAL;
2028                 }
2029
2030                 dev_priv->gart_info.addr =
2031                         dev_priv->gart_info.mapping.handle;
2032
2033                 DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n",
2034                           dev_priv->gart_info.addr,
2035                           dev_priv->pcigart_offset);
2036
2037                 if (!r600_page_table_init(dev)) {
2038                         DRM_ERROR("Failed to init GART table\n");
2039                         r600_do_cleanup_cp(dev);
2040                         return -EINVAL;
2041                 }
2042
2043                 if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770))
2044                         r700_vm_init(dev);
2045                 else
2046                         r600_vm_init(dev);
2047         }
2048
2049         if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770))
2050                 r700_cp_load_microcode(dev_priv);
2051         else
2052                 r600_cp_load_microcode(dev_priv);
2053
2054         r600_cp_init_ring_buffer(dev, dev_priv, file_priv);
2055
2056         dev_priv->last_buf = 0;
2057
2058         r600_do_engine_reset(dev);
2059         r600_test_writeback(dev_priv);
2060
2061         return 0;
2062 }
2063
2064 int r600_do_resume_cp(struct drm_device *dev, struct drm_file *file_priv)
2065 {
2066         drm_radeon_private_t *dev_priv = dev->dev_private;
2067
2068         DRM_DEBUG("\n");
2069         if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)) {
2070                 r700_vm_init(dev);
2071                 r700_cp_load_microcode(dev_priv);
2072         } else {
2073                 r600_vm_init(dev);
2074                 r600_cp_load_microcode(dev_priv);
2075         }
2076         r600_cp_init_ring_buffer(dev, dev_priv, file_priv);
2077         r600_do_engine_reset(dev);
2078
2079         return 0;
2080 }
2081
2082 /* Wait for the CP to go idle.
2083  */
2084 int r600_do_cp_idle(drm_radeon_private_t *dev_priv)
2085 {
2086         RING_LOCALS;
2087         DRM_DEBUG("\n");
2088
2089         BEGIN_RING(5);
2090         OUT_RING(CP_PACKET3(R600_IT_EVENT_WRITE, 0));
2091         OUT_RING(R600_CACHE_FLUSH_AND_INV_EVENT);
2092         /* wait for 3D idle clean */
2093         OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1));
2094         OUT_RING((R600_WAIT_UNTIL - R600_SET_CONFIG_REG_OFFSET) >> 2);
2095         OUT_RING(RADEON_WAIT_3D_IDLE | RADEON_WAIT_3D_IDLECLEAN);
2096
2097         ADVANCE_RING();
2098         COMMIT_RING();
2099
2100         return r600_do_wait_for_idle(dev_priv);
2101 }
2102
2103 /* Start the Command Processor.
2104  */
2105 void r600_do_cp_start(drm_radeon_private_t *dev_priv)
2106 {
2107         u32 cp_me;
2108         RING_LOCALS;
2109         DRM_DEBUG("\n");
2110
2111         BEGIN_RING(7);
2112         OUT_RING(CP_PACKET3(R600_IT_ME_INITIALIZE, 5));
2113         OUT_RING(0x00000001);
2114         if (((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_RV770))
2115                 OUT_RING(0x00000003);
2116         else
2117                 OUT_RING(0x00000000);
2118         OUT_RING((dev_priv->r600_max_hw_contexts - 1));
2119         OUT_RING(R600_ME_INITIALIZE_DEVICE_ID(1));
2120         OUT_RING(0x00000000);
2121         OUT_RING(0x00000000);
2122         ADVANCE_RING();
2123         COMMIT_RING();
2124
2125         /* set the mux and reset the halt bit */
2126         cp_me = 0xff;
2127         RADEON_WRITE(R600_CP_ME_CNTL, cp_me);
2128
2129         dev_priv->cp_running = 1;
2130
2131 }
2132
2133 void r600_do_cp_reset(drm_radeon_private_t *dev_priv)
2134 {
2135         u32 cur_read_ptr;
2136         DRM_DEBUG("\n");
2137
2138         cur_read_ptr = RADEON_READ(R600_CP_RB_RPTR);
2139         RADEON_WRITE(R600_CP_RB_WPTR, cur_read_ptr);
2140         SET_RING_HEAD(dev_priv, cur_read_ptr);
2141         dev_priv->ring.tail = cur_read_ptr;
2142 }
2143
2144 void r600_do_cp_stop(drm_radeon_private_t *dev_priv)
2145 {
2146         uint32_t cp_me;
2147
2148         DRM_DEBUG("\n");
2149
2150         cp_me = 0xff | R600_CP_ME_HALT;
2151
2152         RADEON_WRITE(R600_CP_ME_CNTL, cp_me);
2153
2154         dev_priv->cp_running = 0;
2155 }
2156
2157 int r600_cp_dispatch_indirect(struct drm_device *dev,
2158                               struct drm_buf *buf, int start, int end)
2159 {
2160         drm_radeon_private_t *dev_priv = dev->dev_private;
2161         RING_LOCALS;
2162
2163         if (start != end) {
2164                 unsigned long offset = (dev_priv->gart_buffers_offset
2165                                         + buf->offset + start);
2166                 int dwords = (end - start + 3) / sizeof(u32);
2167
2168                 DRM_DEBUG("dwords:%d\n", dwords);
2169                 DRM_DEBUG("offset 0x%lx\n", offset);
2170
2171
2172                 /* Indirect buffer data must be a multiple of 16 dwords.
2173                  * pad the data with a Type-2 CP packet.
2174                  */
2175                 while (dwords & 0xf) {
2176                         u32 *data = (u32 *)
2177                             ((char *)dev->agp_buffer_map->handle
2178                              + buf->offset + start);
2179                         data[dwords++] = RADEON_CP_PACKET2;
2180                 }
2181
2182                 /* Fire off the indirect buffer */
2183                 BEGIN_RING(4);
2184                 OUT_RING(CP_PACKET3(R600_IT_INDIRECT_BUFFER, 2));
2185                 OUT_RING((offset & 0xfffffffc));
2186                 OUT_RING((upper_32_bits(offset) & 0xff));
2187                 OUT_RING(dwords);
2188                 ADVANCE_RING();
2189         }
2190
2191         return 0;
2192 }