2 * Product specific probe and attach routines for:
3 * 3940, 2940, aic7895, aic7890, aic7880,
4 * aic7870, aic7860 and aic7850 SCSI controllers
6 * Copyright (c) 1994-2001 Justin T. Gibbs.
7 * Copyright (c) 2000-2001 Adaptec Inc.
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions, and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * substantially similar to the "NO WARRANTY" disclaimer below
18 * ("Disclaimer") and any redistribution must be conditioned upon
19 * including a substantially similar Disclaimer requirement for further
20 * binary redistribution.
21 * 3. Neither the names of the above-listed copyright holders nor the names
22 * of any contributors may be used to endorse or promote products derived
23 * from this software without specific prior written permission.
25 * Alternatively, this software may be distributed under the terms of the
26 * GNU General Public License ("GPL") version 2 as published by the Free
27 * Software Foundation.
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
34 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
36 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
38 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
39 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
40 * POSSIBILITY OF SUCH DAMAGES.
42 * $Id: //depot/aic7xxx/aic7xxx/aic7xxx_pci.c#69 $
44 * $FreeBSD: src/sys/dev/aic7xxx/aic7xxx_pci.c,v 1.2.2.17 2003/06/10 03:26:09 gibbs Exp $
45 * $DragonFly: src/sys/dev/disk/aic7xxx/aic7xxx_pci.c,v 1.3 2003/08/07 21:16:51 dillon Exp $
49 #include "aic7xxx_osm.h"
50 #include "aic7xxx_inline.h"
51 #include "aic7xxx_93cx6.h"
53 #include "aic7xxx_osm.h"
54 #include "aic7xxx_inline.h"
55 #include "aic7xxx_93cx6.h"
58 #define AHC_PCI_IOADDR PCIR_MAPS /* I/O Address */
59 #define AHC_PCI_MEMADDR (PCIR_MAPS + 4) /* Mem I/O Address */
61 static __inline uint64_t
62 ahc_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor)
68 | ((uint64_t)vendor << 32)
69 | ((uint64_t)device << 48);
74 #define ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull
75 #define ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull
76 #define ID_9005_GENERIC_MASK 0xFFF0FFFF00000000ull
77 #define ID_9005_SISL_MASK 0x000FFFFF00000000ull
78 #define ID_9005_SISL_ID 0x0005900500000000ull
79 #define ID_AIC7850 0x5078900400000000ull
80 #define ID_AHA_2902_04_10_15_20C_30C 0x5078900478509004ull
81 #define ID_AIC7855 0x5578900400000000ull
82 #define ID_AIC7859 0x3860900400000000ull
83 #define ID_AHA_2930CU 0x3860900438699004ull
84 #define ID_AIC7860 0x6078900400000000ull
85 #define ID_AIC7860C 0x6078900478609004ull
86 #define ID_AHA_1480A 0x6075900400000000ull
87 #define ID_AHA_2940AU_0 0x6178900400000000ull
88 #define ID_AHA_2940AU_1 0x6178900478619004ull
89 #define ID_AHA_2940AU_CN 0x2178900478219004ull
90 #define ID_AHA_2930C_VAR 0x6038900438689004ull
92 #define ID_AIC7870 0x7078900400000000ull
93 #define ID_AHA_2940 0x7178900400000000ull
94 #define ID_AHA_3940 0x7278900400000000ull
95 #define ID_AHA_398X 0x7378900400000000ull
96 #define ID_AHA_2944 0x7478900400000000ull
97 #define ID_AHA_3944 0x7578900400000000ull
98 #define ID_AHA_4944 0x7678900400000000ull
100 #define ID_AIC7880 0x8078900400000000ull
101 #define ID_AIC7880_B 0x8078900478809004ull
102 #define ID_AHA_2940U 0x8178900400000000ull
103 #define ID_AHA_3940U 0x8278900400000000ull
104 #define ID_AHA_2944U 0x8478900400000000ull
105 #define ID_AHA_3944U 0x8578900400000000ull
106 #define ID_AHA_398XU 0x8378900400000000ull
107 #define ID_AHA_4944U 0x8678900400000000ull
108 #define ID_AHA_2940UB 0x8178900478819004ull
109 #define ID_AHA_2930U 0x8878900478889004ull
110 #define ID_AHA_2940U_PRO 0x8778900478879004ull
111 #define ID_AHA_2940U_CN 0x0078900478009004ull
113 #define ID_AIC7895 0x7895900478959004ull
114 #define ID_AIC7895_ARO 0x7890900478939004ull
115 #define ID_AIC7895_ARO_MASK 0xFFF0FFFFFFFFFFFFull
116 #define ID_AHA_2940U_DUAL 0x7895900478919004ull
117 #define ID_AHA_3940AU 0x7895900478929004ull
118 #define ID_AHA_3944AU 0x7895900478949004ull
120 #define ID_AIC7890 0x001F9005000F9005ull
121 #define ID_AIC7890_ARO 0x00139005000F9005ull
122 #define ID_AAA_131U2 0x0013900500039005ull
123 #define ID_AHA_2930U2 0x0011900501819005ull
124 #define ID_AHA_2940U2B 0x00109005A1009005ull
125 #define ID_AHA_2940U2_OEM 0x0010900521809005ull
126 #define ID_AHA_2940U2 0x00109005A1809005ull
127 #define ID_AHA_2950U2B 0x00109005E1009005ull
129 #define ID_AIC7892 0x008F9005FFFF9005ull
130 #define ID_AIC7892_ARO 0x00839005FFFF9005ull
131 #define ID_AHA_29160 0x00809005E2A09005ull
132 #define ID_AHA_29160_CPQ 0x00809005E2A00E11ull
133 #define ID_AHA_29160N 0x0080900562A09005ull
134 #define ID_AHA_29160C 0x0080900562209005ull
135 #define ID_AHA_29160B 0x00809005E2209005ull
136 #define ID_AHA_19160B 0x0081900562A19005ull
138 #define ID_AIC7896 0x005F9005FFFF9005ull
139 #define ID_AIC7896_ARO 0x00539005FFFF9005ull
140 #define ID_AHA_3950U2B_0 0x00509005FFFF9005ull
141 #define ID_AHA_3950U2B_1 0x00509005F5009005ull
142 #define ID_AHA_3950U2D_0 0x00519005FFFF9005ull
143 #define ID_AHA_3950U2D_1 0x00519005B5009005ull
145 #define ID_AIC7899 0x00CF9005FFFF9005ull
146 #define ID_AIC7899_ARO 0x00C39005FFFF9005ull
147 #define ID_AHA_3960D 0x00C09005F6209005ull
148 #define ID_AHA_3960D_CPQ 0x00C09005F6200E11ull
150 #define ID_AIC7810 0x1078900400000000ull
151 #define ID_AIC7815 0x7815900400000000ull
153 #define DEVID_9005_TYPE(id) ((id) & 0xF)
154 #define DEVID_9005_TYPE_HBA 0x0 /* Standard Card */
155 #define DEVID_9005_TYPE_AAA 0x3 /* RAID Card */
156 #define DEVID_9005_TYPE_SISL 0x5 /* Container ROMB */
157 #define DEVID_9005_TYPE_MB 0xF /* On Motherboard */
159 #define DEVID_9005_MAXRATE(id) (((id) & 0x30) >> 4)
160 #define DEVID_9005_MAXRATE_U160 0x0
161 #define DEVID_9005_MAXRATE_ULTRA2 0x1
162 #define DEVID_9005_MAXRATE_ULTRA 0x2
163 #define DEVID_9005_MAXRATE_FAST 0x3
165 #define DEVID_9005_MFUNC(id) (((id) & 0x40) >> 6)
167 #define DEVID_9005_CLASS(id) (((id) & 0xFF00) >> 8)
168 #define DEVID_9005_CLASS_SPI 0x0 /* Parallel SCSI */
170 #define SUBID_9005_TYPE(id) ((id) & 0xF)
171 #define SUBID_9005_TYPE_MB 0xF /* On Motherboard */
172 #define SUBID_9005_TYPE_CARD 0x0 /* Standard Card */
173 #define SUBID_9005_TYPE_LCCARD 0x1 /* Low Cost Card */
174 #define SUBID_9005_TYPE_RAID 0x3 /* Combined with Raid */
176 #define SUBID_9005_TYPE_KNOWN(id) \
177 ((((id) & 0xF) == SUBID_9005_TYPE_MB) \
178 || (((id) & 0xF) == SUBID_9005_TYPE_CARD) \
179 || (((id) & 0xF) == SUBID_9005_TYPE_LCCARD) \
180 || (((id) & 0xF) == SUBID_9005_TYPE_RAID))
182 #define SUBID_9005_MAXRATE(id) (((id) & 0x30) >> 4)
183 #define SUBID_9005_MAXRATE_ULTRA2 0x0
184 #define SUBID_9005_MAXRATE_ULTRA 0x1
185 #define SUBID_9005_MAXRATE_U160 0x2
186 #define SUBID_9005_MAXRATE_RESERVED 0x3
188 #define SUBID_9005_SEEPTYPE(id) \
189 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \
190 ? ((id) & 0xC0) >> 6 \
191 : ((id) & 0x300) >> 8)
192 #define SUBID_9005_SEEPTYPE_NONE 0x0
193 #define SUBID_9005_SEEPTYPE_1K 0x1
194 #define SUBID_9005_SEEPTYPE_2K_4K 0x2
195 #define SUBID_9005_SEEPTYPE_RESERVED 0x3
196 #define SUBID_9005_AUTOTERM(id) \
197 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \
198 ? (((id) & 0x400) >> 10) == 0 \
199 : (((id) & 0x40) >> 6) == 0)
201 #define SUBID_9005_NUMCHAN(id) \
202 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \
203 ? ((id) & 0x300) >> 8 \
204 : ((id) & 0xC00) >> 10)
206 #define SUBID_9005_LEGACYCONN(id) \
207 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \
209 : ((id) & 0x80) >> 7)
211 #define SUBID_9005_MFUNCENB(id) \
212 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \
213 ? ((id) & 0x800) >> 11 \
214 : ((id) & 0x1000) >> 12)
216 * Informational only. Should use chip register to be
217 * certain, but may be use in identification strings.
219 #define SUBID_9005_CARD_SCSIWIDTH_MASK 0x2000
220 #define SUBID_9005_CARD_PCIWIDTH_MASK 0x4000
221 #define SUBID_9005_CARD_SEDIFF_MASK 0x8000
223 static ahc_device_setup_t ahc_aic785X_setup;
224 static ahc_device_setup_t ahc_aic7860_setup;
225 static ahc_device_setup_t ahc_apa1480_setup;
226 static ahc_device_setup_t ahc_aic7870_setup;
227 static ahc_device_setup_t ahc_aha394X_setup;
228 static ahc_device_setup_t ahc_aha494X_setup;
229 static ahc_device_setup_t ahc_aha398X_setup;
230 static ahc_device_setup_t ahc_aic7880_setup;
231 static ahc_device_setup_t ahc_aha2940Pro_setup;
232 static ahc_device_setup_t ahc_aha394XU_setup;
233 static ahc_device_setup_t ahc_aha398XU_setup;
234 static ahc_device_setup_t ahc_aic7890_setup;
235 static ahc_device_setup_t ahc_aic7892_setup;
236 static ahc_device_setup_t ahc_aic7895_setup;
237 static ahc_device_setup_t ahc_aic7896_setup;
238 static ahc_device_setup_t ahc_aic7899_setup;
239 static ahc_device_setup_t ahc_aha29160C_setup;
240 static ahc_device_setup_t ahc_raid_setup;
241 static ahc_device_setup_t ahc_aha394XX_setup;
242 static ahc_device_setup_t ahc_aha494XX_setup;
243 static ahc_device_setup_t ahc_aha398XX_setup;
245 struct ahc_pci_identity ahc_pci_ident_table [] =
247 /* aic7850 based controllers */
249 ID_AHA_2902_04_10_15_20C_30C,
251 "Adaptec 2902/04/10/15/20C/30C SCSI adapter",
254 /* aic7860 based controllers */
258 "Adaptec 2930CU SCSI adapter",
262 ID_AHA_1480A & ID_DEV_VENDOR_MASK,
264 "Adaptec 1480A Ultra SCSI adapter",
268 ID_AHA_2940AU_0 & ID_DEV_VENDOR_MASK,
270 "Adaptec 2940A Ultra SCSI adapter",
274 ID_AHA_2940AU_CN & ID_DEV_VENDOR_MASK,
276 "Adaptec 2940A/CN Ultra SCSI adapter",
280 ID_AHA_2930C_VAR & ID_DEV_VENDOR_MASK,
282 "Adaptec 2930C Ultra SCSI adapter (VAR)",
285 /* aic7870 based controllers */
289 "Adaptec 2940 SCSI adapter",
295 "Adaptec 3940 SCSI adapter",
301 "Adaptec 398X SCSI RAID adapter",
307 "Adaptec 2944 SCSI adapter",
313 "Adaptec 3944 SCSI adapter",
319 "Adaptec 4944 SCSI adapter",
322 /* aic7880 based controllers */
324 ID_AHA_2940U & ID_DEV_VENDOR_MASK,
326 "Adaptec 2940 Ultra SCSI adapter",
330 ID_AHA_3940U & ID_DEV_VENDOR_MASK,
332 "Adaptec 3940 Ultra SCSI adapter",
336 ID_AHA_2944U & ID_DEV_VENDOR_MASK,
338 "Adaptec 2944 Ultra SCSI adapter",
342 ID_AHA_3944U & ID_DEV_VENDOR_MASK,
344 "Adaptec 3944 Ultra SCSI adapter",
348 ID_AHA_398XU & ID_DEV_VENDOR_MASK,
350 "Adaptec 398X Ultra SCSI RAID adapter",
355 * XXX Don't know the slot numbers
356 * so we can't identify channels
358 ID_AHA_4944U & ID_DEV_VENDOR_MASK,
360 "Adaptec 4944 Ultra SCSI adapter",
364 ID_AHA_2930U & ID_DEV_VENDOR_MASK,
366 "Adaptec 2930 Ultra SCSI adapter",
370 ID_AHA_2940U_PRO & ID_DEV_VENDOR_MASK,
372 "Adaptec 2940 Pro Ultra SCSI adapter",
376 ID_AHA_2940U_CN & ID_DEV_VENDOR_MASK,
378 "Adaptec 2940/CN Ultra SCSI adapter",
381 /* Ignore all SISL (AAC on MB) based controllers. */
388 /* aic7890 based controllers */
392 "Adaptec 2930 Ultra2 SCSI adapter",
398 "Adaptec 2940B Ultra2 SCSI adapter",
404 "Adaptec 2940 Ultra2 SCSI adapter (OEM)",
410 "Adaptec 2940 Ultra2 SCSI adapter",
416 "Adaptec 2950 Ultra2 SCSI adapter",
422 "Adaptec aic7890/91 Ultra2 SCSI adapter (ARO)",
428 "Adaptec AAA-131 Ultra2 RAID adapter",
431 /* aic7892 based controllers */
435 "Adaptec 29160 Ultra160 SCSI adapter",
441 "Adaptec (Compaq OEM) 29160 Ultra160 SCSI adapter",
447 "Adaptec 29160N Ultra160 SCSI adapter",
453 "Adaptec 29160C Ultra160 SCSI adapter",
459 "Adaptec 29160B Ultra160 SCSI adapter",
465 "Adaptec 19160B Ultra160 SCSI adapter",
471 "Adaptec aic7892 Ultra160 SCSI adapter (ARO)",
474 /* aic7895 based controllers */
478 "Adaptec 2940/DUAL Ultra SCSI adapter",
484 "Adaptec 3940A Ultra SCSI adapter",
490 "Adaptec 3944A Ultra SCSI adapter",
496 "Adaptec aic7895 Ultra SCSI adapter (ARO)",
499 /* aic7896/97 based controllers */
503 "Adaptec 3950B Ultra2 SCSI adapter",
509 "Adaptec 3950B Ultra2 SCSI adapter",
515 "Adaptec 3950D Ultra2 SCSI adapter",
521 "Adaptec 3950D Ultra2 SCSI adapter",
527 "Adaptec aic7896/97 Ultra2 SCSI adapter (ARO)",
530 /* aic7899 based controllers */
534 "Adaptec 3960D Ultra160 SCSI adapter",
540 "Adaptec (Compaq OEM) 3960D Ultra160 SCSI adapter",
546 "Adaptec aic7899 Ultra160 SCSI adapter (ARO)",
549 /* Generic chip probes for devices we don't know 'exactly' */
551 ID_AIC7850 & ID_DEV_VENDOR_MASK,
553 "Adaptec aic7850 SCSI adapter",
557 ID_AIC7855 & ID_DEV_VENDOR_MASK,
559 "Adaptec aic7855 SCSI adapter",
563 ID_AIC7859 & ID_DEV_VENDOR_MASK,
565 "Adaptec aic7859 SCSI adapter",
569 ID_AIC7860 & ID_DEV_VENDOR_MASK,
571 "Adaptec aic7860 Ultra SCSI adapter",
575 ID_AIC7870 & ID_DEV_VENDOR_MASK,
577 "Adaptec aic7870 SCSI adapter",
581 ID_AIC7880 & ID_DEV_VENDOR_MASK,
583 "Adaptec aic7880 Ultra SCSI adapter",
587 ID_AIC7890 & ID_9005_GENERIC_MASK,
588 ID_9005_GENERIC_MASK,
589 "Adaptec aic7890/91 Ultra2 SCSI adapter",
593 ID_AIC7892 & ID_9005_GENERIC_MASK,
594 ID_9005_GENERIC_MASK,
595 "Adaptec aic7892 Ultra160 SCSI adapter",
599 ID_AIC7895 & ID_DEV_VENDOR_MASK,
601 "Adaptec aic7895 Ultra SCSI adapter",
605 ID_AIC7896 & ID_9005_GENERIC_MASK,
606 ID_9005_GENERIC_MASK,
607 "Adaptec aic7896/97 Ultra2 SCSI adapter",
611 ID_AIC7899 & ID_9005_GENERIC_MASK,
612 ID_9005_GENERIC_MASK,
613 "Adaptec aic7899 Ultra160 SCSI adapter",
617 ID_AIC7810 & ID_DEV_VENDOR_MASK,
619 "Adaptec aic7810 RAID memory controller",
623 ID_AIC7815 & ID_DEV_VENDOR_MASK,
625 "Adaptec aic7815 RAID memory controller",
630 const u_int ahc_num_pci_devs = NUM_ELEMENTS(ahc_pci_ident_table);
632 #define AHC_394X_SLOT_CHANNEL_A 4
633 #define AHC_394X_SLOT_CHANNEL_B 5
635 #define AHC_398X_SLOT_CHANNEL_A 4
636 #define AHC_398X_SLOT_CHANNEL_B 8
637 #define AHC_398X_SLOT_CHANNEL_C 12
639 #define AHC_494X_SLOT_CHANNEL_A 4
640 #define AHC_494X_SLOT_CHANNEL_B 5
641 #define AHC_494X_SLOT_CHANNEL_C 6
642 #define AHC_494X_SLOT_CHANNEL_D 7
644 #define DEVCONFIG 0x40
645 #define PCIERRGENDIS 0x80000000ul
646 #define SCBSIZE32 0x00010000ul /* aic789X only */
647 #define REXTVALID 0x00001000ul /* ultra cards only */
648 #define MPORTMODE 0x00000400ul /* aic7870+ only */
649 #define RAMPSM 0x00000200ul /* aic7870+ only */
650 #define VOLSENSE 0x00000100ul
651 #define PCI64BIT 0x00000080ul /* 64Bit PCI bus (Ultra2 Only)*/
652 #define SCBRAMSEL 0x00000080ul
653 #define MRDCEN 0x00000040ul
654 #define EXTSCBTIME 0x00000020ul /* aic7870 only */
655 #define EXTSCBPEN 0x00000010ul /* aic7870 only */
656 #define BERREN 0x00000008ul
657 #define DACEN 0x00000004ul
658 #define STPWLEVEL 0x00000002ul
659 #define DIFACTNEGEN 0x00000001ul /* aic7870 only */
661 #define CSIZE_LATTIME 0x0c
662 #define CACHESIZE 0x0000003ful /* only 5 bits */
663 #define LATTIME 0x0000ff00ul
665 /* PCI STATUS definitions */
673 static int ahc_9005_subdevinfo_valid(uint16_t vendor, uint16_t device,
674 uint16_t subvendor, uint16_t subdevice);
675 static int ahc_ext_scbram_present(struct ahc_softc *ahc);
676 static void ahc_scbram_config(struct ahc_softc *ahc, int enable,
677 int pcheck, int fast, int large);
678 static void ahc_probe_ext_scbram(struct ahc_softc *ahc);
679 static void check_extport(struct ahc_softc *ahc, u_int *sxfrctl1);
680 static void ahc_parse_pci_eeprom(struct ahc_softc *ahc,
681 struct seeprom_config *sc);
682 static void configure_termination(struct ahc_softc *ahc,
683 struct seeprom_descriptor *sd,
684 u_int adapter_control,
687 static void ahc_new_term_detect(struct ahc_softc *ahc,
692 int *eeprom_present);
693 static void aic787X_cable_detect(struct ahc_softc *ahc, int *internal50_present,
694 int *internal68_present,
695 int *externalcable_present,
696 int *eeprom_present);
697 static void aic785X_cable_detect(struct ahc_softc *ahc, int *internal50_present,
698 int *externalcable_present,
699 int *eeprom_present);
700 static void write_brdctl(struct ahc_softc *ahc, uint8_t value);
701 static uint8_t read_brdctl(struct ahc_softc *ahc);
702 static void ahc_pci_intr(struct ahc_softc *ahc);
703 static int ahc_pci_chip_init(struct ahc_softc *ahc);
704 static int ahc_pci_suspend(struct ahc_softc *ahc);
705 static int ahc_pci_resume(struct ahc_softc *ahc);
708 ahc_9005_subdevinfo_valid(uint16_t device, uint16_t vendor,
709 uint16_t subdevice, uint16_t subvendor)
713 /* Default to invalid. */
716 && subvendor == 0x9005
717 && subdevice != device
718 && SUBID_9005_TYPE_KNOWN(subdevice) != 0) {
720 switch (SUBID_9005_TYPE(subdevice)) {
721 case SUBID_9005_TYPE_MB:
723 case SUBID_9005_TYPE_CARD:
724 case SUBID_9005_TYPE_LCCARD:
726 * Currently only trust Adaptec cards to
727 * get the sub device info correct.
729 if (DEVID_9005_TYPE(device) == DEVID_9005_TYPE_HBA)
732 case SUBID_9005_TYPE_RAID:
741 struct ahc_pci_identity *
742 ahc_find_pci_device(ahc_dev_softc_t pci)
749 struct ahc_pci_identity *entry;
752 vendor = ahc_pci_read_config(pci, PCIR_DEVVENDOR, /*bytes*/2);
753 device = ahc_pci_read_config(pci, PCIR_DEVICE, /*bytes*/2);
754 subvendor = ahc_pci_read_config(pci, PCIR_SUBVEND_0, /*bytes*/2);
755 subdevice = ahc_pci_read_config(pci, PCIR_SUBDEV_0, /*bytes*/2);
756 full_id = ahc_compose_id(device, vendor, subdevice, subvendor);
759 * If the second function is not hooked up, ignore it.
760 * Unfortunately, not all MB vendors implement the
761 * subdevice ID as per the Adaptec spec, so do our best
762 * to sanity check it prior to accepting the subdevice
765 if (ahc_get_pci_function(pci) > 0
766 && ahc_9005_subdevinfo_valid(vendor, device, subvendor, subdevice)
767 && SUBID_9005_MFUNCENB(subdevice) == 0)
770 for (i = 0; i < ahc_num_pci_devs; i++) {
771 entry = &ahc_pci_ident_table[i];
772 if (entry->full_id == (full_id & entry->id_mask)) {
773 /* Honor exclusion entries. */
774 if (entry->name == NULL)
783 ahc_pci_config(struct ahc_softc *ahc, struct ahc_pci_identity *entry)
796 error = entry->setup(ahc);
799 ahc->chip |= AHC_PCI;
800 ahc->description = entry->name;
802 ahc_power_state_change(ahc, AHC_POWER_STATE_D0);
804 error = ahc_pci_map_registers(ahc);
809 * Before we continue probing the card, ensure that
810 * its interrupts are *disabled*. We don't want
811 * a misstep to hang the machine in an interrupt
814 ahc_intr_enable(ahc, FALSE);
816 devconfig = ahc_pci_read_config(ahc->dev_softc, DEVCONFIG, /*bytes*/4);
819 * If we need to support high memory, enable dual
820 * address cycles. This bit must be set to enable
821 * high address bit generation even if we are on a
822 * 64bit bus (PCI64BIT set in devconfig).
824 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
827 printf("%s: Enabling 39Bit Addressing\n",
832 /* Ensure that pci error generation, a test feature, is disabled. */
833 devconfig |= PCIERRGENDIS;
835 ahc_pci_write_config(ahc->dev_softc, DEVCONFIG, devconfig, /*bytes*/4);
837 /* Ensure busmastering is enabled */
838 command = ahc_pci_read_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/2);
839 command |= PCIM_CMD_BUSMASTEREN;
841 ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND, command, /*bytes*/2);
843 /* On all PCI adapters, we allow SCB paging */
844 ahc->flags |= AHC_PAGESCBS;
846 error = ahc_softc_init(ahc);
851 * Disable PCI parity error checking. Users typically
852 * do this to work around broken PCI chipsets that get
853 * the parity timing wrong and thus generate lots of spurious
854 * errors. The chip only allows us to disable *all* parity
855 * error reporting when doing this, so CIO bus, scb ram, and
856 * scratch ram parity errors will be ignored too.
858 if ((ahc->flags & AHC_DISABLE_PCI_PERR) != 0)
859 ahc->seqctl |= FAILDIS;
861 ahc->bus_intr = ahc_pci_intr;
862 ahc->bus_chip_init = ahc_pci_chip_init;
863 ahc->bus_suspend = ahc_pci_suspend;
864 ahc->bus_resume = ahc_pci_resume;
866 /* Remeber how the card was setup in case there is no SEEPROM */
867 if ((ahc_inb(ahc, HCNTRL) & POWRDN) == 0) {
869 if ((ahc->features & AHC_ULTRA2) != 0)
870 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID;
872 our_id = ahc_inb(ahc, SCSIID) & OID;
873 sxfrctl1 = ahc_inb(ahc, SXFRCTL1) & STPWEN;
874 scsiseq = ahc_inb(ahc, SCSISEQ);
881 error = ahc_reset(ahc, /*reinit*/FALSE);
885 if ((ahc->features & AHC_DT) != 0) {
888 /* Perform ALT-Mode Setup */
889 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE;
890 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE);
891 ahc_outb(ahc, OPTIONMODE,
892 OPTIONMODE_DEFAULTS|AUTOACKEN|BUSFREEREV|EXPPHASEDIS);
893 ahc_outb(ahc, SFUNCT, sfunct);
895 /* Normal mode setup */
896 ahc_outb(ahc, CRCCONTROL1, CRCVALCHKEN|CRCENDCHKEN|CRCREQCHKEN
900 dscommand0 = ahc_inb(ahc, DSCOMMAND0);
901 dscommand0 |= MPARCKEN|CACHETHEN;
902 if ((ahc->features & AHC_ULTRA2) != 0) {
905 * DPARCKEN doesn't work correctly on
906 * some MBs so don't use it.
908 dscommand0 &= ~DPARCKEN;
912 * Handle chips that must have cache line
913 * streaming (dis/en)abled.
915 if ((ahc->bugs & AHC_CACHETHEN_DIS_BUG) != 0)
916 dscommand0 |= CACHETHEN;
918 if ((ahc->bugs & AHC_CACHETHEN_BUG) != 0)
919 dscommand0 &= ~CACHETHEN;
921 ahc_outb(ahc, DSCOMMAND0, dscommand0);
924 ahc_pci_read_config(ahc->dev_softc, CSIZE_LATTIME,
925 /*bytes*/1) & CACHESIZE;
926 ahc->pci_cachesize *= 4;
928 if ((ahc->bugs & AHC_PCI_2_1_RETRY_BUG) != 0
929 && ahc->pci_cachesize == 4) {
931 ahc_pci_write_config(ahc->dev_softc, CSIZE_LATTIME,
933 ahc->pci_cachesize = 0;
937 * We cannot perform ULTRA speeds without the presense
938 * of the external precision resistor.
940 if ((ahc->features & AHC_ULTRA) != 0) {
943 devconfig = ahc_pci_read_config(ahc->dev_softc,
944 DEVCONFIG, /*bytes*/4);
945 if ((devconfig & REXTVALID) == 0)
946 ahc->features &= ~AHC_ULTRA;
949 /* See if we have a SEEPROM and perform auto-term */
950 check_extport(ahc, &sxfrctl1);
953 * Take the LED out of diagnostic mode
955 sblkctl = ahc_inb(ahc, SBLKCTL);
956 ahc_outb(ahc, SBLKCTL, (sblkctl & ~(DIAGLEDEN|DIAGLEDON)));
958 if ((ahc->features & AHC_ULTRA2) != 0) {
959 ahc_outb(ahc, DFF_THRSH, RD_DFTHRSH_MAX|WR_DFTHRSH_MAX);
961 ahc_outb(ahc, DSPCISTATUS, DFTHRSH_100);
964 if (ahc->flags & AHC_USEDEFAULTS) {
966 * PCI Adapter default setup
967 * Should only be used if the adapter does not have
970 /* See if someone else set us up already */
971 if ((ahc->flags & AHC_NO_BIOS_INIT) == 0
973 printf("%s: Using left over BIOS settings\n",
975 ahc->flags &= ~AHC_USEDEFAULTS;
976 ahc->flags |= AHC_BIOS_ENABLED;
979 * Assume only one connector and always turn
985 ahc_outb(ahc, SCSICONF, our_id|ENSPCHK|RESET_SCSI);
987 ahc->our_id = our_id;
991 * Take a look to see if we have external SRAM.
992 * We currently do not attempt to use SRAM that is
993 * shared among multiple controllers.
995 ahc_probe_ext_scbram(ahc);
998 * Record our termination setting for the
999 * generic initialization routine.
1001 if ((sxfrctl1 & STPWEN) != 0)
1002 ahc->flags |= AHC_TERM_ENB_A;
1005 * Save chip register configuration data for chip resets
1006 * that occur during runtime and resume events.
1008 ahc->bus_softc.pci_softc.devconfig =
1009 ahc_pci_read_config(ahc->dev_softc, DEVCONFIG, /*bytes*/4);
1010 ahc->bus_softc.pci_softc.command =
1011 ahc_pci_read_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/1);
1012 ahc->bus_softc.pci_softc.csize_lattime =
1013 ahc_pci_read_config(ahc->dev_softc, CSIZE_LATTIME, /*bytes*/1);
1014 ahc->bus_softc.pci_softc.dscommand0 = ahc_inb(ahc, DSCOMMAND0);
1015 ahc->bus_softc.pci_softc.dspcistatus = ahc_inb(ahc, DSPCISTATUS);
1016 if ((ahc->features & AHC_DT) != 0) {
1019 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE;
1020 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE);
1021 ahc->bus_softc.pci_softc.optionmode = ahc_inb(ahc, OPTIONMODE);
1022 ahc->bus_softc.pci_softc.targcrccnt = ahc_inw(ahc, TARGCRCCNT);
1023 ahc_outb(ahc, SFUNCT, sfunct);
1024 ahc->bus_softc.pci_softc.crccontrol1 =
1025 ahc_inb(ahc, CRCCONTROL1);
1027 if ((ahc->features & AHC_MULTI_FUNC) != 0)
1028 ahc->bus_softc.pci_softc.scbbaddr = ahc_inb(ahc, SCBBADDR);
1030 if ((ahc->features & AHC_ULTRA2) != 0)
1031 ahc->bus_softc.pci_softc.dff_thrsh = ahc_inb(ahc, DFF_THRSH);
1033 /* Core initialization */
1034 error = ahc_init(ahc);
1039 * Allow interrupts now that we are completely setup.
1041 error = ahc_pci_map_int(ahc);
1047 * Link this softc in with all other ahc instances.
1049 ahc_softc_insert(ahc);
1050 ahc_list_unlock(&l);
1055 * Test for the presense of external sram in an
1056 * "unshared" configuration.
1059 ahc_ext_scbram_present(struct ahc_softc *ahc)
1066 chip = ahc->chip & AHC_CHIPID_MASK;
1067 devconfig = ahc_pci_read_config(ahc->dev_softc,
1068 DEVCONFIG, /*bytes*/4);
1069 single_user = (devconfig & MPORTMODE) != 0;
1071 if ((ahc->features & AHC_ULTRA2) != 0)
1072 ramps = (ahc_inb(ahc, DSCOMMAND0) & RAMPS) != 0;
1073 else if (chip == AHC_AIC7895 || chip == AHC_AIC7895C)
1075 * External SCBRAM arbitration is flakey
1076 * on these chips. Unfortunately this means
1077 * we don't use the extra SCB ram space on the
1081 else if (chip >= AHC_AIC7870)
1082 ramps = (devconfig & RAMPSM) != 0;
1086 if (ramps && single_user)
1092 * Enable external scbram.
1095 ahc_scbram_config(struct ahc_softc *ahc, int enable, int pcheck,
1096 int fast, int large)
1100 if (ahc->features & AHC_MULTI_FUNC) {
1102 * Set the SCB Base addr (highest address bit)
1103 * depending on which channel we are.
1105 ahc_outb(ahc, SCBBADDR, ahc_get_pci_function(ahc->dev_softc));
1108 ahc->flags &= ~AHC_LSCBS_ENABLED;
1110 ahc->flags |= AHC_LSCBS_ENABLED;
1111 devconfig = ahc_pci_read_config(ahc->dev_softc, DEVCONFIG, /*bytes*/4);
1112 if ((ahc->features & AHC_ULTRA2) != 0) {
1115 dscommand0 = ahc_inb(ahc, DSCOMMAND0);
1117 dscommand0 &= ~INTSCBRAMSEL;
1119 dscommand0 |= INTSCBRAMSEL;
1121 dscommand0 &= ~USCBSIZE32;
1123 dscommand0 |= USCBSIZE32;
1124 ahc_outb(ahc, DSCOMMAND0, dscommand0);
1127 devconfig &= ~EXTSCBTIME;
1129 devconfig |= EXTSCBTIME;
1131 devconfig &= ~SCBRAMSEL;
1133 devconfig |= SCBRAMSEL;
1135 devconfig &= ~SCBSIZE32;
1137 devconfig |= SCBSIZE32;
1140 devconfig |= EXTSCBPEN;
1142 devconfig &= ~EXTSCBPEN;
1144 ahc_pci_write_config(ahc->dev_softc, DEVCONFIG, devconfig, /*bytes*/4);
1148 * Take a look to see if we have external SRAM.
1149 * We currently do not attempt to use SRAM that is
1150 * shared among multiple controllers.
1153 ahc_probe_ext_scbram(struct ahc_softc *ahc)
1168 if (ahc_ext_scbram_present(ahc) == 0)
1172 * Probe for the best parameters to use.
1174 ahc_scbram_config(ahc, /*enable*/TRUE, pcheck, fast, large);
1175 num_scbs = ahc_probe_scbs(ahc);
1176 if (num_scbs == 0) {
1177 /* The SRAM wasn't really present. */
1183 * Clear any outstanding parity error
1184 * and ensure that parity error reporting
1187 ahc_outb(ahc, SEQCTL, 0);
1188 ahc_outb(ahc, CLRINT, CLRPARERR);
1189 ahc_outb(ahc, CLRINT, CLRBRKADRINT);
1191 /* Now see if we can do parity */
1192 ahc_scbram_config(ahc, enable, /*pcheck*/TRUE, fast, large);
1193 num_scbs = ahc_probe_scbs(ahc);
1194 if ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0
1195 || (ahc_inb(ahc, ERROR) & MPARERR) == 0)
1198 /* Clear any resulting parity error */
1199 ahc_outb(ahc, CLRINT, CLRPARERR);
1200 ahc_outb(ahc, CLRINT, CLRBRKADRINT);
1202 /* Now see if we can do fast timing */
1203 ahc_scbram_config(ahc, enable, pcheck, /*fast*/TRUE, large);
1204 test_num_scbs = ahc_probe_scbs(ahc);
1205 if (test_num_scbs == num_scbs
1206 && ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0
1207 || (ahc_inb(ahc, ERROR) & MPARERR) == 0))
1211 * See if we can use large SCBs and still maintain
1212 * the same overall count of SCBs.
1214 if ((ahc->features & AHC_LARGE_SCBS) != 0) {
1215 ahc_scbram_config(ahc, enable, pcheck, fast, /*large*/TRUE);
1216 test_num_scbs = ahc_probe_scbs(ahc);
1217 if (test_num_scbs >= num_scbs) {
1219 num_scbs = test_num_scbs;
1220 if (num_scbs >= 64) {
1222 * We have enough space to move the
1223 * "busy targets table" into SCB space
1224 * and make it qualify all the way to the
1227 ahc->flags |= AHC_SCB_BTT;
1233 * Disable parity error reporting until we
1234 * can load instruction ram.
1236 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS);
1237 /* Clear any latched parity error */
1238 ahc_outb(ahc, CLRINT, CLRPARERR);
1239 ahc_outb(ahc, CLRINT, CLRBRKADRINT);
1240 if (bootverbose && enable) {
1241 printf("%s: External SRAM, %s access%s, %dbytes/SCB\n",
1242 ahc_name(ahc), fast ? "fast" : "slow",
1243 pcheck ? ", parity checking enabled" : "",
1246 ahc_scbram_config(ahc, enable, pcheck, fast, large);
1250 * Perform some simple tests that should catch situations where
1251 * our registers are invalidly mapped.
1254 ahc_pci_test_register_access(struct ahc_softc *ahc)
1264 * Enable PCI error interrupt status, but suppress NMIs
1265 * generated by SERR raised due to target aborts.
1267 cmd = ahc_pci_read_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/2);
1268 ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND,
1269 cmd & ~PCIM_CMD_SERRESPEN, /*bytes*/2);
1272 * First a simple test to see if any
1273 * registers can be read. Reading
1274 * HCNTRL has no side effects and has
1275 * at least one bit that is guaranteed to
1276 * be zero so it is a good register to
1277 * use for this test.
1279 hcntrl = ahc_inb(ahc, HCNTRL);
1284 * Next create a situation where write combining
1285 * or read prefetching could be initiated by the
1286 * CPU or host bridge. Our device does not support
1287 * either, so look for data corruption and/or flagged
1290 ahc_outb(ahc, HCNTRL, hcntrl|PAUSE);
1291 while (ahc_is_paused(ahc) == 0)
1294 /* Clear any PCI errors that occurred before our driver attached. */
1295 status1 = ahc_pci_read_config(ahc->dev_softc,
1296 PCIR_STATUS + 1, /*bytes*/1);
1297 ahc_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1,
1298 status1, /*bytes*/1);
1299 ahc_outb(ahc, CLRINT, CLRPARERR);
1301 ahc_outb(ahc, SEQCTL, PERRORDIS);
1302 ahc_outb(ahc, SCBPTR, 0);
1303 ahc_outl(ahc, SCB_BASE, 0x5aa555aa);
1304 if (ahc_inl(ahc, SCB_BASE) != 0x5aa555aa)
1307 status1 = ahc_pci_read_config(ahc->dev_softc,
1308 PCIR_STATUS + 1, /*bytes*/1);
1309 if ((status1 & STA) != 0)
1315 /* Silently clear any latched errors. */
1316 status1 = ahc_pci_read_config(ahc->dev_softc,
1317 PCIR_STATUS + 1, /*bytes*/1);
1318 ahc_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1,
1319 status1, /*bytes*/1);
1320 ahc_outb(ahc, CLRINT, CLRPARERR);
1321 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS);
1322 ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND, cmd, /*bytes*/2);
1327 * Check the external port logic for a serial eeprom
1328 * and termination/cable detection contrls.
1331 check_extport(struct ahc_softc *ahc, u_int *sxfrctl1)
1333 struct seeprom_descriptor sd;
1334 struct seeprom_config *sc;
1339 sd.sd_control_offset = SEECTL;
1340 sd.sd_status_offset = SEECTL;
1341 sd.sd_dataout_offset = SEECTL;
1342 sc = ahc->seep_config;
1345 * For some multi-channel devices, the c46 is simply too
1346 * small to work. For the other controller types, we can
1347 * get our information from either SEEPROM type. Set the
1348 * type to start our probe with accordingly.
1350 if (ahc->flags & AHC_LARGE_SEEPROM)
1351 sd.sd_chip = C56_66;
1362 have_seeprom = ahc_acquire_seeprom(ahc, &sd);
1366 printf("%s: Reading SEEPROM...", ahc_name(ahc));
1371 start_addr = 32 * (ahc->channel - 'A');
1373 have_seeprom = ahc_read_seeprom(&sd, (uint16_t *)sc,
1378 have_seeprom = ahc_verify_cksum(sc);
1380 if (have_seeprom != 0 || sd.sd_chip == C56_66) {
1382 if (have_seeprom == 0)
1383 printf ("checksum error\n");
1389 sd.sd_chip = C56_66;
1391 ahc_release_seeprom(&sd);
1394 if (!have_seeprom) {
1396 * Pull scratch ram settings and treat them as
1397 * if they are the contents of an seeprom if
1398 * the 'ADPT' signature is found in SCB2.
1399 * We manually compose the data as 16bit values
1400 * to avoid endian issues.
1402 ahc_outb(ahc, SCBPTR, 2);
1403 if (ahc_inb(ahc, SCB_BASE) == 'A'
1404 && ahc_inb(ahc, SCB_BASE + 1) == 'D'
1405 && ahc_inb(ahc, SCB_BASE + 2) == 'P'
1406 && ahc_inb(ahc, SCB_BASE + 3) == 'T') {
1410 sc_data = (uint16_t *)sc;
1411 for (i = 0; i < 32; i++, sc_data++) {
1415 *sc_data = ahc_inb(ahc, SRAM_BASE + j)
1416 | ahc_inb(ahc, SRAM_BASE + j + 1) << 8;
1418 have_seeprom = ahc_verify_cksum(sc);
1420 ahc->flags |= AHC_SCB_CONFIG_USED;
1423 * Clear any SCB parity errors in case this data and
1424 * its associated parity was not initialized by the BIOS
1426 ahc_outb(ahc, CLRINT, CLRPARERR);
1427 ahc_outb(ahc, CLRINT, CLRBRKADRINT);
1430 if (!have_seeprom) {
1432 printf("%s: No SEEPROM available.\n", ahc_name(ahc));
1433 ahc->flags |= AHC_USEDEFAULTS;
1434 free(ahc->seep_config, M_DEVBUF);
1435 ahc->seep_config = NULL;
1438 ahc_parse_pci_eeprom(ahc, sc);
1442 * Cards that have the external logic necessary to talk to
1443 * a SEEPROM, are almost certain to have the remaining logic
1444 * necessary for auto-termination control. This assumption
1445 * hasn't failed yet...
1447 have_autoterm = have_seeprom;
1450 * Some low-cost chips have SEEPROM and auto-term control built
1451 * in, instead of using a GAL. They can tell us directly
1452 * if the termination logic is enabled.
1454 if ((ahc->features & AHC_SPIOCAP) != 0) {
1455 if ((ahc_inb(ahc, SPIOCAP) & SSPIOCPS) == 0)
1456 have_autoterm = FALSE;
1459 if (have_autoterm) {
1460 ahc->flags |= AHC_HAS_TERM_LOGIC;
1461 ahc_acquire_seeprom(ahc, &sd);
1462 configure_termination(ahc, &sd, sc->adapter_control, sxfrctl1);
1463 ahc_release_seeprom(&sd);
1464 } else if (have_seeprom) {
1465 *sxfrctl1 &= ~STPWEN;
1466 if ((sc->adapter_control & CFSTERM) != 0)
1467 *sxfrctl1 |= STPWEN;
1469 printf("%s: Low byte termination %sabled\n",
1471 (*sxfrctl1 & STPWEN) ? "en" : "dis");
1476 ahc_parse_pci_eeprom(struct ahc_softc *ahc, struct seeprom_config *sc)
1479 * Put the data we've collected down into SRAM
1480 * where ahc_init will find it.
1483 int max_targ = sc->max_targets & CFMAXTARG;
1485 uint16_t discenable;
1490 if ((sc->adapter_control & CFULTRAEN) != 0) {
1492 * Determine if this adapter has a "newstyle"
1495 for (i = 0; i < max_targ; i++) {
1496 if ((sc->device_flags[i] & CFSYNCHISULTRA) != 0) {
1497 ahc->flags |= AHC_NEWEEPROM_FMT;
1503 for (i = 0; i < max_targ; i++) {
1505 uint16_t target_mask;
1507 target_mask = 0x01 << i;
1508 if (sc->device_flags[i] & CFDISC)
1509 discenable |= target_mask;
1510 if ((ahc->flags & AHC_NEWEEPROM_FMT) != 0) {
1511 if ((sc->device_flags[i] & CFSYNCHISULTRA) != 0)
1512 ultraenb |= target_mask;
1513 } else if ((sc->adapter_control & CFULTRAEN) != 0) {
1514 ultraenb |= target_mask;
1516 if ((sc->device_flags[i] & CFXFER) == 0x04
1517 && (ultraenb & target_mask) != 0) {
1518 /* Treat 10MHz as a non-ultra speed */
1519 sc->device_flags[i] &= ~CFXFER;
1520 ultraenb &= ~target_mask;
1522 if ((ahc->features & AHC_ULTRA2) != 0) {
1525 if (sc->device_flags[i] & CFSYNCH)
1526 offset = MAX_OFFSET_ULTRA2;
1529 ahc_outb(ahc, TARG_OFFSET + i, offset);
1532 * The ultra enable bits contain the
1533 * high bit of the ultra2 sync rate
1536 scsirate = (sc->device_flags[i] & CFXFER)
1537 | ((ultraenb & target_mask) ? 0x8 : 0x0);
1538 if (sc->device_flags[i] & CFWIDEB)
1539 scsirate |= WIDEXFER;
1541 scsirate = (sc->device_flags[i] & CFXFER) << 4;
1542 if (sc->device_flags[i] & CFSYNCH)
1544 if (sc->device_flags[i] & CFWIDEB)
1545 scsirate |= WIDEXFER;
1547 ahc_outb(ahc, TARG_SCSIRATE + i, scsirate);
1549 ahc->our_id = sc->brtime_id & CFSCSIID;
1551 scsi_conf = (ahc->our_id & 0x7);
1552 if (sc->adapter_control & CFSPARITY)
1553 scsi_conf |= ENSPCHK;
1554 if (sc->adapter_control & CFRESETB)
1555 scsi_conf |= RESET_SCSI;
1557 ahc->flags |= (sc->adapter_control & CFBOOTCHAN) >> CFBOOTCHANSHIFT;
1559 if (sc->bios_control & CFEXTEND)
1560 ahc->flags |= AHC_EXTENDED_TRANS_A;
1562 if (sc->bios_control & CFBIOSEN)
1563 ahc->flags |= AHC_BIOS_ENABLED;
1564 if (ahc->features & AHC_ULTRA
1565 && (ahc->flags & AHC_NEWEEPROM_FMT) == 0) {
1566 /* Should we enable Ultra mode? */
1567 if (!(sc->adapter_control & CFULTRAEN))
1568 /* Treat us as a non-ultra card */
1572 if (sc->signature == CFSIGNATURE
1573 || sc->signature == CFSIGNATURE2) {
1576 /* Honor the STPWLEVEL settings */
1577 devconfig = ahc_pci_read_config(ahc->dev_softc,
1578 DEVCONFIG, /*bytes*/4);
1579 devconfig &= ~STPWLEVEL;
1580 if ((sc->bios_control & CFSTPWLEVEL) != 0)
1581 devconfig |= STPWLEVEL;
1582 ahc_pci_write_config(ahc->dev_softc, DEVCONFIG,
1583 devconfig, /*bytes*/4);
1585 /* Set SCSICONF info */
1586 ahc_outb(ahc, SCSICONF, scsi_conf);
1587 ahc_outb(ahc, DISC_DSB, ~(discenable & 0xff));
1588 ahc_outb(ahc, DISC_DSB + 1, ~((discenable >> 8) & 0xff));
1589 ahc_outb(ahc, ULTRA_ENB, ultraenb & 0xff);
1590 ahc_outb(ahc, ULTRA_ENB + 1, (ultraenb >> 8) & 0xff);
1594 configure_termination(struct ahc_softc *ahc,
1595 struct seeprom_descriptor *sd,
1596 u_int adapter_control,
1604 * Update the settings in sxfrctl1 to match the
1605 * termination settings
1610 * SEECS must be on for the GALS to latch
1611 * the data properly. Be sure to leave MS
1612 * on or we will release the seeprom.
1614 SEEPROM_OUTB(sd, sd->sd_MS | sd->sd_CS);
1615 if ((adapter_control & CFAUTOTERM) != 0
1616 || (ahc->features & AHC_NEW_TERMCTL) != 0) {
1617 int internal50_present;
1618 int internal68_present;
1619 int externalcable_present;
1631 if ((ahc->features & AHC_NEW_TERMCTL) != 0) {
1632 ahc_new_term_detect(ahc, &enableSEC_low,
1637 if ((adapter_control & CFSEAUTOTERM) == 0) {
1639 printf("%s: Manual SE Termination\n",
1641 enableSEC_low = (adapter_control & CFSELOWTERM);
1643 (adapter_control & CFSEHIGHTERM);
1645 if ((adapter_control & CFAUTOTERM) == 0) {
1647 printf("%s: Manual LVD Termination\n",
1649 enablePRI_low = (adapter_control & CFSTERM);
1650 enablePRI_high = (adapter_control & CFWSTERM);
1652 /* Make the table calculations below happy */
1653 internal50_present = 0;
1654 internal68_present = 1;
1655 externalcable_present = 1;
1656 } else if ((ahc->features & AHC_SPIOCAP) != 0) {
1657 aic785X_cable_detect(ahc, &internal50_present,
1658 &externalcable_present,
1660 /* Can never support a wide connector. */
1661 internal68_present = 0;
1663 aic787X_cable_detect(ahc, &internal50_present,
1664 &internal68_present,
1665 &externalcable_present,
1669 if ((ahc->features & AHC_WIDE) == 0)
1670 internal68_present = 0;
1673 && (ahc->features & AHC_ULTRA2) == 0) {
1674 printf("%s: internal 50 cable %s present",
1676 internal50_present ? "is":"not");
1678 if ((ahc->features & AHC_WIDE) != 0)
1679 printf(", internal 68 cable %s present",
1680 internal68_present ? "is":"not");
1681 printf("\n%s: external cable %s present\n",
1683 externalcable_present ? "is":"not");
1686 printf("%s: BIOS eeprom %s present\n",
1687 ahc_name(ahc), eeprom_present ? "is" : "not");
1689 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0) {
1691 * The 50 pin connector is a separate bus,
1692 * so force it to always be terminated.
1693 * In the future, perform current sensing
1694 * to determine if we are in the middle of
1695 * a properly terminated bus.
1697 internal50_present = 0;
1701 * Now set the termination based on what
1703 * Flash Enable = BRDDAT7
1704 * Secondary High Term Enable = BRDDAT6
1705 * Secondary Low Term Enable = BRDDAT5 (7890)
1706 * Primary High Term Enable = BRDDAT4 (7890)
1708 if ((ahc->features & AHC_ULTRA2) == 0
1709 && (internal50_present != 0)
1710 && (internal68_present != 0)
1711 && (externalcable_present != 0)) {
1712 printf("%s: Illegal cable configuration!!. "
1713 "Only two connectors on the "
1714 "adapter may be used at a "
1715 "time!\n", ahc_name(ahc));
1718 * Pretend there are no cables in the hope
1719 * that having all of the termination on
1720 * gives us a more stable bus.
1722 internal50_present = 0;
1723 internal68_present = 0;
1724 externalcable_present = 0;
1727 if ((ahc->features & AHC_WIDE) != 0
1728 && ((externalcable_present == 0)
1729 || (internal68_present == 0)
1730 || (enableSEC_high != 0))) {
1733 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0)
1734 printf("%s: 68 pin termination "
1735 "Enabled\n", ahc_name(ahc));
1737 printf("%s: %sHigh byte termination "
1738 "Enabled\n", ahc_name(ahc),
1739 enableSEC_high ? "Secondary "
1744 sum = internal50_present + internal68_present
1745 + externalcable_present;
1746 if (sum < 2 || (enableSEC_low != 0)) {
1747 if ((ahc->features & AHC_ULTRA2) != 0)
1750 *sxfrctl1 |= STPWEN;
1752 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0)
1753 printf("%s: 50 pin termination "
1754 "Enabled\n", ahc_name(ahc));
1756 printf("%s: %sLow byte termination "
1757 "Enabled\n", ahc_name(ahc),
1758 enableSEC_low ? "Secondary "
1763 if (enablePRI_low != 0) {
1764 *sxfrctl1 |= STPWEN;
1766 printf("%s: Primary Low Byte termination "
1767 "Enabled\n", ahc_name(ahc));
1771 * Setup STPWEN before setting up the rest of
1772 * the termination per the tech note on the U160 cards.
1774 ahc_outb(ahc, SXFRCTL1, *sxfrctl1);
1776 if (enablePRI_high != 0) {
1779 printf("%s: Primary High Byte "
1780 "termination Enabled\n",
1784 write_brdctl(ahc, brddat);
1787 if ((adapter_control & CFSTERM) != 0) {
1788 *sxfrctl1 |= STPWEN;
1791 printf("%s: %sLow byte termination Enabled\n",
1793 (ahc->features & AHC_ULTRA2) ? "Primary "
1797 if ((adapter_control & CFWSTERM) != 0
1798 && (ahc->features & AHC_WIDE) != 0) {
1801 printf("%s: %sHigh byte termination Enabled\n",
1803 (ahc->features & AHC_ULTRA2)
1804 ? "Secondary " : "");
1808 * Setup STPWEN before setting up the rest of
1809 * the termination per the tech note on the U160 cards.
1811 ahc_outb(ahc, SXFRCTL1, *sxfrctl1);
1813 if ((ahc->features & AHC_WIDE) != 0)
1814 write_brdctl(ahc, brddat);
1816 SEEPROM_OUTB(sd, sd->sd_MS); /* Clear CS */
1820 ahc_new_term_detect(struct ahc_softc *ahc, int *enableSEC_low,
1821 int *enableSEC_high, int *enablePRI_low,
1822 int *enablePRI_high, int *eeprom_present)
1828 * BRDDAT6 = Enable Secondary High Byte termination
1829 * BRDDAT5 = Enable Secondary Low Byte termination
1830 * BRDDAT4 = Enable Primary high byte termination
1831 * BRDDAT3 = Enable Primary low byte termination
1833 brdctl = read_brdctl(ahc);
1834 *eeprom_present = brdctl & BRDDAT7;
1835 *enableSEC_high = (brdctl & BRDDAT6);
1836 *enableSEC_low = (brdctl & BRDDAT5);
1837 *enablePRI_high = (brdctl & BRDDAT4);
1838 *enablePRI_low = (brdctl & BRDDAT3);
1842 aic787X_cable_detect(struct ahc_softc *ahc, int *internal50_present,
1843 int *internal68_present, int *externalcable_present,
1844 int *eeprom_present)
1849 * First read the status of our cables.
1850 * Set the rom bank to 0 since the
1851 * bank setting serves as a multiplexor
1852 * for the cable detection logic.
1853 * BRDDAT5 controls the bank switch.
1855 write_brdctl(ahc, 0);
1858 * Now read the state of the internal
1859 * connectors. BRDDAT6 is INT50 and
1862 brdctl = read_brdctl(ahc);
1863 *internal50_present = (brdctl & BRDDAT6) ? 0 : 1;
1864 *internal68_present = (brdctl & BRDDAT7) ? 0 : 1;
1867 * Set the rom bank to 1 and determine
1868 * the other signals.
1870 write_brdctl(ahc, BRDDAT5);
1873 * Now read the state of the external
1874 * connectors. BRDDAT6 is EXT68 and
1875 * BRDDAT7 is EPROMPS.
1877 brdctl = read_brdctl(ahc);
1878 *externalcable_present = (brdctl & BRDDAT6) ? 0 : 1;
1879 *eeprom_present = (brdctl & BRDDAT7) ? 1 : 0;
1883 aic785X_cable_detect(struct ahc_softc *ahc, int *internal50_present,
1884 int *externalcable_present, int *eeprom_present)
1889 spiocap = ahc_inb(ahc, SPIOCAP);
1890 spiocap &= ~SOFTCMDEN;
1891 spiocap |= EXT_BRDCTL;
1892 ahc_outb(ahc, SPIOCAP, spiocap);
1893 ahc_outb(ahc, BRDCTL, BRDRW|BRDCS);
1894 ahc_flush_device_writes(ahc);
1896 ahc_outb(ahc, BRDCTL, 0);
1897 ahc_flush_device_writes(ahc);
1899 brdctl = ahc_inb(ahc, BRDCTL);
1900 *internal50_present = (brdctl & BRDDAT5) ? 0 : 1;
1901 *externalcable_present = (brdctl & BRDDAT6) ? 0 : 1;
1902 *eeprom_present = (ahc_inb(ahc, SPIOCAP) & EEPROM) ? 1 : 0;
1906 ahc_acquire_seeprom(struct ahc_softc *ahc, struct seeprom_descriptor *sd)
1910 if ((ahc->features & AHC_SPIOCAP) != 0
1911 && (ahc_inb(ahc, SPIOCAP) & SEEPROM) == 0)
1915 * Request access of the memory port. When access is
1916 * granted, SEERDY will go high. We use a 1 second
1917 * timeout which should be near 1 second more than
1918 * is needed. Reason: after the chip reset, there
1919 * should be no contention.
1921 SEEPROM_OUTB(sd, sd->sd_MS);
1922 wait = 1000; /* 1 second timeout in msec */
1923 while (--wait && ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0)) {
1924 ahc_delay(1000); /* delay 1 msec */
1926 if ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0) {
1927 SEEPROM_OUTB(sd, 0);
1934 ahc_release_seeprom(struct seeprom_descriptor *sd)
1936 /* Release access to the memory port and the serial EEPROM. */
1937 SEEPROM_OUTB(sd, 0);
1941 write_brdctl(struct ahc_softc *ahc, uint8_t value)
1945 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) {
1947 if (ahc->channel == 'B')
1949 } else if ((ahc->features & AHC_ULTRA2) != 0) {
1952 brdctl = BRDSTB|BRDCS;
1954 ahc_outb(ahc, BRDCTL, brdctl);
1955 ahc_flush_device_writes(ahc);
1957 ahc_outb(ahc, BRDCTL, brdctl);
1958 ahc_flush_device_writes(ahc);
1959 if ((ahc->features & AHC_ULTRA2) != 0)
1960 brdctl |= BRDSTB_ULTRA2;
1963 ahc_outb(ahc, BRDCTL, brdctl);
1964 ahc_flush_device_writes(ahc);
1965 if ((ahc->features & AHC_ULTRA2) != 0)
1969 ahc_outb(ahc, BRDCTL, brdctl);
1973 read_brdctl(struct ahc_softc *ahc)
1978 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) {
1980 if (ahc->channel == 'B')
1982 } else if ((ahc->features & AHC_ULTRA2) != 0) {
1983 brdctl = BRDRW_ULTRA2;
1985 brdctl = BRDRW|BRDCS;
1987 ahc_outb(ahc, BRDCTL, brdctl);
1988 ahc_flush_device_writes(ahc);
1989 value = ahc_inb(ahc, BRDCTL);
1990 ahc_outb(ahc, BRDCTL, 0);
1995 ahc_pci_intr(struct ahc_softc *ahc)
2000 error = ahc_inb(ahc, ERROR);
2001 if ((error & PCIERRSTAT) == 0)
2004 status1 = ahc_pci_read_config(ahc->dev_softc,
2005 PCIR_STATUS + 1, /*bytes*/1);
2007 printf("%s: PCI error Interrupt at seqaddr = 0x%x\n",
2009 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8));
2011 if (status1 & DPE) {
2012 ahc->pci_target_perr_count++;
2013 printf("%s: Data Parity Error Detected during address "
2014 "or write data phase\n", ahc_name(ahc));
2016 if (status1 & SSE) {
2017 printf("%s: Signal System Error Detected\n", ahc_name(ahc));
2019 if (status1 & RMA) {
2020 printf("%s: Received a Master Abort\n", ahc_name(ahc));
2022 if (status1 & RTA) {
2023 printf("%s: Received a Target Abort\n", ahc_name(ahc));
2025 if (status1 & STA) {
2026 printf("%s: Signaled a Target Abort\n", ahc_name(ahc));
2028 if (status1 & DPR) {
2029 printf("%s: Data Parity Error has been reported via PERR#\n",
2033 /* Clear latched errors. */
2034 ahc_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1,
2035 status1, /*bytes*/1);
2037 if ((status1 & (DPE|SSE|RMA|RTA|STA|DPR)) == 0) {
2038 printf("%s: Latched PCIERR interrupt with "
2039 "no status bits set\n", ahc_name(ahc));
2041 ahc_outb(ahc, CLRINT, CLRPARERR);
2044 if (ahc->pci_target_perr_count > AHC_PCI_TARGET_PERR_THRESH) {
2046 "%s: WARNING WARNING WARNING WARNING\n"
2047 "%s: Too many PCI parity errors observed as a target.\n"
2048 "%s: Some device on this bus is generating bad parity.\n"
2049 "%s: This is an error *observed by*, not *generated by*, this controller.\n"
2050 "%s: PCI parity error checking has been disabled.\n"
2051 "%s: WARNING WARNING WARNING WARNING\n",
2052 ahc_name(ahc), ahc_name(ahc), ahc_name(ahc),
2053 ahc_name(ahc), ahc_name(ahc), ahc_name(ahc));
2054 ahc->seqctl |= FAILDIS;
2055 ahc_outb(ahc, SEQCTL, ahc->seqctl);
2061 ahc_pci_chip_init(struct ahc_softc *ahc)
2063 ahc_outb(ahc, DSCOMMAND0, ahc->bus_softc.pci_softc.dscommand0);
2064 ahc_outb(ahc, DSPCISTATUS, ahc->bus_softc.pci_softc.dspcistatus);
2065 if ((ahc->features & AHC_DT) != 0) {
2068 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE;
2069 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE);
2070 ahc_outb(ahc, OPTIONMODE, ahc->bus_softc.pci_softc.optionmode);
2071 ahc_outw(ahc, TARGCRCCNT, ahc->bus_softc.pci_softc.targcrccnt);
2072 ahc_outb(ahc, SFUNCT, sfunct);
2073 ahc_outb(ahc, CRCCONTROL1,
2074 ahc->bus_softc.pci_softc.crccontrol1);
2076 if ((ahc->features & AHC_MULTI_FUNC) != 0)
2077 ahc_outb(ahc, SCBBADDR, ahc->bus_softc.pci_softc.scbbaddr);
2079 if ((ahc->features & AHC_ULTRA2) != 0)
2080 ahc_outb(ahc, DFF_THRSH, ahc->bus_softc.pci_softc.dff_thrsh);
2082 return (ahc_chip_init(ahc));
2086 ahc_pci_suspend(struct ahc_softc *ahc)
2088 return (ahc_suspend(ahc));
2092 ahc_pci_resume(struct ahc_softc *ahc)
2095 ahc_power_state_change(ahc, AHC_POWER_STATE_D0);
2098 * We assume that the OS has restored our register
2099 * mappings, etc. Just update the config space registers
2100 * that the OS doesn't know about and rely on our chip
2101 * reset handler to handle the rest.
2103 ahc_pci_write_config(ahc->dev_softc, DEVCONFIG, /*bytes*/4,
2104 ahc->bus_softc.pci_softc.devconfig);
2105 ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/1,
2106 ahc->bus_softc.pci_softc.command);
2107 ahc_pci_write_config(ahc->dev_softc, CSIZE_LATTIME, /*bytes*/1,
2108 ahc->bus_softc.pci_softc.csize_lattime);
2109 if ((ahc->flags & AHC_HAS_TERM_LOGIC) != 0) {
2110 struct seeprom_descriptor sd;
2114 sd.sd_control_offset = SEECTL;
2115 sd.sd_status_offset = SEECTL;
2116 sd.sd_dataout_offset = SEECTL;
2118 ahc_acquire_seeprom(ahc, &sd);
2119 configure_termination(ahc, &sd,
2120 ahc->seep_config->adapter_control,
2122 ahc_release_seeprom(&sd);
2124 return (ahc_resume(ahc));
2128 ahc_aic785X_setup(struct ahc_softc *ahc)
2130 ahc_dev_softc_t pci;
2133 pci = ahc->dev_softc;
2135 ahc->chip = AHC_AIC7850;
2136 ahc->features = AHC_AIC7850_FE;
2137 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG;
2138 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
2140 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG;
2141 ahc->instruction_ram_size = 512;
2146 ahc_aic7860_setup(struct ahc_softc *ahc)
2148 ahc_dev_softc_t pci;
2151 pci = ahc->dev_softc;
2153 ahc->chip = AHC_AIC7860;
2154 ahc->features = AHC_AIC7860_FE;
2155 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG;
2156 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
2158 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG;
2159 ahc->instruction_ram_size = 512;
2164 ahc_apa1480_setup(struct ahc_softc *ahc)
2168 error = ahc_aic7860_setup(ahc);
2171 ahc->features |= AHC_REMOVABLE;
2176 ahc_aic7870_setup(struct ahc_softc *ahc)
2180 ahc->chip = AHC_AIC7870;
2181 ahc->features = AHC_AIC7870_FE;
2182 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG;
2183 ahc->instruction_ram_size = 512;
2188 ahc_aha394X_setup(struct ahc_softc *ahc)
2192 error = ahc_aic7870_setup(ahc);
2194 error = ahc_aha394XX_setup(ahc);
2199 ahc_aha398X_setup(struct ahc_softc *ahc)
2203 error = ahc_aic7870_setup(ahc);
2205 error = ahc_aha398XX_setup(ahc);
2210 ahc_aha494X_setup(struct ahc_softc *ahc)
2214 error = ahc_aic7870_setup(ahc);
2216 error = ahc_aha494XX_setup(ahc);
2221 ahc_aic7880_setup(struct ahc_softc *ahc)
2223 ahc_dev_softc_t pci;
2226 pci = ahc->dev_softc;
2228 ahc->chip = AHC_AIC7880;
2229 ahc->features = AHC_AIC7880_FE;
2230 ahc->bugs |= AHC_TMODE_WIDEODD_BUG;
2231 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
2233 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG;
2235 ahc->bugs |= AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG;
2237 ahc->instruction_ram_size = 512;
2242 ahc_aha2940Pro_setup(struct ahc_softc *ahc)
2245 ahc->flags |= AHC_INT50_SPEEDFLEX;
2246 return (ahc_aic7880_setup(ahc));
2250 ahc_aha394XU_setup(struct ahc_softc *ahc)
2254 error = ahc_aic7880_setup(ahc);
2256 error = ahc_aha394XX_setup(ahc);
2261 ahc_aha398XU_setup(struct ahc_softc *ahc)
2265 error = ahc_aic7880_setup(ahc);
2267 error = ahc_aha398XX_setup(ahc);
2272 ahc_aic7890_setup(struct ahc_softc *ahc)
2274 ahc_dev_softc_t pci;
2277 pci = ahc->dev_softc;
2279 ahc->chip = AHC_AIC7890;
2280 ahc->features = AHC_AIC7890_FE;
2281 ahc->flags |= AHC_NEWEEPROM_FMT;
2282 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
2284 ahc->bugs |= AHC_AUTOFLUSH_BUG|AHC_CACHETHEN_BUG;
2285 ahc->instruction_ram_size = 768;
2290 ahc_aic7892_setup(struct ahc_softc *ahc)
2294 ahc->chip = AHC_AIC7892;
2295 ahc->features = AHC_AIC7892_FE;
2296 ahc->flags |= AHC_NEWEEPROM_FMT;
2297 ahc->bugs |= AHC_SCBCHAN_UPLOAD_BUG;
2298 ahc->instruction_ram_size = 1024;
2303 ahc_aic7895_setup(struct ahc_softc *ahc)
2305 ahc_dev_softc_t pci;
2308 pci = ahc->dev_softc;
2309 ahc->channel = ahc_get_pci_function(pci) == 1 ? 'B' : 'A';
2311 * The 'C' revision of the aic7895 has a few additional features.
2313 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
2315 ahc->chip = AHC_AIC7895C;
2316 ahc->features = AHC_AIC7895C_FE;
2320 ahc->chip = AHC_AIC7895;
2321 ahc->features = AHC_AIC7895_FE;
2324 * The BIOS disables the use of MWI transactions
2325 * since it does not have the MWI bug work around
2326 * we have. Disabling MWI reduces performance, so
2329 command = ahc_pci_read_config(pci, PCIR_COMMAND, /*bytes*/1);
2330 command |= PCIM_CMD_MWRICEN;
2331 ahc_pci_write_config(pci, PCIR_COMMAND, command, /*bytes*/1);
2332 ahc->bugs |= AHC_PCI_MWI_BUG;
2335 * XXX Does CACHETHEN really not work??? What about PCI retry?
2336 * on C level chips. Need to test, but for now, play it safe.
2338 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_PCI_2_1_RETRY_BUG
2339 | AHC_CACHETHEN_BUG;
2345 * Cachesize must also be zero due to stray DAC
2346 * problem when sitting behind some bridges.
2348 ahc_pci_write_config(pci, CSIZE_LATTIME, 0, /*bytes*/1);
2349 devconfig = ahc_pci_read_config(pci, DEVCONFIG, /*bytes*/1);
2350 devconfig |= MRDCEN;
2351 ahc_pci_write_config(pci, DEVCONFIG, devconfig, /*bytes*/1);
2353 ahc->flags |= AHC_NEWEEPROM_FMT;
2354 ahc->instruction_ram_size = 512;
2359 ahc_aic7896_setup(struct ahc_softc *ahc)
2361 ahc_dev_softc_t pci;
2363 pci = ahc->dev_softc;
2364 ahc->channel = ahc_get_pci_function(pci) == 1 ? 'B' : 'A';
2365 ahc->chip = AHC_AIC7896;
2366 ahc->features = AHC_AIC7896_FE;
2367 ahc->flags |= AHC_NEWEEPROM_FMT;
2368 ahc->bugs |= AHC_CACHETHEN_DIS_BUG;
2369 ahc->instruction_ram_size = 768;
2374 ahc_aic7899_setup(struct ahc_softc *ahc)
2376 ahc_dev_softc_t pci;
2378 pci = ahc->dev_softc;
2379 ahc->channel = ahc_get_pci_function(pci) == 1 ? 'B' : 'A';
2380 ahc->chip = AHC_AIC7899;
2381 ahc->features = AHC_AIC7899_FE;
2382 ahc->flags |= AHC_NEWEEPROM_FMT;
2383 ahc->bugs |= AHC_SCBCHAN_UPLOAD_BUG;
2384 ahc->instruction_ram_size = 1024;
2389 ahc_aha29160C_setup(struct ahc_softc *ahc)
2393 error = ahc_aic7899_setup(ahc);
2396 ahc->features |= AHC_REMOVABLE;
2401 ahc_raid_setup(struct ahc_softc *ahc)
2403 printf("RAID functionality unsupported\n");
2408 ahc_aha394XX_setup(struct ahc_softc *ahc)
2410 ahc_dev_softc_t pci;
2412 pci = ahc->dev_softc;
2413 switch (ahc_get_pci_slot(pci)) {
2414 case AHC_394X_SLOT_CHANNEL_A:
2417 case AHC_394X_SLOT_CHANNEL_B:
2421 printf("adapter at unexpected slot %d\n"
2422 "unable to map to a channel\n",
2423 ahc_get_pci_slot(pci));
2430 ahc_aha398XX_setup(struct ahc_softc *ahc)
2432 ahc_dev_softc_t pci;
2434 pci = ahc->dev_softc;
2435 switch (ahc_get_pci_slot(pci)) {
2436 case AHC_398X_SLOT_CHANNEL_A:
2439 case AHC_398X_SLOT_CHANNEL_B:
2442 case AHC_398X_SLOT_CHANNEL_C:
2446 printf("adapter at unexpected slot %d\n"
2447 "unable to map to a channel\n",
2448 ahc_get_pci_slot(pci));
2452 ahc->flags |= AHC_LARGE_SEEPROM;
2457 ahc_aha494XX_setup(struct ahc_softc *ahc)
2459 ahc_dev_softc_t pci;
2461 pci = ahc->dev_softc;
2462 switch (ahc_get_pci_slot(pci)) {
2463 case AHC_494X_SLOT_CHANNEL_A:
2466 case AHC_494X_SLOT_CHANNEL_B:
2469 case AHC_494X_SLOT_CHANNEL_C:
2472 case AHC_494X_SLOT_CHANNEL_D:
2476 printf("adapter at unexpected slot %d\n"
2477 "unable to map to a channel\n",
2478 ahc_get_pci_slot(pci));
2481 ahc->flags |= AHC_LARGE_SEEPROM;