1 /* $OpenBSD: brgphy.c,v 1.48 2006/05/20 23:03:53 brad Exp $ */
5 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by Bill Paul.
18 * 4. Neither the name of the author nor the names of any co-contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
32 * THE POSSIBILITY OF SUCH DAMAGE.
34 * $FreeBSD: src/sys/dev/mii/brgphy.c,v 1.1.2.7 2003/05/11 18:00:55 ps Exp $
35 * $DragonFly: src/sys/dev/netif/mii_layer/brgphy.c,v 1.13 2006/08/06 10:32:23 sephe Exp $
39 * Driver for the Broadcom BCR5400 1000baseTX PHY. Speed is always
40 * 1000mbps; all we need to negotiate here is full or half duplex.
43 #include <sys/param.h>
44 #include <sys/systm.h>
45 #include <sys/kernel.h>
46 #include <sys/socket.h>
49 #include <machine/bus.h>
50 #include <machine/clock.h>
53 #include <net/if_media.h>
54 #include <net/if_arp.h>
60 #include "brgphyreg.h"
61 #include <dev/netif/bge/if_bgereg.h>
63 #include "miibus_if.h"
65 static int brgphy_probe(device_t);
66 static int brgphy_attach(device_t);
68 static const struct mii_phydesc brgphys[] = {
69 MII_PHYDESC(xxBROADCOM, BCM5400),
70 MII_PHYDESC(xxBROADCOM, BCM5401),
71 MII_PHYDESC(xxBROADCOM, BCM5411),
72 MII_PHYDESC(xxBROADCOM, BCM5421),
73 MII_PHYDESC(xxBROADCOM, BCM54K2),
74 MII_PHYDESC(xxBROADCOM, BCM5462),
76 MII_PHYDESC(xxBROADCOM, BCM5701),
77 MII_PHYDESC(xxBROADCOM, BCM5703),
78 MII_PHYDESC(xxBROADCOM, BCM5704),
79 MII_PHYDESC(xxBROADCOM, BCM5705),
81 MII_PHYDESC(xxBROADCOM, BCM5714),
82 MII_PHYDESC(xxBROADCOM, BCM5750),
83 MII_PHYDESC(xxBROADCOM, BCM5752),
84 MII_PHYDESC(xxBROADCOM, BCM5780),
86 MII_PHYDESC(xxBROADCOM, BCM5706C),
87 MII_PHYDESC(xxBROADCOM, BCM5708C),
92 static device_method_t brgphy_methods[] = {
93 /* device interface */
94 DEVMETHOD(device_probe, brgphy_probe),
95 DEVMETHOD(device_attach, brgphy_attach),
96 DEVMETHOD(device_detach, ukphy_detach),
97 DEVMETHOD(device_shutdown, bus_generic_shutdown),
101 static devclass_t brgphy_devclass;
103 static driver_t brgphy_driver = {
106 sizeof(struct mii_softc)
109 DRIVER_MODULE(brgphy, miibus, brgphy_driver, brgphy_devclass, 0, 0);
111 static int brgphy_service(struct mii_softc *, struct mii_data *, int);
112 static void brgphy_status(struct mii_softc *);
113 static int brgphy_mii_phy_auto(struct mii_softc *, int);
114 static void brgphy_reset(struct mii_softc *);
115 static void brgphy_loop(struct mii_softc *);
117 static void brgphy_load_dspcode(struct mii_softc *);
118 static void brgphy_bcm5401_dspcode(struct mii_softc *);
119 static void brgphy_bcm5411_dspcode(struct mii_softc *);
120 static void brgphy_bcm5421_dspcode(struct mii_softc *);
121 static void brgphy_bcm54k2_dspcode(struct mii_softc *);
122 static void brgphy_bcm5703_dspcode(struct mii_softc *);
123 static void brgphy_bcm5704_dspcode(struct mii_softc *);
124 static void brgphy_bcm5750_dspcode(struct mii_softc *);
127 brgphy_probe(device_t dev)
129 struct mii_attach_args *ma = device_get_ivars(dev);
130 const struct mii_phydesc *mpd;
132 mpd = mii_phy_match(ma, brgphys);
134 device_set_desc(dev, mpd->mpd_name);
141 brgphy_attach(device_t dev)
143 struct mii_softc *sc;
144 struct mii_attach_args *ma;
145 struct mii_data *mii;
147 sc = device_get_softc(dev);
148 ma = device_get_ivars(dev);
149 mii_softc_init(sc, ma);
150 sc->mii_dev = device_get_parent(dev);
151 mii = device_get_softc(sc->mii_dev);
152 LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list);
154 sc->mii_inst = mii->mii_instance;
155 sc->mii_service = brgphy_service;
156 sc->mii_reset = brgphy_reset;
159 sc->mii_flags |= MIIF_NOISOLATE;
164 #define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL)
166 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, sc->mii_inst),
169 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_LOOP, sc->mii_inst),
175 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask;
176 if (sc->mii_capabilities & BMSR_EXTSTAT)
177 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR);
179 device_printf(dev, " ");
180 if ((sc->mii_capabilities & BMSR_MEDIAMASK) ||
181 (sc->mii_extcapabilities & EXTSR_MEDIAMASK))
182 mii_phy_add_media(sc);
184 printf("no media present");
187 MIIBUS_MEDIAINIT(sc->mii_dev);
192 brgphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
194 struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
200 * If we're not polling our PHY instance, just return.
202 if (IFM_INST(ife->ifm_media) != sc->mii_inst)
208 * If the media indicates a different PHY instance,
211 if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
212 reg = PHY_READ(sc, MII_BMCR);
213 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
218 * If the interface is not up, don't do anything.
220 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
223 brgphy_reset(sc); /* XXX hardware bug work-around */
225 switch (IFM_SUBTYPE(ife->ifm_media)) {
229 * If we're already in auto mode, just return.
231 if (PHY_READ(sc, BRGPHY_MII_BMCR) & BRGPHY_BMCR_AUTOEN)
234 brgphy_mii_phy_auto(sc, 1);
237 speed = BRGPHY_S1000;
246 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) {
247 speed |= BRGPHY_BMCR_FDX;
248 gig = BRGPHY_1000CTL_AFD;
250 gig = BRGPHY_1000CTL_AHD;
253 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 0);
254 PHY_WRITE(sc, BRGPHY_MII_BMCR, speed);
255 PHY_WRITE(sc, BRGPHY_MII_ANAR, BRGPHY_SEL_TYPE);
257 if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T)
260 PHY_WRITE(sc, BRGPHY_MII_1000CTL, gig);
261 PHY_WRITE(sc, BRGPHY_MII_BMCR,
262 speed|BRGPHY_BMCR_AUTOEN|BRGPHY_BMCR_STARTNEG);
264 if (sc->mii_model != MII_MODEL_xxBROADCOM_BCM5701)
268 * When settning the link manually, one side must
269 * be the master and the other the slave. However
270 * ifmedia doesn't give us a good way to specify
271 * this, so we fake it by using one of the LINK
272 * flags. If LINK0 is set, we program the PHY to
273 * be a master, otherwise it's a slave.
275 if ((mii->mii_ifp->if_flags & IFF_LINK0)) {
276 PHY_WRITE(sc, BRGPHY_MII_1000CTL,
277 gig|BRGPHY_1000CTL_MSE|BRGPHY_1000CTL_MSC);
279 PHY_WRITE(sc, BRGPHY_MII_1000CTL,
280 gig|BRGPHY_1000CTL_MSE);
285 PHY_WRITE(sc, MII_BMCR, BMCR_ISO|BMCR_PDOWN);
296 * If we're not currently selected, just return.
298 if (IFM_INST(ife->ifm_media) != sc->mii_inst)
302 * Is the interface even up?
304 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
308 * Only used for autonegotiation.
310 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO)
314 * Check to see if we have link. If we do, we don't
315 * need to restart the autonegotiation process. Read
316 * the BMSR twice in case it's latched.
318 reg = PHY_READ(sc, BRGPHY_MII_AUXSTS);
319 if (reg & BRGPHY_AUXSTS_LINK)
323 * Only retry autonegotiation every 5 seconds.
325 if (++sc->mii_ticks <= sc->mii_anegticks)
329 if (brgphy_mii_phy_auto(sc, 0) == EJUSTRETURN)
334 /* Update the media status. */
338 * Callback if something changed. Note that we need to poke
339 * the DSP on the Broadcom PHYs if the media changes.
341 if (sc->mii_media_active != mii->mii_media_active ||
342 sc->mii_media_status != mii->mii_media_status ||
343 cmd == MII_MEDIACHG) {
344 switch (sc->mii_model) {
345 case MII_MODEL_BROADCOM_BCM5400:
346 case MII_MODEL_xxBROADCOM_BCM5401:
347 case MII_MODEL_xxBROADCOM_BCM5411:
348 brgphy_load_dspcode(sc);
352 mii_phy_update(sc, cmd);
357 brgphy_status(struct mii_softc *sc)
359 struct mii_data *mii = sc->mii_pdata;
360 struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
363 mii->mii_media_status = IFM_AVALID;
364 mii->mii_media_active = IFM_ETHER;
366 bmsr = PHY_READ(sc, BRGPHY_MII_BMSR);
367 if (PHY_READ(sc, BRGPHY_MII_AUXSTS) & BRGPHY_AUXSTS_LINK)
368 mii->mii_media_status |= IFM_ACTIVE;
370 bmcr = PHY_READ(sc, BRGPHY_MII_BMCR);
372 if (bmcr & BRGPHY_BMCR_LOOP)
373 mii->mii_media_active |= IFM_LOOP;
375 if (bmcr & BRGPHY_BMCR_AUTOEN) {
376 if ((bmsr & BRGPHY_BMSR_ACOMP) == 0) {
377 /* Erg, still trying, I guess... */
378 mii->mii_media_active |= IFM_NONE;
382 switch (PHY_READ(sc, BRGPHY_MII_AUXSTS) &
383 BRGPHY_AUXSTS_AN_RES) {
384 case BRGPHY_RES_1000FD:
385 mii->mii_media_active |= IFM_1000_T | IFM_FDX;
387 case BRGPHY_RES_1000HD:
388 mii->mii_media_active |= IFM_1000_T | IFM_HDX;
390 case BRGPHY_RES_100FD:
391 mii->mii_media_active |= IFM_100_TX | IFM_FDX;
393 case BRGPHY_RES_100T4:
394 mii->mii_media_active |= IFM_100_T4;
396 case BRGPHY_RES_100HD:
397 mii->mii_media_active |= IFM_100_TX | IFM_HDX;
399 case BRGPHY_RES_10FD:
400 mii->mii_media_active |= IFM_10_T | IFM_FDX;
402 case BRGPHY_RES_10HD:
403 mii->mii_media_active |= IFM_10_T | IFM_HDX;
406 mii->mii_media_active |= IFM_NONE;
412 mii->mii_media_active = ife->ifm_media;
417 brgphy_mii_phy_auto(struct mii_softc *sc, int waitfor)
419 int bmsr, ktcr = 0, i;
421 if ((sc->mii_flags & MIIF_DOINGAUTO) == 0) {
424 ktcr = BRGPHY_1000CTL_AFD|BRGPHY_1000CTL_AHD;
425 if (sc->mii_model == MII_MODEL_xxBROADCOM_BCM5701)
426 ktcr |= BRGPHY_1000CTL_MSE|BRGPHY_1000CTL_MSC;
427 PHY_WRITE(sc, BRGPHY_MII_1000CTL, ktcr);
428 ktcr = PHY_READ(sc, BRGPHY_MII_1000CTL);
430 PHY_WRITE(sc, BRGPHY_MII_ANAR,
431 BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA);
433 PHY_WRITE(sc, BRGPHY_MII_BMCR,
434 BRGPHY_BMCR_AUTOEN | BRGPHY_BMCR_STARTNEG);
435 PHY_WRITE(sc, BRGPHY_MII_IMR, 0xFF00);
439 /* Wait 500ms for it to complete. */
440 for (i = 0; i < 500; i++) {
441 if ((bmsr = PHY_READ(sc, BRGPHY_MII_BMSR)) &
448 * Don't need to worry about clearing MIIF_DOINGAUTO.
449 * If that's set, a timeout is pending, and it will
456 * Just let it finish asynchronously. This is for the benefit of
457 * the tick handler driving autonegotiation. Don't want 500ms
458 * delays all the time while the system is running!
460 if ((sc->mii_flags & MIIF_DOINGAUTO) == 0) {
461 sc->mii_flags |= MIIF_DOINGAUTO;
462 callout_reset(&sc->mii_auto_ch, hz >> 1,
463 mii_phy_auto_timeout, sc);
466 return (EJUSTRETURN);
470 brgphy_loop(struct mii_softc *sc)
475 PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_LOOP);
476 for (i = 0; i < 15000; i++) {
477 bmsr = PHY_READ(sc, BRGPHY_MII_BMSR);
478 if (!(bmsr & BRGPHY_BMSR_LINK))
485 brgphy_reset(struct mii_softc *sc)
489 struct bge_softc *bge_sc;
493 ifp = sc->mii_pdata->mii_ifp;
494 bge_sc = ifp->if_softc;
496 brgphy_load_dspcode(sc);
499 * Don't enable Ethernet@WireSpeed for the 5700 or 5705
500 * other than A0 and A1 chips. Make sure we only do this
501 * test on "bge" NICs, since other drivers may use this
502 * same PHY subdriver.
504 if (strncmp(ifp->if_xname, "bge", 3) == 0 &&
505 (bge_sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
506 (bge_sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
507 (bge_sc->bge_chipid != BGE_CHIPID_BCM5705_A0 &&
508 bge_sc->bge_chipid != BGE_CHIPID_BCM5705_A1))))
511 /* Enable Ethernet@WireSpeed. */
512 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7007);
513 val = PHY_READ(sc, BRGPHY_MII_AUXCTL);
514 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, val | (1 << 15) | (1 << 4));
516 /* Enable Link LED on Dell boxes */
517 if (bge_sc->bge_no_3_led) {
518 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
519 PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL)
520 & ~BRGPHY_PHY_EXTCTL_3_LED);
524 /* Turn off tap power management on 5401. */
526 brgphy_bcm5401_dspcode(struct mii_softc *sc)
528 static const struct {
532 { BRGPHY_MII_AUXCTL, 0x0c20 },
533 { BRGPHY_MII_DSP_ADDR_REG, 0x0012 },
534 { BRGPHY_MII_DSP_RW_PORT, 0x1804 },
535 { BRGPHY_MII_DSP_ADDR_REG, 0x0013 },
536 { BRGPHY_MII_DSP_RW_PORT, 0x1204 },
537 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 },
538 { BRGPHY_MII_DSP_RW_PORT, 0x0132 },
539 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 },
540 { BRGPHY_MII_DSP_RW_PORT, 0x0232 },
541 { BRGPHY_MII_DSP_ADDR_REG, 0x201f },
542 { BRGPHY_MII_DSP_RW_PORT, 0x0a20 },
547 for (i = 0; dspcode[i].reg != 0; i++)
548 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
552 /* Setting some undocumented voltage */
554 brgphy_bcm5411_dspcode(struct mii_softc *sc)
556 static const struct {
567 for (i = 0; dspcode[i].reg != 0; i++)
568 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
572 brgphy_bcm5421_dspcode(struct mii_softc *sc)
576 /* Set Class A mode */
577 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x1007);
578 data = PHY_READ(sc, BRGPHY_MII_AUXCTL);
579 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, data | 0x0400);
581 /* Set FFE gamma override to -0.125 */
582 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0007);
583 data = PHY_READ(sc, BRGPHY_MII_AUXCTL);
584 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, data | 0x0800);
585 PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x000a);
586 data = PHY_READ(sc, BRGPHY_MII_DSP_RW_PORT);
587 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, data | 0x0200);
591 brgphy_bcm54k2_dspcode(struct mii_softc *sc)
593 static const struct {
603 for (i = 0; dspcode[i].reg != 0; i++)
604 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
608 brgphy_bcm5703_dspcode(struct mii_softc *sc)
610 static const struct {
614 { BRGPHY_MII_AUXCTL, 0x0c00 },
615 { BRGPHY_MII_DSP_ADDR_REG, 0x201f },
616 { BRGPHY_MII_DSP_RW_PORT, 0x2aaa },
621 for (i = 0; dspcode[i].reg != 0; i++)
622 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
626 brgphy_bcm5704_dspcode(struct mii_softc *sc)
628 static const struct {
632 { BRGPHY_MII_AUXCTL, 0x0c00 },
633 { BRGPHY_MII_DSP_ADDR_REG, 0x201f },
634 { BRGPHY_MII_DSP_RW_PORT, 0x2aaa },
635 { BRGPHY_MII_DSP_ADDR_REG, 0x000a },
636 { BRGPHY_MII_DSP_RW_PORT, 0x0323 },
637 { BRGPHY_MII_AUXCTL, 0x0400 },
644 for (i = 0; dspcode[i].reg != 0; i++)
645 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
649 brgphy_bcm5750_dspcode(struct mii_softc *sc)
651 static const struct {
655 { BRGPHY_MII_AUXCTL, 0x0c00 },
656 { BRGPHY_MII_DSP_ADDR_REG, 0x000a },
657 { BRGPHY_MII_DSP_RW_PORT, 0x310b },
658 { BRGPHY_MII_DSP_ADDR_REG, 0x201f },
659 { BRGPHY_MII_DSP_RW_PORT, 0x9506 },
660 { BRGPHY_MII_DSP_ADDR_REG, 0x401f },
661 { BRGPHY_MII_DSP_RW_PORT, 0x14e2 },
662 { BRGPHY_MII_AUXCTL, 0x0400 },
667 for (i = 0; dspcode[i].reg != 0; i++)
668 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
672 brgphy_load_dspcode(struct mii_softc *sc)
674 switch (sc->mii_model) {
675 case MII_MODEL_BROADCOM_BCM5400:
676 brgphy_bcm5401_dspcode(sc);
678 case MII_MODEL_BROADCOM_BCM5401:
679 if (sc->mii_rev == 1 || sc->mii_rev == 3)
680 brgphy_bcm5401_dspcode(sc);
682 case MII_MODEL_BROADCOM_BCM5411:
683 brgphy_bcm5411_dspcode(sc);
685 case MII_MODEL_xxBROADCOM_BCM5421:
686 brgphy_bcm5421_dspcode(sc);
688 case MII_MODEL_xxBROADCOM_BCM54K2:
689 brgphy_bcm54k2_dspcode(sc);
691 case MII_MODEL_xxBROADCOM_BCM5703:
692 brgphy_bcm5703_dspcode(sc);
694 case MII_MODEL_xxBROADCOM_BCM5704:
695 brgphy_bcm5704_dspcode(sc);
697 case MII_MODEL_xxBROADCOM_BCM5705:
698 case MII_MODEL_xxBROADCOM_BCM5750:
699 case MII_MODEL_xxBROADCOM_BCM5714:
700 case MII_MODEL_xxBROADCOM_BCM5780:
701 case MII_MODEL_xxBROADCOM_BCM5752:
702 case MII_MODEL_xxBROADCOM_BCM5706C:
703 case MII_MODEL_xxBROADCOM_BCM5708C:
704 brgphy_bcm5750_dspcode(sc);