2 * Copyright (c) 1991 The Regents of the University of California.
3 * Copyright (c) 1996, by Steve Passe. All rights reserved.
4 * Copyright (c) 2005,2008 The DragonFly Project. All rights reserved.
7 * This code is derived from software contributed to The DragonFly Project
8 * by Matthew Dillon <dillon@backplane.com>
10 * This code is derived from software contributed to Berkeley by
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in
21 * the documentation and/or other materials provided with the
23 * 3. Neither the name of The DragonFly Project nor the names of its
24 * contributors may be used to endorse or promote products derived
25 * from this software without specific, prior written permission.
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
30 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
31 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
32 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
33 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
34 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
35 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
36 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
37 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
40 * $DragonFly: src/sys/platform/pc64/apic/apic_abi.c,v 1.1 2008/08/29 17:07:12 dillon Exp $
43 #include <sys/param.h>
44 #include <sys/systm.h>
45 #include <sys/kernel.h>
46 #include <sys/machintr.h>
47 #include <sys/interrupt.h>
50 #include <machine/smp.h>
51 #include <machine/segments.h>
52 #include <machine/md_var.h>
53 #include <machine/clock.h> /* apic_8254_intr */
54 #include <machine_base/isa/intr_machdep.h>
55 #include <machine_base/icu/icu.h>
56 #include <machine/globaldata.h>
58 #include <sys/thread2.h>
64 extern void APIC_INTREN(int);
65 extern void APIC_INTRDIS(int);
68 IDTVEC(apic_fastintr0), IDTVEC(apic_fastintr1),
69 IDTVEC(apic_fastintr2), IDTVEC(apic_fastintr3),
70 IDTVEC(apic_fastintr4), IDTVEC(apic_fastintr5),
71 IDTVEC(apic_fastintr6), IDTVEC(apic_fastintr7),
72 IDTVEC(apic_fastintr8), IDTVEC(apic_fastintr9),
73 IDTVEC(apic_fastintr10), IDTVEC(apic_fastintr11),
74 IDTVEC(apic_fastintr12), IDTVEC(apic_fastintr13),
75 IDTVEC(apic_fastintr14), IDTVEC(apic_fastintr15),
76 IDTVEC(apic_fastintr16), IDTVEC(apic_fastintr17),
77 IDTVEC(apic_fastintr18), IDTVEC(apic_fastintr19),
78 IDTVEC(apic_fastintr20), IDTVEC(apic_fastintr21),
79 IDTVEC(apic_fastintr22), IDTVEC(apic_fastintr23);
82 IDTVEC(apic_slowintr0), IDTVEC(apic_slowintr1),
83 IDTVEC(apic_slowintr2), IDTVEC(apic_slowintr3),
84 IDTVEC(apic_slowintr4), IDTVEC(apic_slowintr5),
85 IDTVEC(apic_slowintr6), IDTVEC(apic_slowintr7),
86 IDTVEC(apic_slowintr8), IDTVEC(apic_slowintr9),
87 IDTVEC(apic_slowintr10), IDTVEC(apic_slowintr11),
88 IDTVEC(apic_slowintr12), IDTVEC(apic_slowintr13),
89 IDTVEC(apic_slowintr14), IDTVEC(apic_slowintr15),
90 IDTVEC(apic_slowintr16), IDTVEC(apic_slowintr17),
91 IDTVEC(apic_slowintr18), IDTVEC(apic_slowintr19),
92 IDTVEC(apic_slowintr20), IDTVEC(apic_slowintr21),
93 IDTVEC(apic_slowintr22), IDTVEC(apic_slowintr23);
96 IDTVEC(apic_wrongintr0), IDTVEC(apic_wrongintr1),
97 IDTVEC(apic_wrongintr2), IDTVEC(apic_wrongintr3),
98 IDTVEC(apic_wrongintr4), IDTVEC(apic_wrongintr5),
99 IDTVEC(apic_wrongintr6), IDTVEC(apic_wrongintr7),
100 IDTVEC(apic_wrongintr8), IDTVEC(apic_wrongintr9),
101 IDTVEC(apic_wrongintr10), IDTVEC(apic_wrongintr11),
102 IDTVEC(apic_wrongintr12), IDTVEC(apic_wrongintr13),
103 IDTVEC(apic_wrongintr14), IDTVEC(apic_wrongintr15),
104 IDTVEC(apic_wrongintr16), IDTVEC(apic_wrongintr17),
105 IDTVEC(apic_wrongintr18), IDTVEC(apic_wrongintr19),
106 IDTVEC(apic_wrongintr20), IDTVEC(apic_wrongintr21),
107 IDTVEC(apic_wrongintr22), IDTVEC(apic_wrongintr23);
109 static int apic_setvar(int, const void *);
110 static int apic_getvar(int, void *);
111 static int apic_vectorctl(int, int, int);
112 static void apic_finalize(void);
113 static void apic_cleanup(void);
115 static inthand_t *apic_fastintr[APIC_HWI_VECTORS] = {
116 &IDTVEC(apic_fastintr0), &IDTVEC(apic_fastintr1),
117 &IDTVEC(apic_fastintr2), &IDTVEC(apic_fastintr3),
118 &IDTVEC(apic_fastintr4), &IDTVEC(apic_fastintr5),
119 &IDTVEC(apic_fastintr6), &IDTVEC(apic_fastintr7),
120 &IDTVEC(apic_fastintr8), &IDTVEC(apic_fastintr9),
121 &IDTVEC(apic_fastintr10), &IDTVEC(apic_fastintr11),
122 &IDTVEC(apic_fastintr12), &IDTVEC(apic_fastintr13),
123 &IDTVEC(apic_fastintr14), &IDTVEC(apic_fastintr15),
124 &IDTVEC(apic_fastintr16), &IDTVEC(apic_fastintr17),
125 &IDTVEC(apic_fastintr18), &IDTVEC(apic_fastintr19),
126 &IDTVEC(apic_fastintr20), &IDTVEC(apic_fastintr21),
127 &IDTVEC(apic_fastintr22), &IDTVEC(apic_fastintr23)
130 static inthand_t *apic_slowintr[APIC_HWI_VECTORS] = {
131 &IDTVEC(apic_slowintr0), &IDTVEC(apic_slowintr1),
132 &IDTVEC(apic_slowintr2), &IDTVEC(apic_slowintr3),
133 &IDTVEC(apic_slowintr4), &IDTVEC(apic_slowintr5),
134 &IDTVEC(apic_slowintr6), &IDTVEC(apic_slowintr7),
135 &IDTVEC(apic_slowintr8), &IDTVEC(apic_slowintr9),
136 &IDTVEC(apic_slowintr10), &IDTVEC(apic_slowintr11),
137 &IDTVEC(apic_slowintr12), &IDTVEC(apic_slowintr13),
138 &IDTVEC(apic_slowintr14), &IDTVEC(apic_slowintr15),
139 &IDTVEC(apic_slowintr16), &IDTVEC(apic_slowintr17),
140 &IDTVEC(apic_slowintr18), &IDTVEC(apic_slowintr19),
141 &IDTVEC(apic_slowintr20), &IDTVEC(apic_slowintr21),
142 &IDTVEC(apic_slowintr22), &IDTVEC(apic_slowintr23)
145 static inthand_t *apic_wrongintr[APIC_HWI_VECTORS] = {
146 &IDTVEC(apic_wrongintr0), &IDTVEC(apic_wrongintr1),
147 &IDTVEC(apic_wrongintr2), &IDTVEC(apic_wrongintr3),
148 &IDTVEC(apic_wrongintr4), &IDTVEC(apic_wrongintr5),
149 &IDTVEC(apic_wrongintr6), &IDTVEC(apic_wrongintr7),
150 &IDTVEC(apic_wrongintr8), &IDTVEC(apic_wrongintr9),
151 &IDTVEC(apic_wrongintr10), &IDTVEC(apic_wrongintr11),
152 &IDTVEC(apic_wrongintr12), &IDTVEC(apic_wrongintr13),
153 &IDTVEC(apic_wrongintr14), &IDTVEC(apic_wrongintr15),
154 &IDTVEC(apic_wrongintr16), &IDTVEC(apic_wrongintr17),
155 &IDTVEC(apic_wrongintr18), &IDTVEC(apic_wrongintr19),
156 &IDTVEC(apic_wrongintr20), &IDTVEC(apic_wrongintr21),
157 &IDTVEC(apic_wrongintr22), &IDTVEC(apic_wrongintr23)
160 static int apic_imcr_present;
162 struct machintr_abi MachIntrABI = {
164 .intrdis = APIC_INTRDIS,
165 .intren = APIC_INTREN,
166 .vectorctl = apic_vectorctl,
167 .setvar = apic_setvar,
168 .getvar = apic_getvar,
169 .finalize = apic_finalize,
170 .cleanup = apic_cleanup
174 apic_setvar(int varid, const void *buf)
179 case MACHINTR_VAR_IMCR_PRESENT:
180 apic_imcr_present = *(const int *)buf;
190 apic_getvar(int varid, void *buf)
195 case MACHINTR_VAR_IMCR_PRESENT:
196 *(int *)buf = apic_imcr_present;
206 * Called before interrupts are physically enabled, this routine does the
207 * final configuration of the BSP's local APIC:
209 * - disable 'pic mode'.
210 * - disable 'virtual wire mode'.
219 * If an IMCR is present, program bit 0 to disconnect the 8259
220 * from the BSP. The 8259 may still be connected to LINT0 on
223 if (apic_imcr_present) {
224 outb(0x22, 0x70); /* select IMCR */
225 outb(0x23, 0x01); /* disconnect 8259 */
229 * Setup lint0 (the 8259 'virtual wire' connection). We
230 * mask the interrupt, completing the disconnection of the
233 temp = lapic->lvt_lint0;
234 temp |= APIC_LVT_MASKED;
235 lapic->lvt_lint0 = temp;
238 * setup lint1 to handle an NMI
240 temp = lapic->lvt_lint1;
241 temp &= ~APIC_LVT_MASKED;
242 lapic->lvt_lint1 = temp;
245 apic_dump("bsp_apic_configure()");
249 * This routine is called after physical interrupts are enabled but before
250 * the critical section is released. We need to clean out any interrupts
251 * that had already been posted to the cpu.
256 mdcpu->gd_fpending = 0;
257 mdcpu->gd_ipending = 0;
262 apic_vectorctl(int op, int intr, int flags)
270 if (intr < 0 || intr >= APIC_HWI_VECTORS)
278 case MACHINTR_VECTOR_SETUP:
280 * Setup an interrupt vector. First install the vector in the
281 * cpu's Interrupt Descriptor Table (IDT).
283 if (flags & INTR_FAST) {
284 vector = TPR_SLOW_INTS + intr;
285 setidt(vector, apic_wrongintr[intr],
286 SDT_SYSIGT, SEL_KPL, 0);
287 vector = TPR_FAST_INTS + intr;
288 setidt(vector, apic_fastintr[intr],
289 SDT_SYSIGT, SEL_KPL, 0);
291 vector = TPR_SLOW_INTS + intr;
294 * This is probably not needed any more. XXX
296 if (intr == apic_8254_intr || intr == 8) {
297 vector = TPR_FAST_INTS + intr;
299 setidt(vector, apic_slowintr[intr],
300 SDT_SYSIGT, SEL_KPL, 0);
304 * Now reprogram the vector in the IO APIC. In order to avoid
305 * losing an EOI for a level interrupt, which is vector based,
306 * make sure that the IO APIC is programmed for edge-triggering
307 * first, then reprogrammed with the new vector. This should
310 if (int_to_apicintpin[intr].ioapic >= 0) {
312 select = int_to_apicintpin[intr].redirindex;
313 value = io_apic_read(int_to_apicintpin[intr].ioapic, select);
314 io_apic_write(int_to_apicintpin[intr].ioapic,
315 select, (value & ~APIC_TRIGMOD_MASK));
316 io_apic_write(int_to_apicintpin[intr].ioapic,
317 select, (value & ~IOART_INTVEC) | vector);
320 machintr_intren(intr);
322 case MACHINTR_VECTOR_TEARDOWN:
324 * Teardown an interrupt vector. The vector should already be
325 * installed in the cpu's IDT, but make sure.
327 machintr_intrdis(intr);
328 vector = TPR_SLOW_INTS + intr;
329 setidt(vector, apic_slowintr[intr], SDT_SYSIGT, SEL_KPL,
333 * And then reprogram the IO APIC to point to the SLOW vector (it may
334 * have previously been pointed to the FAST version of the vector).
335 * This will allow us to keep track of spurious interrupts.
337 * In order to avoid losing an EOI for a level interrupt, which is
338 * vector based, make sure that the IO APIC is programmed for
339 * edge-triggering first, then reprogrammed with the new vector.
340 * This should clear the IRR bit.
342 if (int_to_apicintpin[intr].ioapic >= 0) {
344 select = int_to_apicintpin[intr].redirindex;
345 value = io_apic_read(int_to_apicintpin[intr].ioapic, select);
346 io_apic_write(int_to_apicintpin[intr].ioapic,
347 select, (value & ~APIC_TRIGMOD_MASK));
348 io_apic_write(int_to_apicintpin[intr].ioapic,
349 select, (value & ~IOART_INTVEC) | vector);
353 case MACHINTR_VECTOR_SETDEFAULT:
355 * This is a just-in-case an int pin is running through the 8259
356 * when we don't expect it to, or an IO APIC pin somehow wound
357 * up getting enabled without us specifically programming it in
358 * this ABI. Note that IO APIC pins are by default programmed
359 * to IDT_OFFSET + intr.
361 vector = IDT_OFFSET + intr;
362 setidt(vector, apic_slowintr[intr], SDT_SYSIGT, SEL_KPL, 0);