2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
3 * Copyright (c) 2002-2008 Atheros Communications, Inc.
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 * $FreeBSD: head/sys/dev/ath/ath_hal/ar5416/ar5416_misc.c 203750 2010-02-10 11:11:37Z rpaulo $
23 #include "ah_internal.h"
26 #include "ah_desc.h" /* NB: for HAL_PHYERR* */
29 #include "ar5416/ar5416.h"
30 #include "ar5416/ar5416reg.h"
31 #include "ar5416/ar5416phy.h"
34 * Return the wireless modes (a,b,g,n,t) supported by hardware.
36 * This value is what is actually supported by the hardware
37 * and is unaffected by regulatory/country code settings.
41 ar5416GetWirelessModes(struct ath_hal *ah)
45 mode = ar5212GetWirelessModes(ah);
46 if (mode & HAL_MODE_11A)
47 mode |= HAL_MODE_11NA_HT20
48 | HAL_MODE_11NA_HT40PLUS
49 | HAL_MODE_11NA_HT40MINUS
51 if (mode & HAL_MODE_11G)
52 mode |= HAL_MODE_11NG_HT20
53 | HAL_MODE_11NG_HT40PLUS
54 | HAL_MODE_11NG_HT40MINUS
60 * Change the LED blinking pattern to correspond to the connectivity
63 ar5416SetLedState(struct ath_hal *ah, HAL_LED_STATE state)
65 static const uint32_t ledbits[8] = {
66 AR_MAC_LED_ASSOC_NONE, /* HAL_LED_INIT */
67 AR_MAC_LED_ASSOC_PEND, /* HAL_LED_SCAN */
68 AR_MAC_LED_ASSOC_PEND, /* HAL_LED_AUTH */
69 AR_MAC_LED_ASSOC_ACTIVE, /* HAL_LED_ASSOC*/
70 AR_MAC_LED_ASSOC_ACTIVE, /* HAL_LED_RUN */
71 AR_MAC_LED_ASSOC_NONE,
72 AR_MAC_LED_ASSOC_NONE,
73 AR_MAC_LED_ASSOC_NONE,
77 bits = OS_REG_READ(ah, AR_MAC_LED);
78 bits = (bits &~ AR_MAC_LED_MODE)
79 | SM(AR_MAC_LED_MODE_POWON, AR_MAC_LED_MODE)
81 | SM(AR_MAC_LED_MODE_NETON, AR_MAC_LED_MODE)
84 bits = (bits &~ AR_MAC_LED_ASSOC)
85 | SM(ledbits[state & 0x7], AR_MAC_LED_ASSOC);
86 OS_REG_WRITE(ah, AR_MAC_LED, bits);
90 * Reset the current hardware tsf for stamlme.
93 ar5416ResetTsf(struct ath_hal *ah)
98 for (i = 0; i < 10; i++) {
99 v = OS_REG_READ(ah, AR_SLP32_MODE);
100 if ((v & AR_SLP32_TSF_WRITE_STATUS) == 0)
104 OS_REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
108 ar5416SetAntennaSwitch(struct ath_hal *ah, HAL_ANT_SETTING settings)
113 /* Setup decompression for given key index */
115 ar5416SetDecompMask(struct ath_hal *ah, uint16_t keyidx, int en)
120 /* Setup coverage class */
122 ar5416SetCoverageClass(struct ath_hal *ah, uint8_t coverageclass, int now)
127 * Return approximation of extension channel busy over an time interval
128 * 0% (clear) -> 100% (busy)
132 ar5416Get11nExtBusy(struct ath_hal *ah)
134 struct ath_hal_5416 *ahp = AH5416(ah);
135 uint32_t busy; /* percentage */
136 uint32_t cycleCount, ctlBusy, extBusy;
138 ctlBusy = OS_REG_READ(ah, AR_RCCNT);
139 extBusy = OS_REG_READ(ah, AR_EXTRCCNT);
140 cycleCount = OS_REG_READ(ah, AR_CCCNT);
142 if (ahp->ah_cycleCount == 0 || ahp->ah_cycleCount > cycleCount) {
144 * Cycle counter wrap (or initial call); it's not possible
145 * to accurately calculate a value because the registers
146 * right shift rather than wrap--so punt and return 0.
149 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: cycle counter wrap. ExtBusy = 0\n",
153 uint32_t cycleDelta = cycleCount - ahp->ah_cycleCount;
154 uint32_t ctlBusyDelta = ctlBusy - ahp->ah_ctlBusy;
155 uint32_t extBusyDelta = extBusy - ahp->ah_extBusy;
156 uint32_t ctlClearDelta = 0;
158 /* Compute control channel rxclear.
159 * The cycle delta may be less than the control channel delta.
160 * This could be solved by freezing the timers (or an atomic read,
161 * if one was available). Checking for the condition should be
164 if (cycleDelta > ctlBusyDelta) {
165 ctlClearDelta = cycleDelta - ctlBusyDelta;
168 /* Compute ratio of extension channel busy to control channel clear
169 * as an approximation to extension channel cleanliness.
171 * According to the hardware folks, ext rxclear is undefined
172 * if the ctrl rxclear is de-asserted (i.e. busy)
175 busy = (extBusyDelta * 100) / ctlClearDelta;
183 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: cycleDelta 0x%x, ctlBusyDelta 0x%x, "
184 "extBusyDelta 0x%x, ctlClearDelta 0x%x, "
186 __func__, cycleDelta, ctlBusyDelta, extBusyDelta, ctlClearDelta, busy);
190 ahp->ah_cycleCount = cycleCount;
191 ahp->ah_ctlBusy = ctlBusy;
192 ahp->ah_extBusy = extBusy;
198 * Configure 20/40 operation
200 * 20/40 = joint rx clear (control and extension)
201 * 20 = rx clear (control)
203 * - NOTE: must stop MAC (tx) and requeue 40 MHz packets as 20 MHz when changing
204 * from 20/40 => 20 only
207 ar5416Set11nMac2040(struct ath_hal *ah, HAL_HT_MACMODE mode)
211 /* Configure MAC for 20/40 operation */
212 if (mode == HAL_HT_MACMODE_2040) {
213 macmode = AR_2040_JOINED_RX_CLEAR;
217 OS_REG_WRITE(ah, AR_2040_MODE, macmode);
221 * Get Rx clear (control/extension channel)
223 * Returns active low (busy) for ctrl/ext channel
227 ar5416Get11nRxClear(struct ath_hal *ah)
229 HAL_HT_RXCLEAR rxclear = 0;
232 val = OS_REG_READ(ah, AR_DIAG_SW);
234 /* control channel */
235 if (val & AR_DIAG_RXCLEAR_CTL_LOW) {
236 rxclear |= HAL_RX_CLEAR_CTL_LOW;
238 /* extension channel */
239 if (val & AR_DIAG_RXCLEAR_CTL_LOW) {
240 rxclear |= HAL_RX_CLEAR_EXT_LOW;
246 * Set Rx clear (control/extension channel)
248 * Useful for forcing the channel to appear busy for
249 * debugging/diagnostics
253 ar5416Set11nRxClear(struct ath_hal *ah, HAL_HT_RXCLEAR rxclear)
255 /* control channel */
256 if (rxclear & HAL_RX_CLEAR_CTL_LOW) {
257 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RXCLEAR_CTL_LOW);
259 OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_RXCLEAR_CTL_LOW);
261 /* extension channel */
262 if (rxclear & HAL_RX_CLEAR_EXT_LOW) {
263 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RXCLEAR_EXT_LOW);
265 OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_RXCLEAR_EXT_LOW);
270 ar5416GetCapability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type,
271 uint32_t capability, uint32_t *result)
274 case HAL_CAP_BB_HANG:
275 switch (capability) {
276 case HAL_BB_HANG_RIFS:
277 return AR_SREV_SOWL(ah) ? HAL_OK : HAL_ENOTSUPP;
278 case HAL_BB_HANG_DFS:
279 return AR_SREV_SOWL(ah) ? HAL_OK : HAL_ENOTSUPP;
280 case HAL_BB_HANG_RX_CLEAR:
281 return AR_SREV_MERLIN(ah) ? HAL_OK : HAL_ENOTSUPP;
284 case HAL_CAP_MAC_HANG:
285 return ((ah->ah_macVersion == AR_XSREV_VERSION_OWL_PCI) ||
286 (ah->ah_macVersion == AR_XSREV_VERSION_OWL_PCIE) ||
288 HAL_OK : HAL_ENOTSUPP;
292 return ar5212GetCapability(ah, type, capability, result);
295 static int ar5416DetectMacHang(struct ath_hal *ah);
296 static int ar5416DetectBBHang(struct ath_hal *ah);
299 ar5416GetDiagState(struct ath_hal *ah, int request,
300 const void *args, uint32_t argsize,
301 void **result, uint32_t *resultsize)
303 struct ath_hal_5416 *ahp = AH5416(ah);
306 if (ath_hal_getdiagstate(ah, request, args, argsize, result, resultsize))
309 case HAL_DIAG_EEPROM:
310 return ath_hal_eepromDiag(ah, request,
311 args, argsize, result, resultsize);
312 case HAL_DIAG_CHECK_HANGS:
313 if (argsize != sizeof(int))
315 hangs = *(const int *) args;
317 if (hangs & HAL_BB_HANGS)
318 ahp->ah_hangs |= ar5416DetectBBHang(ah);
319 /* NB: if BB is hung MAC will be hung too so skip check */
320 if (ahp->ah_hangs == 0 && (hangs & HAL_MAC_HANGS))
321 ahp->ah_hangs |= ar5416DetectMacHang(ah);
322 *result = &ahp->ah_hangs;
323 *resultsize = sizeof(ahp->ah_hangs);
326 return ar5212GetDiagState(ah, request,
327 args, argsize, result, resultsize);
338 dcu_chain_state = 0x1,
339 dcu_complete_state = 0x2,
342 qcu_fsp_state = 0x10,
343 qcu_stitch_state = 0x20,
344 qcu_fetch_state = 0x40,
345 qcu_complete_state = 0x80
350 uint8_t dcu_chain_state;
351 uint8_t dcu_complete_state;
354 uint8_t qcu_fsp_state;
355 uint8_t qcu_stitch_state;
356 uint8_t qcu_fetch_state;
357 uint8_t qcu_complete_state;
358 } hal_mac_hang_check_t;
361 ar5416CompareDbgHang(struct ath_hal *ah, const mac_dbg_regs_t *regs,
362 const hal_mac_hang_check_t *check)
367 if (check->states & dcu_chain_state) {
370 for (i = 0; i < 6; i++) {
371 if (((regs->dma_dbg_4 >> (5*i)) & 0x1f) ==
372 check->dcu_chain_state)
373 found_states |= dcu_chain_state;
375 for (i = 0; i < 4; i++) {
376 if (((regs->dma_dbg_5 >> (5*i)) & 0x1f) ==
377 check->dcu_chain_state)
378 found_states |= dcu_chain_state;
381 if (check->states & dcu_complete_state) {
382 if ((regs->dma_dbg_6 & 0x3) == check->dcu_complete_state)
383 found_states |= dcu_complete_state;
385 if (check->states & qcu_stitch_state) {
386 if (((regs->dma_dbg_3 >> 18) & 0xf) == check->qcu_stitch_state)
387 found_states |= qcu_stitch_state;
389 if (check->states & qcu_fetch_state) {
390 if (((regs->dma_dbg_3 >> 22) & 0xf) == check->qcu_fetch_state)
391 found_states |= qcu_fetch_state;
393 if (check->states & qcu_complete_state) {
394 if (((regs->dma_dbg_3 >> 26) & 0x7) == check->qcu_complete_state)
395 found_states |= qcu_complete_state;
397 return (found_states == check->states);
400 #define NUM_STATUS_READS 50
403 ar5416DetectMacHang(struct ath_hal *ah)
405 static const hal_mac_hang_check_t hang_sig1 = {
406 .dcu_chain_state = 0x6,
407 .dcu_complete_state = 0x1,
408 .states = dcu_chain_state
409 | dcu_complete_state,
411 static const hal_mac_hang_check_t hang_sig2 = {
412 .qcu_stitch_state = 0x9,
413 .qcu_fetch_state = 0x8,
414 .qcu_complete_state = 0x4,
415 .states = qcu_stitch_state
417 | qcu_complete_state,
419 mac_dbg_regs_t mac_dbg;
422 mac_dbg.dma_dbg_3 = OS_REG_READ(ah, AR_DMADBG_3);
423 mac_dbg.dma_dbg_4 = OS_REG_READ(ah, AR_DMADBG_4);
424 mac_dbg.dma_dbg_5 = OS_REG_READ(ah, AR_DMADBG_5);
425 mac_dbg.dma_dbg_6 = OS_REG_READ(ah, AR_DMADBG_6);
426 for (i = 1; i <= NUM_STATUS_READS; i++) {
427 if (mac_dbg.dma_dbg_3 != OS_REG_READ(ah, AR_DMADBG_3) ||
428 mac_dbg.dma_dbg_4 != OS_REG_READ(ah, AR_DMADBG_4) ||
429 mac_dbg.dma_dbg_5 != OS_REG_READ(ah, AR_DMADBG_5) ||
430 mac_dbg.dma_dbg_6 != OS_REG_READ(ah, AR_DMADBG_6))
434 if (ar5416CompareDbgHang(ah, &mac_dbg, &hang_sig1))
435 return HAL_MAC_HANG_SIG1;
436 if (ar5416CompareDbgHang(ah, &mac_dbg, &hang_sig2))
437 return HAL_MAC_HANG_SIG2;
439 HALDEBUG(ah, HAL_DEBUG_ANY, "%s Found an unknown MAC hang signature "
440 "DMADBG_3=0x%x DMADBG_4=0x%x DMADBG_5=0x%x DMADBG_6=0x%x\n",
441 __func__, mac_dbg.dma_dbg_3, mac_dbg.dma_dbg_4, mac_dbg.dma_dbg_5,
444 return HAL_MAC_HANG_UNKNOWN;
448 * Determine if the baseband using the Observation Bus Register
451 ar5416DetectBBHang(struct ath_hal *ah)
453 #define N(a) (sizeof(a)/sizeof(a[0]))
455 * Check the PCU Observation Bus 1 register (0x806c)
456 * NUM_STATUS_READS times
458 * 4 known BB hang signatures -
459 * [1] bits 8,9,11 are 0. State machine state (bits 25-31) is 0x1E
460 * [2] bits 8,9 are 1, bit 11 is 0. State machine state
461 * (bits 25-31) is 0x52
462 * [3] bits 8,9 are 1, bit 11 is 0. State machine state
463 * (bits 25-31) is 0x18
464 * [4] bit 10 is 1, bit 11 is 0. WEP state (bits 12-17) is 0x2,
465 * Rx State (bits 20-24) is 0x7.
467 static const struct {
472 /* Reg Value Reg Mask Hang Code XXX */
473 { 0x1E000000, 0x7E000B00, HAL_BB_HANG_DFS },
474 { 0x52000B00, 0x7E000B00, HAL_BB_HANG_RIFS },
475 { 0x18000B00, 0x7E000B00, HAL_BB_HANG_RX_CLEAR },
476 { 0x00702400, 0x7E7FFFEF, HAL_BB_HANG_RX_CLEAR }
481 hang_sig = OS_REG_READ(ah, AR_OBSERV_1);
482 for (i = 1; i <= NUM_STATUS_READS; i++) {
483 if (hang_sig != OS_REG_READ(ah, AR_OBSERV_1))
486 for (i = 0; i < N(hang_list); i++)
487 if ((hang_sig & hang_list[i].mask) == hang_list[i].val) {
488 HALDEBUG(ah, HAL_DEBUG_ANY,
489 "%s BB hang, signature 0x%x, code 0x%x\n",
490 __func__, hang_sig, hang_list[i].code);
491 return hang_list[i].code;
494 HALDEBUG(ah, HAL_DEBUG_ANY, "%s Found an unknown BB hang signature! "
495 "<0x806c>=0x%x\n", __func__, hang_sig);
497 return HAL_BB_HANG_UNKNOWN;
500 #undef NUM_STATUS_READS