1 /******************************************************************************
3 Copyright (c) 2001-2010, Intel Corporation
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7 modification, are permitted provided that the following conditions are met:
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13 notice, this list of conditions and the following disclaimer in the
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32 ******************************************************************************/
35 #include "e1000_api.h"
37 static s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw);
38 static void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw);
41 * e1000_init_mac_ops_generic - Initialize MAC function pointers
42 * @hw: pointer to the HW structure
44 * Setups up the function pointers to no-op functions
46 void e1000_init_mac_ops_generic(struct e1000_hw *hw)
48 struct e1000_mac_info *mac = &hw->mac;
49 DEBUGFUNC("e1000_init_mac_ops_generic");
52 mac->ops.init_params = e1000_null_ops_generic;
53 mac->ops.init_hw = e1000_null_ops_generic;
54 mac->ops.reset_hw = e1000_null_ops_generic;
55 mac->ops.setup_physical_interface = e1000_null_ops_generic;
56 mac->ops.get_bus_info = e1000_null_ops_generic;
57 mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pcie;
58 mac->ops.read_mac_addr = e1000_read_mac_addr_generic;
59 mac->ops.config_collision_dist = e1000_config_collision_dist_generic;
60 mac->ops.clear_hw_cntrs = e1000_null_mac_generic;
62 mac->ops.cleanup_led = e1000_null_ops_generic;
63 mac->ops.setup_led = e1000_null_ops_generic;
64 mac->ops.blink_led = e1000_null_ops_generic;
65 mac->ops.led_on = e1000_null_ops_generic;
66 mac->ops.led_off = e1000_null_ops_generic;
68 mac->ops.setup_link = e1000_null_ops_generic;
69 mac->ops.get_link_up_info = e1000_null_link_info;
70 mac->ops.check_for_link = e1000_null_ops_generic;
71 mac->ops.wait_autoneg = e1000_wait_autoneg_generic;
73 mac->ops.check_mng_mode = e1000_null_mng_mode;
74 mac->ops.mng_host_if_write = e1000_mng_host_if_write_generic;
75 mac->ops.mng_write_cmd_header = e1000_mng_write_cmd_header_generic;
76 mac->ops.mng_enable_host_if = e1000_mng_enable_host_if_generic;
78 mac->ops.update_mc_addr_list = e1000_null_update_mc;
79 mac->ops.clear_vfta = e1000_null_mac_generic;
80 mac->ops.write_vfta = e1000_null_write_vfta;
81 mac->ops.rar_set = e1000_rar_set_generic;
82 mac->ops.validate_mdi_setting = e1000_validate_mdi_setting_generic;
86 * e1000_null_ops_generic - No-op function, returns 0
87 * @hw: pointer to the HW structure
89 s32 e1000_null_ops_generic(struct e1000_hw *hw)
91 DEBUGFUNC("e1000_null_ops_generic");
96 * e1000_null_mac_generic - No-op function, return void
97 * @hw: pointer to the HW structure
99 void e1000_null_mac_generic(struct e1000_hw *hw)
101 DEBUGFUNC("e1000_null_mac_generic");
106 * e1000_null_link_info - No-op function, return 0
107 * @hw: pointer to the HW structure
109 s32 e1000_null_link_info(struct e1000_hw *hw, u16 *s, u16 *d)
111 DEBUGFUNC("e1000_null_link_info");
112 return E1000_SUCCESS;
116 * e1000_null_mng_mode - No-op function, return FALSE
117 * @hw: pointer to the HW structure
119 bool e1000_null_mng_mode(struct e1000_hw *hw)
121 DEBUGFUNC("e1000_null_mng_mode");
126 * e1000_null_update_mc - No-op function, return void
127 * @hw: pointer to the HW structure
129 void e1000_null_update_mc(struct e1000_hw *hw, u8 *h, u32 a)
131 DEBUGFUNC("e1000_null_update_mc");
136 * e1000_null_write_vfta - No-op function, return void
137 * @hw: pointer to the HW structure
139 void e1000_null_write_vfta(struct e1000_hw *hw, u32 a, u32 b)
141 DEBUGFUNC("e1000_null_write_vfta");
146 * e1000_null_rar_set - No-op function, return void
147 * @hw: pointer to the HW structure
149 void e1000_null_rar_set(struct e1000_hw *hw, u8 *h, u32 a)
151 DEBUGFUNC("e1000_null_rar_set");
156 * e1000_get_bus_info_pci_generic - Get PCI(x) bus information
157 * @hw: pointer to the HW structure
159 * Determines and stores the system bus information for a particular
160 * network interface. The following bus information is determined and stored:
161 * bus speed, bus width, type (PCI/PCIx), and PCI(-x) function.
163 s32 e1000_get_bus_info_pci_generic(struct e1000_hw *hw)
165 struct e1000_mac_info *mac = &hw->mac;
166 struct e1000_bus_info *bus = &hw->bus;
167 u32 status = E1000_READ_REG(hw, E1000_STATUS);
168 s32 ret_val = E1000_SUCCESS;
170 DEBUGFUNC("e1000_get_bus_info_pci_generic");
173 bus->type = (status & E1000_STATUS_PCIX_MODE)
174 ? e1000_bus_type_pcix
175 : e1000_bus_type_pci;
178 if (bus->type == e1000_bus_type_pci) {
179 bus->speed = (status & E1000_STATUS_PCI66)
181 : e1000_bus_speed_33;
183 switch (status & E1000_STATUS_PCIX_SPEED) {
184 case E1000_STATUS_PCIX_SPEED_66:
185 bus->speed = e1000_bus_speed_66;
187 case E1000_STATUS_PCIX_SPEED_100:
188 bus->speed = e1000_bus_speed_100;
190 case E1000_STATUS_PCIX_SPEED_133:
191 bus->speed = e1000_bus_speed_133;
194 bus->speed = e1000_bus_speed_reserved;
200 bus->width = (status & E1000_STATUS_BUS64)
202 : e1000_bus_width_32;
204 /* Which PCI(-X) function? */
205 mac->ops.set_lan_id(hw);
211 * e1000_get_bus_info_pcie_generic - Get PCIe bus information
212 * @hw: pointer to the HW structure
214 * Determines and stores the system bus information for a particular
215 * network interface. The following bus information is determined and stored:
216 * bus speed, bus width, type (PCIe), and PCIe function.
218 s32 e1000_get_bus_info_pcie_generic(struct e1000_hw *hw)
220 struct e1000_mac_info *mac = &hw->mac;
221 struct e1000_bus_info *bus = &hw->bus;
223 u16 pcie_link_status;
225 DEBUGFUNC("e1000_get_bus_info_pcie_generic");
227 bus->type = e1000_bus_type_pci_express;
228 bus->speed = e1000_bus_speed_2500;
230 ret_val = e1000_read_pcie_cap_reg(hw,
234 bus->width = e1000_bus_width_unknown;
236 bus->width = (enum e1000_bus_width)((pcie_link_status &
237 PCIE_LINK_WIDTH_MASK) >>
238 PCIE_LINK_WIDTH_SHIFT);
240 mac->ops.set_lan_id(hw);
242 return E1000_SUCCESS;
246 * e1000_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
248 * @hw: pointer to the HW structure
250 * Determines the LAN function id by reading memory-mapped registers
251 * and swaps the port value if requested.
253 static void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw)
255 struct e1000_bus_info *bus = &hw->bus;
259 * The status register reports the correct function number
260 * for the device regardless of function swap state.
262 reg = E1000_READ_REG(hw, E1000_STATUS);
263 bus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT;
267 * e1000_set_lan_id_multi_port_pci - Set LAN id for PCI multiple port devices
268 * @hw: pointer to the HW structure
270 * Determines the LAN function id by reading PCI config space.
272 void e1000_set_lan_id_multi_port_pci(struct e1000_hw *hw)
274 struct e1000_bus_info *bus = &hw->bus;
278 e1000_read_pci_cfg(hw, PCI_HEADER_TYPE_REGISTER, &pci_header_type);
279 if (pci_header_type & PCI_HEADER_TYPE_MULTIFUNC) {
280 status = E1000_READ_REG(hw, E1000_STATUS);
281 bus->func = (status & E1000_STATUS_FUNC_MASK)
282 >> E1000_STATUS_FUNC_SHIFT;
289 * e1000_set_lan_id_single_port - Set LAN id for a single port device
290 * @hw: pointer to the HW structure
292 * Sets the LAN function id to zero for a single port device.
294 void e1000_set_lan_id_single_port(struct e1000_hw *hw)
296 struct e1000_bus_info *bus = &hw->bus;
302 * e1000_clear_vfta_generic - Clear VLAN filter table
303 * @hw: pointer to the HW structure
305 * Clears the register array which contains the VLAN filter table by
306 * setting all the values to 0.
308 void e1000_clear_vfta_generic(struct e1000_hw *hw)
312 DEBUGFUNC("e1000_clear_vfta_generic");
314 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
315 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0);
316 E1000_WRITE_FLUSH(hw);
321 * e1000_write_vfta_generic - Write value to VLAN filter table
322 * @hw: pointer to the HW structure
323 * @offset: register offset in VLAN filter table
324 * @value: register value written to VLAN filter table
326 * Writes value at the given offset in the register array which stores
327 * the VLAN filter table.
329 void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value)
331 DEBUGFUNC("e1000_write_vfta_generic");
333 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
334 E1000_WRITE_FLUSH(hw);
338 * e1000_init_rx_addrs_generic - Initialize receive address's
339 * @hw: pointer to the HW structure
340 * @rar_count: receive address registers
342 * Setups the receive address registers by setting the base receive address
343 * register to the devices MAC address and clearing all the other receive
344 * address registers to 0.
346 void e1000_init_rx_addrs_generic(struct e1000_hw *hw, u16 rar_count)
349 u8 mac_addr[ETH_ADDR_LEN] = {0};
351 DEBUGFUNC("e1000_init_rx_addrs_generic");
353 /* Setup the receive address */
354 DEBUGOUT("Programming MAC Address into RAR[0]\n");
356 hw->mac.ops.rar_set(hw, hw->mac.addr, 0);
358 /* Zero out the other (rar_entry_count - 1) receive addresses */
359 DEBUGOUT1("Clearing RAR[1-%u]\n", rar_count-1);
360 for (i = 1; i < rar_count; i++)
361 hw->mac.ops.rar_set(hw, mac_addr, i);
365 * e1000_check_alt_mac_addr_generic - Check for alternate MAC addr
366 * @hw: pointer to the HW structure
368 * Checks the nvm for an alternate MAC address. An alternate MAC address
369 * can be setup by pre-boot software and must be treated like a permanent
370 * address and must override the actual permanent MAC address. If an
371 * alternate MAC address is found it is programmed into RAR0, replacing
372 * the permanent address that was installed into RAR0 by the Si on reset.
373 * This function will return SUCCESS unless it encounters an error while
374 * reading the EEPROM.
376 s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw)
379 s32 ret_val = E1000_SUCCESS;
380 u16 offset, nvm_alt_mac_addr_offset, nvm_data;
381 u8 alt_mac_addr[ETH_ADDR_LEN];
383 DEBUGFUNC("e1000_check_alt_mac_addr_generic");
385 ret_val = hw->nvm.ops.read(hw, NVM_ALT_MAC_ADDR_PTR, 1,
386 &nvm_alt_mac_addr_offset);
388 DEBUGOUT("NVM Read Error\n");
392 if (nvm_alt_mac_addr_offset == 0xFFFF) {
393 /* There is no Alternate MAC Address */
397 if (hw->bus.func == E1000_FUNC_1)
398 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN1;
399 if (hw->bus.func == E1000_FUNC_2)
400 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN2;
402 if (hw->bus.func == E1000_FUNC_3)
403 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN3;
404 for (i = 0; i < ETH_ADDR_LEN; i += 2) {
405 offset = nvm_alt_mac_addr_offset + (i >> 1);
406 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data);
408 DEBUGOUT("NVM Read Error\n");
412 alt_mac_addr[i] = (u8)(nvm_data & 0xFF);
413 alt_mac_addr[i + 1] = (u8)(nvm_data >> 8);
416 /* if multicast bit is set, the alternate address will not be used */
417 if (alt_mac_addr[0] & 0x01) {
418 DEBUGOUT("Ignoring Alternate Mac Address with MC bit set\n");
423 * We have a valid alternate MAC address, and we want to treat it the
424 * same as the normal permanent MAC address stored by the HW into the
425 * RAR. Do this by mapping this address into RAR0.
427 hw->mac.ops.rar_set(hw, alt_mac_addr, 0);
434 * e1000_rar_set_generic - Set receive address register
435 * @hw: pointer to the HW structure
436 * @addr: pointer to the receive address
437 * @index: receive address array register
439 * Sets the receive address array register at index to the address passed
442 void e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index)
444 u32 rar_low, rar_high;
446 DEBUGFUNC("e1000_rar_set_generic");
449 * HW expects these in little endian so we reverse the byte order
450 * from network order (big endian) to little endian
452 rar_low = ((u32) addr[0] |
453 ((u32) addr[1] << 8) |
454 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
456 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
458 /* If MAC address zero, no need to set the AV bit */
459 if (rar_low || rar_high)
460 rar_high |= E1000_RAH_AV;
463 * Some bridges will combine consecutive 32-bit writes into
464 * a single burst write, which will malfunction on some parts.
465 * The flushes avoid this.
467 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low);
468 E1000_WRITE_FLUSH(hw);
469 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high);
470 E1000_WRITE_FLUSH(hw);
474 * e1000_update_mc_addr_list_generic - Update Multicast addresses
475 * @hw: pointer to the HW structure
476 * @mc_addr_list: array of multicast addresses to program
477 * @mc_addr_count: number of multicast addresses to program
479 * Updates entire Multicast Table Array.
480 * The caller must have a packed mc_addr_list of multicast addresses.
482 void e1000_update_mc_addr_list_generic(struct e1000_hw *hw,
483 u8 *mc_addr_list, u32 mc_addr_count)
485 u32 hash_value, hash_bit, hash_reg;
488 DEBUGFUNC("e1000_update_mc_addr_list_generic");
490 /* clear mta_shadow */
491 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
493 /* update mta_shadow from mc_addr_list */
494 for (i = 0; (u32) i < mc_addr_count; i++) {
495 hash_value = e1000_hash_mc_addr_generic(hw, mc_addr_list);
497 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1);
498 hash_bit = hash_value & 0x1F;
500 hw->mac.mta_shadow[hash_reg] |= (1 << hash_bit);
501 mc_addr_list += (ETH_ADDR_LEN);
504 /* replace the entire MTA table */
505 for (i = hw->mac.mta_reg_count - 1; i >= 0; i--)
506 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, hw->mac.mta_shadow[i]);
507 E1000_WRITE_FLUSH(hw);
511 * e1000_hash_mc_addr_generic - Generate a multicast hash value
512 * @hw: pointer to the HW structure
513 * @mc_addr: pointer to a multicast address
515 * Generates a multicast address hash value which is used to determine
516 * the multicast filter table array address and new table value.
518 u32 e1000_hash_mc_addr_generic(struct e1000_hw *hw, u8 *mc_addr)
520 u32 hash_value, hash_mask;
523 DEBUGFUNC("e1000_hash_mc_addr_generic");
525 /* Register count multiplied by bits per register */
526 hash_mask = (hw->mac.mta_reg_count * 32) - 1;
529 * For a mc_filter_type of 0, bit_shift is the number of left-shifts
530 * where 0xFF would still fall within the hash mask.
532 while (hash_mask >> bit_shift != 0xFF)
536 * The portion of the address that is used for the hash table
537 * is determined by the mc_filter_type setting.
538 * The algorithm is such that there is a total of 8 bits of shifting.
539 * The bit_shift for a mc_filter_type of 0 represents the number of
540 * left-shifts where the MSB of mc_addr[5] would still fall within
541 * the hash_mask. Case 0 does this exactly. Since there are a total
542 * of 8 bits of shifting, then mc_addr[4] will shift right the
543 * remaining number of bits. Thus 8 - bit_shift. The rest of the
544 * cases are a variation of this algorithm...essentially raising the
545 * number of bits to shift mc_addr[5] left, while still keeping the
546 * 8-bit shifting total.
548 * For example, given the following Destination MAC Address and an
549 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask),
550 * we can see that the bit_shift for case 0 is 4. These are the hash
551 * values resulting from each mc_filter_type...
552 * [0] [1] [2] [3] [4] [5]
556 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563
557 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6
558 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163
559 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634
561 switch (hw->mac.mc_filter_type) {
576 hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) |
577 (((u16) mc_addr[5]) << bit_shift)));
583 * e1000_pcix_mmrbc_workaround_generic - Fix incorrect MMRBC value
584 * @hw: pointer to the HW structure
586 * In certain situations, a system BIOS may report that the PCIx maximum
587 * memory read byte count (MMRBC) value is higher than than the actual
588 * value. We check the PCIx command register with the current PCIx status
591 void e1000_pcix_mmrbc_workaround_generic(struct e1000_hw *hw)
595 u16 pcix_stat_hi_word;
598 DEBUGFUNC("e1000_pcix_mmrbc_workaround_generic");
600 /* Workaround for PCI-X issue when BIOS sets MMRBC incorrectly */
601 if (hw->bus.type != e1000_bus_type_pcix)
604 e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd);
605 e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI, &pcix_stat_hi_word);
606 cmd_mmrbc = (pcix_cmd & PCIX_COMMAND_MMRBC_MASK) >>
607 PCIX_COMMAND_MMRBC_SHIFT;
608 stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
609 PCIX_STATUS_HI_MMRBC_SHIFT;
610 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
611 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
612 if (cmd_mmrbc > stat_mmrbc) {
613 pcix_cmd &= ~PCIX_COMMAND_MMRBC_MASK;
614 pcix_cmd |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
615 e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd);
620 * e1000_clear_hw_cntrs_base_generic - Clear base hardware counters
621 * @hw: pointer to the HW structure
623 * Clears the base hardware counters by reading the counter registers.
625 void e1000_clear_hw_cntrs_base_generic(struct e1000_hw *hw)
627 DEBUGFUNC("e1000_clear_hw_cntrs_base_generic");
629 E1000_READ_REG(hw, E1000_CRCERRS);
630 E1000_READ_REG(hw, E1000_SYMERRS);
631 E1000_READ_REG(hw, E1000_MPC);
632 E1000_READ_REG(hw, E1000_SCC);
633 E1000_READ_REG(hw, E1000_ECOL);
634 E1000_READ_REG(hw, E1000_MCC);
635 E1000_READ_REG(hw, E1000_LATECOL);
636 E1000_READ_REG(hw, E1000_COLC);
637 E1000_READ_REG(hw, E1000_DC);
638 E1000_READ_REG(hw, E1000_SEC);
639 E1000_READ_REG(hw, E1000_RLEC);
640 E1000_READ_REG(hw, E1000_XONRXC);
641 E1000_READ_REG(hw, E1000_XONTXC);
642 E1000_READ_REG(hw, E1000_XOFFRXC);
643 E1000_READ_REG(hw, E1000_XOFFTXC);
644 E1000_READ_REG(hw, E1000_FCRUC);
645 E1000_READ_REG(hw, E1000_GPRC);
646 E1000_READ_REG(hw, E1000_BPRC);
647 E1000_READ_REG(hw, E1000_MPRC);
648 E1000_READ_REG(hw, E1000_GPTC);
649 E1000_READ_REG(hw, E1000_GORCL);
650 E1000_READ_REG(hw, E1000_GORCH);
651 E1000_READ_REG(hw, E1000_GOTCL);
652 E1000_READ_REG(hw, E1000_GOTCH);
653 E1000_READ_REG(hw, E1000_RNBC);
654 E1000_READ_REG(hw, E1000_RUC);
655 E1000_READ_REG(hw, E1000_RFC);
656 E1000_READ_REG(hw, E1000_ROC);
657 E1000_READ_REG(hw, E1000_RJC);
658 E1000_READ_REG(hw, E1000_TORL);
659 E1000_READ_REG(hw, E1000_TORH);
660 E1000_READ_REG(hw, E1000_TOTL);
661 E1000_READ_REG(hw, E1000_TOTH);
662 E1000_READ_REG(hw, E1000_TPR);
663 E1000_READ_REG(hw, E1000_TPT);
664 E1000_READ_REG(hw, E1000_MPTC);
665 E1000_READ_REG(hw, E1000_BPTC);
669 * e1000_check_for_copper_link_generic - Check for link (Copper)
670 * @hw: pointer to the HW structure
672 * Checks to see of the link status of the hardware has changed. If a
673 * change in link status has been detected, then we read the PHY registers
674 * to get the current speed/duplex if link exists.
676 s32 e1000_check_for_copper_link_generic(struct e1000_hw *hw)
678 struct e1000_mac_info *mac = &hw->mac;
682 DEBUGFUNC("e1000_check_for_copper_link");
685 * We only want to go out to the PHY registers to see if Auto-Neg
686 * has completed and/or if our link status has changed. The
687 * get_link_status flag is set upon receiving a Link Status
688 * Change or Rx Sequence Error interrupt.
690 if (!mac->get_link_status) {
691 ret_val = E1000_SUCCESS;
696 * First we want to see if the MII Status Register reports
697 * link. If so, then we want to get the current speed/duplex
700 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
705 goto out; /* No link detected */
707 mac->get_link_status = FALSE;
710 * Check if there was DownShift, must be checked
711 * immediately after link-up
713 e1000_check_downshift_generic(hw);
716 * If we are forcing speed/duplex, then we simply return since
717 * we have already determined whether we have link or not.
720 ret_val = -E1000_ERR_CONFIG;
725 * Auto-Neg is enabled. Auto Speed Detection takes care
726 * of MAC speed/duplex configuration. So we only need to
727 * configure Collision Distance in the MAC.
729 mac->ops.config_collision_dist(hw);
732 * Configure Flow Control now that Auto-Neg has completed.
733 * First, we need to restore the desired flow control
734 * settings because we may have had to re-autoneg with a
735 * different link partner.
737 ret_val = e1000_config_fc_after_link_up_generic(hw);
739 DEBUGOUT("Error configuring flow control\n");
746 * e1000_check_for_fiber_link_generic - Check for link (Fiber)
747 * @hw: pointer to the HW structure
749 * Checks for link up on the hardware. If link is not up and we have
750 * a signal, then we need to force link up.
752 s32 e1000_check_for_fiber_link_generic(struct e1000_hw *hw)
754 struct e1000_mac_info *mac = &hw->mac;
758 s32 ret_val = E1000_SUCCESS;
760 DEBUGFUNC("e1000_check_for_fiber_link_generic");
762 ctrl = E1000_READ_REG(hw, E1000_CTRL);
763 status = E1000_READ_REG(hw, E1000_STATUS);
764 rxcw = E1000_READ_REG(hw, E1000_RXCW);
767 * If we don't have link (auto-negotiation failed or link partner
768 * cannot auto-negotiate), the cable is plugged in (we have signal),
769 * and our link partner is not trying to auto-negotiate with us (we
770 * are receiving idles or data), we need to force link up. We also
771 * need to give auto-negotiation time to complete, in case the cable
772 * was just plugged in. The autoneg_failed flag does this.
774 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
775 if ((ctrl & E1000_CTRL_SWDPIN1) && (!(status & E1000_STATUS_LU)) &&
776 (!(rxcw & E1000_RXCW_C))) {
777 if (mac->autoneg_failed == 0) {
778 mac->autoneg_failed = 1;
781 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n");
783 /* Disable auto-negotiation in the TXCW register */
784 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE));
786 /* Force link-up and also force full-duplex. */
787 ctrl = E1000_READ_REG(hw, E1000_CTRL);
788 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
789 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
791 /* Configure Flow Control after forcing link up. */
792 ret_val = e1000_config_fc_after_link_up_generic(hw);
794 DEBUGOUT("Error configuring flow control\n");
797 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
799 * If we are forcing link and we are receiving /C/ ordered
800 * sets, re-enable auto-negotiation in the TXCW register
801 * and disable forced link in the Device Control register
802 * in an attempt to auto-negotiate with our link partner.
804 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n");
805 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
806 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU));
808 mac->serdes_has_link = TRUE;
816 * e1000_check_for_serdes_link_generic - Check for link (Serdes)
817 * @hw: pointer to the HW structure
819 * Checks for link up on the hardware. If link is not up and we have
820 * a signal, then we need to force link up.
822 s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw)
824 struct e1000_mac_info *mac = &hw->mac;
828 s32 ret_val = E1000_SUCCESS;
830 DEBUGFUNC("e1000_check_for_serdes_link_generic");
832 ctrl = E1000_READ_REG(hw, E1000_CTRL);
833 status = E1000_READ_REG(hw, E1000_STATUS);
834 rxcw = E1000_READ_REG(hw, E1000_RXCW);
837 * If we don't have link (auto-negotiation failed or link partner
838 * cannot auto-negotiate), and our link partner is not trying to
839 * auto-negotiate with us (we are receiving idles or data),
840 * we need to force link up. We also need to give auto-negotiation
843 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
844 if ((!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) {
845 if (mac->autoneg_failed == 0) {
846 mac->autoneg_failed = 1;
849 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n");
851 /* Disable auto-negotiation in the TXCW register */
852 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE));
854 /* Force link-up and also force full-duplex. */
855 ctrl = E1000_READ_REG(hw, E1000_CTRL);
856 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
857 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
859 /* Configure Flow Control after forcing link up. */
860 ret_val = e1000_config_fc_after_link_up_generic(hw);
862 DEBUGOUT("Error configuring flow control\n");
865 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
867 * If we are forcing link and we are receiving /C/ ordered
868 * sets, re-enable auto-negotiation in the TXCW register
869 * and disable forced link in the Device Control register
870 * in an attempt to auto-negotiate with our link partner.
872 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n");
873 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
874 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU));
876 mac->serdes_has_link = TRUE;
877 } else if (!(E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW))) {
879 * If we force link for non-auto-negotiation switch, check
880 * link status based on MAC synchronization for internal
883 /* SYNCH bit and IV bit are sticky. */
885 rxcw = E1000_READ_REG(hw, E1000_RXCW);
886 if (rxcw & E1000_RXCW_SYNCH) {
887 if (!(rxcw & E1000_RXCW_IV)) {
888 mac->serdes_has_link = TRUE;
889 DEBUGOUT("SERDES: Link up - forced.\n");
892 mac->serdes_has_link = FALSE;
893 DEBUGOUT("SERDES: Link down - force failed.\n");
897 if (E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW)) {
898 status = E1000_READ_REG(hw, E1000_STATUS);
899 if (status & E1000_STATUS_LU) {
900 /* SYNCH bit and IV bit are sticky, so reread rxcw. */
902 rxcw = E1000_READ_REG(hw, E1000_RXCW);
903 if (rxcw & E1000_RXCW_SYNCH) {
904 if (!(rxcw & E1000_RXCW_IV)) {
905 mac->serdes_has_link = TRUE;
906 DEBUGOUT("SERDES: Link up - autoneg "
907 "completed sucessfully.\n");
909 mac->serdes_has_link = FALSE;
910 DEBUGOUT("SERDES: Link down - invalid"
911 "codewords detected in autoneg.\n");
914 mac->serdes_has_link = FALSE;
915 DEBUGOUT("SERDES: Link down - no sync.\n");
918 mac->serdes_has_link = FALSE;
919 DEBUGOUT("SERDES: Link down - autoneg failed\n");
928 * e1000_setup_link_generic - Setup flow control and link settings
929 * @hw: pointer to the HW structure
931 * Determines which flow control settings to use, then configures flow
932 * control. Calls the appropriate media-specific link configuration
933 * function. Assuming the adapter has a valid link partner, a valid link
934 * should be established. Assumes the hardware has previously been reset
935 * and the transmitter and receiver are not enabled.
937 s32 e1000_setup_link_generic(struct e1000_hw *hw)
939 s32 ret_val = E1000_SUCCESS;
941 DEBUGFUNC("e1000_setup_link_generic");
944 * In the case of the phy reset being blocked, we already have a link.
945 * We do not need to set it up again.
947 if (e1000_check_reset_block(hw))
951 * If requested flow control is set to default, set flow control
952 * based on the EEPROM flow control settings.
954 if (hw->fc.requested_mode == e1000_fc_default) {
955 ret_val = e1000_set_default_fc_generic(hw);
961 * Save off the requested flow control mode for use later. Depending
962 * on the link partner's capabilities, we may or may not use this mode.
964 hw->fc.current_mode = hw->fc.requested_mode;
966 DEBUGOUT1("After fix-ups FlowControl is now = %x\n",
967 hw->fc.current_mode);
969 /* Call the necessary media_type subroutine to configure the link. */
970 ret_val = hw->mac.ops.setup_physical_interface(hw);
975 * Initialize the flow control address, type, and PAUSE timer
976 * registers to their default values. This is done even if flow
977 * control is disabled, because it does not hurt anything to
978 * initialize these registers.
980 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");
981 E1000_WRITE_REG(hw, E1000_FCT, FLOW_CONTROL_TYPE);
982 E1000_WRITE_REG(hw, E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH);
983 E1000_WRITE_REG(hw, E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW);
985 E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time);
987 ret_val = e1000_set_fc_watermarks_generic(hw);
994 * e1000_setup_fiber_serdes_link_generic - Setup link for fiber/serdes
995 * @hw: pointer to the HW structure
997 * Configures collision distance and flow control for fiber and serdes
998 * links. Upon successful setup, poll for link.
1000 s32 e1000_setup_fiber_serdes_link_generic(struct e1000_hw *hw)
1002 struct e1000_mac_info *mac = &hw->mac;
1004 s32 ret_val = E1000_SUCCESS;
1006 DEBUGFUNC("e1000_setup_fiber_serdes_link_generic");
1008 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1010 /* Take the link out of reset */
1011 ctrl &= ~E1000_CTRL_LRST;
1013 mac->ops.config_collision_dist(hw);
1015 ret_val = e1000_commit_fc_settings_generic(hw);
1020 * Since auto-negotiation is enabled, take the link out of reset (the
1021 * link will be in reset, because we previously reset the chip). This
1022 * will restart auto-negotiation. If auto-negotiation is successful
1023 * then the link-up status bit will be set and the flow control enable
1024 * bits (RFCE and TFCE) will be set according to their negotiated value.
1026 DEBUGOUT("Auto-negotiation enabled\n");
1028 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1029 E1000_WRITE_FLUSH(hw);
1033 * For these adapters, the SW definable pin 1 is set when the optics
1034 * detect a signal. If we have a signal, then poll for a "Link-Up"
1037 if (hw->phy.media_type == e1000_media_type_internal_serdes ||
1038 (E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1)) {
1039 ret_val = e1000_poll_fiber_serdes_link_generic(hw);
1041 DEBUGOUT("No signal detected\n");
1049 * e1000_config_collision_dist_generic - Configure collision distance
1050 * @hw: pointer to the HW structure
1052 * Configures the collision distance to the default value and is used
1053 * during link setup.
1055 void e1000_config_collision_dist_generic(struct e1000_hw *hw)
1059 DEBUGFUNC("e1000_config_collision_dist_generic");
1061 tctl = E1000_READ_REG(hw, E1000_TCTL);
1063 tctl &= ~E1000_TCTL_COLD;
1064 tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT;
1066 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1067 E1000_WRITE_FLUSH(hw);
1071 * e1000_poll_fiber_serdes_link_generic - Poll for link up
1072 * @hw: pointer to the HW structure
1074 * Polls for link up by reading the status register, if link fails to come
1075 * up with auto-negotiation, then the link is forced if a signal is detected.
1077 s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw)
1079 struct e1000_mac_info *mac = &hw->mac;
1081 s32 ret_val = E1000_SUCCESS;
1083 DEBUGFUNC("e1000_poll_fiber_serdes_link_generic");
1086 * If we have a signal (the cable is plugged in, or assumed TRUE for
1087 * serdes media) then poll for a "Link-Up" indication in the Device
1088 * Status Register. Time-out if a link isn't seen in 500 milliseconds
1089 * seconds (Auto-negotiation should complete in less than 500
1090 * milliseconds even if the other end is doing it in SW).
1092 for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) {
1094 status = E1000_READ_REG(hw, E1000_STATUS);
1095 if (status & E1000_STATUS_LU)
1098 if (i == FIBER_LINK_UP_LIMIT) {
1099 DEBUGOUT("Never got a valid link from auto-neg!!!\n");
1100 mac->autoneg_failed = 1;
1102 * AutoNeg failed to achieve a link, so we'll call
1103 * mac->check_for_link. This routine will force the
1104 * link up if we detect a signal. This will allow us to
1105 * communicate with non-autonegotiating link partners.
1107 ret_val = mac->ops.check_for_link(hw);
1109 DEBUGOUT("Error while checking for link\n");
1112 mac->autoneg_failed = 0;
1114 mac->autoneg_failed = 0;
1115 DEBUGOUT("Valid Link Found\n");
1123 * e1000_commit_fc_settings_generic - Configure flow control
1124 * @hw: pointer to the HW structure
1126 * Write the flow control settings to the Transmit Config Word Register (TXCW)
1127 * base on the flow control settings in e1000_mac_info.
1129 s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw)
1131 struct e1000_mac_info *mac = &hw->mac;
1133 s32 ret_val = E1000_SUCCESS;
1135 DEBUGFUNC("e1000_commit_fc_settings_generic");
1138 * Check for a software override of the flow control settings, and
1139 * setup the device accordingly. If auto-negotiation is enabled, then
1140 * software will have to set the "PAUSE" bits to the correct value in
1141 * the Transmit Config Word Register (TXCW) and re-start auto-
1142 * negotiation. However, if auto-negotiation is disabled, then
1143 * software will have to manually configure the two flow control enable
1144 * bits in the CTRL register.
1146 * The possible values of the "fc" parameter are:
1147 * 0: Flow control is completely disabled
1148 * 1: Rx flow control is enabled (we can receive pause frames,
1149 * but not send pause frames).
1150 * 2: Tx flow control is enabled (we can send pause frames but we
1151 * do not support receiving pause frames).
1152 * 3: Both Rx and Tx flow control (symmetric) are enabled.
1154 switch (hw->fc.current_mode) {
1156 /* Flow control completely disabled by a software over-ride. */
1157 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
1159 case e1000_fc_rx_pause:
1161 * Rx Flow control is enabled and Tx Flow control is disabled
1162 * by a software over-ride. Since there really isn't a way to
1163 * advertise that we are capable of Rx Pause ONLY, we will
1164 * advertise that we support both symmetric and asymmetric Rx
1165 * PAUSE. Later, we will disable the adapter's ability to send
1168 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1170 case e1000_fc_tx_pause:
1172 * Tx Flow control is enabled, and Rx Flow control is disabled,
1173 * by a software over-ride.
1175 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
1179 * Flow control (both Rx and Tx) is enabled by a software
1182 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1185 DEBUGOUT("Flow control param set incorrectly\n");
1186 ret_val = -E1000_ERR_CONFIG;
1191 E1000_WRITE_REG(hw, E1000_TXCW, txcw);
1199 * e1000_set_fc_watermarks_generic - Set flow control high/low watermarks
1200 * @hw: pointer to the HW structure
1202 * Sets the flow control high/low threshold (watermark) registers. If
1203 * flow control XON frame transmission is enabled, then set XON frame
1204 * transmission as well.
1206 s32 e1000_set_fc_watermarks_generic(struct e1000_hw *hw)
1208 u32 fcrtl = 0, fcrth = 0;
1210 DEBUGFUNC("e1000_set_fc_watermarks_generic");
1213 * Set the flow control receive threshold registers. Normally,
1214 * these registers will be set to a default threshold that may be
1215 * adjusted later by the driver's runtime code. However, if the
1216 * ability to transmit pause frames is not enabled, then these
1217 * registers will be set to 0.
1219 if (hw->fc.current_mode & e1000_fc_tx_pause) {
1221 * We need to set up the Receive Threshold high and low water
1222 * marks as well as (optionally) enabling the transmission of
1225 fcrtl = hw->fc.low_water;
1226 if (hw->fc.send_xon)
1227 fcrtl |= E1000_FCRTL_XONE;
1229 fcrth = hw->fc.high_water;
1231 E1000_WRITE_REG(hw, E1000_FCRTL, fcrtl);
1232 E1000_WRITE_REG(hw, E1000_FCRTH, fcrth);
1234 return E1000_SUCCESS;
1238 * e1000_set_default_fc_generic - Set flow control default values
1239 * @hw: pointer to the HW structure
1241 * Read the EEPROM for the default values for flow control and store the
1244 s32 e1000_set_default_fc_generic(struct e1000_hw *hw)
1246 s32 ret_val = E1000_SUCCESS;
1249 DEBUGFUNC("e1000_set_default_fc_generic");
1252 * Read and store word 0x0F of the EEPROM. This word contains bits
1253 * that determine the hardware's default PAUSE (flow control) mode,
1254 * a bit that determines whether the HW defaults to enabling or
1255 * disabling auto-negotiation, and the direction of the
1256 * SW defined pins. If there is no SW over-ride of the flow
1257 * control setting, then the variable hw->fc will
1258 * be initialized based on a value in the EEPROM.
1260 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &nvm_data);
1263 DEBUGOUT("NVM Read Error\n");
1267 if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 0)
1268 hw->fc.requested_mode = e1000_fc_none;
1269 else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) ==
1271 hw->fc.requested_mode = e1000_fc_tx_pause;
1273 hw->fc.requested_mode = e1000_fc_full;
1280 * e1000_force_mac_fc_generic - Force the MAC's flow control settings
1281 * @hw: pointer to the HW structure
1283 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the
1284 * device control register to reflect the adapter settings. TFCE and RFCE
1285 * need to be explicitly set by software when a copper PHY is used because
1286 * autonegotiation is managed by the PHY rather than the MAC. Software must
1287 * also configure these bits when link is forced on a fiber connection.
1289 s32 e1000_force_mac_fc_generic(struct e1000_hw *hw)
1292 s32 ret_val = E1000_SUCCESS;
1294 DEBUGFUNC("e1000_force_mac_fc_generic");
1296 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1299 * Because we didn't get link via the internal auto-negotiation
1300 * mechanism (we either forced link or we got link via PHY
1301 * auto-neg), we have to manually enable/disable transmit an
1302 * receive flow control.
1304 * The "Case" statement below enables/disable flow control
1305 * according to the "hw->fc.current_mode" parameter.
1307 * The possible values of the "fc" parameter are:
1308 * 0: Flow control is completely disabled
1309 * 1: Rx flow control is enabled (we can receive pause
1310 * frames but not send pause frames).
1311 * 2: Tx flow control is enabled (we can send pause frames
1312 * frames but we do not receive pause frames).
1313 * 3: Both Rx and Tx flow control (symmetric) is enabled.
1314 * other: No other values should be possible at this point.
1316 DEBUGOUT1("hw->fc.current_mode = %u\n", hw->fc.current_mode);
1318 switch (hw->fc.current_mode) {
1320 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
1322 case e1000_fc_rx_pause:
1323 ctrl &= (~E1000_CTRL_TFCE);
1324 ctrl |= E1000_CTRL_RFCE;
1326 case e1000_fc_tx_pause:
1327 ctrl &= (~E1000_CTRL_RFCE);
1328 ctrl |= E1000_CTRL_TFCE;
1331 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
1334 DEBUGOUT("Flow control param set incorrectly\n");
1335 ret_val = -E1000_ERR_CONFIG;
1339 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1346 * e1000_config_fc_after_link_up_generic - Configures flow control after link
1347 * @hw: pointer to the HW structure
1349 * Checks the status of auto-negotiation after link up to ensure that the
1350 * speed and duplex were not forced. If the link needed to be forced, then
1351 * flow control needs to be forced also. If auto-negotiation is enabled
1352 * and did not fail, then we configure flow control based on our link
1355 s32 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw)
1357 struct e1000_mac_info *mac = &hw->mac;
1358 s32 ret_val = E1000_SUCCESS;
1359 u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg;
1362 DEBUGFUNC("e1000_config_fc_after_link_up_generic");
1365 * Check for the case where we have fiber media and auto-neg failed
1366 * so we had to force link. In this case, we need to force the
1367 * configuration of the MAC to match the "fc" parameter.
1369 if (mac->autoneg_failed) {
1370 if (hw->phy.media_type == e1000_media_type_fiber ||
1371 hw->phy.media_type == e1000_media_type_internal_serdes)
1372 ret_val = e1000_force_mac_fc_generic(hw);
1374 if (hw->phy.media_type == e1000_media_type_copper)
1375 ret_val = e1000_force_mac_fc_generic(hw);
1379 DEBUGOUT("Error forcing flow control settings\n");
1384 * Check for the case where we have copper media and auto-neg is
1385 * enabled. In this case, we need to check and see if Auto-Neg
1386 * has completed, and if so, how the PHY and link partner has
1387 * flow control configured.
1389 if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) {
1391 * Read the MII Status Register and check to see if AutoNeg
1392 * has completed. We read this twice because this reg has
1393 * some "sticky" (latched) bits.
1395 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);
1398 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);
1402 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) {
1403 DEBUGOUT("Copper PHY and Auto Neg "
1404 "has not completed.\n");
1409 * The AutoNeg process has completed, so we now need to
1410 * read both the Auto Negotiation Advertisement
1411 * Register (Address 4) and the Auto_Negotiation Base
1412 * Page Ability Register (Address 5) to determine how
1413 * flow control was negotiated.
1415 ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV,
1419 ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY,
1420 &mii_nway_lp_ability_reg);
1425 * Two bits in the Auto Negotiation Advertisement Register
1426 * (Address 4) and two bits in the Auto Negotiation Base
1427 * Page Ability Register (Address 5) determine flow control
1428 * for both the PHY and the link partner. The following
1429 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
1430 * 1999, describes these PAUSE resolution bits and how flow
1431 * control is determined based upon these settings.
1432 * NOTE: DC = Don't Care
1434 * LOCAL DEVICE | LINK PARTNER
1435 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
1436 *-------|---------|-------|---------|--------------------
1437 * 0 | 0 | DC | DC | e1000_fc_none
1438 * 0 | 1 | 0 | DC | e1000_fc_none
1439 * 0 | 1 | 1 | 0 | e1000_fc_none
1440 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1441 * 1 | 0 | 0 | DC | e1000_fc_none
1442 * 1 | DC | 1 | DC | e1000_fc_full
1443 * 1 | 1 | 0 | 0 | e1000_fc_none
1444 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1446 * Are both PAUSE bits set to 1? If so, this implies
1447 * Symmetric Flow Control is enabled at both ends. The
1448 * ASM_DIR bits are irrelevant per the spec.
1450 * For Symmetric Flow Control:
1452 * LOCAL DEVICE | LINK PARTNER
1453 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1454 *-------|---------|-------|---------|--------------------
1455 * 1 | DC | 1 | DC | E1000_fc_full
1458 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1459 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
1461 * Now we need to check if the user selected Rx ONLY
1462 * of pause frames. In this case, we had to advertise
1463 * FULL flow control because we could not advertise Rx
1464 * ONLY. Hence, we must now check to see if we need to
1465 * turn OFF the TRANSMISSION of PAUSE frames.
1467 if (hw->fc.requested_mode == e1000_fc_full) {
1468 hw->fc.current_mode = e1000_fc_full;
1469 DEBUGOUT("Flow Control = FULL.\r\n");
1471 hw->fc.current_mode = e1000_fc_rx_pause;
1472 DEBUGOUT("Flow Control = "
1473 "Rx PAUSE frames only.\r\n");
1477 * For receiving PAUSE frames ONLY.
1479 * LOCAL DEVICE | LINK PARTNER
1480 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1481 *-------|---------|-------|---------|--------------------
1482 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1484 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1485 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1486 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1487 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1488 hw->fc.current_mode = e1000_fc_tx_pause;
1489 DEBUGOUT("Flow Control = Tx PAUSE frames only.\r\n");
1492 * For transmitting PAUSE frames ONLY.
1494 * LOCAL DEVICE | LINK PARTNER
1495 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1496 *-------|---------|-------|---------|--------------------
1497 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1499 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1500 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1501 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1502 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1503 hw->fc.current_mode = e1000_fc_rx_pause;
1504 DEBUGOUT("Flow Control = Rx PAUSE frames only.\r\n");
1507 * Per the IEEE spec, at this point flow control
1508 * should be disabled.
1510 hw->fc.current_mode = e1000_fc_none;
1511 DEBUGOUT("Flow Control = NONE.\r\n");
1515 * Now we need to do one last check... If we auto-
1516 * negotiated to HALF DUPLEX, flow control should not be
1517 * enabled per IEEE 802.3 spec.
1519 ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex);
1521 DEBUGOUT("Error getting link speed and duplex\n");
1525 if (duplex == HALF_DUPLEX)
1526 hw->fc.current_mode = e1000_fc_none;
1529 * Now we call a subroutine to actually force the MAC
1530 * controller to use the correct flow control settings.
1532 ret_val = e1000_force_mac_fc_generic(hw);
1534 DEBUGOUT("Error forcing flow control settings\n");
1544 * e1000_get_speed_and_duplex_copper_generic - Retrieve current speed/duplex
1545 * @hw: pointer to the HW structure
1546 * @speed: stores the current speed
1547 * @duplex: stores the current duplex
1549 * Read the status register for the current speed/duplex and store the current
1550 * speed and duplex for copper connections.
1552 s32 e1000_get_speed_and_duplex_copper_generic(struct e1000_hw *hw, u16 *speed,
1557 DEBUGFUNC("e1000_get_speed_and_duplex_copper_generic");
1559 status = E1000_READ_REG(hw, E1000_STATUS);
1560 if (status & E1000_STATUS_SPEED_1000) {
1561 *speed = SPEED_1000;
1562 DEBUGOUT("1000 Mbs, ");
1563 } else if (status & E1000_STATUS_SPEED_100) {
1565 DEBUGOUT("100 Mbs, ");
1568 DEBUGOUT("10 Mbs, ");
1571 if (status & E1000_STATUS_FD) {
1572 *duplex = FULL_DUPLEX;
1573 DEBUGOUT("Full Duplex\n");
1575 *duplex = HALF_DUPLEX;
1576 DEBUGOUT("Half Duplex\n");
1579 return E1000_SUCCESS;
1583 * e1000_get_speed_and_duplex_fiber_generic - Retrieve current speed/duplex
1584 * @hw: pointer to the HW structure
1585 * @speed: stores the current speed
1586 * @duplex: stores the current duplex
1588 * Sets the speed and duplex to gigabit full duplex (the only possible option)
1589 * for fiber/serdes links.
1591 s32 e1000_get_speed_and_duplex_fiber_serdes_generic(struct e1000_hw *hw,
1592 u16 *speed, u16 *duplex)
1594 DEBUGFUNC("e1000_get_speed_and_duplex_fiber_serdes_generic");
1596 *speed = SPEED_1000;
1597 *duplex = FULL_DUPLEX;
1599 return E1000_SUCCESS;
1603 * e1000_get_hw_semaphore_generic - Acquire hardware semaphore
1604 * @hw: pointer to the HW structure
1606 * Acquire the HW semaphore to access the PHY or NVM
1608 s32 e1000_get_hw_semaphore_generic(struct e1000_hw *hw)
1611 s32 ret_val = E1000_SUCCESS;
1612 s32 timeout = hw->nvm.word_size + 1;
1615 DEBUGFUNC("e1000_get_hw_semaphore_generic");
1617 /* Get the SW semaphore */
1618 while (i < timeout) {
1619 swsm = E1000_READ_REG(hw, E1000_SWSM);
1620 if (!(swsm & E1000_SWSM_SMBI))
1628 DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
1629 ret_val = -E1000_ERR_NVM;
1633 /* Get the FW semaphore. */
1634 for (i = 0; i < timeout; i++) {
1635 swsm = E1000_READ_REG(hw, E1000_SWSM);
1636 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI);
1638 /* Semaphore acquired if bit latched */
1639 if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI)
1646 /* Release semaphores */
1647 e1000_put_hw_semaphore_generic(hw);
1648 DEBUGOUT("Driver can't access the NVM\n");
1649 ret_val = -E1000_ERR_NVM;
1658 * e1000_put_hw_semaphore_generic - Release hardware semaphore
1659 * @hw: pointer to the HW structure
1661 * Release hardware semaphore used to access the PHY or NVM
1663 void e1000_put_hw_semaphore_generic(struct e1000_hw *hw)
1667 DEBUGFUNC("e1000_put_hw_semaphore_generic");
1669 swsm = E1000_READ_REG(hw, E1000_SWSM);
1671 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
1673 E1000_WRITE_REG(hw, E1000_SWSM, swsm);
1677 * e1000_get_auto_rd_done_generic - Check for auto read completion
1678 * @hw: pointer to the HW structure
1680 * Check EEPROM for Auto Read done bit.
1682 s32 e1000_get_auto_rd_done_generic(struct e1000_hw *hw)
1685 s32 ret_val = E1000_SUCCESS;
1687 DEBUGFUNC("e1000_get_auto_rd_done_generic");
1689 while (i < AUTO_READ_DONE_TIMEOUT) {
1690 if (E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_AUTO_RD)
1696 if (i == AUTO_READ_DONE_TIMEOUT) {
1697 DEBUGOUT("Auto read by HW from NVM has not completed.\n");
1698 ret_val = -E1000_ERR_RESET;
1707 * e1000_valid_led_default_generic - Verify a valid default LED config
1708 * @hw: pointer to the HW structure
1709 * @data: pointer to the NVM (EEPROM)
1711 * Read the EEPROM for the current default LED configuration. If the
1712 * LED configuration is not valid, set to a valid LED configuration.
1714 s32 e1000_valid_led_default_generic(struct e1000_hw *hw, u16 *data)
1718 DEBUGFUNC("e1000_valid_led_default_generic");
1720 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1722 DEBUGOUT("NVM Read Error\n");
1726 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
1727 *data = ID_LED_DEFAULT;
1734 * e1000_id_led_init_generic -
1735 * @hw: pointer to the HW structure
1738 s32 e1000_id_led_init_generic(struct e1000_hw *hw)
1740 struct e1000_mac_info *mac = &hw->mac;
1742 const u32 ledctl_mask = 0x000000FF;
1743 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON;
1744 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
1746 const u16 led_mask = 0x0F;
1748 DEBUGFUNC("e1000_id_led_init_generic");
1750 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
1754 mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL);
1755 mac->ledctl_mode1 = mac->ledctl_default;
1756 mac->ledctl_mode2 = mac->ledctl_default;
1758 for (i = 0; i < 4; i++) {
1759 temp = (data >> (i << 2)) & led_mask;
1761 case ID_LED_ON1_DEF2:
1762 case ID_LED_ON1_ON2:
1763 case ID_LED_ON1_OFF2:
1764 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
1765 mac->ledctl_mode1 |= ledctl_on << (i << 3);
1767 case ID_LED_OFF1_DEF2:
1768 case ID_LED_OFF1_ON2:
1769 case ID_LED_OFF1_OFF2:
1770 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
1771 mac->ledctl_mode1 |= ledctl_off << (i << 3);
1778 case ID_LED_DEF1_ON2:
1779 case ID_LED_ON1_ON2:
1780 case ID_LED_OFF1_ON2:
1781 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
1782 mac->ledctl_mode2 |= ledctl_on << (i << 3);
1784 case ID_LED_DEF1_OFF2:
1785 case ID_LED_ON1_OFF2:
1786 case ID_LED_OFF1_OFF2:
1787 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
1788 mac->ledctl_mode2 |= ledctl_off << (i << 3);
1801 * e1000_setup_led_generic - Configures SW controllable LED
1802 * @hw: pointer to the HW structure
1804 * This prepares the SW controllable LED for use and saves the current state
1805 * of the LED so it can be later restored.
1807 s32 e1000_setup_led_generic(struct e1000_hw *hw)
1810 s32 ret_val = E1000_SUCCESS;
1812 DEBUGFUNC("e1000_setup_led_generic");
1814 if (hw->mac.ops.setup_led != e1000_setup_led_generic) {
1815 ret_val = -E1000_ERR_CONFIG;
1819 if (hw->phy.media_type == e1000_media_type_fiber) {
1820 ledctl = E1000_READ_REG(hw, E1000_LEDCTL);
1821 hw->mac.ledctl_default = ledctl;
1823 ledctl &= ~(E1000_LEDCTL_LED0_IVRT |
1824 E1000_LEDCTL_LED0_BLINK |
1825 E1000_LEDCTL_LED0_MODE_MASK);
1826 ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
1827 E1000_LEDCTL_LED0_MODE_SHIFT);
1828 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl);
1829 } else if (hw->phy.media_type == e1000_media_type_copper) {
1830 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
1838 * e1000_cleanup_led_generic - Set LED config to default operation
1839 * @hw: pointer to the HW structure
1841 * Remove the current LED configuration and set the LED configuration
1842 * to the default value, saved from the EEPROM.
1844 s32 e1000_cleanup_led_generic(struct e1000_hw *hw)
1846 DEBUGFUNC("e1000_cleanup_led_generic");
1848 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default);
1849 return E1000_SUCCESS;
1853 * e1000_blink_led_generic - Blink LED
1854 * @hw: pointer to the HW structure
1856 * Blink the LEDs which are set to be on.
1858 s32 e1000_blink_led_generic(struct e1000_hw *hw)
1860 u32 ledctl_blink = 0;
1863 DEBUGFUNC("e1000_blink_led_generic");
1865 if (hw->phy.media_type == e1000_media_type_fiber) {
1866 /* always blink LED0 for PCI-E fiber */
1867 ledctl_blink = E1000_LEDCTL_LED0_BLINK |
1868 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT);
1871 * set the blink bit for each LED that's "on" (0x0E)
1874 ledctl_blink = hw->mac.ledctl_mode2;
1875 for (i = 0; i < 4; i++)
1876 if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
1877 E1000_LEDCTL_MODE_LED_ON)
1878 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK <<
1882 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl_blink);
1884 return E1000_SUCCESS;
1888 * e1000_led_on_generic - Turn LED on
1889 * @hw: pointer to the HW structure
1893 s32 e1000_led_on_generic(struct e1000_hw *hw)
1897 DEBUGFUNC("e1000_led_on_generic");
1899 switch (hw->phy.media_type) {
1900 case e1000_media_type_fiber:
1901 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1902 ctrl &= ~E1000_CTRL_SWDPIN0;
1903 ctrl |= E1000_CTRL_SWDPIO0;
1904 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1906 case e1000_media_type_copper:
1907 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2);
1913 return E1000_SUCCESS;
1917 * e1000_led_off_generic - Turn LED off
1918 * @hw: pointer to the HW structure
1922 s32 e1000_led_off_generic(struct e1000_hw *hw)
1926 DEBUGFUNC("e1000_led_off_generic");
1928 switch (hw->phy.media_type) {
1929 case e1000_media_type_fiber:
1930 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1931 ctrl |= E1000_CTRL_SWDPIN0;
1932 ctrl |= E1000_CTRL_SWDPIO0;
1933 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1935 case e1000_media_type_copper:
1936 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
1942 return E1000_SUCCESS;
1946 * e1000_set_pcie_no_snoop_generic - Set PCI-express capabilities
1947 * @hw: pointer to the HW structure
1948 * @no_snoop: bitmap of snoop events
1950 * Set the PCI-express register to snoop for events enabled in 'no_snoop'.
1952 void e1000_set_pcie_no_snoop_generic(struct e1000_hw *hw, u32 no_snoop)
1956 DEBUGFUNC("e1000_set_pcie_no_snoop_generic");
1958 if (hw->bus.type != e1000_bus_type_pci_express)
1962 gcr = E1000_READ_REG(hw, E1000_GCR);
1963 gcr &= ~(PCIE_NO_SNOOP_ALL);
1965 E1000_WRITE_REG(hw, E1000_GCR, gcr);
1972 * e1000_disable_pcie_master_generic - Disables PCI-express master access
1973 * @hw: pointer to the HW structure
1975 * Returns E1000_SUCCESS if successful, else returns -10
1976 * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused
1977 * the master requests to be disabled.
1979 * Disables PCI-Express master access and verifies there are no pending
1982 s32 e1000_disable_pcie_master_generic(struct e1000_hw *hw)
1985 s32 timeout = MASTER_DISABLE_TIMEOUT;
1986 s32 ret_val = E1000_SUCCESS;
1988 DEBUGFUNC("e1000_disable_pcie_master_generic");
1990 if (hw->bus.type != e1000_bus_type_pci_express)
1993 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1994 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE;
1995 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1998 if (!(E1000_READ_REG(hw, E1000_STATUS) &
1999 E1000_STATUS_GIO_MASTER_ENABLE))
2006 DEBUGOUT("Master requests are pending.\n");
2007 ret_val = -E1000_ERR_MASTER_REQUESTS_PENDING;
2015 * e1000_reset_adaptive_generic - Reset Adaptive Interframe Spacing
2016 * @hw: pointer to the HW structure
2018 * Reset the Adaptive Interframe Spacing throttle to default values.
2020 void e1000_reset_adaptive_generic(struct e1000_hw *hw)
2022 struct e1000_mac_info *mac = &hw->mac;
2024 DEBUGFUNC("e1000_reset_adaptive_generic");
2026 if (!mac->adaptive_ifs) {
2027 DEBUGOUT("Not in Adaptive IFS mode!\n");
2031 mac->current_ifs_val = 0;
2032 mac->ifs_min_val = IFS_MIN;
2033 mac->ifs_max_val = IFS_MAX;
2034 mac->ifs_step_size = IFS_STEP;
2035 mac->ifs_ratio = IFS_RATIO;
2037 mac->in_ifs_mode = FALSE;
2038 E1000_WRITE_REG(hw, E1000_AIT, 0);
2044 * e1000_update_adaptive_generic - Update Adaptive Interframe Spacing
2045 * @hw: pointer to the HW structure
2047 * Update the Adaptive Interframe Spacing Throttle value based on the
2048 * time between transmitted packets and time between collisions.
2050 void e1000_update_adaptive_generic(struct e1000_hw *hw)
2052 struct e1000_mac_info *mac = &hw->mac;
2054 DEBUGFUNC("e1000_update_adaptive_generic");
2056 if (!mac->adaptive_ifs) {
2057 DEBUGOUT("Not in Adaptive IFS mode!\n");
2061 if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) {
2062 if (mac->tx_packet_delta > MIN_NUM_XMITS) {
2063 mac->in_ifs_mode = TRUE;
2064 if (mac->current_ifs_val < mac->ifs_max_val) {
2065 if (!mac->current_ifs_val)
2066 mac->current_ifs_val = mac->ifs_min_val;
2068 mac->current_ifs_val +=
2070 E1000_WRITE_REG(hw, E1000_AIT, mac->current_ifs_val);
2074 if (mac->in_ifs_mode &&
2075 (mac->tx_packet_delta <= MIN_NUM_XMITS)) {
2076 mac->current_ifs_val = 0;
2077 mac->in_ifs_mode = FALSE;
2078 E1000_WRITE_REG(hw, E1000_AIT, 0);
2086 * e1000_validate_mdi_setting_generic - Verify MDI/MDIx settings
2087 * @hw: pointer to the HW structure
2089 * Verify that when not using auto-negotiation that MDI/MDIx is correctly
2090 * set, which is forced to MDI mode only.
2092 static s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw)
2094 s32 ret_val = E1000_SUCCESS;
2096 DEBUGFUNC("e1000_validate_mdi_setting_generic");
2098 if (!hw->mac.autoneg && (hw->phy.mdix == 0 || hw->phy.mdix == 3)) {
2099 DEBUGOUT("Invalid MDI setting detected\n");
2101 ret_val = -E1000_ERR_CONFIG;
2110 * e1000_write_8bit_ctrl_reg_generic - Write a 8bit CTRL register
2111 * @hw: pointer to the HW structure
2112 * @reg: 32bit register offset such as E1000_SCTL
2113 * @offset: register offset to write to
2114 * @data: data to write at register offset
2116 * Writes an address/data control type register. There are several of these
2117 * and they all have the format address << 8 | data and bit 31 is polled for
2120 s32 e1000_write_8bit_ctrl_reg_generic(struct e1000_hw *hw, u32 reg,
2121 u32 offset, u8 data)
2123 u32 i, regvalue = 0;
2124 s32 ret_val = E1000_SUCCESS;
2126 DEBUGFUNC("e1000_write_8bit_ctrl_reg_generic");
2128 /* Set up the address and data */
2129 regvalue = ((u32)data) | (offset << E1000_GEN_CTL_ADDRESS_SHIFT);
2130 E1000_WRITE_REG(hw, reg, regvalue);
2132 /* Poll the ready bit to see if the MDI read completed */
2133 for (i = 0; i < E1000_GEN_POLL_TIMEOUT; i++) {
2135 regvalue = E1000_READ_REG(hw, reg);
2136 if (regvalue & E1000_GEN_CTL_READY)
2139 if (!(regvalue & E1000_GEN_CTL_READY)) {
2140 DEBUGOUT1("Reg %08x did not indicate ready\n", reg);
2141 ret_val = -E1000_ERR_PHY;