sys/dev/netif/igb/if_igb.c

   1 /*
   2  * Copyright (c) 2001-2011, Intel Corporation
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *
   8  *  1. Redistributions of source code must retain the above copyright notice,
   9  *     this list of conditions and the following disclaimer.
  10  *
  11  *  2. Redistributions in binary form must reproduce the above copyright
  12  *     notice, this list of conditions and the following disclaimer in the
  13  *     documentation and/or other materials provided with the distribution.
  14  *
  15  *  3. Neither the name of the Intel Corporation nor the names of its
  16  *     contributors may be used to endorse or promote products derived from
  17  *     this software without specific prior written permission.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  20  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  22  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  23  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  29  * POSSIBILITY OF SUCH DAMAGE.
  30  */
  31
  32 #include "opt_ifpoll.h"
  33 #include "opt_igb.h"
  34
  35 #include <sys/param.h>
  36 #include <sys/bus.h>
  37 #include <sys/endian.h>
  38 #include <sys/interrupt.h>
  39 #include <sys/kernel.h>
  40 #include <sys/malloc.h>
  41 #include <sys/mbuf.h>
  42 #include <sys/proc.h>
  43 #include <sys/rman.h>
  44 #include <sys/serialize.h>
  45 #include <sys/serialize2.h>
  46 #include <sys/socket.h>
  47 #include <sys/sockio.h>
  48 #include <sys/sysctl.h>
  49 #include <sys/systm.h>
  50
  51 #include <net/bpf.h>
  52 #include <net/ethernet.h>
  53 #include <net/if.h>
  54 #include <net/if_arp.h>
  55 #include <net/if_dl.h>
  56 #include <net/if_media.h>
  57 #include <net/ifq_var.h>
  58 #include <net/toeplitz.h>
  59 #include <net/toeplitz2.h>
  60 #include <net/vlan/if_vlan_var.h>
  61 #include <net/vlan/if_vlan_ether.h>
  62 #include <net/if_poll.h>
  63
  64 #include <netinet/in_systm.h>
  65 #include <netinet/in.h>
  66 #include <netinet/ip.h>
  67 #include <netinet/tcp.h>
  68 #include <netinet/udp.h>
  69
  70 #include <bus/pci/pcivar.h>
  71 #include <bus/pci/pcireg.h>
  72
  73 #include <dev/netif/ig_hal/e1000_api.h>
  74 #include <dev/netif/ig_hal/e1000_82575.h>
  75 #include <dev/netif/igb/if_igb.h>
  76
  77 #ifdef IGB_RSS_DEBUG
  78 #define IGB_RSS_DPRINTF(sc, lvl, fmt, ...) \
  79 do { \
  80         if (sc->rss_debug >= lvl) \
  81                 if_printf(&sc->arpcom.ac_if, fmt, __VA_ARGS__); \
  82 } while (0)
  83 #else   /* !IGB_RSS_DEBUG */
  84 #define IGB_RSS_DPRINTF(sc, lvl, fmt, ...)      ((void)0)
  85 #endif  /* IGB_RSS_DEBUG */
  86
  87 #define IGB_NAME        "Intel(R) PRO/1000 "
  88 #define IGB_DEVICE(id)  \
  89         { IGB_VENDOR_ID, E1000_DEV_ID_##id, IGB_NAME #id }
  90 #define IGB_DEVICE_NULL { 0, 0, NULL }
  91
  92 static struct igb_device {
  93         uint16_t        vid;
  94         uint16_t        did;
  95         const char      *desc;
  96 } igb_devices[] = {
  97         IGB_DEVICE(82575EB_COPPER),
  98         IGB_DEVICE(82575EB_FIBER_SERDES),
  99         IGB_DEVICE(82575GB_QUAD_COPPER),
 100         IGB_DEVICE(82576),
 101         IGB_DEVICE(82576_NS),
 102         IGB_DEVICE(82576_NS_SERDES),
 103         IGB_DEVICE(82576_FIBER),
 104         IGB_DEVICE(82576_SERDES),
 105         IGB_DEVICE(82576_SERDES_QUAD),
 106         IGB_DEVICE(82576_QUAD_COPPER),
 107         IGB_DEVICE(82576_QUAD_COPPER_ET2),
 108         IGB_DEVICE(82576_VF),
 109         IGB_DEVICE(82580_COPPER),
 110         IGB_DEVICE(82580_FIBER),
 111         IGB_DEVICE(82580_SERDES),
 112         IGB_DEVICE(82580_SGMII),
 113         IGB_DEVICE(82580_COPPER_DUAL),
 114         IGB_DEVICE(82580_QUAD_FIBER),
 115         IGB_DEVICE(DH89XXCC_SERDES),
 116         IGB_DEVICE(DH89XXCC_SGMII),
 117         IGB_DEVICE(DH89XXCC_SFP),
 118         IGB_DEVICE(DH89XXCC_BACKPLANE),
 119         IGB_DEVICE(I350_COPPER),
 120         IGB_DEVICE(I350_FIBER),
 121         IGB_DEVICE(I350_SERDES),
 122         IGB_DEVICE(I350_SGMII),
 123         IGB_DEVICE(I350_VF),
 124         IGB_DEVICE(I210_COPPER),
 125         IGB_DEVICE(I210_COPPER_IT),
 126         IGB_DEVICE(I210_COPPER_OEM1),
 127         IGB_DEVICE(I210_FIBER),
 128         IGB_DEVICE(I210_SERDES),
 129         IGB_DEVICE(I210_SGMII),
 130         IGB_DEVICE(I211_COPPER),
 131
 132         /* required last entry */
 133         IGB_DEVICE_NULL
 134 };
 135
 136 static int      igb_probe(device_t);
 137 static int      igb_attach(device_t);
 138 static int      igb_detach(device_t);
 139 static int      igb_shutdown(device_t);
 140 static int      igb_suspend(device_t);
 141 static int      igb_resume(device_t);
 142
 143 static boolean_t igb_is_valid_ether_addr(const uint8_t *);
 144 static void     igb_setup_ifp(struct igb_softc *);
 145 static boolean_t igb_txcsum_ctx(struct igb_tx_ring *, struct mbuf *);
 146 static int      igb_tso_pullup(struct igb_tx_ring *, struct mbuf **);
 147 static void     igb_tso_ctx(struct igb_tx_ring *, struct mbuf *, uint32_t *);
 148 static void     igb_add_sysctl(struct igb_softc *);
 149 static int      igb_sysctl_intr_rate(SYSCTL_HANDLER_ARGS);
 150 static int      igb_sysctl_msix_rate(SYSCTL_HANDLER_ARGS);
 151 static int      igb_sysctl_tx_intr_nsegs(SYSCTL_HANDLER_ARGS);
 152 static int      igb_sysctl_tx_wreg_nsegs(SYSCTL_HANDLER_ARGS);
 153 static int      igb_sysctl_rx_wreg_nsegs(SYSCTL_HANDLER_ARGS);
 154 static void     igb_set_ring_inuse(struct igb_softc *, boolean_t);
 155 static int      igb_get_rxring_inuse(const struct igb_softc *, boolean_t);
 156 static int      igb_get_txring_inuse(const struct igb_softc *, boolean_t);
 157 static void     igb_set_timer_cpuid(struct igb_softc *, boolean_t);
 158 #ifdef IFPOLL_ENABLE
 159 static int      igb_sysctl_npoll_rxoff(SYSCTL_HANDLER_ARGS);
 160 static int      igb_sysctl_npoll_txoff(SYSCTL_HANDLER_ARGS);
 161 #endif
 162
 163 static void     igb_vf_init_stats(struct igb_softc *);
 164 static void     igb_reset(struct igb_softc *);
 165 static void     igb_update_stats_counters(struct igb_softc *);
 166 static void     igb_update_vf_stats_counters(struct igb_softc *);
 167 static void     igb_update_link_status(struct igb_softc *);
 168 static void     igb_init_tx_unit(struct igb_softc *);
 169 static void     igb_init_rx_unit(struct igb_softc *);
 170
 171 static void     igb_set_vlan(struct igb_softc *);
 172 static void     igb_set_multi(struct igb_softc *);
 173 static void     igb_set_promisc(struct igb_softc *);
 174 static void     igb_disable_promisc(struct igb_softc *);
 175
 176 static int      igb_alloc_rings(struct igb_softc *);
 177 static void     igb_free_rings(struct igb_softc *);
 178 static int      igb_create_tx_ring(struct igb_tx_ring *);
 179 static int      igb_create_rx_ring(struct igb_rx_ring *);
 180 static void     igb_free_tx_ring(struct igb_tx_ring *);
 181 static void     igb_free_rx_ring(struct igb_rx_ring *);
 182 static void     igb_destroy_tx_ring(struct igb_tx_ring *, int);
 183 static void     igb_destroy_rx_ring(struct igb_rx_ring *, int);
 184 static void     igb_init_tx_ring(struct igb_tx_ring *);
 185 static int      igb_init_rx_ring(struct igb_rx_ring *);
 186 static int      igb_newbuf(struct igb_rx_ring *, int, boolean_t);
 187 static int      igb_encap(struct igb_tx_ring *, struct mbuf **, int *, int *);
 188 static void     igb_rx_refresh(struct igb_rx_ring *, int);
 189 static void     igb_setup_serializer(struct igb_softc *);
 190
 191 static void     igb_stop(struct igb_softc *);
 192 static void     igb_init(void *);
 193 static int      igb_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
 194 static void     igb_media_status(struct ifnet *, struct ifmediareq *);
 195 static int      igb_media_change(struct ifnet *);
 196 static void     igb_timer(void *);
 197 static void     igb_watchdog(struct ifaltq_subque *);
 198 static void     igb_start(struct ifnet *, struct ifaltq_subque *);
 199 #ifdef IFPOLL_ENABLE
 200 static void     igb_npoll(struct ifnet *, struct ifpoll_info *);
 201 static void     igb_npoll_rx(struct ifnet *, void *, int);
 202 static void     igb_npoll_tx(struct ifnet *, void *, int);
 203 static void     igb_npoll_status(struct ifnet *);
 204 #endif
 205 static void     igb_serialize(struct ifnet *, enum ifnet_serialize);
 206 static void     igb_deserialize(struct ifnet *, enum ifnet_serialize);
 207 static int      igb_tryserialize(struct ifnet *, enum ifnet_serialize);
 208 #ifdef INVARIANTS
 209 static void     igb_serialize_assert(struct ifnet *, enum ifnet_serialize,
 210                     boolean_t);
 211 #endif
 212
 213 static void     igb_intr(void *);
 214 static void     igb_intr_shared(void *);
 215 static void     igb_rxeof(struct igb_rx_ring *, int);
 216 static void     igb_txeof(struct igb_tx_ring *);
 217 static void     igb_set_eitr(struct igb_softc *, int, int);
 218 static void     igb_enable_intr(struct igb_softc *);
 219 static void     igb_disable_intr(struct igb_softc *);
 220 static void     igb_init_unshared_intr(struct igb_softc *);
 221 static void     igb_init_intr(struct igb_softc *);
 222 static int      igb_setup_intr(struct igb_softc *);
 223 static void     igb_set_txintr_mask(struct igb_tx_ring *, int *, int);
 224 static void     igb_set_rxintr_mask(struct igb_rx_ring *, int *, int);
 225 static void     igb_set_intr_mask(struct igb_softc *);
 226 static int      igb_alloc_intr(struct igb_softc *);
 227 static void     igb_free_intr(struct igb_softc *);
 228 static void     igb_teardown_intr(struct igb_softc *);
 229 static void     igb_msix_try_alloc(struct igb_softc *);
 230 static void     igb_msix_rx_conf(struct igb_softc *, int, int *, int);
 231 static void     igb_msix_tx_conf(struct igb_softc *, int, int *, int);
 232 static void     igb_msix_free(struct igb_softc *, boolean_t);
 233 static int      igb_msix_setup(struct igb_softc *);
 234 static void     igb_msix_teardown(struct igb_softc *, int);
 235 static void     igb_msix_rx(void *);
 236 static void     igb_msix_tx(void *);
 237 static void     igb_msix_status(void *);
 238 static void     igb_msix_rxtx(void *);
 239
 240 /* Management and WOL Support */
 241 static void     igb_get_mgmt(struct igb_softc *);
 242 static void     igb_rel_mgmt(struct igb_softc *);
 243 static void     igb_get_hw_control(struct igb_softc *);
 244 static void     igb_rel_hw_control(struct igb_softc *);
 245 static void     igb_enable_wol(device_t);
 246
 247 static device_method_t igb_methods[] = {
 248         /* Device interface */
 249         DEVMETHOD(device_probe,         igb_probe),
 250         DEVMETHOD(device_attach,        igb_attach),
 251         DEVMETHOD(device_detach,        igb_detach),
 252         DEVMETHOD(device_shutdown,      igb_shutdown),
 253         DEVMETHOD(device_suspend,       igb_suspend),
 254         DEVMETHOD(device_resume,        igb_resume),
 255         DEVMETHOD_END
 256 };
 257
 258 static driver_t igb_driver = {
 259         "igb",
 260         igb_methods,
 261         sizeof(struct igb_softc),
 262 };
 263
 264 static devclass_t igb_devclass;
 265
 266 DECLARE_DUMMY_MODULE(if_igb);
 267 MODULE_DEPEND(igb, ig_hal, 1, 1, 1);
 268 DRIVER_MODULE(if_igb, pci, igb_driver, igb_devclass, NULL, NULL);
 269
 270 static int      igb_rxd = IGB_DEFAULT_RXD;
 271 static int      igb_txd = IGB_DEFAULT_TXD;
 272 static int      igb_rxr = 0;
 273 static int      igb_txr = 0;
 274 static int      igb_msi_enable = 1;
 275 static int      igb_msix_enable = 1;
 276 static int      igb_eee_disabled = 1;   /* Energy Efficient Ethernet */
 277 static int      igb_fc_setting = e1000_fc_full;
 278
 279 /*
 280  * DMA Coalescing, only for i350 - default to off,
 281  * this feature is for power savings
 282  */
 283 static int      igb_dma_coalesce = 0;
 284
 285 TUNABLE_INT("hw.igb.rxd", &igb_rxd);
 286 TUNABLE_INT("hw.igb.txd", &igb_txd);
 287 TUNABLE_INT("hw.igb.rxr", &igb_rxr);
 288 TUNABLE_INT("hw.igb.txr", &igb_txr);
 289 TUNABLE_INT("hw.igb.msi.enable", &igb_msi_enable);
 290 TUNABLE_INT("hw.igb.msix.enable", &igb_msix_enable);
 291 TUNABLE_INT("hw.igb.fc_setting", &igb_fc_setting);
 292
 293 /* i350 specific */
 294 TUNABLE_INT("hw.igb.eee_disabled", &igb_eee_disabled);
 295 TUNABLE_INT("hw.igb.dma_coalesce", &igb_dma_coalesce);
 296
 297 static __inline void
 298 igb_rxcsum(uint32_t staterr, struct mbuf *mp)
 299 {
 300         /* Ignore Checksum bit is set */
 301         if (staterr & E1000_RXD_STAT_IXSM)
 302                 return;
 303
 304         if ((staterr & (E1000_RXD_STAT_IPCS | E1000_RXDEXT_STATERR_IPE)) ==
 305             E1000_RXD_STAT_IPCS)
 306                 mp->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | CSUM_IP_VALID;
 307
 308         if (staterr & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)) {
 309                 if ((staterr & E1000_RXDEXT_STATERR_TCPE) == 0) {
 310                         mp->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
 311                             CSUM_PSEUDO_HDR | CSUM_FRAG_NOT_CHECKED;
 312                         mp->m_pkthdr.csum_data = htons(0xffff);
 313                 }
 314         }
 315 }
 316
 317 static __inline struct pktinfo *
 318 igb_rssinfo(struct mbuf *m, struct pktinfo *pi,
 319     uint32_t hash, uint32_t hashtype, uint32_t staterr)
 320 {
 321         switch (hashtype) {
 322         case E1000_RXDADV_RSSTYPE_IPV4_TCP:
 323                 pi->pi_netisr = NETISR_IP;
 324                 pi->pi_flags = 0;
 325                 pi->pi_l3proto = IPPROTO_TCP;
 326                 break;
 327
 328         case E1000_RXDADV_RSSTYPE_IPV4:
 329                 if (staterr & E1000_RXD_STAT_IXSM)
 330                         return NULL;
 331
 332                 if ((staterr &
 333                      (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) ==
 334                     E1000_RXD_STAT_TCPCS) {
 335                         pi->pi_netisr = NETISR_IP;
 336                         pi->pi_flags = 0;
 337                         pi->pi_l3proto = IPPROTO_UDP;
 338                         break;
 339                 }
 340                 /* FALL THROUGH */
 341         default:
 342                 return NULL;
 343         }
 344
 345         m->m_flags |= M_HASH;
 346         m->m_pkthdr.hash = toeplitz_hash(hash);
 347         return pi;
 348 }
 349
 350 static int
 351 igb_probe(device_t dev)
 352 {
 353         const struct igb_device *d;
 354         uint16_t vid, did;
 355
 356         vid = pci_get_vendor(dev);
 357         did = pci_get_device(dev);
 358
 359         for (d = igb_devices; d->desc != NULL; ++d) {
 360                 if (vid == d->vid && did == d->did) {
 361                         device_set_desc(dev, d->desc);
 362                         return 0;
 363                 }
 364         }
 365         return ENXIO;
 366 }
 367
 368 static int
 369 igb_attach(device_t dev)
 370 {
 371         struct igb_softc *sc = device_get_softc(dev);
 372         uint16_t eeprom_data;
 373         int error = 0, ring_max;
 374 #ifdef IFPOLL_ENABLE
 375         int offset, offset_def;
 376 #endif
 377
 378 #ifdef notyet
 379         /* SYSCTL stuff */
 380         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 381             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 382             OID_AUTO, "nvm", CTLTYPE_INT|CTLFLAG_RW, adapter, 0,
 383             igb_sysctl_nvm_info, "I", "NVM Information");
 384         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 385             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 386             OID_AUTO, "flow_control", CTLTYPE_INT|CTLFLAG_RW,
 387             adapter, 0, igb_set_flowcntl, "I", "Flow Control");
 388 #endif
 389
 390         callout_init_mp(&sc->timer);
 391         lwkt_serialize_init(&sc->main_serialize);
 392
 393         if_initname(&sc->arpcom.ac_if, device_get_name(dev),
 394             device_get_unit(dev));
 395         sc->dev = sc->osdep.dev = dev;
 396
 397         /*
 398          * Determine hardware and mac type
 399          */
 400         sc->hw.vendor_id = pci_get_vendor(dev);
 401         sc->hw.device_id = pci_get_device(dev);
 402         sc->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1);
 403         sc->hw.subsystem_vendor_id = pci_read_config(dev, PCIR_SUBVEND_0, 2);
 404         sc->hw.subsystem_device_id = pci_read_config(dev, PCIR_SUBDEV_0, 2);
 405
 406         if (e1000_set_mac_type(&sc->hw))
 407                 return ENXIO;
 408
 409         /* Are we a VF device? */
 410         if (sc->hw.mac.type == e1000_vfadapt ||
 411             sc->hw.mac.type == e1000_vfadapt_i350)
 412                 sc->vf_ifp = 1;
 413         else
 414                 sc->vf_ifp = 0;
 415
 416         /*
 417          * Configure total supported RX/TX ring count
 418          */
 419         switch (sc->hw.mac.type) {
 420         case e1000_82575:
 421                 ring_max = IGB_MAX_RING_82575;
 422                 break;
 423
 424         case e1000_82576:
 425                 ring_max = IGB_MAX_RING_82576;
 426                 break;
 427
 428         case e1000_82580:
 429                 ring_max = IGB_MAX_RING_82580;
 430                 break;
 431
 432         case e1000_i350:
 433                 ring_max = IGB_MAX_RING_I350;
 434                 break;
 435
 436         case e1000_i210:
 437                 ring_max = IGB_MAX_RING_I210;
 438                 break;
 439
 440         case e1000_i211:
 441                 ring_max = IGB_MAX_RING_I211;
 442                 break;
 443
 444         default:
 445                 ring_max = IGB_MIN_RING;
 446                 break;
 447         }
 448
 449         sc->rx_ring_cnt = device_getenv_int(dev, "rxr", igb_rxr);
 450         sc->rx_ring_cnt = if_ring_count2(sc->rx_ring_cnt, ring_max);
 451 #ifdef IGB_RSS_DEBUG
 452         sc->rx_ring_cnt = device_getenv_int(dev, "rxr_debug", sc->rx_ring_cnt);
 453 #endif
 454         sc->rx_ring_inuse = sc->rx_ring_cnt;
 455
 456         sc->tx_ring_cnt = device_getenv_int(dev, "txr", igb_txr);
 457         sc->tx_ring_cnt = if_ring_count2(sc->tx_ring_cnt, ring_max);
 458 #ifdef IGB_TSS_DEBUG
 459         sc->tx_ring_cnt = device_getenv_int(dev, "txr_debug", sc->tx_ring_cnt);
 460 #endif
 461         sc->tx_ring_inuse = sc->tx_ring_cnt;
 462
 463         /* Enable bus mastering */
 464         pci_enable_busmaster(dev);
 465
 466         /*
 467          * Allocate IO memory
 468          */
 469         sc->mem_rid = PCIR_BAR(0);
 470         sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid,
 471             RF_ACTIVE);
 472         if (sc->mem_res == NULL) {
 473                 device_printf(dev, "Unable to allocate bus resource: memory\n");
 474                 error = ENXIO;
 475                 goto failed;
 476         }
 477         sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->mem_res);
 478         sc->osdep.mem_bus_space_handle = rman_get_bushandle(sc->mem_res);
 479
 480         sc->hw.hw_addr = (uint8_t *)&sc->osdep.mem_bus_space_handle;
 481
 482         /* Save PCI command register for Shared Code */
 483         sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
 484         sc->hw.back = &sc->osdep;
 485
 486         /* Do Shared Code initialization */
 487         if (e1000_setup_init_funcs(&sc->hw, TRUE)) {
 488                 device_printf(dev, "Setup of Shared code failed\n");
 489                 error = ENXIO;
 490                 goto failed;
 491         }
 492
 493         e1000_get_bus_info(&sc->hw);
 494
 495         sc->hw.mac.autoneg = DO_AUTO_NEG;
 496         sc->hw.phy.autoneg_wait_to_complete = FALSE;
 497         sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
 498
 499         /* Copper options */
 500         if (sc->hw.phy.media_type == e1000_media_type_copper) {
 501                 sc->hw.phy.mdix = AUTO_ALL_MODES;
 502                 sc->hw.phy.disable_polarity_correction = FALSE;
 503                 sc->hw.phy.ms_type = IGB_MASTER_SLAVE;
 504         }
 505
 506         /* Set the frame limits assuming  standard ethernet sized frames. */
 507         sc->max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN;
 508
 509         /* Allocate RX/TX rings */
 510         error = igb_alloc_rings(sc);
 511         if (error)
 512                 goto failed;
 513
 514 #ifdef IFPOLL_ENABLE
 515         /*
 516          * NPOLLING RX CPU offset
 517          */
 518         if (sc->rx_ring_cnt == ncpus2) {
 519                 offset = 0;
 520         } else {
 521                 offset_def = (sc->rx_ring_cnt * device_get_unit(dev)) % ncpus2;
 522                 offset = device_getenv_int(dev, "npoll.rxoff", offset_def);
 523                 if (offset >= ncpus2 ||
 524                     offset % sc->rx_ring_cnt != 0) {
 525                         device_printf(dev, "invalid npoll.rxoff %d, use %d\n",
 526                             offset, offset_def);
 527                         offset = offset_def;
 528                 }
 529         }
 530         sc->rx_npoll_off = offset;
 531
 532         /*
 533          * NPOLLING TX CPU offset
 534          */
 535         if (sc->tx_ring_cnt == ncpus2) {
 536                 offset = 0;
 537         } else {
 538                 offset_def = (sc->tx_ring_cnt * device_get_unit(dev)) % ncpus2;
 539                 offset = device_getenv_int(dev, "npoll.txoff", offset_def);
 540                 if (offset >= ncpus2 ||
 541                     offset % sc->tx_ring_cnt != 0) {
 542                         device_printf(dev, "invalid npoll.txoff %d, use %d\n",
 543                             offset, offset_def);
 544                         offset = offset_def;
 545                 }
 546         }
 547         sc->tx_npoll_off = offset;
 548 #endif
 549
 550         /* Allocate interrupt */
 551         error = igb_alloc_intr(sc);
 552         if (error)
 553                 goto failed;
 554
 555         /* Setup serializers */
 556         igb_setup_serializer(sc);
 557
 558         /* Allocate the appropriate stats memory */
 559         if (sc->vf_ifp) {
 560                 sc->stats = kmalloc(sizeof(struct e1000_vf_stats), M_DEVBUF,
 561                     M_WAITOK | M_ZERO);
 562                 igb_vf_init_stats(sc);
 563         } else {
 564                 sc->stats = kmalloc(sizeof(struct e1000_hw_stats), M_DEVBUF,
 565                     M_WAITOK | M_ZERO);
 566         }
 567
 568         /* Allocate multicast array memory. */
 569         sc->mta = kmalloc(ETHER_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES,
 570             M_DEVBUF, M_WAITOK);
 571
 572         /* Some adapter-specific advanced features */
 573         if (sc->hw.mac.type >= e1000_i350) {
 574 #ifdef notyet
 575                 igb_set_sysctl_value(adapter, "dma_coalesce",
 576                     "configure dma coalesce",
 577                     &adapter->dma_coalesce, igb_dma_coalesce);
 578                 igb_set_sysctl_value(adapter, "eee_disabled",
 579                     "enable Energy Efficient Ethernet",
 580                     &adapter->hw.dev_spec._82575.eee_disable,
 581                     igb_eee_disabled);
 582 #else
 583                 sc->dma_coalesce = igb_dma_coalesce;
 584                 sc->hw.dev_spec._82575.eee_disable = igb_eee_disabled;
 585 #endif
 586                 if (sc->hw.phy.media_type == e1000_media_type_copper)
 587                         e1000_set_eee_i350(&sc->hw);
 588         }
 589
 590         /*
 591          * Start from a known state, this is important in reading the nvm and
 592          * mac from that.
 593          */
 594         e1000_reset_hw(&sc->hw);
 595
 596         /* Make sure we have a good EEPROM before we read from it */
 597         if (sc->hw.mac.type != e1000_i210 && sc->hw.mac.type != e1000_i211 &&
 598             e1000_validate_nvm_checksum(&sc->hw) < 0) {
 599                 /*
 600                  * Some PCI-E parts fail the first check due to
 601                  * the link being in sleep state, call it again,
 602                  * if it fails a second time its a real issue.
 603                  */
 604                 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
 605                         device_printf(dev,
 606                             "The EEPROM Checksum Is Not Valid\n");
 607                         error = EIO;
 608                         goto failed;
 609                 }
 610         }
 611
 612         /* Copy the permanent MAC address out of the EEPROM */
 613         if (e1000_read_mac_addr(&sc->hw) < 0) {
 614                 device_printf(dev, "EEPROM read error while reading MAC"
 615                     " address\n");
 616                 error = EIO;
 617                 goto failed;
 618         }
 619         if (!igb_is_valid_ether_addr(sc->hw.mac.addr)) {
 620                 device_printf(dev, "Invalid MAC address\n");
 621                 error = EIO;
 622                 goto failed;
 623         }
 624
 625         /* Setup OS specific network interface */
 626         igb_setup_ifp(sc);
 627
 628         /* Add sysctl tree, must after igb_setup_ifp() */
 629         igb_add_sysctl(sc);
 630
 631         /* Now get a good starting state */
 632         igb_reset(sc);
 633
 634         /* Initialize statistics */
 635         igb_update_stats_counters(sc);
 636
 637         sc->hw.mac.get_link_status = 1;
 638         igb_update_link_status(sc);
 639
 640         /* Indicate SOL/IDER usage */
 641         if (e1000_check_reset_block(&sc->hw)) {
 642                 device_printf(dev,
 643                     "PHY reset is blocked due to SOL/IDER session.\n");
 644         }
 645
 646         /* Determine if we have to control management hardware */
 647         if (e1000_enable_mng_pass_thru(&sc->hw))
 648                 sc->flags |= IGB_FLAG_HAS_MGMT;
 649
 650         /*
 651          * Setup Wake-on-Lan
 652          */
 653         /* APME bit in EEPROM is mapped to WUC.APME */
 654         eeprom_data = E1000_READ_REG(&sc->hw, E1000_WUC) & E1000_WUC_APME;
 655         if (eeprom_data)
 656                 sc->wol = E1000_WUFC_MAG;
 657         /* XXX disable WOL */
 658         sc->wol = 0;
 659
 660 #ifdef notyet
 661         /* Register for VLAN events */
 662         adapter->vlan_attach = EVENTHANDLER_REGISTER(vlan_config,
 663              igb_register_vlan, adapter, EVENTHANDLER_PRI_FIRST);
 664         adapter->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig,
 665              igb_unregister_vlan, adapter, EVENTHANDLER_PRI_FIRST);
 666 #endif
 667
 668 #ifdef notyet
 669         igb_add_hw_stats(adapter);
 670 #endif
 671
 672         /*
 673          * Disable interrupt to prevent spurious interrupts (line based
 674          * interrupt, MSI or even MSI-X), which had been observed on
 675          * several types of LOMs, from being handled.
 676          */
 677         igb_disable_intr(sc);
 678
 679         error = igb_setup_intr(sc);
 680         if (error) {
 681                 ether_ifdetach(&sc->arpcom.ac_if);
 682                 goto failed;
 683         }
 684         return 0;
 685
 686 failed:
 687         igb_detach(dev);
 688         return error;
 689 }
 690
 691 static int
 692 igb_detach(device_t dev)
 693 {
 694         struct igb_softc *sc = device_get_softc(dev);
 695
 696         if (device_is_attached(dev)) {
 697                 struct ifnet *ifp = &sc->arpcom.ac_if;
 698
 699                 ifnet_serialize_all(ifp);
 700
 701                 igb_stop(sc);
 702
 703                 e1000_phy_hw_reset(&sc->hw);
 704
 705                 /* Give control back to firmware */
 706                 igb_rel_mgmt(sc);
 707                 igb_rel_hw_control(sc);
 708
 709                 if (sc->wol) {
 710                         E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
 711                         E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
 712                         igb_enable_wol(dev);
 713                 }
 714
 715                 igb_teardown_intr(sc);
 716
 717                 ifnet_deserialize_all(ifp);
 718
 719                 ether_ifdetach(ifp);
 720         } else if (sc->mem_res != NULL) {
 721                 igb_rel_hw_control(sc);
 722         }
 723         bus_generic_detach(dev);
 724
 725         if (sc->sysctl_tree != NULL)
 726                 sysctl_ctx_free(&sc->sysctl_ctx);
 727
 728         igb_free_intr(sc);
 729
 730         if (sc->msix_mem_res != NULL) {
 731                 bus_release_resource(dev, SYS_RES_MEMORY, sc->msix_mem_rid,
 732                     sc->msix_mem_res);
 733         }
 734         if (sc->mem_res != NULL) {
 735                 bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid,
 736                     sc->mem_res);
 737         }
 738
 739         igb_free_rings(sc);
 740
 741         if (sc->mta != NULL)
 742                 kfree(sc->mta, M_DEVBUF);
 743         if (sc->stats != NULL)
 744                 kfree(sc->stats, M_DEVBUF);
 745         if (sc->serializes != NULL)
 746                 kfree(sc->serializes, M_DEVBUF);
 747
 748         return 0;
 749 }
 750
 751 static int
 752 igb_shutdown(device_t dev)
 753 {
 754         return igb_suspend(dev);
 755 }
 756
 757 static int
 758 igb_suspend(device_t dev)
 759 {
 760         struct igb_softc *sc = device_get_softc(dev);
 761         struct ifnet *ifp = &sc->arpcom.ac_if;
 762
 763         ifnet_serialize_all(ifp);
 764
 765         igb_stop(sc);
 766
 767         igb_rel_mgmt(sc);
 768         igb_rel_hw_control(sc);
 769
 770         if (sc->wol) {
 771                 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
 772                 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
 773                 igb_enable_wol(dev);
 774         }
 775
 776         ifnet_deserialize_all(ifp);
 777
 778         return bus_generic_suspend(dev);
 779 }
 780
 781 static int
 782 igb_resume(device_t dev)
 783 {
 784         struct igb_softc *sc = device_get_softc(dev);
 785         struct ifnet *ifp = &sc->arpcom.ac_if;
 786         int i;
 787
 788         ifnet_serialize_all(ifp);
 789
 790         igb_init(sc);
 791         igb_get_mgmt(sc);
 792
 793         for (i = 0; i < sc->tx_ring_inuse; ++i)
 794                 ifsq_devstart_sched(sc->tx_rings[i].ifsq);
 795
 796         ifnet_deserialize_all(ifp);
 797
 798         return bus_generic_resume(dev);
 799 }
 800
 801 static int
 802 igb_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
 803 {
 804         struct igb_softc *sc = ifp->if_softc;
 805         struct ifreq *ifr = (struct ifreq *)data;
 806         int max_frame_size, mask, reinit;
 807         int error = 0;
 808
 809         ASSERT_IFNET_SERIALIZED_ALL(ifp);
 810
 811         switch (command) {
 812         case SIOCSIFMTU:
 813                 max_frame_size = 9234;
 814                 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN -
 815                     ETHER_CRC_LEN) {
 816                         error = EINVAL;
 817                         break;
 818                 }
 819
 820                 ifp->if_mtu = ifr->ifr_mtu;
 821                 sc->max_frame_size = ifp->if_mtu + ETHER_HDR_LEN +
 822                     ETHER_CRC_LEN;
 823
 824                 if (ifp->if_flags & IFF_RUNNING)
 825                         igb_init(sc);
 826                 break;
 827
 828         case SIOCSIFFLAGS:
 829                 if (ifp->if_flags & IFF_UP) {
 830                         if (ifp->if_flags & IFF_RUNNING) {
 831                                 if ((ifp->if_flags ^ sc->if_flags) &
 832                                     (IFF_PROMISC | IFF_ALLMULTI)) {
 833                                         igb_disable_promisc(sc);
 834                                         igb_set_promisc(sc);
 835                                 }
 836                         } else {
 837                                 igb_init(sc);
 838                         }
 839                 } else if (ifp->if_flags & IFF_RUNNING) {
 840                         igb_stop(sc);
 841                 }
 842                 sc->if_flags = ifp->if_flags;
 843                 break;
 844
 845         case SIOCADDMULTI:
 846         case SIOCDELMULTI:
 847                 if (ifp->if_flags & IFF_RUNNING) {
 848                         igb_disable_intr(sc);
 849                         igb_set_multi(sc);
 850 #ifdef IFPOLL_ENABLE
 851                         if (!(ifp->if_flags & IFF_NPOLLING))
 852 #endif
 853                                 igb_enable_intr(sc);
 854                 }
 855                 break;
 856
 857         case SIOCSIFMEDIA:
 858                 /* Check SOL/IDER usage */
 859                 if (e1000_check_reset_block(&sc->hw)) {
 860                         if_printf(ifp, "Media change is "
 861                             "blocked due to SOL/IDER session.\n");
 862                         break;
 863                 }
 864                 /* FALL THROUGH */
 865
 866         case SIOCGIFMEDIA:
 867                 error = ifmedia_ioctl(ifp, ifr, &sc->media, command);
 868                 break;
 869
 870         case SIOCSIFCAP:
 871                 reinit = 0;
 872                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
 873                 if (mask & IFCAP_RXCSUM) {
 874                         ifp->if_capenable ^= IFCAP_RXCSUM;
 875                         reinit = 1;
 876                 }
 877                 if (mask & IFCAP_VLAN_HWTAGGING) {
 878                         ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
 879                         reinit = 1;
 880                 }
 881                 if (mask & IFCAP_TXCSUM) {
 882                         ifp->if_capenable ^= IFCAP_TXCSUM;
 883                         if (ifp->if_capenable & IFCAP_TXCSUM)
 884                                 ifp->if_hwassist |= IGB_CSUM_FEATURES;
 885                         else
 886                                 ifp->if_hwassist &= ~IGB_CSUM_FEATURES;
 887                 }
 888                 if (mask & IFCAP_TSO) {
 889                         ifp->if_capenable ^= IFCAP_TSO;
 890                         if (ifp->if_capenable & IFCAP_TSO)
 891                                 ifp->if_hwassist |= CSUM_TSO;
 892                         else
 893                                 ifp->if_hwassist &= ~CSUM_TSO;
 894                 }
 895                 if (mask & IFCAP_RSS)
 896                         ifp->if_capenable ^= IFCAP_RSS;
 897                 if (reinit && (ifp->if_flags & IFF_RUNNING))
 898                         igb_init(sc);
 899                 break;
 900
 901         default:
 902                 error = ether_ioctl(ifp, command, data);
 903                 break;
 904         }
 905         return error;
 906 }
 907
 908 static void
 909 igb_init(void *xsc)
 910 {
 911         struct igb_softc *sc = xsc;
 912         struct ifnet *ifp = &sc->arpcom.ac_if;
 913         boolean_t polling;
 914         int i;
 915
 916         ASSERT_IFNET_SERIALIZED_ALL(ifp);
 917
 918         igb_stop(sc);
 919
 920         /* Get the latest mac address, User can use a LAA */
 921         bcopy(IF_LLADDR(ifp), sc->hw.mac.addr, ETHER_ADDR_LEN);
 922
 923         /* Put the address into the Receive Address Array */
 924         e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0);
 925
 926         igb_reset(sc);
 927         igb_update_link_status(sc);
 928
 929         E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
 930
 931         /* Configure for OS presence */
 932         igb_get_mgmt(sc);
 933
 934         polling = FALSE;
 935 #ifdef IFPOLL_ENABLE
 936         if (ifp->if_flags & IFF_NPOLLING)
 937                 polling = TRUE;
 938 #endif
 939
 940         /* Configured used RX/TX rings */
 941         igb_set_ring_inuse(sc, polling);
 942         ifq_set_subq_mask(&ifp->if_snd, sc->tx_ring_inuse - 1);
 943
 944         /* Initialize interrupt */
 945         igb_init_intr(sc);
 946
 947         /* Prepare transmit descriptors and buffers */
 948         for (i = 0; i < sc->tx_ring_inuse; ++i)
 949                 igb_init_tx_ring(&sc->tx_rings[i]);
 950         igb_init_tx_unit(sc);
 951
 952         /* Setup Multicast table */
 953         igb_set_multi(sc);
 954
 955 #if 0
 956         /*
 957          * Figure out the desired mbuf pool
 958          * for doing jumbo/packetsplit
 959          */
 960         if (adapter->max_frame_size <= 2048)
 961                 adapter->rx_mbuf_sz = MCLBYTES;
 962         else if (adapter->max_frame_size <= 4096)
 963                 adapter->rx_mbuf_sz = MJUMPAGESIZE;
 964         else
 965                 adapter->rx_mbuf_sz = MJUM9BYTES;
 966 #endif
 967
 968         /* Prepare receive descriptors and buffers */
 969         for (i = 0; i < sc->rx_ring_inuse; ++i) {
 970                 int error;
 971
 972                 error = igb_init_rx_ring(&sc->rx_rings[i]);
 973                 if (error) {
 974                         if_printf(ifp, "Could not setup receive structures\n");
 975                         igb_stop(sc);
 976                         return;
 977                 }
 978         }
 979         igb_init_rx_unit(sc);
 980
 981         /* Enable VLAN support */
 982         if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
 983                 igb_set_vlan(sc);
 984
 985         /* Don't lose promiscuous settings */
 986         igb_set_promisc(sc);
 987
 988         ifp->if_flags |= IFF_RUNNING;
 989         for (i = 0; i < sc->tx_ring_inuse; ++i) {
 990                 ifsq_clr_oactive(sc->tx_rings[i].ifsq);
 991                 ifsq_watchdog_start(&sc->tx_rings[i].tx_watchdog);
 992         }
 993
 994         igb_set_timer_cpuid(sc, polling);
 995         callout_reset_bycpu(&sc->timer, hz, igb_timer, sc, sc->timer_cpuid);
 996         e1000_clear_hw_cntrs_base_generic(&sc->hw);
 997
 998         /* This clears any pending interrupts */
 999         E1000_READ_REG(&sc->hw, E1000_ICR);
1000
1001         /*
1002          * Only enable interrupts if we are not polling, make sure
1003          * they are off otherwise.
1004          */
1005         if (polling) {
1006                 igb_disable_intr(sc);
1007         } else {
1008                 igb_enable_intr(sc);
1009                 E1000_WRITE_REG(&sc->hw, E1000_ICS, E1000_ICS_LSC);
1010         }
1011
1012         /* Set Energy Efficient Ethernet */
1013         if (sc->hw.phy.media_type == e1000_media_type_copper)
1014                 e1000_set_eee_i350(&sc->hw);
1015 }
1016
1017 static void
1018 igb_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
1019 {
1020         struct igb_softc *sc = ifp->if_softc;
1021
1022         ASSERT_IFNET_SERIALIZED_ALL(ifp);
1023
1024         igb_update_link_status(sc);
1025
1026         ifmr->ifm_status = IFM_AVALID;
1027         ifmr->ifm_active = IFM_ETHER;
1028
1029         if (!sc->link_active)
1030                 return;
1031
1032         ifmr->ifm_status |= IFM_ACTIVE;
1033
1034         switch (sc->link_speed) {
1035         case 10:
1036                 ifmr->ifm_active |= IFM_10_T;
1037                 break;
1038
1039         case 100:
1040                 /*
1041                  * Support for 100Mb SFP - these are Fiber
1042                  * but the media type appears as serdes
1043                  */
1044                 if (sc->hw.phy.media_type == e1000_media_type_internal_serdes)
1045                         ifmr->ifm_active |= IFM_100_FX;
1046                 else
1047                         ifmr->ifm_active |= IFM_100_TX;
1048                 break;
1049
1050         case 1000:
1051                 ifmr->ifm_active |= IFM_1000_T;
1052                 break;
1053         }
1054
1055         if (sc->link_duplex == FULL_DUPLEX)
1056                 ifmr->ifm_active |= IFM_FDX;
1057         else
1058                 ifmr->ifm_active |= IFM_HDX;
1059 }
1060
1061 static int
1062 igb_media_change(struct ifnet *ifp)
1063 {
1064         struct igb_softc *sc = ifp->if_softc;
1065         struct ifmedia *ifm = &sc->media;
1066
1067         ASSERT_IFNET_SERIALIZED_ALL(ifp);
1068
1069         if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1070                 return EINVAL;
1071
1072         switch (IFM_SUBTYPE(ifm->ifm_media)) {
1073         case IFM_AUTO:
1074                 sc->hw.mac.autoneg = DO_AUTO_NEG;
1075                 sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
1076                 break;
1077
1078         case IFM_1000_LX:
1079         case IFM_1000_SX:
1080         case IFM_1000_T:
1081                 sc->hw.mac.autoneg = DO_AUTO_NEG;
1082                 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
1083                 break;
1084
1085         case IFM_100_TX:
1086                 sc->hw.mac.autoneg = FALSE;
1087                 sc->hw.phy.autoneg_advertised = 0;
1088                 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1089                         sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL;
1090                 else
1091                         sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF;
1092                 break;
1093
1094         case IFM_10_T:
1095                 sc->hw.mac.autoneg = FALSE;
1096                 sc->hw.phy.autoneg_advertised = 0;
1097                 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1098                         sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL;
1099                 else
1100                         sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF;
1101                 break;
1102
1103         default:
1104                 if_printf(ifp, "Unsupported media type\n");
1105                 break;
1106         }
1107
1108         igb_init(sc);
1109
1110         return 0;
1111 }
1112
1113 static void
1114 igb_set_promisc(struct igb_softc *sc)
1115 {
1116         struct ifnet *ifp = &sc->arpcom.ac_if;
1117         struct e1000_hw *hw = &sc->hw;
1118         uint32_t reg;
1119
1120         if (sc->vf_ifp) {
1121                 e1000_promisc_set_vf(hw, e1000_promisc_enabled);
1122                 return;
1123         }
1124
1125         reg = E1000_READ_REG(hw, E1000_RCTL);
1126         if (ifp->if_flags & IFF_PROMISC) {
1127                 reg |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1128                 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1129         } else if (ifp->if_flags & IFF_ALLMULTI) {
1130                 reg |= E1000_RCTL_MPE;
1131                 reg &= ~E1000_RCTL_UPE;
1132                 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1133         }
1134 }
1135
1136 static void
1137 igb_disable_promisc(struct igb_softc *sc)
1138 {
1139         struct e1000_hw *hw = &sc->hw;
1140         uint32_t reg;
1141
1142         if (sc->vf_ifp) {
1143                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
1144                 return;
1145         }
1146         reg = E1000_READ_REG(hw, E1000_RCTL);
1147         reg &= ~E1000_RCTL_UPE;
1148         reg &= ~E1000_RCTL_MPE;
1149         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1150 }
1151
1152 static void
1153 igb_set_multi(struct igb_softc *sc)
1154 {
1155         struct ifnet *ifp = &sc->arpcom.ac_if;
1156         struct ifmultiaddr *ifma;
1157         uint32_t reg_rctl = 0;
1158         uint8_t *mta;
1159         int mcnt = 0;
1160
1161         mta = sc->mta;
1162         bzero(mta, ETH_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES);
1163
1164         TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1165                 if (ifma->ifma_addr->sa_family != AF_LINK)
1166                         continue;
1167
1168                 if (mcnt == MAX_NUM_MULTICAST_ADDRESSES)
1169                         break;
1170
1171                 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1172                     &mta[mcnt * ETH_ADDR_LEN], ETH_ADDR_LEN);
1173                 mcnt++;
1174         }
1175
1176         if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) {
1177                 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1178                 reg_rctl |= E1000_RCTL_MPE;
1179                 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1180         } else {
1181                 e1000_update_mc_addr_list(&sc->hw, mta, mcnt);
1182         }
1183 }
1184
1185 static void
1186 igb_timer(void *xsc)
1187 {
1188         struct igb_softc *sc = xsc;
1189
1190         lwkt_serialize_enter(&sc->main_serialize);
1191
1192         igb_update_link_status(sc);
1193         igb_update_stats_counters(sc);
1194
1195         callout_reset_bycpu(&sc->timer, hz, igb_timer, sc, sc->timer_cpuid);
1196
1197         lwkt_serialize_exit(&sc->main_serialize);
1198 }
1199
1200 static void
1201 igb_update_link_status(struct igb_softc *sc)
1202 {
1203         struct ifnet *ifp = &sc->arpcom.ac_if;
1204         struct e1000_hw *hw = &sc->hw;
1205         uint32_t link_check, thstat, ctrl;
1206
1207         link_check = thstat = ctrl = 0;
1208
1209         /* Get the cached link value or read for real */
1210         switch (hw->phy.media_type) {
1211         case e1000_media_type_copper:
1212                 if (hw->mac.get_link_status) {
1213                         /* Do the work to read phy */
1214                         e1000_check_for_link(hw);
1215                         link_check = !hw->mac.get_link_status;
1216                 } else {
1217                         link_check = TRUE;
1218                 }
1219                 break;
1220
1221         case e1000_media_type_fiber:
1222                 e1000_check_for_link(hw);
1223                 link_check = E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU;
1224                 break;
1225
1226         case e1000_media_type_internal_serdes:
1227                 e1000_check_for_link(hw);
1228                 link_check = hw->mac.serdes_has_link;
1229                 break;
1230
1231         /* VF device is type_unknown */
1232         case e1000_media_type_unknown:
1233                 e1000_check_for_link(hw);
1234                 link_check = !hw->mac.get_link_status;
1235                 /* Fall thru */
1236         default:
1237                 break;
1238         }
1239
1240         /* Check for thermal downshift or shutdown */
1241         if (hw->mac.type == e1000_i350) {
1242                 thstat = E1000_READ_REG(hw, E1000_THSTAT);
1243                 ctrl = E1000_READ_REG(hw, E1000_CTRL_EXT);
1244         }
1245
1246         /* Now we check if a transition has happened */
1247         if (link_check && sc->link_active == 0) {
1248                 e1000_get_speed_and_duplex(hw,
1249                     &sc->link_speed, &sc->link_duplex);
1250                 if (bootverbose) {
1251                         const char *flowctl;
1252
1253                         /* Get the flow control for display */
1254                         switch (hw->fc.current_mode) {
1255                         case e1000_fc_rx_pause:
1256                                 flowctl = "RX";
1257                                 break;
1258
1259                         case e1000_fc_tx_pause:
1260                                 flowctl = "TX";
1261                                 break;
1262
1263                         case e1000_fc_full:
1264                                 flowctl = "Full";
1265                                 break;
1266
1267                         default:
1268                                 flowctl = "None";
1269                                 break;
1270                         }
1271
1272                         if_printf(ifp, "Link is up %d Mbps %s, "
1273                             "Flow control: %s\n",
1274                             sc->link_speed,
1275                             sc->link_duplex == FULL_DUPLEX ?
1276                             "Full Duplex" : "Half Duplex",
1277                             flowctl);
1278                 }
1279                 sc->link_active = 1;
1280
1281                 ifp->if_baudrate = sc->link_speed * 1000000;
1282                 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_GMII) &&
1283                     (thstat & E1000_THSTAT_LINK_THROTTLE))
1284                         if_printf(ifp, "Link: thermal downshift\n");
1285                 /* This can sleep */
1286                 ifp->if_link_state = LINK_STATE_UP;
1287                 if_link_state_change(ifp);
1288         } else if (!link_check && sc->link_active == 1) {
1289                 ifp->if_baudrate = sc->link_speed = 0;
1290                 sc->link_duplex = 0;
1291                 if (bootverbose)
1292                         if_printf(ifp, "Link is Down\n");
1293                 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_GMII) &&
1294                     (thstat & E1000_THSTAT_PWR_DOWN))
1295                         if_printf(ifp, "Link: thermal shutdown\n");
1296                 sc->link_active = 0;
1297                 /* This can sleep */
1298                 ifp->if_link_state = LINK_STATE_DOWN;
1299                 if_link_state_change(ifp);
1300         }
1301 }
1302
1303 static void
1304 igb_stop(struct igb_softc *sc)
1305 {
1306         struct ifnet *ifp = &sc->arpcom.ac_if;
1307         int i;
1308
1309         ASSERT_IFNET_SERIALIZED_ALL(ifp);
1310
1311         igb_disable_intr(sc);
1312
1313         callout_stop(&sc->timer);
1314
1315         ifp->if_flags &= ~IFF_RUNNING;
1316         for (i = 0; i < sc->tx_ring_cnt; ++i) {
1317                 ifsq_clr_oactive(sc->tx_rings[i].ifsq);
1318                 ifsq_watchdog_stop(&sc->tx_rings[i].tx_watchdog);
1319                 sc->tx_rings[i].tx_flags &= ~IGB_TXFLAG_ENABLED;
1320         }
1321
1322         e1000_reset_hw(&sc->hw);
1323         E1000_WRITE_REG(&sc->hw, E1000_WUC, 0);
1324
1325         e1000_led_off(&sc->hw);
1326         e1000_cleanup_led(&sc->hw);
1327
1328         for (i = 0; i < sc->tx_ring_cnt; ++i)
1329                 igb_free_tx_ring(&sc->tx_rings[i]);
1330         for (i = 0; i < sc->rx_ring_cnt; ++i)
1331                 igb_free_rx_ring(&sc->rx_rings[i]);
1332 }
1333
1334 static void
1335 igb_reset(struct igb_softc *sc)
1336 {
1337         struct ifnet *ifp = &sc->arpcom.ac_if;
1338         struct e1000_hw *hw = &sc->hw;
1339         struct e1000_fc_info *fc = &hw->fc;
1340         uint32_t pba = 0;
1341         uint16_t hwm;
1342
1343         /* Let the firmware know the OS is in control */
1344         igb_get_hw_control(sc);
1345
1346         /*
1347          * Packet Buffer Allocation (PBA)
1348          * Writing PBA sets the receive portion of the buffer
1349          * the remainder is used for the transmit buffer.
1350          */
1351         switch (hw->mac.type) {
1352         case e1000_82575:
1353                 pba = E1000_PBA_32K;
1354                 break;
1355
1356         case e1000_82576:
1357         case e1000_vfadapt:
1358                 pba = E1000_READ_REG(hw, E1000_RXPBS);
1359                 pba &= E1000_RXPBS_SIZE_MASK_82576;
1360                 break;
1361
1362         case e1000_82580:
1363         case e1000_i350:
1364         case e1000_vfadapt_i350:
1365                 pba = E1000_READ_REG(hw, E1000_RXPBS);
1366                 pba = e1000_rxpbs_adjust_82580(pba);
1367                 break;
1368
1369         case e1000_i210:
1370         case e1000_i211:
1371                 pba = E1000_PBA_34K;
1372                 break;
1373
1374         default:
1375                 break;
1376         }
1377
1378         /* Special needs in case of Jumbo frames */
1379         if (hw->mac.type == e1000_82575 && ifp->if_mtu > ETHERMTU) {
1380                 uint32_t tx_space, min_tx, min_rx;
1381
1382                 pba = E1000_READ_REG(hw, E1000_PBA);
1383                 tx_space = pba >> 16;
1384                 pba &= 0xffff;
1385
1386                 min_tx = (sc->max_frame_size +
1387                     sizeof(struct e1000_tx_desc) - ETHER_CRC_LEN) * 2;
1388                 min_tx = roundup2(min_tx, 1024);
1389                 min_tx >>= 10;
1390                 min_rx = sc->max_frame_size;
1391                 min_rx = roundup2(min_rx, 1024);
1392                 min_rx >>= 10;
1393                 if (tx_space < min_tx && (min_tx - tx_space) < pba) {
1394                         pba = pba - (min_tx - tx_space);
1395                         /*
1396                          * if short on rx space, rx wins
1397                          * and must trump tx adjustment
1398                          */
1399                         if (pba < min_rx)
1400                                 pba = min_rx;
1401                 }
1402                 E1000_WRITE_REG(hw, E1000_PBA, pba);
1403         }
1404
1405         /*
1406          * These parameters control the automatic generation (Tx) and
1407          * response (Rx) to Ethernet PAUSE frames.
1408          * - High water mark should allow for at least two frames to be
1409          *   received after sending an XOFF.
1410          * - Low water mark works best when it is very near the high water mark.
1411          *   This allows the receiver to restart by sending XON when it has
1412          *   drained a bit.
1413          */
1414         hwm = min(((pba << 10) * 9 / 10),
1415             ((pba << 10) - 2 * sc->max_frame_size));
1416
1417         if (hw->mac.type < e1000_82576) {
1418                 fc->high_water = hwm & 0xFFF8; /* 8-byte granularity */
1419                 fc->low_water = fc->high_water - 8;
1420         } else {
1421                 fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */
1422                 fc->low_water = fc->high_water - 16;
1423         }
1424         fc->pause_time = IGB_FC_PAUSE_TIME;
1425         fc->send_xon = TRUE;
1426         fc->requested_mode = e1000_fc_default;
1427
1428         /* Issue a global reset */
1429         e1000_reset_hw(hw);
1430         E1000_WRITE_REG(hw, E1000_WUC, 0);
1431
1432         if (e1000_init_hw(hw) < 0)
1433                 if_printf(ifp, "Hardware Initialization Failed\n");
1434
1435         /* Setup DMA Coalescing */
1436         if (hw->mac.type > e1000_82580 && hw->mac.type != e1000_i211) {
1437                 uint32_t dmac;
1438                 uint32_t reg;
1439
1440                 if (sc->dma_coalesce == 0) {
1441                         /*
1442                          * Disabled
1443                          */
1444                         reg = E1000_READ_REG(hw, E1000_DMACR);
1445                         reg &= ~E1000_DMACR_DMAC_EN;
1446                         E1000_WRITE_REG(hw, E1000_DMACR, reg);
1447                         goto reset_out;
1448                 }
1449
1450                 /* Set starting thresholds */
1451                 E1000_WRITE_REG(hw, E1000_DMCTXTH, 0);
1452                 E1000_WRITE_REG(hw, E1000_DMCRTRH, 0);
1453
1454                 hwm = 64 * pba - sc->max_frame_size / 16;
1455                 if (hwm < 64 * (pba - 6))
1456                         hwm = 64 * (pba - 6);
1457                 reg = E1000_READ_REG(hw, E1000_FCRTC);
1458                 reg &= ~E1000_FCRTC_RTH_COAL_MASK;
1459                 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)
1460                     & E1000_FCRTC_RTH_COAL_MASK);
1461                 E1000_WRITE_REG(hw, E1000_FCRTC, reg);
1462
1463                 dmac = pba - sc->max_frame_size / 512;
1464                 if (dmac < pba - 10)
1465                         dmac = pba - 10;
1466                 reg = E1000_READ_REG(hw, E1000_DMACR);
1467                 reg &= ~E1000_DMACR_DMACTHR_MASK;
1468                 reg = ((dmac << E1000_DMACR_DMACTHR_SHIFT)
1469                     & E1000_DMACR_DMACTHR_MASK);
1470                 /* Transition to L0x or L1 if available.. */
1471                 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
1472                 /* timer = value in sc->dma_coalesce in 32usec intervals */
1473                 reg |= (sc->dma_coalesce >> 5);
1474                 E1000_WRITE_REG(hw, E1000_DMACR, reg);
1475
1476                 /* Set the interval before transition */
1477                 reg = E1000_READ_REG(hw, E1000_DMCTLX);
1478                 reg |= 0x80000004;
1479                 E1000_WRITE_REG(hw, E1000_DMCTLX, reg);
1480
1481                 /* Free space in tx packet buffer to wake from DMA coal */
1482                 E1000_WRITE_REG(hw, E1000_DMCTXTH,
1483                     (20480 - (2 * sc->max_frame_size)) >> 6);
1484
1485                 /* Make low power state decision controlled by DMA coal */
1486                 reg = E1000_READ_REG(hw, E1000_PCIEMISC);
1487                 reg &= ~E1000_PCIEMISC_LX_DECISION;
1488                 E1000_WRITE_REG(hw, E1000_PCIEMISC, reg);
1489                 if_printf(ifp, "DMA Coalescing enabled\n");
1490         } else if (hw->mac.type == e1000_82580) {
1491                 uint32_t reg = E1000_READ_REG(hw, E1000_PCIEMISC);
1492
1493                 E1000_WRITE_REG(hw, E1000_DMACR, 0);
1494                 E1000_WRITE_REG(hw, E1000_PCIEMISC,
1495                     reg & ~E1000_PCIEMISC_LX_DECISION);
1496         }
1497
1498 reset_out:
1499         E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
1500         e1000_get_phy_info(hw);
1501         e1000_check_for_link(hw);
1502 }
1503
1504 static void
1505 igb_setup_ifp(struct igb_softc *sc)
1506 {
1507         struct ifnet *ifp = &sc->arpcom.ac_if;
1508         int i;
1509
1510         ifp->if_softc = sc;
1511         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1512         ifp->if_init = igb_init;
1513         ifp->if_ioctl = igb_ioctl;
1514         ifp->if_start = igb_start;
1515         ifp->if_serialize = igb_serialize;
1516         ifp->if_deserialize = igb_deserialize;
1517         ifp->if_tryserialize = igb_tryserialize;
1518 #ifdef INVARIANTS
1519         ifp->if_serialize_assert = igb_serialize_assert;
1520 #endif
1521 #ifdef IFPOLL_ENABLE
1522         ifp->if_npoll = igb_npoll;
1523 #endif
1524
1525         ifq_set_maxlen(&ifp->if_snd, sc->tx_rings[0].num_tx_desc - 1);
1526         ifq_set_ready(&ifp->if_snd);
1527         ifq_set_subq_cnt(&ifp->if_snd, sc->tx_ring_cnt);
1528
1529         ifp->if_mapsubq = ifq_mapsubq_mask;
1530         ifq_set_subq_mask(&ifp->if_snd, 0);
1531
1532         ether_ifattach(ifp, sc->hw.mac.addr, NULL);
1533
1534         ifp->if_capabilities =
1535             IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_TSO;
1536         if (IGB_ENABLE_HWRSS(sc))
1537                 ifp->if_capabilities |= IFCAP_RSS;
1538         ifp->if_capenable = ifp->if_capabilities;
1539         ifp->if_hwassist = IGB_CSUM_FEATURES | CSUM_TSO;
1540
1541         /*
1542          * Tell the upper layer(s) we support long frames
1543          */
1544         ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1545
1546         /* Setup TX rings and subqueues */
1547         for (i = 0; i < sc->tx_ring_cnt; ++i) {
1548                 struct ifaltq_subque *ifsq = ifq_get_subq(&ifp->if_snd, i);
1549                 struct igb_tx_ring *txr = &sc->tx_rings[i];
1550
1551                 ifsq_set_cpuid(ifsq, txr->tx_intr_cpuid);
1552                 ifsq_set_priv(ifsq, txr);
1553                 ifsq_set_hw_serialize(ifsq, &txr->tx_serialize);
1554                 txr->ifsq = ifsq;
1555
1556                 ifsq_watchdog_init(&txr->tx_watchdog, ifsq, igb_watchdog);
1557         }
1558
1559         /*
1560          * Specify the media types supported by this adapter and register
1561          * callbacks to update media and link information
1562          */
1563         ifmedia_init(&sc->media, IFM_IMASK, igb_media_change, igb_media_status);
1564         if (sc->hw.phy.media_type == e1000_media_type_fiber ||
1565             sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
1566                 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX | IFM_FDX,
1567                     0, NULL);
1568                 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX, 0, NULL);
1569         } else {
1570                 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T, 0, NULL);
1571                 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T | IFM_FDX,
1572                     0, NULL);
1573                 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX, 0, NULL);
1574                 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX,
1575                     0, NULL);
1576                 if (sc->hw.phy.type != e1000_phy_ife) {
1577                         ifmedia_add(&sc->media,
1578                             IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
1579                         ifmedia_add(&sc->media,
1580                             IFM_ETHER | IFM_1000_T, 0, NULL);
1581                 }
1582         }
1583         ifmedia_add(&sc->media, IFM_ETHER | IFM_AUTO, 0, NULL);
1584         ifmedia_set(&sc->media, IFM_ETHER | IFM_AUTO);
1585 }
1586
1587 static void
1588 igb_add_sysctl(struct igb_softc *sc)
1589 {
1590         char node[32];
1591         int i;
1592
1593         sysctl_ctx_init(&sc->sysctl_ctx);
1594         sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx,
1595             SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
1596             device_get_nameunit(sc->dev), CTLFLAG_RD, 0, "");
1597         if (sc->sysctl_tree == NULL) {
1598                 device_printf(sc->dev, "can't add sysctl node\n");
1599                 return;
1600         }
1601
1602         SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1603             OID_AUTO, "rxr", CTLFLAG_RD, &sc->rx_ring_cnt, 0, "# of RX rings");
1604         SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1605             OID_AUTO, "rxr_inuse", CTLFLAG_RD, &sc->rx_ring_inuse, 0,
1606             "# of RX rings used");
1607         SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1608             OID_AUTO, "txr", CTLFLAG_RD, &sc->tx_ring_cnt, 0, "# of TX rings");
1609         SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1610             OID_AUTO, "txr_inuse", CTLFLAG_RD, &sc->tx_ring_inuse, 0,
1611             "# of TX rings used");
1612         SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1613             OID_AUTO, "rxd", CTLFLAG_RD, &sc->rx_rings[0].num_rx_desc, 0,
1614             "# of RX descs");
1615         SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1616             OID_AUTO, "txd", CTLFLAG_RD, &sc->tx_rings[0].num_tx_desc, 0,
1617             "# of TX descs");
1618
1619         if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
1620                 SYSCTL_ADD_PROC(&sc->sysctl_ctx,
1621                     SYSCTL_CHILDREN(sc->sysctl_tree),
1622                     OID_AUTO, "intr_rate", CTLTYPE_INT | CTLFLAG_RW,
1623                     sc, 0, igb_sysctl_intr_rate, "I", "interrupt rate");
1624         } else {
1625                 for (i = 0; i < sc->msix_cnt; ++i) {
1626                         struct igb_msix_data *msix = &sc->msix_data[i];
1627
1628                         ksnprintf(node, sizeof(node), "msix%d_rate", i);
1629                         SYSCTL_ADD_PROC(&sc->sysctl_ctx,
1630                             SYSCTL_CHILDREN(sc->sysctl_tree),
1631                             OID_AUTO, node, CTLTYPE_INT | CTLFLAG_RW,
1632                             msix, 0, igb_sysctl_msix_rate, "I",
1633                             msix->msix_rate_desc);
1634                 }
1635         }
1636
1637         SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1638             OID_AUTO, "tx_intr_nsegs", CTLTYPE_INT | CTLFLAG_RW,
1639             sc, 0, igb_sysctl_tx_intr_nsegs, "I",
1640             "# of segments per TX interrupt");
1641
1642         SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1643             OID_AUTO, "tx_wreg_nsegs", CTLTYPE_INT | CTLFLAG_RW,
1644             sc, 0, igb_sysctl_tx_wreg_nsegs, "I",
1645             "# of segments sent before write to hardware register");
1646
1647         SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1648             OID_AUTO, "rx_wreg_nsegs", CTLTYPE_INT | CTLFLAG_RW,
1649             sc, 0, igb_sysctl_rx_wreg_nsegs, "I",
1650             "# of segments received before write to hardware register");
1651
1652 #ifdef IFPOLL_ENABLE
1653         SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1654             OID_AUTO, "npoll_rxoff", CTLTYPE_INT|CTLFLAG_RW,
1655             sc, 0, igb_sysctl_npoll_rxoff, "I", "NPOLLING RX cpu offset");
1656         SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1657             OID_AUTO, "npoll_txoff", CTLTYPE_INT|CTLFLAG_RW,
1658             sc, 0, igb_sysctl_npoll_txoff, "I", "NPOLLING TX cpu offset");
1659 #endif
1660
1661 #ifdef IGB_RSS_DEBUG
1662         SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1663             OID_AUTO, "rss_debug", CTLFLAG_RW, &sc->rss_debug, 0,
1664             "RSS debug level");
1665         for (i = 0; i < sc->rx_ring_cnt; ++i) {
1666                 ksnprintf(node, sizeof(node), "rx%d_pkt", i);
1667                 SYSCTL_ADD_ULONG(&sc->sysctl_ctx,
1668                     SYSCTL_CHILDREN(sc->sysctl_tree), OID_AUTO, node,
1669                     CTLFLAG_RW, &sc->rx_rings[i].rx_packets, "RXed packets");
1670         }
1671 #endif
1672 #ifdef IGB_TSS_DEBUG
1673         for  (i = 0; i < sc->tx_ring_cnt; ++i) {
1674                 ksnprintf(node, sizeof(node), "tx%d_pkt", i);
1675                 SYSCTL_ADD_ULONG(&sc->sysctl_ctx,
1676                     SYSCTL_CHILDREN(sc->sysctl_tree), OID_AUTO, node,
1677                     CTLFLAG_RW, &sc->tx_rings[i].tx_packets, "TXed packets");
1678         }
1679 #endif
1680 }
1681
1682 static int
1683 igb_alloc_rings(struct igb_softc *sc)
1684 {
1685         int error, i;
1686
1687         /*
1688          * Create top level busdma tag
1689          */
1690         error = bus_dma_tag_create(NULL, 1, 0,
1691             BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
1692             BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0,
1693             &sc->parent_tag);
1694         if (error) {
1695                 device_printf(sc->dev, "could not create top level DMA tag\n");
1696                 return error;
1697         }
1698
1699         /*
1700          * Allocate TX descriptor rings and buffers
1701          */
1702         sc->tx_rings = kmalloc_cachealign(
1703             sizeof(struct igb_tx_ring) * sc->tx_ring_cnt,
1704             M_DEVBUF, M_WAITOK | M_ZERO);
1705         for (i = 0; i < sc->tx_ring_cnt; ++i) {
1706                 struct igb_tx_ring *txr = &sc->tx_rings[i];
1707
1708                 /* Set up some basics */
1709                 txr->sc = sc;
1710                 txr->me = i;
1711                 lwkt_serialize_init(&txr->tx_serialize);
1712
1713                 error = igb_create_tx_ring(txr);
1714                 if (error)
1715                         return error;
1716         }
1717
1718         /*
1719          * Allocate RX descriptor rings and buffers
1720          */
1721         sc->rx_rings = kmalloc_cachealign(
1722             sizeof(struct igb_rx_ring) * sc->rx_ring_cnt,
1723             M_DEVBUF, M_WAITOK | M_ZERO);
1724         for (i = 0; i < sc->rx_ring_cnt; ++i) {
1725                 struct igb_rx_ring *rxr = &sc->rx_rings[i];
1726
1727                 /* Set up some basics */
1728                 rxr->sc = sc;
1729                 rxr->me = i;
1730                 lwkt_serialize_init(&rxr->rx_serialize);
1731
1732                 error = igb_create_rx_ring(rxr);
1733                 if (error)
1734                         return error;
1735         }
1736
1737         return 0;
1738 }
1739
1740 static void
1741 igb_free_rings(struct igb_softc *sc)
1742 {
1743         int i;
1744
1745         if (sc->tx_rings != NULL) {
1746                 for (i = 0; i < sc->tx_ring_cnt; ++i) {
1747                         struct igb_tx_ring *txr = &sc->tx_rings[i];
1748
1749                         igb_destroy_tx_ring(txr, txr->num_tx_desc);
1750                 }
1751                 kfree(sc->tx_rings, M_DEVBUF);
1752         }
1753
1754         if (sc->rx_rings != NULL) {
1755                 for (i = 0; i < sc->rx_ring_cnt; ++i) {
1756                         struct igb_rx_ring *rxr = &sc->rx_rings[i];
1757
1758                         igb_destroy_rx_ring(rxr, rxr->num_rx_desc);
1759                 }
1760                 kfree(sc->rx_rings, M_DEVBUF);
1761         }
1762 }
1763
1764 static int
1765 igb_create_tx_ring(struct igb_tx_ring *txr)
1766 {
1767         int tsize, error, i, ntxd;
1768
1769         /*
1770          * Validate number of transmit descriptors. It must not exceed
1771          * hardware maximum, and must be multiple of IGB_DBA_ALIGN.
1772          */
1773         ntxd = device_getenv_int(txr->sc->dev, "txd", igb_txd);
1774         if ((ntxd * sizeof(struct e1000_tx_desc)) % IGB_DBA_ALIGN != 0 ||
1775             ntxd > IGB_MAX_TXD || ntxd < IGB_MIN_TXD) {
1776                 device_printf(txr->sc->dev,
1777                     "Using %d TX descriptors instead of %d!\n",
1778                     IGB_DEFAULT_TXD, ntxd);
1779                 txr->num_tx_desc = IGB_DEFAULT_TXD;
1780         } else {
1781                 txr->num_tx_desc = ntxd;
1782         }
1783
1784         /*
1785          * Allocate TX descriptor ring
1786          */
1787         tsize = roundup2(txr->num_tx_desc * sizeof(union e1000_adv_tx_desc),
1788             IGB_DBA_ALIGN);
1789         txr->txdma.dma_vaddr = bus_dmamem_coherent_any(txr->sc->parent_tag,
1790             IGB_DBA_ALIGN, tsize, BUS_DMA_WAITOK,
1791             &txr->txdma.dma_tag, &txr->txdma.dma_map, &txr->txdma.dma_paddr);
1792         if (txr->txdma.dma_vaddr == NULL) {
1793                 device_printf(txr->sc->dev,
1794                     "Unable to allocate TX Descriptor memory\n");
1795                 return ENOMEM;
1796         }
1797         txr->tx_base = txr->txdma.dma_vaddr;
1798         bzero(txr->tx_base, tsize);
1799
1800         tsize = __VM_CACHELINE_ALIGN(
1801             sizeof(struct igb_tx_buf) * txr->num_tx_desc);
1802         txr->tx_buf = kmalloc_cachealign(tsize, M_DEVBUF, M_WAITOK | M_ZERO);
1803
1804         /*
1805          * Allocate TX head write-back buffer
1806          */
1807         txr->tx_hdr = bus_dmamem_coherent_any(txr->sc->parent_tag,
1808             __VM_CACHELINE_SIZE, __VM_CACHELINE_SIZE, BUS_DMA_WAITOK,
1809             &txr->tx_hdr_dtag, &txr->tx_hdr_dmap, &txr->tx_hdr_paddr);
1810         if (txr->tx_hdr == NULL) {
1811                 device_printf(txr->sc->dev,
1812                     "Unable to allocate TX head write-back buffer\n");
1813                 return ENOMEM;
1814         }
1815
1816         /*
1817          * Create DMA tag for TX buffers
1818          */
1819         error = bus_dma_tag_create(txr->sc->parent_tag,
1820             1, 0,               /* alignment, bounds */
1821             BUS_SPACE_MAXADDR,  /* lowaddr */
1822             BUS_SPACE_MAXADDR,  /* highaddr */
1823             NULL, NULL,         /* filter, filterarg */
1824             IGB_TSO_SIZE,       /* maxsize */
1825             IGB_MAX_SCATTER,    /* nsegments */
1826             PAGE_SIZE,          /* maxsegsize */
1827             BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW |
1828             BUS_DMA_ONEBPAGE,   /* flags */
1829             &txr->tx_tag);
1830         if (error) {
1831                 device_printf(txr->sc->dev, "Unable to allocate TX DMA tag\n");
1832                 kfree(txr->tx_buf, M_DEVBUF);
1833                 txr->tx_buf = NULL;
1834                 return error;
1835         }
1836
1837         /*
1838          * Create DMA maps for TX buffers
1839          */
1840         for (i = 0; i < txr->num_tx_desc; ++i) {
1841                 struct igb_tx_buf *txbuf = &txr->tx_buf[i];
1842
1843                 error = bus_dmamap_create(txr->tx_tag,
1844                     BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE, &txbuf->map);
1845                 if (error) {
1846                         device_printf(txr->sc->dev,
1847                             "Unable to create TX DMA map\n");
1848                         igb_destroy_tx_ring(txr, i);
1849                         return error;
1850                 }
1851         }
1852
1853         if (txr->sc->hw.mac.type == e1000_82575)
1854                 txr->tx_flags |= IGB_TXFLAG_TSO_IPLEN0;
1855
1856         /*
1857          * Initialize various watermark
1858          */
1859         txr->spare_desc = IGB_TX_SPARE;
1860         txr->intr_nsegs = txr->num_tx_desc / 16;
1861         txr->wreg_nsegs = IGB_DEF_TXWREG_NSEGS;
1862         txr->oact_hi_desc = txr->num_tx_desc / 2;
1863         txr->oact_lo_desc = txr->num_tx_desc / 8;
1864         if (txr->oact_lo_desc > IGB_TX_OACTIVE_MAX)
1865                 txr->oact_lo_desc = IGB_TX_OACTIVE_MAX;
1866         if (txr->oact_lo_desc < txr->spare_desc + IGB_TX_RESERVED)
1867                 txr->oact_lo_desc = txr->spare_desc + IGB_TX_RESERVED;
1868
1869         return 0;
1870 }
1871
1872 static void
1873 igb_free_tx_ring(struct igb_tx_ring *txr)
1874 {
1875         int i;
1876
1877         for (i = 0; i < txr->num_tx_desc; ++i) {
1878                 struct igb_tx_buf *txbuf = &txr->tx_buf[i];
1879
1880                 if (txbuf->m_head != NULL) {
1881                         bus_dmamap_unload(txr->tx_tag, txbuf->map);
1882                         m_freem(txbuf->m_head);
1883                         txbuf->m_head = NULL;
1884                 }
1885         }
1886 }
1887
1888 static void
1889 igb_destroy_tx_ring(struct igb_tx_ring *txr, int ndesc)
1890 {
1891         int i;
1892
1893         if (txr->txdma.dma_vaddr != NULL) {
1894                 bus_dmamap_unload(txr->txdma.dma_tag, txr->txdma.dma_map);
1895                 bus_dmamem_free(txr->txdma.dma_tag, txr->txdma.dma_vaddr,
1896                     txr->txdma.dma_map);
1897                 bus_dma_tag_destroy(txr->txdma.dma_tag);
1898                 txr->txdma.dma_vaddr = NULL;
1899         }
1900
1901         if (txr->tx_hdr != NULL) {
1902                 bus_dmamap_unload(txr->tx_hdr_dtag, txr->tx_hdr_dmap);
1903                 bus_dmamem_free(txr->tx_hdr_dtag, txr->tx_hdr,
1904                     txr->tx_hdr_dmap);
1905                 bus_dma_tag_destroy(txr->tx_hdr_dtag);
1906                 txr->tx_hdr = NULL;
1907         }
1908
1909         if (txr->tx_buf == NULL)
1910                 return;
1911
1912         for (i = 0; i < ndesc; ++i) {
1913                 struct igb_tx_buf *txbuf = &txr->tx_buf[i];
1914
1915                 KKASSERT(txbuf->m_head == NULL);
1916                 bus_dmamap_destroy(txr->tx_tag, txbuf->map);
1917         }
1918         bus_dma_tag_destroy(txr->tx_tag);
1919
1920         kfree(txr->tx_buf, M_DEVBUF);
1921         txr->tx_buf = NULL;
1922 }
1923
1924 static void
1925 igb_init_tx_ring(struct igb_tx_ring *txr)
1926 {
1927         /* Clear the old descriptor contents */
1928         bzero(txr->tx_base,
1929             sizeof(union e1000_adv_tx_desc) * txr->num_tx_desc);
1930
1931         /* Clear TX head write-back buffer */
1932         *(txr->tx_hdr) = 0;
1933
1934         /* Reset indices */
1935         txr->next_avail_desc = 0;
1936         txr->next_to_clean = 0;
1937         txr->tx_nsegs = 0;
1938
1939         /* Set number of descriptors available */
1940         txr->tx_avail = txr->num_tx_desc;
1941
1942         /* Enable this TX ring */
1943         txr->tx_flags |= IGB_TXFLAG_ENABLED;
1944 }
1945
1946 static void
1947 igb_init_tx_unit(struct igb_softc *sc)
1948 {
1949         struct e1000_hw *hw = &sc->hw;
1950         uint32_t tctl;
1951         int i;
1952
1953         /* Setup the Tx Descriptor Rings */
1954         for (i = 0; i < sc->tx_ring_inuse; ++i) {
1955                 struct igb_tx_ring *txr = &sc->tx_rings[i];
1956                 uint64_t bus_addr = txr->txdma.dma_paddr;
1957                 uint64_t hdr_paddr = txr->tx_hdr_paddr;
1958                 uint32_t txdctl = 0;
1959                 uint32_t dca_txctrl;
1960
1961                 E1000_WRITE_REG(hw, E1000_TDLEN(i),
1962                     txr->num_tx_desc * sizeof(struct e1000_tx_desc));
1963                 E1000_WRITE_REG(hw, E1000_TDBAH(i),
1964                     (uint32_t)(bus_addr >> 32));
1965                 E1000_WRITE_REG(hw, E1000_TDBAL(i),
1966                     (uint32_t)bus_addr);
1967
1968                 /* Setup the HW Tx Head and Tail descriptor pointers */
1969                 E1000_WRITE_REG(hw, E1000_TDT(i), 0);
1970                 E1000_WRITE_REG(hw, E1000_TDH(i), 0);
1971
1972                 dca_txctrl = E1000_READ_REG(hw, E1000_DCA_TXCTRL(i));
1973                 dca_txctrl &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN;
1974                 E1000_WRITE_REG(hw, E1000_DCA_TXCTRL(i), dca_txctrl);
1975
1976                 /*
1977                  * Don't set WB_on_EITR:
1978                  * - 82575 does not have it
1979                  * - It almost has no effect on 82576, see:
1980                  *   82576 specification update errata #26
1981                  * - It causes unnecessary bus traffic
1982                  */
1983                 E1000_WRITE_REG(hw, E1000_TDWBAH(i),
1984                     (uint32_t)(hdr_paddr >> 32));
1985                 E1000_WRITE_REG(hw, E1000_TDWBAL(i),
1986                     ((uint32_t)hdr_paddr) | E1000_TX_HEAD_WB_ENABLE);
1987
1988                 /*
1989                  * WTHRESH is ignored by the hardware, since header
1990                  * write back mode is used.
1991                  */
1992                 txdctl |= IGB_TX_PTHRESH;
1993                 txdctl |= IGB_TX_HTHRESH << 8;
1994                 txdctl |= IGB_TX_WTHRESH << 16;
1995                 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
1996                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl);
1997         }
1998
1999         if (sc->vf_ifp)
2000                 return;
2001
2002         e1000_config_collision_dist(hw);
2003
2004         /* Program the Transmit Control Register */
2005         tctl = E1000_READ_REG(hw, E1000_TCTL);
2006         tctl &= ~E1000_TCTL_CT;
2007         tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
2008             (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT));
2009
2010         /* This write will effectively turn on the transmit unit. */
2011         E1000_WRITE_REG(hw, E1000_TCTL, tctl);
2012 }
2013
2014 static boolean_t
2015 igb_txcsum_ctx(struct igb_tx_ring *txr, struct mbuf *mp)
2016 {
2017         struct e1000_adv_tx_context_desc *TXD;
2018         uint32_t vlan_macip_lens, type_tucmd_mlhl, mss_l4len_idx;
2019         int ehdrlen, ctxd, ip_hlen = 0;
2020         boolean_t offload = TRUE;
2021
2022         if ((mp->m_pkthdr.csum_flags & IGB_CSUM_FEATURES) == 0)
2023                 offload = FALSE;
2024
2025         vlan_macip_lens = type_tucmd_mlhl = mss_l4len_idx = 0;
2026
2027         ctxd = txr->next_avail_desc;
2028         TXD = (struct e1000_adv_tx_context_desc *)&txr->tx_base[ctxd];
2029
2030         /*
2031          * In advanced descriptors the vlan tag must
2032          * be placed into the context descriptor, thus
2033          * we need to be here just for that setup.
2034          */
2035         if (mp->m_flags & M_VLANTAG) {
2036                 uint16_t vlantag;
2037
2038                 vlantag = htole16(mp->m_pkthdr.ether_vlantag);
2039                 vlan_macip_lens |= (vlantag << E1000_ADVTXD_VLAN_SHIFT);
2040         } else if (!offload) {
2041                 return FALSE;
2042         }
2043
2044         ehdrlen = mp->m_pkthdr.csum_lhlen;
2045         KASSERT(ehdrlen > 0, ("invalid ether hlen"));
2046
2047         /* Set the ether header length */
2048         vlan_macip_lens |= ehdrlen << E1000_ADVTXD_MACLEN_SHIFT;
2049         if (mp->m_pkthdr.csum_flags & CSUM_IP) {
2050                 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_IPV4;
2051                 ip_hlen = mp->m_pkthdr.csum_iphlen;
2052                 KASSERT(ip_hlen > 0, ("invalid ip hlen"));
2053         }
2054         vlan_macip_lens |= ip_hlen;
2055
2056         type_tucmd_mlhl |= E1000_ADVTXD_DCMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
2057         if (mp->m_pkthdr.csum_flags & CSUM_TCP)
2058                 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_TCP;
2059         else if (mp->m_pkthdr.csum_flags & CSUM_UDP)
2060                 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_UDP;
2061
2062         /*
2063          * 82575 needs the TX context index added; the queue
2064          * index is used as TX context index here.
2065          */
2066         if (txr->sc->hw.mac.type == e1000_82575)
2067                 mss_l4len_idx = txr->me << 4;
2068
2069         /* Now copy bits into descriptor */
2070         TXD->vlan_macip_lens = htole32(vlan_macip_lens);
2071         TXD->type_tucmd_mlhl = htole32(type_tucmd_mlhl);
2072         TXD->seqnum_seed = htole32(0);
2073         TXD->mss_l4len_idx = htole32(mss_l4len_idx);
2074
2075         /* We've consumed the first desc, adjust counters */
2076         if (++ctxd == txr->num_tx_desc)
2077                 ctxd = 0;
2078         txr->next_avail_desc = ctxd;
2079         --txr->tx_avail;
2080
2081         return offload;
2082 }
2083
2084 static void
2085 igb_txeof(struct igb_tx_ring *txr)
2086 {
2087         struct ifnet *ifp = &txr->sc->arpcom.ac_if;
2088         int first, hdr, avail;
2089
2090         if (txr->tx_avail == txr->num_tx_desc)
2091                 return;
2092
2093         first = txr->next_to_clean;
2094         hdr = *(txr->tx_hdr);
2095
2096         if (first == hdr)
2097                 return;
2098
2099         avail = txr->tx_avail;
2100         while (first != hdr) {
2101                 struct igb_tx_buf *txbuf = &txr->tx_buf[first];
2102
2103                 ++avail;
2104                 if (txbuf->m_head) {
2105                         bus_dmamap_unload(txr->tx_tag, txbuf->map);
2106                         m_freem(txbuf->m_head);
2107                         txbuf->m_head = NULL;
2108                         IFNET_STAT_INC(ifp, opackets, 1);
2109                 }
2110                 if (++first == txr->num_tx_desc)
2111                         first = 0;
2112         }
2113         txr->next_to_clean = first;
2114         txr->tx_avail = avail;
2115
2116         /*
2117          * If we have a minimum free, clear OACTIVE
2118          * to tell the stack that it is OK to send packets.
2119          */
2120         if (IGB_IS_NOT_OACTIVE(txr)) {
2121                 ifsq_clr_oactive(txr->ifsq);
2122
2123                 /*
2124                  * We have enough TX descriptors, turn off
2125                  * the watchdog.  We allow small amount of
2126                  * packets (roughly intr_nsegs) pending on
2127                  * the transmit ring.
2128                  */
2129                 txr->tx_watchdog.wd_timer = 0;
2130         }
2131 }
2132
2133 static int
2134 igb_create_rx_ring(struct igb_rx_ring *rxr)
2135 {
2136         int rsize, i, error, nrxd;
2137
2138         /*
2139          * Validate number of receive descriptors. It must not exceed
2140          * hardware maximum, and must be multiple of IGB_DBA_ALIGN.
2141          */
2142         nrxd = device_getenv_int(rxr->sc->dev, "rxd", igb_rxd);
2143         if ((nrxd * sizeof(struct e1000_rx_desc)) % IGB_DBA_ALIGN != 0 ||
2144             nrxd > IGB_MAX_RXD || nrxd < IGB_MIN_RXD) {
2145                 device_printf(rxr->sc->dev,
2146                     "Using %d RX descriptors instead of %d!\n",
2147                     IGB_DEFAULT_RXD, nrxd);
2148                 rxr->num_rx_desc = IGB_DEFAULT_RXD;
2149         } else {
2150                 rxr->num_rx_desc = nrxd;
2151         }
2152
2153         /*
2154          * Allocate RX descriptor ring
2155          */
2156         rsize = roundup2(rxr->num_rx_desc * sizeof(union e1000_adv_rx_desc),
2157             IGB_DBA_ALIGN);
2158         rxr->rxdma.dma_vaddr = bus_dmamem_coherent_any(rxr->sc->parent_tag,
2159             IGB_DBA_ALIGN, rsize, BUS_DMA_WAITOK,
2160             &rxr->rxdma.dma_tag, &rxr->rxdma.dma_map,
2161             &rxr->rxdma.dma_paddr);
2162         if (rxr->rxdma.dma_vaddr == NULL) {
2163                 device_printf(rxr->sc->dev,
2164                     "Unable to allocate RxDescriptor memory\n");
2165                 return ENOMEM;
2166         }
2167         rxr->rx_base = rxr->rxdma.dma_vaddr;
2168         bzero(rxr->rx_base, rsize);
2169
2170         rsize = __VM_CACHELINE_ALIGN(
2171             sizeof(struct igb_rx_buf) * rxr->num_rx_desc);
2172         rxr->rx_buf = kmalloc_cachealign(rsize, M_DEVBUF, M_WAITOK | M_ZERO);
2173
2174         /*
2175          * Create DMA tag for RX buffers
2176          */
2177         error = bus_dma_tag_create(rxr->sc->parent_tag,
2178             1, 0,               /* alignment, bounds */
2179             BUS_SPACE_MAXADDR,  /* lowaddr */
2180             BUS_SPACE_MAXADDR,  /* highaddr */
2181             NULL, NULL,         /* filter, filterarg */
2182             MCLBYTES,           /* maxsize */
2183             1,                  /* nsegments */
2184             MCLBYTES,           /* maxsegsize */
2185             BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, /* flags */
2186             &rxr->rx_tag);
2187         if (error) {
2188                 device_printf(rxr->sc->dev,
2189                     "Unable to create RX payload DMA tag\n");
2190                 kfree(rxr->rx_buf, M_DEVBUF);
2191                 rxr->rx_buf = NULL;
2192                 return error;
2193         }
2194
2195         /*
2196          * Create spare DMA map for RX buffers
2197          */
2198         error = bus_dmamap_create(rxr->rx_tag, BUS_DMA_WAITOK,
2199             &rxr->rx_sparemap);
2200         if (error) {
2201                 device_printf(rxr->sc->dev,
2202                     "Unable to create spare RX DMA maps\n");
2203                 bus_dma_tag_destroy(rxr->rx_tag);
2204                 kfree(rxr->rx_buf, M_DEVBUF);
2205                 rxr->rx_buf = NULL;
2206                 return error;
2207         }
2208
2209         /*
2210          * Create DMA maps for RX buffers
2211          */
2212         for (i = 0; i < rxr->num_rx_desc; i++) {
2213                 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2214
2215                 error = bus_dmamap_create(rxr->rx_tag,
2216                     BUS_DMA_WAITOK, &rxbuf->map);
2217                 if (error) {
2218                         device_printf(rxr->sc->dev,
2219                             "Unable to create RX DMA maps\n");
2220                         igb_destroy_rx_ring(rxr, i);
2221                         return error;
2222                 }
2223         }
2224
2225         /*
2226          * Initialize various watermark
2227          */
2228         rxr->wreg_nsegs = IGB_DEF_RXWREG_NSEGS;
2229
2230         return 0;
2231 }
2232
2233 static void
2234 igb_free_rx_ring(struct igb_rx_ring *rxr)
2235 {
2236         int i;
2237
2238         for (i = 0; i < rxr->num_rx_desc; ++i) {
2239                 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2240
2241                 if (rxbuf->m_head != NULL) {
2242                         bus_dmamap_unload(rxr->rx_tag, rxbuf->map);
2243                         m_freem(rxbuf->m_head);
2244                         rxbuf->m_head = NULL;
2245                 }
2246         }
2247
2248         if (rxr->fmp != NULL)
2249                 m_freem(rxr->fmp);
2250         rxr->fmp = NULL;
2251         rxr->lmp = NULL;
2252 }
2253
2254 static void
2255 igb_destroy_rx_ring(struct igb_rx_ring *rxr, int ndesc)
2256 {
2257         int i;
2258
2259         if (rxr->rxdma.dma_vaddr != NULL) {
2260                 bus_dmamap_unload(rxr->rxdma.dma_tag, rxr->rxdma.dma_map);
2261                 bus_dmamem_free(rxr->rxdma.dma_tag, rxr->rxdma.dma_vaddr,
2262                     rxr->rxdma.dma_map);
2263                 bus_dma_tag_destroy(rxr->rxdma.dma_tag);
2264                 rxr->rxdma.dma_vaddr = NULL;
2265         }
2266
2267         if (rxr->rx_buf == NULL)
2268                 return;
2269
2270         for (i = 0; i < ndesc; ++i) {
2271                 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2272
2273                 KKASSERT(rxbuf->m_head == NULL);
2274                 bus_dmamap_destroy(rxr->rx_tag, rxbuf->map);
2275         }
2276         bus_dmamap_destroy(rxr->rx_tag, rxr->rx_sparemap);
2277         bus_dma_tag_destroy(rxr->rx_tag);
2278
2279         kfree(rxr->rx_buf, M_DEVBUF);
2280         rxr->rx_buf = NULL;
2281 }
2282
2283 static void
2284 igb_setup_rxdesc(union e1000_adv_rx_desc *rxd, const struct igb_rx_buf *rxbuf)
2285 {
2286         rxd->read.pkt_addr = htole64(rxbuf->paddr);
2287         rxd->wb.upper.status_error = 0;
2288 }
2289
2290 static int
2291 igb_newbuf(struct igb_rx_ring *rxr, int i, boolean_t wait)
2292 {
2293         struct mbuf *m;
2294         bus_dma_segment_t seg;
2295         bus_dmamap_t map;
2296         struct igb_rx_buf *rxbuf;
2297         int error, nseg;
2298
2299         m = m_getcl(wait ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
2300         if (m == NULL) {
2301                 if (wait) {
2302                         if_printf(&rxr->sc->arpcom.ac_if,
2303                             "Unable to allocate RX mbuf\n");
2304                 }
2305                 return ENOBUFS;
2306         }
2307         m->m_len = m->m_pkthdr.len = MCLBYTES;
2308
2309         if (rxr->sc->max_frame_size <= MCLBYTES - ETHER_ALIGN)
2310                 m_adj(m, ETHER_ALIGN);
2311
2312         error = bus_dmamap_load_mbuf_segment(rxr->rx_tag,
2313             rxr->rx_sparemap, m, &seg, 1, &nseg, BUS_DMA_NOWAIT);
2314         if (error) {
2315                 m_freem(m);
2316                 if (wait) {
2317                         if_printf(&rxr->sc->arpcom.ac_if,
2318                             "Unable to load RX mbuf\n");
2319                 }
2320                 return error;
2321         }
2322
2323         rxbuf = &rxr->rx_buf[i];
2324         if (rxbuf->m_head != NULL)
2325                 bus_dmamap_unload(rxr->rx_tag, rxbuf->map);
2326
2327         map = rxbuf->map;
2328         rxbuf->map = rxr->rx_sparemap;
2329         rxr->rx_sparemap = map;
2330
2331         rxbuf->m_head = m;
2332         rxbuf->paddr = seg.ds_addr;
2333
2334         igb_setup_rxdesc(&rxr->rx_base[i], rxbuf);
2335         return 0;
2336 }
2337
2338 static int
2339 igb_init_rx_ring(struct igb_rx_ring *rxr)
2340 {
2341         int i;
2342
2343         /* Clear the ring contents */
2344         bzero(rxr->rx_base,
2345             rxr->num_rx_desc * sizeof(union e1000_adv_rx_desc));
2346
2347         /* Now replenish the ring mbufs */
2348         for (i = 0; i < rxr->num_rx_desc; ++i) {
2349                 int error;
2350
2351                 error = igb_newbuf(rxr, i, TRUE);
2352                 if (error)
2353                         return error;
2354         }
2355
2356         /* Setup our descriptor indices */
2357         rxr->next_to_check = 0;
2358
2359         rxr->fmp = NULL;
2360         rxr->lmp = NULL;
2361         rxr->discard = FALSE;
2362
2363         return 0;
2364 }
2365
2366 static void
2367 igb_init_rx_unit(struct igb_softc *sc)
2368 {
2369         struct ifnet *ifp = &sc->arpcom.ac_if;
2370         struct e1000_hw *hw = &sc->hw;
2371         uint32_t rctl, rxcsum, srrctl = 0;
2372         int i;
2373
2374         /*
2375          * Make sure receives are disabled while setting
2376          * up the descriptor ring
2377          */
2378         rctl = E1000_READ_REG(hw, E1000_RCTL);
2379         E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
2380
2381 #if 0
2382         /*
2383         ** Set up for header split
2384         */
2385         if (igb_header_split) {
2386                 /* Use a standard mbuf for the header */
2387                 srrctl |= IGB_HDR_BUF << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
2388                 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2389         } else
2390 #endif
2391                 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
2392
2393         /*
2394         ** Set up for jumbo frames
2395         */
2396         if (ifp->if_mtu > ETHERMTU) {
2397                 rctl |= E1000_RCTL_LPE;
2398 #if 0
2399                 if (adapter->rx_mbuf_sz == MJUMPAGESIZE) {
2400                         srrctl |= 4096 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2401                         rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX;
2402                 } else if (adapter->rx_mbuf_sz > MJUMPAGESIZE) {
2403                         srrctl |= 8192 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2404                         rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX;
2405                 }
2406                 /* Set maximum packet len */
2407                 psize = adapter->max_frame_size;
2408                 /* are we on a vlan? */
2409                 if (adapter->ifp->if_vlantrunk != NULL)
2410                         psize += VLAN_TAG_SIZE;
2411                 E1000_WRITE_REG(&adapter->hw, E1000_RLPML, psize);
2412 #else
2413                 srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2414                 rctl |= E1000_RCTL_SZ_2048;
2415 #endif
2416         } else {
2417                 rctl &= ~E1000_RCTL_LPE;
2418                 srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2419                 rctl |= E1000_RCTL_SZ_2048;
2420         }
2421
2422         /* Setup the Base and Length of the Rx Descriptor Rings */
2423         for (i = 0; i < sc->rx_ring_inuse; ++i) {
2424                 struct igb_rx_ring *rxr = &sc->rx_rings[i];
2425                 uint64_t bus_addr = rxr->rxdma.dma_paddr;
2426                 uint32_t rxdctl;
2427
2428                 E1000_WRITE_REG(hw, E1000_RDLEN(i),
2429                     rxr->num_rx_desc * sizeof(struct e1000_rx_desc));
2430                 E1000_WRITE_REG(hw, E1000_RDBAH(i),
2431                     (uint32_t)(bus_addr >> 32));
2432                 E1000_WRITE_REG(hw, E1000_RDBAL(i),
2433                     (uint32_t)bus_addr);
2434                 E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl);
2435                 /* Enable this Queue */
2436                 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));
2437                 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
2438                 rxdctl &= 0xFFF00000;
2439                 rxdctl |= IGB_RX_PTHRESH;
2440                 rxdctl |= IGB_RX_HTHRESH << 8;
2441                 /*
2442                  * Don't set WTHRESH to a value above 1 on 82576, see:
2443                  * 82576 specification update errata #26
2444                  */
2445                 rxdctl |= IGB_RX_WTHRESH << 16;
2446                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
2447         }
2448
2449         rxcsum = E1000_READ_REG(&sc->hw, E1000_RXCSUM);
2450         rxcsum &= ~(E1000_RXCSUM_PCSS_MASK | E1000_RXCSUM_IPPCSE);
2451
2452         /*
2453          * Receive Checksum Offload for TCP and UDP
2454          *
2455          * Checksum offloading is also enabled if multiple receive
2456          * queue is to be supported, since we need it to figure out
2457          * fragments.
2458          */
2459         if ((ifp->if_capenable & IFCAP_RXCSUM) || IGB_ENABLE_HWRSS(sc)) {
2460                 /*
2461                  * NOTE:
2462                  * PCSD must be enabled to enable multiple
2463                  * receive queues.
2464                  */
2465                 rxcsum |= E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL |
2466                     E1000_RXCSUM_PCSD;
2467         } else {
2468                 rxcsum &= ~(E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL |
2469                     E1000_RXCSUM_PCSD);
2470         }
2471         E1000_WRITE_REG(&sc->hw, E1000_RXCSUM, rxcsum);
2472
2473         if (IGB_ENABLE_HWRSS(sc)) {
2474                 uint8_t key[IGB_NRSSRK * IGB_RSSRK_SIZE];
2475                 uint32_t reta_shift;
2476                 int j, r;
2477
2478                 /*
2479                  * NOTE:
2480                  * When we reach here, RSS has already been disabled
2481                  * in igb_stop(), so we could safely configure RSS key
2482                  * and redirect table.
2483                  */
2484
2485                 /*
2486                  * Configure RSS key
2487                  */
2488                 toeplitz_get_key(key, sizeof(key));
2489                 for (i = 0; i < IGB_NRSSRK; ++i) {
2490                         uint32_t rssrk;
2491
2492                         rssrk = IGB_RSSRK_VAL(key, i);
2493                         IGB_RSS_DPRINTF(sc, 1, "rssrk%d 0x%08x\n", i, rssrk);
2494
2495                         E1000_WRITE_REG(hw, E1000_RSSRK(i), rssrk);
2496                 }
2497
2498                 /*
2499                  * Configure RSS redirect table in following fashion:
2500                  * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)]
2501                  */
2502                 reta_shift = IGB_RETA_SHIFT;
2503                 if (hw->mac.type == e1000_82575)
2504                         reta_shift = IGB_RETA_SHIFT_82575;
2505
2506                 r = 0;
2507                 for (j = 0; j < IGB_NRETA; ++j) {
2508                         uint32_t reta = 0;
2509
2510                         for (i = 0; i < IGB_RETA_SIZE; ++i) {
2511                                 uint32_t q;
2512
2513                                 q = (r % sc->rx_ring_inuse) << reta_shift;
2514                                 reta |= q << (8 * i);
2515                                 ++r;
2516                         }
2517                         IGB_RSS_DPRINTF(sc, 1, "reta 0x%08x\n", reta);
2518                         E1000_WRITE_REG(hw, E1000_RETA(j), reta);
2519                 }
2520
2521                 /*
2522                  * Enable multiple receive queues.
2523                  * Enable IPv4 RSS standard hash functions.
2524                  * Disable RSS interrupt on 82575
2525                  */
2526                 E1000_WRITE_REG(&sc->hw, E1000_MRQC,
2527                                 E1000_MRQC_ENABLE_RSS_4Q |
2528                                 E1000_MRQC_RSS_FIELD_IPV4_TCP |
2529                                 E1000_MRQC_RSS_FIELD_IPV4);
2530         }
2531
2532         /* Setup the Receive Control Register */
2533         rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2534         rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO |
2535             E1000_RCTL_RDMTS_HALF |
2536             (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
2537         /* Strip CRC bytes. */
2538         rctl |= E1000_RCTL_SECRC;
2539         /* Make sure VLAN Filters are off */
2540         rctl &= ~E1000_RCTL_VFE;
2541         /* Don't store bad packets */
2542         rctl &= ~E1000_RCTL_SBP;
2543
2544         /* Enable Receives */
2545         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2546
2547         /*
2548          * Setup the HW Rx Head and Tail Descriptor Pointers
2549          *   - needs to be after enable
2550          */
2551         for (i = 0; i < sc->rx_ring_inuse; ++i) {
2552                 struct igb_rx_ring *rxr = &sc->rx_rings[i];
2553
2554                 E1000_WRITE_REG(hw, E1000_RDH(i), rxr->next_to_check);
2555                 E1000_WRITE_REG(hw, E1000_RDT(i), rxr->num_rx_desc - 1);
2556         }
2557 }
2558
2559 static void
2560 igb_rx_refresh(struct igb_rx_ring *rxr, int i)
2561 {
2562         if (--i < 0)
2563                 i = rxr->num_rx_desc - 1;
2564         E1000_WRITE_REG(&rxr->sc->hw, E1000_RDT(rxr->me), i);
2565 }
2566
2567 static void
2568 igb_rxeof(struct igb_rx_ring *rxr, int count)
2569 {
2570         struct ifnet *ifp = &rxr->sc->arpcom.ac_if;
2571         union e1000_adv_rx_desc *cur;
2572         uint32_t staterr;
2573         int i, ncoll = 0;
2574
2575         i = rxr->next_to_check;
2576         cur = &rxr->rx_base[i];
2577         staterr = le32toh(cur->wb.upper.status_error);
2578
2579         if ((staterr & E1000_RXD_STAT_DD) == 0)
2580                 return;
2581
2582         while ((staterr & E1000_RXD_STAT_DD) && count != 0) {
2583                 struct pktinfo *pi = NULL, pi0;
2584                 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2585                 struct mbuf *m = NULL;
2586                 boolean_t eop;
2587
2588                 eop = (staterr & E1000_RXD_STAT_EOP) ? TRUE : FALSE;
2589                 if (eop)
2590                         --count;
2591
2592                 ++ncoll;
2593                 if ((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) == 0 &&
2594                     !rxr->discard) {
2595                         struct mbuf *mp = rxbuf->m_head;
2596                         uint32_t hash, hashtype;
2597                         uint16_t vlan;
2598                         int len;
2599
2600                         len = le16toh(cur->wb.upper.length);
2601                         if (rxr->sc->hw.mac.type == e1000_i350 &&
2602                             (staterr & E1000_RXDEXT_STATERR_LB))
2603                                 vlan = be16toh(cur->wb.upper.vlan);
2604                         else
2605                                 vlan = le16toh(cur->wb.upper.vlan);
2606
2607                         hash = le32toh(cur->wb.lower.hi_dword.rss);
2608                         hashtype = le32toh(cur->wb.lower.lo_dword.data) &
2609                             E1000_RXDADV_RSSTYPE_MASK;
2610
2611                         IGB_RSS_DPRINTF(rxr->sc, 10,
2612                             "ring%d, hash 0x%08x, hashtype %u\n",
2613                             rxr->me, hash, hashtype);
2614
2615                         bus_dmamap_sync(rxr->rx_tag, rxbuf->map,
2616                             BUS_DMASYNC_POSTREAD);
2617
2618                         if (igb_newbuf(rxr, i, FALSE) != 0) {
2619                                 IFNET_STAT_INC(ifp, iqdrops, 1);
2620                                 goto discard;
2621                         }
2622
2623                         mp->m_len = len;
2624                         if (rxr->fmp == NULL) {
2625                                 mp->m_pkthdr.len = len;
2626                                 rxr->fmp = mp;
2627                                 rxr->lmp = mp;
2628                         } else {
2629                                 rxr->lmp->m_next = mp;
2630                                 rxr->lmp = rxr->lmp->m_next;
2631                                 rxr->fmp->m_pkthdr.len += len;
2632                         }
2633
2634                         if (eop) {
2635                                 m = rxr->fmp;
2636                                 rxr->fmp = NULL;
2637                                 rxr->lmp = NULL;
2638
2639                                 m->m_pkthdr.rcvif = ifp;
2640                                 IFNET_STAT_INC(ifp, ipackets, 1);
2641
2642                                 if (ifp->if_capenable & IFCAP_RXCSUM)
2643                                         igb_rxcsum(staterr, m);
2644
2645                                 if (staterr & E1000_RXD_STAT_VP) {
2646                                         m->m_pkthdr.ether_vlantag = vlan;
2647                                         m->m_flags |= M_VLANTAG;
2648                                 }
2649
2650                                 if (ifp->if_capenable & IFCAP_RSS) {
2651                                         pi = igb_rssinfo(m, &pi0,
2652                                             hash, hashtype, staterr);
2653                                 }
2654 #ifdef IGB_RSS_DEBUG
2655                                 rxr->rx_packets++;
2656 #endif
2657                         }
2658                 } else {
2659                         IFNET_STAT_INC(ifp, ierrors, 1);
2660 discard:
2661                         igb_setup_rxdesc(cur, rxbuf);
2662                         if (!eop)
2663                                 rxr->discard = TRUE;
2664                         else
2665                                 rxr->discard = FALSE;
2666                         if (rxr->fmp != NULL) {
2667                                 m_freem(rxr->fmp);
2668                                 rxr->fmp = NULL;
2669                                 rxr->lmp = NULL;
2670                         }
2671                         m = NULL;
2672                 }
2673
2674                 if (m != NULL)
2675                         ether_input_pkt(ifp, m, pi);
2676
2677                 /* Advance our pointers to the next descriptor. */
2678                 if (++i == rxr->num_rx_desc)
2679                         i = 0;
2680
2681                 if (ncoll >= rxr->wreg_nsegs) {
2682                         igb_rx_refresh(rxr, i);
2683                         ncoll = 0;
2684                 }
2685
2686                 cur = &rxr->rx_base[i];
2687                 staterr = le32toh(cur->wb.upper.status_error);
2688         }
2689         rxr->next_to_check = i;
2690
2691         if (ncoll > 0)
2692                 igb_rx_refresh(rxr, i);
2693 }
2694
2695
2696 static void
2697 igb_set_vlan(struct igb_softc *sc)
2698 {
2699         struct e1000_hw *hw = &sc->hw;
2700         uint32_t reg;
2701 #if 0
2702         struct ifnet *ifp = sc->arpcom.ac_if;
2703 #endif
2704
2705         if (sc->vf_ifp) {
2706                 e1000_rlpml_set_vf(hw, sc->max_frame_size + VLAN_TAG_SIZE);
2707                 return;
2708         }
2709
2710         reg = E1000_READ_REG(hw, E1000_CTRL);
2711         reg |= E1000_CTRL_VME;
2712         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2713
2714 #if 0
2715         /* Enable the Filter Table */
2716         if (ifp->if_capenable & IFCAP_VLAN_HWFILTER) {
2717                 reg = E1000_READ_REG(hw, E1000_RCTL);
2718                 reg &= ~E1000_RCTL_CFIEN;
2719                 reg |= E1000_RCTL_VFE;
2720                 E1000_WRITE_REG(hw, E1000_RCTL, reg);
2721         }
2722 #endif
2723
2724         /* Update the frame size */
2725         E1000_WRITE_REG(&sc->hw, E1000_RLPML,
2726             sc->max_frame_size + VLAN_TAG_SIZE);
2727
2728 #if 0
2729         /* Don't bother with table if no vlans */
2730         if ((adapter->num_vlans == 0) ||
2731             ((ifp->if_capenable & IFCAP_VLAN_HWFILTER) == 0))
2732                 return;
2733         /*
2734         ** A soft reset zero's out the VFTA, so
2735         ** we need to repopulate it now.
2736         */
2737         for (int i = 0; i < IGB_VFTA_SIZE; i++)
2738                 if (adapter->shadow_vfta[i] != 0) {
2739                         if (adapter->vf_ifp)
2740                                 e1000_vfta_set_vf(hw,
2741                                     adapter->shadow_vfta[i], TRUE);
2742                         else
2743                                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA,
2744                                  i, adapter->shadow_vfta[i]);
2745                 }
2746 #endif
2747 }
2748
2749 static void
2750 igb_enable_intr(struct igb_softc *sc)
2751 {
2752         if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
2753                 lwkt_serialize_handler_enable(&sc->main_serialize);
2754         } else {
2755                 int i;
2756
2757                 for (i = 0; i < sc->msix_cnt; ++i) {
2758                         lwkt_serialize_handler_enable(
2759                             sc->msix_data[i].msix_serialize);
2760                 }
2761         }
2762
2763         if ((sc->flags & IGB_FLAG_SHARED_INTR) == 0) {
2764                 if (sc->intr_type == PCI_INTR_TYPE_MSIX)
2765                         E1000_WRITE_REG(&sc->hw, E1000_EIAC, sc->intr_mask);
2766                 else
2767                         E1000_WRITE_REG(&sc->hw, E1000_EIAC, 0);
2768                 E1000_WRITE_REG(&sc->hw, E1000_EIAM, sc->intr_mask);
2769                 E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->intr_mask);
2770                 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC);
2771         } else {
2772                 E1000_WRITE_REG(&sc->hw, E1000_IMS, IMS_ENABLE_MASK);
2773         }
2774         E1000_WRITE_FLUSH(&sc->hw);
2775 }
2776
2777 static void
2778 igb_disable_intr(struct igb_softc *sc)
2779 {
2780         if ((sc->flags & IGB_FLAG_SHARED_INTR) == 0) {
2781                 E1000_WRITE_REG(&sc->hw, E1000_EIMC, 0xffffffff);
2782                 E1000_WRITE_REG(&sc->hw, E1000_EIAC, 0);
2783         }
2784         E1000_WRITE_REG(&sc->hw, E1000_IMC, 0xffffffff);
2785         E1000_WRITE_FLUSH(&sc->hw);
2786
2787         if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
2788                 lwkt_serialize_handler_disable(&sc->main_serialize);
2789         } else {
2790                 int i;
2791
2792                 for (i = 0; i < sc->msix_cnt; ++i) {
2793                         lwkt_serialize_handler_disable(
2794                             sc->msix_data[i].msix_serialize);
2795                 }
2796         }
2797 }
2798
2799 /*
2800  * Bit of a misnomer, what this really means is
2801  * to enable OS management of the system... aka
2802  * to disable special hardware management features
2803  */
2804 static void
2805 igb_get_mgmt(struct igb_softc *sc)
2806 {
2807         if (sc->flags & IGB_FLAG_HAS_MGMT) {
2808                 int manc2h = E1000_READ_REG(&sc->hw, E1000_MANC2H);
2809                 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
2810
2811                 /* disable hardware interception of ARP */
2812                 manc &= ~E1000_MANC_ARP_EN;
2813
2814                 /* enable receiving management packets to the host */
2815                 manc |= E1000_MANC_EN_MNG2HOST;
2816                 manc2h |= 1 << 5; /* Mng Port 623 */
2817                 manc2h |= 1 << 6; /* Mng Port 664 */
2818                 E1000_WRITE_REG(&sc->hw, E1000_MANC2H, manc2h);
2819                 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
2820         }
2821 }
2822
2823 /*
2824  * Give control back to hardware management controller
2825  * if there is one.
2826  */
2827 static void
2828 igb_rel_mgmt(struct igb_softc *sc)
2829 {
2830         if (sc->flags & IGB_FLAG_HAS_MGMT) {
2831                 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
2832
2833                 /* Re-enable hardware interception of ARP */
2834                 manc |= E1000_MANC_ARP_EN;
2835                 manc &= ~E1000_MANC_EN_MNG2HOST;
2836
2837                 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
2838         }
2839 }
2840
2841 /*
2842  * Sets CTRL_EXT:DRV_LOAD bit.
2843  *
2844  * For ASF and Pass Through versions of f/w this means that
2845  * the driver is loaded.
2846  */
2847 static void
2848 igb_get_hw_control(struct igb_softc *sc)
2849 {
2850         uint32_t ctrl_ext;
2851
2852         if (sc->vf_ifp)
2853                 return;
2854
2855         /* Let firmware know the driver has taken over */
2856         ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
2857         E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
2858             ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2859 }
2860
2861 /*
2862  * Resets CTRL_EXT:DRV_LOAD bit.
2863  *
2864  * For ASF and Pass Through versions of f/w this means that the
2865  * driver is no longer loaded.
2866  */
2867 static void
2868 igb_rel_hw_control(struct igb_softc *sc)
2869 {
2870         uint32_t ctrl_ext;
2871
2872         if (sc->vf_ifp)
2873                 return;
2874
2875         /* Let firmware taken over control of h/w */
2876         ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
2877         E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
2878             ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2879 }
2880
2881 static int
2882 igb_is_valid_ether_addr(const uint8_t *addr)
2883 {
2884         uint8_t zero_addr[ETHER_ADDR_LEN] = { 0, 0, 0, 0, 0, 0 };
2885
2886         if ((addr[0] & 1) || !bcmp(addr, zero_addr, ETHER_ADDR_LEN))
2887                 return FALSE;
2888         return TRUE;
2889 }
2890
2891 /*
2892  * Enable PCI Wake On Lan capability
2893  */
2894 static void
2895 igb_enable_wol(device_t dev)
2896 {
2897         uint16_t cap, status;
2898         uint8_t id;
2899
2900         /* First find the capabilities pointer*/
2901         cap = pci_read_config(dev, PCIR_CAP_PTR, 2);
2902
2903         /* Read the PM Capabilities */
2904         id = pci_read_config(dev, cap, 1);
2905         if (id != PCIY_PMG)     /* Something wrong */
2906                 return;
2907
2908         /*
2909          * OK, we have the power capabilities,
2910          * so now get the status register
2911          */
2912         cap += PCIR_POWER_STATUS;
2913         status = pci_read_config(dev, cap, 2);
2914         status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
2915         pci_write_config(dev, cap, status, 2);
2916 }
2917
2918 static void
2919 igb_update_stats_counters(struct igb_softc *sc)
2920 {
2921         struct e1000_hw *hw = &sc->hw;
2922         struct e1000_hw_stats *stats;
2923         struct ifnet *ifp = &sc->arpcom.ac_if;
2924
2925         /*
2926          * The virtual function adapter has only a
2927          * small controlled set of stats, do only
2928          * those and return.
2929          */
2930         if (sc->vf_ifp) {
2931                 igb_update_vf_stats_counters(sc);
2932                 return;
2933         }
2934         stats = sc->stats;
2935
2936         if (sc->hw.phy.media_type == e1000_media_type_copper ||
2937             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
2938                 stats->symerrs +=
2939                     E1000_READ_REG(hw,E1000_SYMERRS);
2940                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
2941         }
2942
2943         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
2944         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
2945         stats->scc += E1000_READ_REG(hw, E1000_SCC);
2946         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
2947
2948         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
2949         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
2950         stats->colc += E1000_READ_REG(hw, E1000_COLC);
2951         stats->dc += E1000_READ_REG(hw, E1000_DC);
2952         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
2953         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
2954         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
2955
2956         /*
2957          * For watchdog management we need to know if we have been
2958          * paused during the last interval, so capture that here.
2959          */
2960         sc->pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
2961         stats->xoffrxc += sc->pause_frames;
2962         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
2963         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
2964         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
2965         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
2966         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
2967         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
2968         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
2969         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
2970         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
2971         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
2972         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
2973         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
2974
2975         /* For the 64-bit byte counters the low dword must be read first. */
2976         /* Both registers clear on the read of the high dword */
2977
2978         stats->gorc += E1000_READ_REG(hw, E1000_GORCL) +
2979             ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
2980         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL) +
2981             ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
2982
2983         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
2984         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
2985         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
2986         stats->roc += E1000_READ_REG(hw, E1000_ROC);
2987         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
2988
2989         stats->tor += E1000_READ_REG(hw, E1000_TORH);
2990         stats->tot += E1000_READ_REG(hw, E1000_TOTH);
2991
2992         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
2993         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
2994         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
2995         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
2996         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
2997         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
2998         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
2999         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
3000         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
3001         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
3002
3003         /* Interrupt Counts */
3004
3005         stats->iac += E1000_READ_REG(hw, E1000_IAC);
3006         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
3007         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
3008         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
3009         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
3010         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
3011         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
3012         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
3013         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
3014
3015         /* Host to Card Statistics */
3016
3017         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
3018         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
3019         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
3020         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
3021         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
3022         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
3023         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
3024         stats->hgorc += (E1000_READ_REG(hw, E1000_HGORCL) +
3025             ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32));
3026         stats->hgotc += (E1000_READ_REG(hw, E1000_HGOTCL) +
3027             ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32));
3028         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
3029         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
3030         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
3031
3032         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
3033         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
3034         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
3035         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
3036         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
3037         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
3038
3039         IFNET_STAT_SET(ifp, collisions, stats->colc);
3040
3041         /* Rx Errors */
3042         IFNET_STAT_SET(ifp, ierrors,
3043             stats->rxerrc + stats->crcerrs + stats->algnerrc +
3044             stats->ruc + stats->roc + stats->mpc + stats->cexterr);
3045
3046         /* Tx Errors */
3047         IFNET_STAT_SET(ifp, oerrors,
3048             stats->ecol + stats->latecol + sc->watchdog_events);
3049
3050         /* Driver specific counters */
3051         sc->device_control = E1000_READ_REG(hw, E1000_CTRL);
3052         sc->rx_control = E1000_READ_REG(hw, E1000_RCTL);
3053         sc->int_mask = E1000_READ_REG(hw, E1000_IMS);
3054         sc->eint_mask = E1000_READ_REG(hw, E1000_EIMS);
3055         sc->packet_buf_alloc_tx =
3056             ((E1000_READ_REG(hw, E1000_PBA) & 0xffff0000) >> 16);
3057         sc->packet_buf_alloc_rx =
3058             (E1000_READ_REG(hw, E1000_PBA) & 0xffff);
3059 }
3060
3061 static void
3062 igb_vf_init_stats(struct igb_softc *sc)
3063 {
3064         struct e1000_hw *hw = &sc->hw;
3065         struct e1000_vf_stats *stats;
3066
3067         stats = sc->stats;
3068         stats->last_gprc = E1000_READ_REG(hw, E1000_VFGPRC);
3069         stats->last_gorc = E1000_READ_REG(hw, E1000_VFGORC);
3070         stats->last_gptc = E1000_READ_REG(hw, E1000_VFGPTC);
3071         stats->last_gotc = E1000_READ_REG(hw, E1000_VFGOTC);
3072         stats->last_mprc = E1000_READ_REG(hw, E1000_VFMPRC);
3073 }
3074
3075 static void
3076 igb_update_vf_stats_counters(struct igb_softc *sc)
3077 {
3078         struct e1000_hw *hw = &sc->hw;
3079         struct e1000_vf_stats *stats;
3080
3081         if (sc->link_speed == 0)
3082                 return;
3083
3084         stats = sc->stats;
3085         UPDATE_VF_REG(E1000_VFGPRC, stats->last_gprc, stats->gprc);
3086         UPDATE_VF_REG(E1000_VFGORC, stats->last_gorc, stats->gorc);
3087         UPDATE_VF_REG(E1000_VFGPTC, stats->last_gptc, stats->gptc);
3088         UPDATE_VF_REG(E1000_VFGOTC, stats->last_gotc, stats->gotc);
3089         UPDATE_VF_REG(E1000_VFMPRC, stats->last_mprc, stats->mprc);
3090 }
3091
3092 #ifdef IFPOLL_ENABLE
3093
3094 static void
3095 igb_npoll_status(struct ifnet *ifp)
3096 {
3097         struct igb_softc *sc = ifp->if_softc;
3098         uint32_t reg_icr;
3099
3100         ASSERT_SERIALIZED(&sc->main_serialize);
3101
3102         reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
3103         if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3104                 sc->hw.mac.get_link_status = 1;
3105                 igb_update_link_status(sc);
3106         }
3107 }
3108
3109 static void
3110 igb_npoll_tx(struct ifnet *ifp, void *arg, int cycle __unused)
3111 {
3112         struct igb_tx_ring *txr = arg;
3113
3114         ASSERT_SERIALIZED(&txr->tx_serialize);
3115
3116         igb_txeof(txr);
3117         if (!ifsq_is_empty(txr->ifsq))
3118                 ifsq_devstart(txr->ifsq);
3119 }
3120
3121 static void
3122 igb_npoll_rx(struct ifnet *ifp __unused, void *arg, int cycle)
3123 {
3124         struct igb_rx_ring *rxr = arg;
3125
3126         ASSERT_SERIALIZED(&rxr->rx_serialize);
3127
3128         igb_rxeof(rxr, cycle);
3129 }
3130
3131 static void
3132 igb_npoll(struct ifnet *ifp, struct ifpoll_info *info)
3133 {
3134         struct igb_softc *sc = ifp->if_softc;
3135         int i, txr_cnt, rxr_cnt;
3136
3137         ASSERT_IFNET_SERIALIZED_ALL(ifp);
3138
3139         if (info) {
3140                 int off;
3141
3142                 info->ifpi_status.status_func = igb_npoll_status;
3143                 info->ifpi_status.serializer = &sc->main_serialize;
3144
3145                 txr_cnt = igb_get_txring_inuse(sc, TRUE);
3146                 off = sc->tx_npoll_off;
3147                 for (i = 0; i < txr_cnt; ++i) {
3148                         struct igb_tx_ring *txr = &sc->tx_rings[i];
3149                         int idx = i + off;
3150
3151                         KKASSERT(idx < ncpus2);
3152                         info->ifpi_tx[idx].poll_func = igb_npoll_tx;
3153                         info->ifpi_tx[idx].arg = txr;
3154                         info->ifpi_tx[idx].serializer = &txr->tx_serialize;
3155                         ifsq_set_cpuid(txr->ifsq, idx);
3156                 }
3157
3158                 rxr_cnt = igb_get_rxring_inuse(sc, TRUE);
3159                 off = sc->rx_npoll_off;
3160                 for (i = 0; i < rxr_cnt; ++i) {
3161                         struct igb_rx_ring *rxr = &sc->rx_rings[i];
3162                         int idx = i + off;
3163
3164                         KKASSERT(idx < ncpus2);
3165                         info->ifpi_rx[idx].poll_func = igb_npoll_rx;
3166                         info->ifpi_rx[idx].arg = rxr;
3167                         info->ifpi_rx[idx].serializer = &rxr->rx_serialize;
3168                 }
3169
3170                 if (ifp->if_flags & IFF_RUNNING) {
3171                         if (rxr_cnt == sc->rx_ring_inuse &&
3172                             txr_cnt == sc->tx_ring_inuse) {
3173                                 igb_set_timer_cpuid(sc, TRUE);
3174                                 igb_disable_intr(sc);
3175                         } else {
3176                                 igb_init(sc);
3177                         }
3178                 }
3179         } else {
3180                 for (i = 0; i < sc->tx_ring_cnt; ++i) {
3181                         struct igb_tx_ring *txr = &sc->tx_rings[i];
3182
3183                         ifsq_set_cpuid(txr->ifsq, txr->tx_intr_cpuid);
3184                 }
3185
3186                 if (ifp->if_flags & IFF_RUNNING) {
3187                         txr_cnt = igb_get_txring_inuse(sc, FALSE);
3188                         rxr_cnt = igb_get_rxring_inuse(sc, FALSE);
3189
3190                         if (rxr_cnt == sc->rx_ring_inuse &&
3191                             txr_cnt == sc->tx_ring_inuse) {
3192                                 igb_set_timer_cpuid(sc, FALSE);
3193                                 igb_enable_intr(sc);
3194                         } else {
3195                                 igb_init(sc);
3196                         }
3197                 }
3198         }
3199 }
3200
3201 #endif /* IFPOLL_ENABLE */
3202
3203 static void
3204 igb_intr(void *xsc)
3205 {
3206         struct igb_softc *sc = xsc;
3207         struct ifnet *ifp = &sc->arpcom.ac_if;
3208         uint32_t eicr;
3209
3210         ASSERT_SERIALIZED(&sc->main_serialize);
3211
3212         eicr = E1000_READ_REG(&sc->hw, E1000_EICR);
3213
3214         if (eicr == 0)
3215                 return;
3216
3217         if (ifp->if_flags & IFF_RUNNING) {
3218                 struct igb_tx_ring *txr = &sc->tx_rings[0];
3219                 int i;
3220
3221                 for (i = 0; i < sc->rx_ring_inuse; ++i) {
3222                         struct igb_rx_ring *rxr = &sc->rx_rings[i];
3223
3224                         if (eicr & rxr->rx_intr_mask) {
3225                                 lwkt_serialize_enter(&rxr->rx_serialize);
3226                                 igb_rxeof(rxr, -1);
3227                                 lwkt_serialize_exit(&rxr->rx_serialize);
3228                         }
3229                 }
3230
3231                 if (eicr & txr->tx_intr_mask) {
3232                         lwkt_serialize_enter(&txr->tx_serialize);
3233                         igb_txeof(txr);
3234                         if (!ifsq_is_empty(txr->ifsq))
3235                                 ifsq_devstart(txr->ifsq);
3236                         lwkt_serialize_exit(&txr->tx_serialize);
3237                 }
3238         }
3239
3240         if (eicr & E1000_EICR_OTHER) {
3241                 uint32_t icr = E1000_READ_REG(&sc->hw, E1000_ICR);
3242
3243                 /* Link status change */
3244                 if (icr & E1000_ICR_LSC) {
3245                         sc->hw.mac.get_link_status = 1;
3246                         igb_update_link_status(sc);
3247                 }
3248         }
3249
3250         /*
3251          * Reading EICR has the side effect to clear interrupt mask,
3252          * so all interrupts need to be enabled here.
3253          */
3254         E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->intr_mask);
3255 }
3256
3257 static void
3258 igb_intr_shared(void *xsc)
3259 {
3260         struct igb_softc *sc = xsc;
3261         struct ifnet *ifp = &sc->arpcom.ac_if;
3262         uint32_t reg_icr;
3263
3264         ASSERT_SERIALIZED(&sc->main_serialize);
3265
3266         reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
3267
3268         /* Hot eject?  */
3269         if (reg_icr == 0xffffffff)
3270                 return;
3271
3272         /* Definitely not our interrupt.  */
3273         if (reg_icr == 0x0)
3274                 return;
3275
3276         if ((reg_icr & E1000_ICR_INT_ASSERTED) == 0)
3277                 return;
3278
3279         if (ifp->if_flags & IFF_RUNNING) {
3280                 if (reg_icr &
3281                     (E1000_ICR_RXT0 | E1000_ICR_RXDMT0 | E1000_ICR_RXO)) {
3282                         int i;
3283
3284                         for (i = 0; i < sc->rx_ring_inuse; ++i) {
3285                                 struct igb_rx_ring *rxr = &sc->rx_rings[i];
3286
3287                                 lwkt_serialize_enter(&rxr->rx_serialize);
3288                                 igb_rxeof(rxr, -1);
3289                                 lwkt_serialize_exit(&rxr->rx_serialize);
3290                         }
3291                 }
3292
3293                 if (reg_icr & E1000_ICR_TXDW) {
3294                         struct igb_tx_ring *txr = &sc->tx_rings[0];
3295
3296                         lwkt_serialize_enter(&txr->tx_serialize);
3297                         igb_txeof(txr);
3298                         if (!ifsq_is_empty(txr->ifsq))
3299                                 ifsq_devstart(txr->ifsq);
3300                         lwkt_serialize_exit(&txr->tx_serialize);
3301                 }
3302         }
3303
3304         /* Link status change */
3305         if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3306                 sc->hw.mac.get_link_status = 1;
3307                 igb_update_link_status(sc);
3308         }
3309
3310         if (reg_icr & E1000_ICR_RXO)
3311                 sc->rx_overruns++;
3312 }
3313
3314 static int
3315 igb_encap(struct igb_tx_ring *txr, struct mbuf **m_headp,
3316     int *segs_used, int *idx)
3317 {
3318         bus_dma_segment_t segs[IGB_MAX_SCATTER];
3319         bus_dmamap_t map;
3320         struct igb_tx_buf *tx_buf, *tx_buf_mapped;
3321         union e1000_adv_tx_desc *txd = NULL;
3322         struct mbuf *m_head = *m_headp;
3323         uint32_t olinfo_status = 0, cmd_type_len = 0, cmd_rs = 0;
3324         int maxsegs, nsegs, i, j, error;
3325         uint32_t hdrlen = 0;
3326
3327         if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3328                 error = igb_tso_pullup(txr, m_headp);
3329                 if (error)
3330                         return error;
3331                 m_head = *m_headp;
3332         }
3333
3334         /* Set basic descriptor constants */
3335         cmd_type_len |= E1000_ADVTXD_DTYP_DATA;
3336         cmd_type_len |= E1000_ADVTXD_DCMD_IFCS | E1000_ADVTXD_DCMD_DEXT;
3337         if (m_head->m_flags & M_VLANTAG)
3338                 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
3339
3340         /*
3341          * Map the packet for DMA.
3342          */
3343         tx_buf = &txr->tx_buf[txr->next_avail_desc];
3344         tx_buf_mapped = tx_buf;
3345         map = tx_buf->map;
3346
3347         maxsegs = txr->tx_avail - IGB_TX_RESERVED;
3348         KASSERT(maxsegs >= txr->spare_desc, ("not enough spare TX desc\n"));
3349         if (maxsegs > IGB_MAX_SCATTER)
3350                 maxsegs = IGB_MAX_SCATTER;
3351
3352         error = bus_dmamap_load_mbuf_defrag(txr->tx_tag, map, m_headp,
3353             segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
3354         if (error) {
3355                 if (error == ENOBUFS)
3356                         txr->sc->mbuf_defrag_failed++;
3357                 else
3358                         txr->sc->no_tx_dma_setup++;
3359
3360                 m_freem(*m_headp);
3361                 *m_headp = NULL;
3362                 return error;
3363         }
3364         bus_dmamap_sync(txr->tx_tag, map, BUS_DMASYNC_PREWRITE);
3365
3366         m_head = *m_headp;
3367
3368         /*
3369          * Set up the TX context descriptor, if any hardware offloading is
3370          * needed.  This includes CSUM, VLAN, and TSO.  It will consume one
3371          * TX descriptor.
3372          *
3373          * Unlike these chips' predecessors (em/emx), TX context descriptor
3374          * will _not_ interfere TX data fetching pipelining.
3375          */
3376         if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3377                 igb_tso_ctx(txr, m_head, &hdrlen);
3378                 cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
3379                 olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
3380                 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3381                 txr->tx_nsegs++;
3382                 (*segs_used)++;
3383         } else if (igb_txcsum_ctx(txr, m_head)) {
3384                 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
3385                         olinfo_status |= (E1000_TXD_POPTS_IXSM << 8);
3386                 if (m_head->m_pkthdr.csum_flags & (CSUM_UDP | CSUM_TCP))
3387                         olinfo_status |= (E1000_TXD_POPTS_TXSM << 8);
3388                 txr->tx_nsegs++;
3389                 (*segs_used)++;
3390         }
3391
3392         *segs_used += nsegs;
3393         txr->tx_nsegs += nsegs;
3394         if (txr->tx_nsegs >= txr->intr_nsegs) {
3395                 /*
3396                  * Report Status (RS) is turned on every intr_nsegs
3397                  * descriptors (roughly).
3398                  */
3399                 txr->tx_nsegs = 0;
3400                 cmd_rs = E1000_ADVTXD_DCMD_RS;
3401         }
3402
3403         /* Calculate payload length */
3404         olinfo_status |= ((m_head->m_pkthdr.len - hdrlen)
3405             << E1000_ADVTXD_PAYLEN_SHIFT);
3406
3407         /*
3408          * 82575 needs the TX context index added; the queue
3409          * index is used as TX context index here.
3410          */
3411         if (txr->sc->hw.mac.type == e1000_82575)
3412                 olinfo_status |= txr->me << 4;
3413
3414         /* Set up our transmit descriptors */
3415         i = txr->next_avail_desc;
3416         for (j = 0; j < nsegs; j++) {
3417                 bus_size_t seg_len;
3418                 bus_addr_t seg_addr;
3419
3420                 tx_buf = &txr->tx_buf[i];
3421                 txd = (union e1000_adv_tx_desc *)&txr->tx_base[i];
3422                 seg_addr = segs[j].ds_addr;
3423                 seg_len = segs[j].ds_len;
3424
3425                 txd->read.buffer_addr = htole64(seg_addr);
3426                 txd->read.cmd_type_len = htole32(cmd_type_len | seg_len);
3427                 txd->read.olinfo_status = htole32(olinfo_status);
3428                 if (++i == txr->num_tx_desc)
3429                         i = 0;
3430                 tx_buf->m_head = NULL;
3431         }
3432
3433         KASSERT(txr->tx_avail > nsegs, ("invalid avail TX desc\n"));
3434         txr->next_avail_desc = i;
3435         txr->tx_avail -= nsegs;
3436
3437         tx_buf->m_head = m_head;
3438         tx_buf_mapped->map = tx_buf->map;
3439         tx_buf->map = map;
3440
3441         /*
3442          * Last Descriptor of Packet needs End Of Packet (EOP)
3443          */
3444         txd->read.cmd_type_len |= htole32(E1000_ADVTXD_DCMD_EOP | cmd_rs);
3445
3446         /*
3447          * Defer TDT updating, until enough descrptors are setup
3448          */
3449         *idx = i;
3450 #ifdef IGB_TSS_DEBUG
3451         ++txr->tx_packets;
3452 #endif
3453
3454         return 0;
3455 }
3456
3457 static void
3458 igb_start(struct ifnet *ifp, struct ifaltq_subque *ifsq)
3459 {
3460         struct igb_softc *sc = ifp->if_softc;
3461         struct igb_tx_ring *txr = ifsq_get_priv(ifsq);
3462         struct mbuf *m_head;
3463         int idx = -1, nsegs = 0;
3464
3465         KKASSERT(txr->ifsq == ifsq);
3466         ASSERT_SERIALIZED(&txr->tx_serialize);
3467
3468         if ((ifp->if_flags & IFF_RUNNING) == 0 || ifsq_is_oactive(ifsq))
3469                 return;
3470
3471         if (!sc->link_active || (txr->tx_flags & IGB_TXFLAG_ENABLED) == 0) {
3472                 ifsq_purge(ifsq);
3473                 return;
3474         }
3475
3476         if (!IGB_IS_NOT_OACTIVE(txr))
3477                 igb_txeof(txr);
3478
3479         while (!ifsq_is_empty(ifsq)) {
3480                 if (IGB_IS_OACTIVE(txr)) {
3481                         ifsq_set_oactive(ifsq);
3482                         /* Set watchdog on */
3483                         txr->tx_watchdog.wd_timer = 5;
3484                         break;
3485                 }
3486
3487                 m_head = ifsq_dequeue(ifsq, NULL);
3488                 if (m_head == NULL)
3489                         break;
3490
3491                 if (igb_encap(txr, &m_head, &nsegs, &idx)) {
3492                         IFNET_STAT_INC(ifp, oerrors, 1);
3493                         continue;
3494                 }
3495
3496                 if (nsegs >= txr->wreg_nsegs) {
3497                         E1000_WRITE_REG(&txr->sc->hw, E1000_TDT(txr->me), idx);
3498                         idx = -1;
3499                         nsegs = 0;
3500                 }
3501
3502                 /* Send a copy of the frame to the BPF listener */
3503                 ETHER_BPF_MTAP(ifp, m_head);
3504         }
3505         if (idx >= 0)
3506                 E1000_WRITE_REG(&txr->sc->hw, E1000_TDT(txr->me), idx);
3507 }
3508
3509 static void
3510 igb_watchdog(struct ifaltq_subque *ifsq)
3511 {
3512         struct igb_tx_ring *txr = ifsq_get_priv(ifsq);
3513         struct ifnet *ifp = ifsq_get_ifp(ifsq);
3514         struct igb_softc *sc = ifp->if_softc;
3515         int i;
3516
3517         KKASSERT(txr->ifsq == ifsq);
3518         ASSERT_IFNET_SERIALIZED_ALL(ifp);
3519
3520         /*
3521          * If flow control has paused us since last checking
3522          * it invalidates the watchdog timing, so dont run it.
3523          */
3524         if (sc->pause_frames) {
3525                 sc->pause_frames = 0;
3526                 txr->tx_watchdog.wd_timer = 5;
3527                 return;
3528         }
3529
3530         if_printf(ifp, "Watchdog timeout -- resetting\n");
3531         if_printf(ifp, "Queue(%d) tdh = %d, hw tdt = %d\n", txr->me,
3532             E1000_READ_REG(&sc->hw, E1000_TDH(txr->me)),
3533             E1000_READ_REG(&sc->hw, E1000_TDT(txr->me)));
3534         if_printf(ifp, "TX(%d) desc avail = %d, "
3535             "Next TX to Clean = %d\n",
3536             txr->me, txr->tx_avail, txr->next_to_clean);
3537
3538         IFNET_STAT_INC(ifp, oerrors, 1);
3539         sc->watchdog_events++;
3540
3541         igb_init(sc);
3542         for (i = 0; i < sc->tx_ring_inuse; ++i)
3543                 ifsq_devstart_sched(sc->tx_rings[i].ifsq);
3544 }
3545
3546 static void
3547 igb_set_eitr(struct igb_softc *sc, int idx, int rate)
3548 {
3549         uint32_t eitr = 0;
3550
3551         if (rate > 0) {
3552                 if (sc->hw.mac.type == e1000_82575) {
3553                         eitr = 1000000000 / 256 / rate;
3554                         /*
3555                          * NOTE:
3556                          * Document is wrong on the 2 bits left shift
3557                          */
3558                 } else {
3559                         eitr = 1000000 / rate;
3560                         eitr <<= IGB_EITR_INTVL_SHIFT;
3561                 }
3562
3563                 if (eitr == 0) {
3564                         /* Don't disable it */
3565                         eitr = 1 << IGB_EITR_INTVL_SHIFT;
3566                 } else if (eitr > IGB_EITR_INTVL_MASK) {
3567                         /* Don't allow it to be too large */
3568                         eitr = IGB_EITR_INTVL_MASK;
3569                 }
3570         }
3571         if (sc->hw.mac.type == e1000_82575)
3572                 eitr |= eitr << 16;
3573         else
3574                 eitr |= E1000_EITR_CNT_IGNR;
3575         E1000_WRITE_REG(&sc->hw, E1000_EITR(idx), eitr);
3576 }
3577
3578 static int
3579 igb_sysctl_intr_rate(SYSCTL_HANDLER_ARGS)
3580 {
3581         struct igb_softc *sc = (void *)arg1;
3582         struct ifnet *ifp = &sc->arpcom.ac_if;
3583         int error, intr_rate;
3584
3585         intr_rate = sc->intr_rate;
3586         error = sysctl_handle_int(oidp, &intr_rate, 0, req);
3587         if (error || req->newptr == NULL)
3588                 return error;
3589         if (intr_rate < 0)
3590                 return EINVAL;
3591
3592         ifnet_serialize_all(ifp);
3593
3594         sc->intr_rate = intr_rate;
3595         if (ifp->if_flags & IFF_RUNNING)
3596                 igb_set_eitr(sc, 0, sc->intr_rate);
3597
3598         if (bootverbose)
3599                 if_printf(ifp, "interrupt rate set to %d/sec\n", sc->intr_rate);
3600
3601         ifnet_deserialize_all(ifp);
3602
3603         return 0;
3604 }
3605
3606 static int
3607 igb_sysctl_msix_rate(SYSCTL_HANDLER_ARGS)
3608 {
3609         struct igb_msix_data *msix = (void *)arg1;
3610         struct igb_softc *sc = msix->msix_sc;
3611         struct ifnet *ifp = &sc->arpcom.ac_if;
3612         int error, msix_rate;
3613
3614         msix_rate = msix->msix_rate;
3615         error = sysctl_handle_int(oidp, &msix_rate, 0, req);
3616         if (error || req->newptr == NULL)
3617                 return error;
3618         if (msix_rate < 0)
3619                 return EINVAL;
3620
3621         lwkt_serialize_enter(msix->msix_serialize);
3622
3623         msix->msix_rate = msix_rate;
3624         if (ifp->if_flags & IFF_RUNNING)
3625                 igb_set_eitr(sc, msix->msix_vector, msix->msix_rate);
3626
3627         if (bootverbose) {
3628                 if_printf(ifp, "%s set to %d/sec\n", msix->msix_rate_desc,
3629                     msix->msix_rate);
3630         }
3631
3632         lwkt_serialize_exit(msix->msix_serialize);
3633
3634         return 0;
3635 }
3636
3637 static int
3638 igb_sysctl_tx_intr_nsegs(SYSCTL_HANDLER_ARGS)
3639 {
3640         struct igb_softc *sc = (void *)arg1;
3641         struct ifnet *ifp = &sc->arpcom.ac_if;
3642         struct igb_tx_ring *txr = &sc->tx_rings[0];
3643         int error, nsegs;
3644
3645         nsegs = txr->intr_nsegs;
3646         error = sysctl_handle_int(oidp, &nsegs, 0, req);
3647         if (error || req->newptr == NULL)
3648                 return error;
3649         if (nsegs <= 0)
3650                 return EINVAL;
3651
3652         ifnet_serialize_all(ifp);
3653
3654         if (nsegs >= txr->num_tx_desc - txr->oact_lo_desc ||
3655             nsegs >= txr->oact_hi_desc - IGB_MAX_SCATTER) {
3656                 error = EINVAL;
3657         } else {
3658                 int i;
3659
3660                 error = 0;
3661                 for (i = 0; i < sc->tx_ring_cnt; ++i)
3662                         sc->tx_rings[i].intr_nsegs = nsegs;
3663         }
3664
3665         ifnet_deserialize_all(ifp);
3666
3667         return error;
3668 }
3669
3670 static int
3671 igb_sysctl_rx_wreg_nsegs(SYSCTL_HANDLER_ARGS)
3672 {
3673         struct igb_softc *sc = (void *)arg1;
3674         struct ifnet *ifp = &sc->arpcom.ac_if;
3675         int error, nsegs, i;
3676
3677         nsegs = sc->rx_rings[0].wreg_nsegs;
3678         error = sysctl_handle_int(oidp, &nsegs, 0, req);
3679         if (error || req->newptr == NULL)
3680                 return error;
3681
3682         ifnet_serialize_all(ifp);
3683         for (i = 0; i < sc->rx_ring_cnt; ++i)
3684                 sc->rx_rings[i].wreg_nsegs =nsegs;
3685         ifnet_deserialize_all(ifp);
3686
3687         return 0;
3688 }
3689
3690 static int
3691 igb_sysctl_tx_wreg_nsegs(SYSCTL_HANDLER_ARGS)
3692 {
3693         struct igb_softc *sc = (void *)arg1;
3694         struct ifnet *ifp = &sc->arpcom.ac_if;
3695         int error, nsegs, i;
3696
3697         nsegs = sc->tx_rings[0].wreg_nsegs;
3698         error = sysctl_handle_int(oidp, &nsegs, 0, req);
3699         if (error || req->newptr == NULL)
3700                 return error;
3701
3702         ifnet_serialize_all(ifp);
3703         for (i = 0; i < sc->tx_ring_cnt; ++i)
3704                 sc->tx_rings[i].wreg_nsegs =nsegs;
3705         ifnet_deserialize_all(ifp);
3706
3707         return 0;
3708 }
3709
3710 #ifdef IFPOLL_ENABLE
3711
3712 static int
3713 igb_sysctl_npoll_rxoff(SYSCTL_HANDLER_ARGS)
3714 {
3715         struct igb_softc *sc = (void *)arg1;
3716         struct ifnet *ifp = &sc->arpcom.ac_if;
3717         int error, off;
3718
3719         off = sc->rx_npoll_off;
3720         error = sysctl_handle_int(oidp, &off, 0, req);
3721         if (error || req->newptr == NULL)
3722                 return error;
3723         if (off < 0)
3724                 return EINVAL;
3725
3726         ifnet_serialize_all(ifp);
3727         if (off >= ncpus2 || off % sc->rx_ring_cnt != 0) {
3728                 error = EINVAL;
3729         } else {
3730                 error = 0;
3731                 sc->rx_npoll_off = off;
3732         }
3733         ifnet_deserialize_all(ifp);
3734
3735         return error;
3736 }
3737
3738 static int
3739 igb_sysctl_npoll_txoff(SYSCTL_HANDLER_ARGS)
3740 {
3741         struct igb_softc *sc = (void *)arg1;
3742         struct ifnet *ifp = &sc->arpcom.ac_if;
3743         int error, off;
3744
3745         off = sc->tx_npoll_off;
3746         error = sysctl_handle_int(oidp, &off, 0, req);
3747         if (error || req->newptr == NULL)
3748                 return error;
3749         if (off < 0)
3750                 return EINVAL;
3751
3752         ifnet_serialize_all(ifp);
3753         if (off >= ncpus2 || off % sc->tx_ring_cnt != 0) {
3754                 error = EINVAL;
3755         } else {
3756                 error = 0;
3757                 sc->tx_npoll_off = off;
3758         }
3759         ifnet_deserialize_all(ifp);
3760
3761         return error;
3762 }
3763
3764 #endif  /* IFPOLL_ENABLE */
3765
3766 static void
3767 igb_init_intr(struct igb_softc *sc)
3768 {
3769         igb_set_intr_mask(sc);
3770
3771         if ((sc->flags & IGB_FLAG_SHARED_INTR) == 0)
3772                 igb_init_unshared_intr(sc);
3773
3774         if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
3775                 igb_set_eitr(sc, 0, sc->intr_rate);
3776         } else {
3777                 int i;
3778
3779                 for (i = 0; i < sc->msix_cnt; ++i)
3780                         igb_set_eitr(sc, i, sc->msix_data[i].msix_rate);
3781         }
3782 }
3783
3784 static void
3785 igb_init_unshared_intr(struct igb_softc *sc)
3786 {
3787         struct e1000_hw *hw = &sc->hw;
3788         const struct igb_rx_ring *rxr;
3789         const struct igb_tx_ring *txr;
3790         uint32_t ivar, index;
3791         int i;
3792
3793         /*
3794          * Enable extended mode
3795          */
3796         if (sc->hw.mac.type != e1000_82575) {
3797                 uint32_t gpie;
3798                 int ivar_max;
3799
3800                 gpie = E1000_GPIE_NSICR;
3801                 if (sc->intr_type == PCI_INTR_TYPE_MSIX) {
3802                         gpie |= E1000_GPIE_MSIX_MODE |
3803                             E1000_GPIE_EIAME |
3804                             E1000_GPIE_PBA;
3805                 }
3806                 E1000_WRITE_REG(hw, E1000_GPIE, gpie);
3807
3808                 /*
3809                  * Clear IVARs
3810                  */
3811                 switch (sc->hw.mac.type) {
3812                 case e1000_82576:
3813                         ivar_max = IGB_MAX_IVAR_82576;
3814                         break;
3815
3816                 case e1000_82580:
3817                         ivar_max = IGB_MAX_IVAR_82580;
3818                         break;
3819
3820                 case e1000_i350:
3821                         ivar_max = IGB_MAX_IVAR_I350;
3822                         break;
3823
3824                 case e1000_vfadapt:
3825                 case e1000_vfadapt_i350:
3826                         ivar_max = IGB_MAX_IVAR_VF;
3827                         break;
3828
3829                 case e1000_i210:
3830                         ivar_max = IGB_MAX_IVAR_I210;
3831                         break;
3832
3833                 case e1000_i211:
3834                         ivar_max = IGB_MAX_IVAR_I211;
3835                         break;
3836
3837                 default:
3838                         panic("unknown mac type %d\n", sc->hw.mac.type);
3839                 }
3840                 for (i = 0; i < ivar_max; ++i)
3841                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, i, 0);
3842                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, 0);
3843         } else {
3844                 uint32_t tmp;
3845
3846                 KASSERT(sc->intr_type != PCI_INTR_TYPE_MSIX,
3847                     ("82575 w/ MSI-X"));
3848                 tmp = E1000_READ_REG(hw, E1000_CTRL_EXT);
3849                 tmp |= E1000_CTRL_EXT_IRCA;
3850                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmp);
3851         }
3852
3853         /*
3854          * Map TX/RX interrupts to EICR
3855          */
3856         switch (sc->hw.mac.type) {
3857         case e1000_82580:
3858         case e1000_i350:
3859         case e1000_vfadapt:
3860         case e1000_vfadapt_i350:
3861         case e1000_i210:
3862         case e1000_i211:
3863                 /* RX entries */
3864                 for (i = 0; i < sc->rx_ring_inuse; ++i) {
3865                         rxr = &sc->rx_rings[i];
3866
3867                         index = i >> 1;
3868                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3869
3870                         if (i & 1) {
3871                                 ivar &= 0xff00ffff;
3872                                 ivar |=
3873                                 (rxr->rx_intr_bit | E1000_IVAR_VALID) << 16;
3874                         } else {
3875                                 ivar &= 0xffffff00;
3876                                 ivar |=
3877                                 (rxr->rx_intr_bit | E1000_IVAR_VALID);
3878                         }
3879                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3880                 }
3881                 /* TX entries */
3882                 for (i = 0; i < sc->tx_ring_inuse; ++i) {
3883                         txr = &sc->tx_rings[i];
3884
3885                         index = i >> 1;
3886                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3887
3888                         if (i & 1) {
3889                                 ivar &= 0x00ffffff;
3890                                 ivar |=
3891                                 (txr->tx_intr_bit | E1000_IVAR_VALID) << 24;
3892                         } else {
3893                                 ivar &= 0xffff00ff;
3894                                 ivar |=
3895                                 (txr->tx_intr_bit | E1000_IVAR_VALID) << 8;
3896                         }
3897                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3898                 }
3899                 if (sc->intr_type == PCI_INTR_TYPE_MSIX) {
3900                         ivar = (sc->sts_intr_bit | E1000_IVAR_VALID) << 8;
3901                         E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar);
3902                 }
3903                 break;
3904
3905         case e1000_82576:
3906                 /* RX entries */
3907                 for (i = 0; i < sc->rx_ring_inuse; ++i) {
3908                         rxr = &sc->rx_rings[i];
3909
3910                         index = i & 0x7; /* Each IVAR has two entries */
3911                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3912
3913                         if (i < 8) {
3914                                 ivar &= 0xffffff00;
3915                                 ivar |=
3916                                 (rxr->rx_intr_bit | E1000_IVAR_VALID);
3917                         } else {
3918                                 ivar &= 0xff00ffff;
3919                                 ivar |=
3920                                 (rxr->rx_intr_bit | E1000_IVAR_VALID) << 16;
3921                         }
3922                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3923                 }
3924                 /* TX entries */
3925                 for (i = 0; i < sc->tx_ring_inuse; ++i) {
3926                         txr = &sc->tx_rings[i];
3927
3928                         index = i & 0x7; /* Each IVAR has two entries */
3929                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3930
3931                         if (i < 8) {
3932                                 ivar &= 0xffff00ff;
3933                                 ivar |=
3934                                 (txr->tx_intr_bit | E1000_IVAR_VALID) << 8;
3935                         } else {
3936                                 ivar &= 0x00ffffff;
3937                                 ivar |=
3938                                 (txr->tx_intr_bit | E1000_IVAR_VALID) << 24;
3939                         }
3940                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3941                 }
3942                 if (sc->intr_type == PCI_INTR_TYPE_MSIX) {
3943                         ivar = (sc->sts_intr_bit | E1000_IVAR_VALID) << 8;
3944                         E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar);
3945                 }
3946                 break;
3947
3948         case e1000_82575:
3949                 /*
3950                  * Enable necessary interrupt bits.
3951                  *
3952                  * The name of the register is confusing; in addition to
3953                  * configuring the first vector of MSI-X, it also configures
3954                  * which bits of EICR could be set by the hardware even when
3955                  * MSI or line interrupt is used; it thus controls interrupt
3956                  * generation.  It MUST be configured explicitly; the default
3957                  * value mentioned in the datasheet is wrong: RX queue0 and
3958                  * TX queue0 are NOT enabled by default.
3959                  */
3960                 E1000_WRITE_REG(&sc->hw, E1000_MSIXBM(0), sc->intr_mask);
3961                 break;
3962
3963         default:
3964                 panic("unknown mac type %d\n", sc->hw.mac.type);
3965         }
3966 }
3967
3968 static int
3969 igb_setup_intr(struct igb_softc *sc)
3970 {
3971         int error;
3972
3973         if (sc->intr_type == PCI_INTR_TYPE_MSIX)
3974                 return igb_msix_setup(sc);
3975
3976         error = bus_setup_intr(sc->dev, sc->intr_res, INTR_MPSAFE,
3977             (sc->flags & IGB_FLAG_SHARED_INTR) ? igb_intr_shared : igb_intr,
3978             sc, &sc->intr_tag, &sc->main_serialize);
3979         if (error) {
3980                 device_printf(sc->dev, "Failed to register interrupt handler");
3981                 return error;
3982         }
3983         return 0;
3984 }
3985
3986 static void
3987 igb_set_txintr_mask(struct igb_tx_ring *txr, int *intr_bit0, int intr_bitmax)
3988 {
3989         if (txr->sc->hw.mac.type == e1000_82575) {
3990                 txr->tx_intr_bit = 0;   /* unused */
3991                 switch (txr->me) {
3992                 case 0:
3993                         txr->tx_intr_mask = E1000_EICR_TX_QUEUE0;
3994                         break;
3995                 case 1:
3996                         txr->tx_intr_mask = E1000_EICR_TX_QUEUE1;
3997                         break;
3998                 case 2:
3999                         txr->tx_intr_mask = E1000_EICR_TX_QUEUE2;
4000                         break;
4001                 case 3:
4002                         txr->tx_intr_mask = E1000_EICR_TX_QUEUE3;
4003                         break;
4004                 default:
4005                         panic("unsupported # of TX ring, %d\n", txr->me);
4006                 }
4007         } else {
4008                 int intr_bit = *intr_bit0;
4009
4010                 txr->tx_intr_bit = intr_bit % intr_bitmax;
4011                 txr->tx_intr_mask = 1 << txr->tx_intr_bit;
4012
4013                 *intr_bit0 = intr_bit + 1;
4014         }
4015 }
4016
4017 static void
4018 igb_set_rxintr_mask(struct igb_rx_ring *rxr, int *intr_bit0, int intr_bitmax)
4019 {
4020         if (rxr->sc->hw.mac.type == e1000_82575) {
4021                 rxr->rx_intr_bit = 0;   /* unused */
4022                 switch (rxr->me) {
4023                 case 0:
4024                         rxr->rx_intr_mask = E1000_EICR_RX_QUEUE0;
4025                         break;
4026                 case 1:
4027                         rxr->rx_intr_mask = E1000_EICR_RX_QUEUE1;
4028                         break;
4029                 case 2:
4030                         rxr->rx_intr_mask = E1000_EICR_RX_QUEUE2;
4031                         break;
4032                 case 3:
4033                         rxr->rx_intr_mask = E1000_EICR_RX_QUEUE3;
4034                         break;
4035                 default:
4036                         panic("unsupported # of RX ring, %d\n", rxr->me);
4037                 }
4038         } else {
4039                 int intr_bit = *intr_bit0;
4040
4041                 rxr->rx_intr_bit = intr_bit % intr_bitmax;
4042                 rxr->rx_intr_mask = 1 << rxr->rx_intr_bit;
4043
4044                 *intr_bit0 = intr_bit + 1;
4045         }
4046 }
4047
4048 static void
4049 igb_serialize(struct ifnet *ifp, enum ifnet_serialize slz)
4050 {
4051         struct igb_softc *sc = ifp->if_softc;
4052
4053         ifnet_serialize_array_enter(sc->serializes, sc->serialize_cnt, slz);
4054 }
4055
4056 static void
4057 igb_deserialize(struct ifnet *ifp, enum ifnet_serialize slz)
4058 {
4059         struct igb_softc *sc = ifp->if_softc;
4060
4061         ifnet_serialize_array_exit(sc->serializes, sc->serialize_cnt, slz);
4062 }
4063
4064 static int
4065 igb_tryserialize(struct ifnet *ifp, enum ifnet_serialize slz)
4066 {
4067         struct igb_softc *sc = ifp->if_softc;
4068
4069         return ifnet_serialize_array_try(sc->serializes, sc->serialize_cnt,
4070             slz);
4071 }
4072
4073 #ifdef INVARIANTS
4074
4075 static void
4076 igb_serialize_assert(struct ifnet *ifp, enum ifnet_serialize slz,
4077     boolean_t serialized)
4078 {
4079         struct igb_softc *sc = ifp->if_softc;
4080
4081         ifnet_serialize_array_assert(sc->serializes, sc->serialize_cnt,
4082             slz, serialized);
4083 }
4084
4085 #endif  /* INVARIANTS */
4086
4087 static void
4088 igb_set_intr_mask(struct igb_softc *sc)
4089 {
4090         int i;
4091
4092         sc->intr_mask = sc->sts_intr_mask;
4093         for (i = 0; i < sc->rx_ring_inuse; ++i)
4094                 sc->intr_mask |= sc->rx_rings[i].rx_intr_mask;
4095         for (i = 0; i < sc->tx_ring_inuse; ++i)
4096                 sc->intr_mask |= sc->tx_rings[i].tx_intr_mask;
4097         if (bootverbose) {
4098                 if_printf(&sc->arpcom.ac_if, "intr mask 0x%08x\n",
4099                     sc->intr_mask);
4100         }
4101 }
4102
4103 static int
4104 igb_alloc_intr(struct igb_softc *sc)
4105 {
4106         int i, intr_bit, intr_bitmax;
4107         u_int intr_flags;
4108
4109         igb_msix_try_alloc(sc);
4110         if (sc->intr_type == PCI_INTR_TYPE_MSIX)
4111                 goto done;
4112
4113         /*
4114          * Allocate MSI/legacy interrupt resource
4115          */
4116         sc->intr_type = pci_alloc_1intr(sc->dev, igb_msi_enable,
4117             &sc->intr_rid, &intr_flags);
4118
4119         if (sc->intr_type == PCI_INTR_TYPE_LEGACY) {
4120                 int unshared;
4121
4122                 unshared = device_getenv_int(sc->dev, "irq.unshared", 0);
4123                 if (!unshared) {
4124                         sc->flags |= IGB_FLAG_SHARED_INTR;
4125                         if (bootverbose)
4126                                 device_printf(sc->dev, "IRQ shared\n");
4127                 } else {
4128                         intr_flags &= ~RF_SHAREABLE;
4129                         if (bootverbose)
4130                                 device_printf(sc->dev, "IRQ unshared\n");
4131                 }
4132         }
4133
4134         sc->intr_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ,
4135             &sc->intr_rid, intr_flags);
4136         if (sc->intr_res == NULL) {
4137                 device_printf(sc->dev, "Unable to allocate bus resource: "
4138                     "interrupt\n");
4139                 return ENXIO;
4140         }
4141
4142         for (i = 0; i < sc->tx_ring_cnt; ++i)
4143                 sc->tx_rings[i].tx_intr_cpuid = rman_get_cpuid(sc->intr_res);
4144
4145         /*
4146          * Setup MSI/legacy interrupt mask
4147          */
4148         switch (sc->hw.mac.type) {
4149         case e1000_82575:
4150                 intr_bitmax = IGB_MAX_TXRXINT_82575;
4151                 break;
4152
4153         case e1000_82576:
4154                 intr_bitmax = IGB_MAX_TXRXINT_82576;
4155                 break;
4156
4157         case e1000_82580:
4158                 intr_bitmax = IGB_MAX_TXRXINT_82580;
4159                 break;
4160
4161         case e1000_i350:
4162                 intr_bitmax = IGB_MAX_TXRXINT_I350;
4163                 break;
4164
4165         case e1000_i210:
4166                 intr_bitmax = IGB_MAX_TXRXINT_I210;
4167                 break;
4168
4169         case e1000_i211:
4170                 intr_bitmax = IGB_MAX_TXRXINT_I211;
4171                 break;
4172
4173         default:
4174                 intr_bitmax = IGB_MIN_TXRXINT;
4175                 break;
4176         }
4177         intr_bit = 0;
4178         for (i = 0; i < sc->tx_ring_cnt; ++i)
4179                 igb_set_txintr_mask(&sc->tx_rings[i], &intr_bit, intr_bitmax);
4180         for (i = 0; i < sc->rx_ring_cnt; ++i)
4181                 igb_set_rxintr_mask(&sc->rx_rings[i], &intr_bit, intr_bitmax);
4182         sc->sts_intr_bit = 0;
4183         sc->sts_intr_mask = E1000_EICR_OTHER;
4184
4185         /* Initialize interrupt rate */
4186         sc->intr_rate = IGB_INTR_RATE;
4187 done:
4188         igb_set_ring_inuse(sc, FALSE);
4189         igb_set_intr_mask(sc);
4190         return 0;
4191 }
4192
4193 static void
4194 igb_free_intr(struct igb_softc *sc)
4195 {
4196         if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
4197                 if (sc->intr_res != NULL) {
4198                         bus_release_resource(sc->dev, SYS_RES_IRQ, sc->intr_rid,
4199                             sc->intr_res);
4200                 }
4201                 if (sc->intr_type == PCI_INTR_TYPE_MSI)
4202                         pci_release_msi(sc->dev);
4203         } else {
4204                 igb_msix_free(sc, TRUE);
4205         }
4206 }
4207
4208 static void
4209 igb_teardown_intr(struct igb_softc *sc)
4210 {
4211         if (sc->intr_type != PCI_INTR_TYPE_MSIX)
4212                 bus_teardown_intr(sc->dev, sc->intr_res, sc->intr_tag);
4213         else
4214                 igb_msix_teardown(sc, sc->msix_cnt);
4215 }
4216
4217 static void
4218 igb_msix_try_alloc(struct igb_softc *sc)
4219 {
4220         int msix_enable, msix_cnt, msix_cnt2, alloc_cnt;
4221         int i, x, error;
4222         int offset, offset_def;
4223         struct igb_msix_data *msix;
4224         boolean_t aggregate, setup = FALSE;
4225
4226         /*
4227          * Don't enable MSI-X on 82575, see:
4228          * 82575 specification update errata #25
4229          */
4230         if (sc->hw.mac.type == e1000_82575)
4231                 return;
4232
4233         /* Don't enable MSI-X on VF */
4234         if (sc->vf_ifp)
4235                 return;
4236
4237         msix_enable = device_getenv_int(sc->dev, "msix.enable",
4238             igb_msix_enable);
4239         if (!msix_enable)
4240                 return;
4241
4242         msix_cnt = pci_msix_count(sc->dev);
4243 #ifdef IGB_MSIX_DEBUG
4244         msix_cnt = device_getenv_int(sc->dev, "msix.count", msix_cnt);
4245 #endif
4246         if (msix_cnt <= 1) {
4247                 /* One MSI-X model does not make sense */
4248                 return;
4249         }
4250
4251         i = 0;
4252         while ((1 << (i + 1)) <= msix_cnt)
4253                 ++i;
4254         msix_cnt2 = 1 << i;
4255
4256         if (bootverbose) {
4257                 device_printf(sc->dev, "MSI-X count %d/%d\n",
4258                     msix_cnt2, msix_cnt);
4259         }
4260
4261         KKASSERT(msix_cnt2 <= msix_cnt);
4262         if (msix_cnt == msix_cnt2) {
4263                 /* We need at least one MSI-X for link status */
4264                 msix_cnt2 >>= 1;
4265                 if (msix_cnt2 <= 1) {
4266                         /* One MSI-X for RX/TX does not make sense */
4267                         device_printf(sc->dev, "not enough MSI-X for TX/RX, "
4268                             "MSI-X count %d/%d\n", msix_cnt2, msix_cnt);
4269                         return;
4270                 }
4271                 KKASSERT(msix_cnt > msix_cnt2);
4272
4273                 if (bootverbose) {
4274                         device_printf(sc->dev, "MSI-X count fixup %d/%d\n",
4275                             msix_cnt2, msix_cnt);
4276                 }
4277         }
4278
4279         sc->rx_ring_msix = sc->rx_ring_cnt;
4280         if (sc->rx_ring_msix > msix_cnt2)
4281                 sc->rx_ring_msix = msix_cnt2;
4282
4283         sc->tx_ring_msix = sc->tx_ring_cnt;
4284         if (sc->tx_ring_msix > msix_cnt2)
4285                 sc->tx_ring_msix = msix_cnt2;
4286
4287         if (msix_cnt >= sc->tx_ring_msix + sc->rx_ring_msix + 1) {
4288                 /*
4289                  * Independent TX/RX MSI-X
4290                  */
4291                 aggregate = FALSE;
4292                 if (bootverbose)
4293                         device_printf(sc->dev, "independent TX/RX MSI-X\n");
4294                 alloc_cnt = sc->tx_ring_msix + sc->rx_ring_msix;
4295         } else {
4296                 /*
4297                  * Aggregate TX/RX MSI-X
4298                  */
4299                 aggregate = TRUE;
4300                 if (bootverbose)
4301                         device_printf(sc->dev, "aggregate TX/RX MSI-X\n");
4302                 alloc_cnt = msix_cnt2;
4303                 if (alloc_cnt > ncpus2)
4304                         alloc_cnt = ncpus2;
4305                 if (sc->rx_ring_msix > alloc_cnt)
4306                         sc->rx_ring_msix = alloc_cnt;
4307                 if (sc->tx_ring_msix > alloc_cnt)
4308                         sc->tx_ring_msix = alloc_cnt;
4309         }
4310         ++alloc_cnt;    /* For link status */
4311
4312         if (bootverbose) {
4313                 device_printf(sc->dev, "MSI-X alloc %d, "
4314                     "RX ring %d, TX ring %d\n", alloc_cnt,
4315                     sc->rx_ring_msix, sc->tx_ring_msix);
4316         }
4317
4318         sc->msix_mem_rid = PCIR_BAR(IGB_MSIX_BAR);
4319         sc->msix_mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
4320             &sc->msix_mem_rid, RF_ACTIVE);
4321         if (sc->msix_mem_res == NULL) {
4322                 device_printf(sc->dev, "Unable to map MSI-X table\n");
4323                 return;
4324         }
4325
4326         sc->msix_cnt = alloc_cnt;
4327         sc->msix_data = kmalloc_cachealign(
4328             sizeof(struct igb_msix_data) * sc->msix_cnt,
4329             M_DEVBUF, M_WAITOK | M_ZERO);
4330         for (x = 0; x < sc->msix_cnt; ++x) {
4331                 msix = &sc->msix_data[x];
4332
4333                 lwkt_serialize_init(&msix->msix_serialize0);
4334                 msix->msix_sc = sc;
4335                 msix->msix_rid = -1;
4336                 msix->msix_vector = x;
4337                 msix->msix_mask = 1 << msix->msix_vector;
4338                 msix->msix_rate = IGB_INTR_RATE;
4339         }
4340
4341         x = 0;
4342         if (!aggregate) {
4343                 /*
4344                  * RX rings
4345                  */
4346                 if (sc->rx_ring_msix == ncpus2) {
4347                         offset = 0;
4348                 } else {
4349                         offset_def = (sc->rx_ring_msix *
4350                             device_get_unit(sc->dev)) % ncpus2;
4351
4352                         offset = device_getenv_int(sc->dev,
4353                             "msix.rxoff", offset_def);
4354                         if (offset >= ncpus2 ||
4355                             offset % sc->rx_ring_msix != 0) {
4356                                 device_printf(sc->dev,
4357                                     "invalid msix.rxoff %d, use %d\n",
4358                                     offset, offset_def);
4359                                 offset = offset_def;
4360                         }
4361                 }
4362                 igb_msix_rx_conf(sc, 0, &x, offset);
4363
4364                 /*
4365                  * TX rings
4366                  */
4367                 if (sc->tx_ring_msix == ncpus2) {
4368                         offset = 0;
4369                 } else {
4370                         offset_def = (sc->tx_ring_msix *
4371                             device_get_unit(sc->dev)) % ncpus2;
4372
4373                         offset = device_getenv_int(sc->dev,
4374                             "msix.txoff", offset_def);
4375                         if (offset >= ncpus2 ||
4376                             offset % sc->tx_ring_msix != 0) {
4377                                 device_printf(sc->dev,
4378                                     "invalid msix.txoff %d, use %d\n",
4379                                     offset, offset_def);
4380                                 offset = offset_def;
4381                         }
4382                 }
4383                 igb_msix_tx_conf(sc, 0, &x, offset);
4384         } else {
4385                 int ring_agg, ring_max;
4386
4387                 ring_agg = sc->rx_ring_msix;
4388                 if (ring_agg > sc->tx_ring_msix)
4389                         ring_agg = sc->tx_ring_msix;
4390
4391                 ring_max = sc->rx_ring_msix;
4392                 if (ring_max < sc->tx_ring_msix)
4393                         ring_max = sc->tx_ring_msix;
4394
4395                 if (ring_max == ncpus2) {
4396                         offset = 0;
4397                 } else {
4398                         offset_def = (ring_max * device_get_unit(sc->dev)) %
4399                             ncpus2;
4400
4401                         offset = device_getenv_int(sc->dev, "msix.off",
4402                             offset_def);
4403                         if (offset >= ncpus2 || offset % ring_max != 0) {
4404                                 device_printf(sc->dev,
4405                                     "invalid msix.off %d, use %d\n",
4406                                     offset, offset_def);
4407                                 offset = offset_def;
4408                         }
4409                 }
4410
4411                 for (i = 0; i < ring_agg; ++i) {
4412                         struct igb_tx_ring *txr = &sc->tx_rings[i];
4413                         struct igb_rx_ring *rxr = &sc->rx_rings[i];
4414
4415                         KKASSERT(x < sc->msix_cnt);
4416                         msix = &sc->msix_data[x++];
4417
4418                         txr->tx_intr_bit = msix->msix_vector;
4419                         txr->tx_intr_mask = msix->msix_mask;
4420                         rxr->rx_intr_bit = msix->msix_vector;
4421                         rxr->rx_intr_mask = msix->msix_mask;
4422
4423                         msix->msix_serialize = &msix->msix_serialize0;
4424                         msix->msix_func = igb_msix_rxtx;
4425                         msix->msix_arg = msix;
4426                         msix->msix_rx = rxr;
4427                         msix->msix_tx = txr;
4428
4429                         msix->msix_cpuid = i + offset;
4430                         KKASSERT(msix->msix_cpuid < ncpus2);
4431                         txr->tx_intr_cpuid = msix->msix_cpuid;
4432
4433                         ksnprintf(msix->msix_desc, sizeof(msix->msix_desc),
4434                             "%s rxtx%d", device_get_nameunit(sc->dev), i);
4435                         msix->msix_rate = IGB_MSIX_RX_RATE;
4436                         ksnprintf(msix->msix_rate_desc,
4437                             sizeof(msix->msix_rate_desc),
4438                             "RXTX%d interrupt rate", i);
4439                 }
4440
4441                 if (ring_agg != ring_max) {
4442                         if (ring_max == sc->tx_ring_msix)
4443                                 igb_msix_tx_conf(sc, i, &x, offset);
4444                         else
4445                                 igb_msix_rx_conf(sc, i, &x, offset);
4446                 }
4447         }
4448
4449         /*
4450          * Link status
4451          */
4452         KKASSERT(x < sc->msix_cnt);
4453         msix = &sc->msix_data[x++];
4454         sc->sts_intr_bit = msix->msix_vector;
4455         sc->sts_intr_mask = msix->msix_mask;
4456
4457         msix->msix_serialize = &sc->main_serialize;
4458         msix->msix_func = igb_msix_status;
4459         msix->msix_arg = sc;
4460         msix->msix_cpuid = 0;
4461         ksnprintf(msix->msix_desc, sizeof(msix->msix_desc), "%s sts",
4462             device_get_nameunit(sc->dev));
4463         ksnprintf(msix->msix_rate_desc, sizeof(msix->msix_rate_desc),
4464             "status interrupt rate");
4465
4466         KKASSERT(x == sc->msix_cnt);
4467
4468         error = pci_setup_msix(sc->dev);
4469         if (error) {
4470                 device_printf(sc->dev, "Setup MSI-X failed\n");
4471                 goto back;
4472         }
4473         setup = TRUE;
4474
4475         for (i = 0; i < sc->msix_cnt; ++i) {
4476                 msix = &sc->msix_data[i];
4477
4478                 error = pci_alloc_msix_vector(sc->dev, msix->msix_vector,
4479                     &msix->msix_rid, msix->msix_cpuid);
4480                 if (error) {
4481                         device_printf(sc->dev,
4482                             "Unable to allocate MSI-X %d on cpu%d\n",
4483                             msix->msix_vector, msix->msix_cpuid);
4484                         goto back;
4485                 }
4486
4487                 msix->msix_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ,
4488                     &msix->msix_rid, RF_ACTIVE);
4489                 if (msix->msix_res == NULL) {
4490                         device_printf(sc->dev,
4491                             "Unable to allocate MSI-X %d resource\n",
4492                             msix->msix_vector);
4493                         error = ENOMEM;
4494                         goto back;
4495                 }
4496         }
4497
4498         pci_enable_msix(sc->dev);
4499         sc->intr_type = PCI_INTR_TYPE_MSIX;
4500 back:
4501         if (error)
4502                 igb_msix_free(sc, setup);
4503 }
4504
4505 static void
4506 igb_msix_free(struct igb_softc *sc, boolean_t setup)
4507 {
4508         int i;
4509
4510         KKASSERT(sc->msix_cnt > 1);
4511
4512         for (i = 0; i < sc->msix_cnt; ++i) {
4513                 struct igb_msix_data *msix = &sc->msix_data[i];
4514
4515                 if (msix->msix_res != NULL) {
4516                         bus_release_resource(sc->dev, SYS_RES_IRQ,
4517                             msix->msix_rid, msix->msix_res);
4518                 }
4519                 if (msix->msix_rid >= 0)
4520                         pci_release_msix_vector(sc->dev, msix->msix_rid);
4521         }
4522         if (setup)
4523                 pci_teardown_msix(sc->dev);
4524
4525         sc->msix_cnt = 0;
4526         kfree(sc->msix_data, M_DEVBUF);
4527         sc->msix_data = NULL;
4528 }
4529
4530 static int
4531 igb_msix_setup(struct igb_softc *sc)
4532 {
4533         int i;
4534
4535         for (i = 0; i < sc->msix_cnt; ++i) {
4536                 struct igb_msix_data *msix = &sc->msix_data[i];
4537                 int error;
4538
4539                 error = bus_setup_intr_descr(sc->dev, msix->msix_res,
4540                     INTR_MPSAFE, msix->msix_func, msix->msix_arg,
4541                     &msix->msix_handle, msix->msix_serialize, msix->msix_desc);
4542                 if (error) {
4543                         device_printf(sc->dev, "could not set up %s "
4544                             "interrupt handler.\n", msix->msix_desc);
4545                         igb_msix_teardown(sc, i);
4546                         return error;
4547                 }
4548         }
4549         return 0;
4550 }
4551
4552 static void
4553 igb_msix_teardown(struct igb_softc *sc, int msix_cnt)
4554 {
4555         int i;
4556
4557         for (i = 0; i < msix_cnt; ++i) {
4558                 struct igb_msix_data *msix = &sc->msix_data[i];
4559
4560                 bus_teardown_intr(sc->dev, msix->msix_res, msix->msix_handle);
4561         }
4562 }
4563
4564 static void
4565 igb_msix_rx(void *arg)
4566 {
4567         struct igb_rx_ring *rxr = arg;
4568
4569         ASSERT_SERIALIZED(&rxr->rx_serialize);
4570         igb_rxeof(rxr, -1);
4571
4572         E1000_WRITE_REG(&rxr->sc->hw, E1000_EIMS, rxr->rx_intr_mask);
4573 }
4574
4575 static void
4576 igb_msix_tx(void *arg)
4577 {
4578         struct igb_tx_ring *txr = arg;
4579
4580         ASSERT_SERIALIZED(&txr->tx_serialize);
4581
4582         igb_txeof(txr);
4583         if (!ifsq_is_empty(txr->ifsq))
4584                 ifsq_devstart(txr->ifsq);
4585
4586         E1000_WRITE_REG(&txr->sc->hw, E1000_EIMS, txr->tx_intr_mask);
4587 }
4588
4589 static void
4590 igb_msix_status(void *arg)
4591 {
4592         struct igb_softc *sc = arg;
4593         uint32_t icr;
4594
4595         ASSERT_SERIALIZED(&sc->main_serialize);
4596
4597         icr = E1000_READ_REG(&sc->hw, E1000_ICR);
4598         if (icr & E1000_ICR_LSC) {
4599                 sc->hw.mac.get_link_status = 1;
4600                 igb_update_link_status(sc);
4601         }
4602
4603         E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->sts_intr_mask);
4604 }
4605
4606 static void
4607 igb_set_ring_inuse(struct igb_softc *sc, boolean_t polling)
4608 {
4609         sc->rx_ring_inuse = igb_get_rxring_inuse(sc, polling);
4610         sc->tx_ring_inuse = igb_get_txring_inuse(sc, polling);
4611         if (bootverbose) {
4612                 if_printf(&sc->arpcom.ac_if, "RX rings %d/%d, TX rings %d/%d\n",
4613                     sc->rx_ring_inuse, sc->rx_ring_cnt,
4614                     sc->tx_ring_inuse, sc->tx_ring_cnt);
4615         }
4616 }
4617
4618 static int
4619 igb_get_rxring_inuse(const struct igb_softc *sc, boolean_t polling)
4620 {
4621         if (!IGB_ENABLE_HWRSS(sc))
4622                 return 1;
4623
4624         if (polling)
4625                 return sc->rx_ring_cnt;
4626         else if (sc->intr_type != PCI_INTR_TYPE_MSIX)
4627                 return IGB_MIN_RING_RSS;
4628         else
4629                 return sc->rx_ring_msix;
4630 }
4631
4632 static int
4633 igb_get_txring_inuse(const struct igb_softc *sc, boolean_t polling)
4634 {
4635         if (!IGB_ENABLE_HWTSS(sc))
4636                 return 1;
4637
4638         if (polling)
4639                 return sc->tx_ring_cnt;
4640         else if (sc->intr_type != PCI_INTR_TYPE_MSIX)
4641                 return IGB_MIN_RING;
4642         else
4643                 return sc->tx_ring_msix;
4644 }
4645
4646 static int
4647 igb_tso_pullup(struct igb_tx_ring *txr, struct mbuf **mp)
4648 {
4649         int hoff, iphlen, thoff;
4650         struct mbuf *m;
4651
4652         m = *mp;
4653         KASSERT(M_WRITABLE(m), ("TSO mbuf not writable"));
4654
4655         iphlen = m->m_pkthdr.csum_iphlen;
4656         thoff = m->m_pkthdr.csum_thlen;
4657         hoff = m->m_pkthdr.csum_lhlen;
4658
4659         KASSERT(iphlen > 0, ("invalid ip hlen"));
4660         KASSERT(thoff > 0, ("invalid tcp hlen"));
4661         KASSERT(hoff > 0, ("invalid ether hlen"));
4662
4663         if (__predict_false(m->m_len < hoff + iphlen + thoff)) {
4664                 m = m_pullup(m, hoff + iphlen + thoff);
4665                 if (m == NULL) {
4666                         *mp = NULL;
4667                         return ENOBUFS;
4668                 }
4669                 *mp = m;
4670         }
4671         if (txr->tx_flags & IGB_TXFLAG_TSO_IPLEN0) {
4672                 struct ip *ip;
4673
4674                 ip = mtodoff(m, struct ip *, hoff);
4675                 ip->ip_len = 0;
4676         }
4677
4678         return 0;
4679 }
4680
4681 static void
4682 igb_tso_ctx(struct igb_tx_ring *txr, struct mbuf *m, uint32_t *hlen)
4683 {
4684         struct e1000_adv_tx_context_desc *TXD;
4685         uint32_t vlan_macip_lens, type_tucmd_mlhl, mss_l4len_idx;
4686         int hoff, ctxd, iphlen, thoff;
4687
4688         iphlen = m->m_pkthdr.csum_iphlen;
4689         thoff = m->m_pkthdr.csum_thlen;
4690         hoff = m->m_pkthdr.csum_lhlen;
4691
4692         vlan_macip_lens = type_tucmd_mlhl = mss_l4len_idx = 0;
4693
4694         ctxd = txr->next_avail_desc;
4695         TXD = (struct e1000_adv_tx_context_desc *)&txr->tx_base[ctxd];
4696
4697         if (m->m_flags & M_VLANTAG) {
4698                 uint16_t vlantag;
4699
4700                 vlantag = htole16(m->m_pkthdr.ether_vlantag);
4701                 vlan_macip_lens |= (vlantag << E1000_ADVTXD_VLAN_SHIFT);
4702         }
4703
4704         vlan_macip_lens |= (hoff << E1000_ADVTXD_MACLEN_SHIFT);
4705         vlan_macip_lens |= iphlen;
4706
4707         type_tucmd_mlhl |= E1000_ADVTXD_DCMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
4708         type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_TCP;
4709         type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_IPV4;
4710
4711         mss_l4len_idx |= (m->m_pkthdr.tso_segsz << E1000_ADVTXD_MSS_SHIFT);
4712         mss_l4len_idx |= (thoff << E1000_ADVTXD_L4LEN_SHIFT);
4713
4714         /*
4715          * 82575 needs the TX context index added; the queue
4716          * index is used as TX context index here.
4717          */
4718         if (txr->sc->hw.mac.type == e1000_82575)
4719                 mss_l4len_idx |= txr->me << 4;
4720
4721         TXD->vlan_macip_lens = htole32(vlan_macip_lens);
4722         TXD->type_tucmd_mlhl = htole32(type_tucmd_mlhl);
4723         TXD->seqnum_seed = htole32(0);
4724         TXD->mss_l4len_idx = htole32(mss_l4len_idx);
4725
4726         /* We've consumed the first desc, adjust counters */
4727         if (++ctxd == txr->num_tx_desc)
4728                 ctxd = 0;
4729         txr->next_avail_desc = ctxd;
4730         --txr->tx_avail;
4731
4732         *hlen = hoff + iphlen + thoff;
4733 }
4734
4735 static void
4736 igb_setup_serializer(struct igb_softc *sc)
4737 {
4738         const struct igb_msix_data *msix;
4739         int i, j;
4740
4741         /*
4742          * Allocate serializer array
4743          */
4744
4745         /* Main + TX + RX */
4746         sc->serialize_cnt = 1 + sc->tx_ring_cnt + sc->rx_ring_cnt;
4747
4748         /* Aggregate TX/RX MSI-X */
4749         for (i = 0; i < sc->msix_cnt; ++i) {
4750                 msix = &sc->msix_data[i];
4751                 if (msix->msix_serialize == &msix->msix_serialize0)
4752                         sc->serialize_cnt++;
4753         }
4754
4755         sc->serializes =
4756             kmalloc(sc->serialize_cnt * sizeof(struct lwkt_serialize *),
4757                 M_DEVBUF, M_WAITOK | M_ZERO);
4758
4759         /*
4760          * Setup serializers
4761          *
4762          * NOTE: Order is critical
4763          */
4764
4765         i = 0;
4766
4767         KKASSERT(i < sc->serialize_cnt);
4768         sc->serializes[i++] = &sc->main_serialize;
4769
4770         for (j = 0; j < sc->msix_cnt; ++j) {
4771                 msix = &sc->msix_data[j];
4772                 if (msix->msix_serialize == &msix->msix_serialize0) {
4773                         KKASSERT(i < sc->serialize_cnt);
4774                         sc->serializes[i++] = msix->msix_serialize;
4775                 }
4776         }
4777
4778         for (j = 0; j < sc->tx_ring_cnt; ++j) {
4779                 KKASSERT(i < sc->serialize_cnt);
4780                 sc->serializes[i++] = &sc->tx_rings[j].tx_serialize;
4781         }
4782
4783         for (j = 0; j < sc->rx_ring_cnt; ++j) {
4784                 KKASSERT(i < sc->serialize_cnt);
4785                 sc->serializes[i++] = &sc->rx_rings[j].rx_serialize;
4786         }
4787
4788         KKASSERT(i == sc->serialize_cnt);
4789 }
4790
4791 static void
4792 igb_msix_rx_conf(struct igb_softc *sc, int i, int *x0, int offset)
4793 {
4794         int x = *x0;
4795
4796         for (; i < sc->rx_ring_msix; ++i) {
4797                 struct igb_rx_ring *rxr = &sc->rx_rings[i];
4798                 struct igb_msix_data *msix;
4799
4800                 KKASSERT(x < sc->msix_cnt);
4801                 msix = &sc->msix_data[x++];
4802
4803                 rxr->rx_intr_bit = msix->msix_vector;
4804                 rxr->rx_intr_mask = msix->msix_mask;
4805
4806                 msix->msix_serialize = &rxr->rx_serialize;
4807                 msix->msix_func = igb_msix_rx;
4808                 msix->msix_arg = rxr;
4809
4810                 msix->msix_cpuid = i + offset;
4811                 KKASSERT(msix->msix_cpuid < ncpus2);
4812
4813                 ksnprintf(msix->msix_desc, sizeof(msix->msix_desc), "%s rx%d",
4814                     device_get_nameunit(sc->dev), i);
4815
4816                 msix->msix_rate = IGB_MSIX_RX_RATE;
4817                 ksnprintf(msix->msix_rate_desc, sizeof(msix->msix_rate_desc),
4818                     "RX%d interrupt rate", i);
4819         }
4820         *x0 = x;
4821 }
4822
4823 static void
4824 igb_msix_tx_conf(struct igb_softc *sc, int i, int *x0, int offset)
4825 {
4826         int x = *x0;
4827
4828         for (; i < sc->tx_ring_msix; ++i) {
4829                 struct igb_tx_ring *txr = &sc->tx_rings[i];
4830                 struct igb_msix_data *msix;
4831
4832                 KKASSERT(x < sc->msix_cnt);
4833                 msix = &sc->msix_data[x++];
4834
4835                 txr->tx_intr_bit = msix->msix_vector;
4836                 txr->tx_intr_mask = msix->msix_mask;
4837
4838                 msix->msix_serialize = &txr->tx_serialize;
4839                 msix->msix_func = igb_msix_tx;
4840                 msix->msix_arg = txr;
4841
4842                 msix->msix_cpuid = i + offset;
4843                 KKASSERT(msix->msix_cpuid < ncpus2);
4844                 txr->tx_intr_cpuid = msix->msix_cpuid;
4845
4846                 ksnprintf(msix->msix_desc, sizeof(msix->msix_desc), "%s tx%d",
4847                     device_get_nameunit(sc->dev), i);
4848
4849                 msix->msix_rate = IGB_MSIX_TX_RATE;
4850                 ksnprintf(msix->msix_rate_desc, sizeof(msix->msix_rate_desc),
4851                     "TX%d interrupt rate", i);
4852         }
4853         *x0 = x;
4854 }
4855
4856 static void
4857 igb_msix_rxtx(void *arg)
4858 {
4859         struct igb_msix_data *msix = arg;
4860         struct igb_rx_ring *rxr = msix->msix_rx;
4861         struct igb_tx_ring *txr = msix->msix_tx;
4862
4863         ASSERT_SERIALIZED(&msix->msix_serialize0);
4864
4865         lwkt_serialize_enter(&rxr->rx_serialize);
4866         igb_rxeof(rxr, -1);
4867         lwkt_serialize_exit(&rxr->rx_serialize);
4868
4869         lwkt_serialize_enter(&txr->tx_serialize);
4870         igb_txeof(txr);
4871         if (!ifsq_is_empty(txr->ifsq))
4872                 ifsq_devstart(txr->ifsq);
4873         lwkt_serialize_exit(&txr->tx_serialize);
4874
4875         E1000_WRITE_REG(&msix->msix_sc->hw, E1000_EIMS, msix->msix_mask);
4876 }
4877
4878 static void
4879 igb_set_timer_cpuid(struct igb_softc *sc, boolean_t polling)
4880 {
4881         if (polling || sc->intr_type == PCI_INTR_TYPE_MSIX)
4882                 sc->timer_cpuid = 0; /* XXX fixed */
4883         else
4884                 sc->timer_cpuid = rman_get_cpuid(sc->intr_res);
4885 }