2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/seq_file.h>
29 #include <linux/firmware.h>
30 #include <linux/module.h>
32 #include <drm/radeon_drm.h>
34 #include "radeon_asic.h"
35 #include "radeon_audio.h"
36 #include "radeon_mode.h"
40 #include "radeon_ucode.h"
43 MODULE_FIRMWARE("radeon/R600_pfp.bin");
44 MODULE_FIRMWARE("radeon/R600_me.bin");
45 MODULE_FIRMWARE("radeon/RV610_pfp.bin");
46 MODULE_FIRMWARE("radeon/RV610_me.bin");
47 MODULE_FIRMWARE("radeon/RV630_pfp.bin");
48 MODULE_FIRMWARE("radeon/RV630_me.bin");
49 MODULE_FIRMWARE("radeon/RV620_pfp.bin");
50 MODULE_FIRMWARE("radeon/RV620_me.bin");
51 MODULE_FIRMWARE("radeon/RV635_pfp.bin");
52 MODULE_FIRMWARE("radeon/RV635_me.bin");
53 MODULE_FIRMWARE("radeon/RV670_pfp.bin");
54 MODULE_FIRMWARE("radeon/RV670_me.bin");
55 MODULE_FIRMWARE("radeon/RS780_pfp.bin");
56 MODULE_FIRMWARE("radeon/RS780_me.bin");
57 MODULE_FIRMWARE("radeon/RV770_pfp.bin");
58 MODULE_FIRMWARE("radeon/RV770_me.bin");
59 MODULE_FIRMWARE("radeon/RV770_smc.bin");
60 MODULE_FIRMWARE("radeon/RV730_pfp.bin");
61 MODULE_FIRMWARE("radeon/RV730_me.bin");
62 MODULE_FIRMWARE("radeon/RV730_smc.bin");
63 MODULE_FIRMWARE("radeon/RV740_smc.bin");
64 MODULE_FIRMWARE("radeon/RV710_pfp.bin");
65 MODULE_FIRMWARE("radeon/RV710_me.bin");
66 MODULE_FIRMWARE("radeon/RV710_smc.bin");
67 MODULE_FIRMWARE("radeon/R600_rlc.bin");
68 MODULE_FIRMWARE("radeon/R700_rlc.bin");
69 MODULE_FIRMWARE("radeon/CEDAR_pfp.bin");
70 MODULE_FIRMWARE("radeon/CEDAR_me.bin");
71 MODULE_FIRMWARE("radeon/CEDAR_rlc.bin");
72 MODULE_FIRMWARE("radeon/CEDAR_smc.bin");
73 MODULE_FIRMWARE("radeon/REDWOOD_pfp.bin");
74 MODULE_FIRMWARE("radeon/REDWOOD_me.bin");
75 MODULE_FIRMWARE("radeon/REDWOOD_rlc.bin");
76 MODULE_FIRMWARE("radeon/REDWOOD_smc.bin");
77 MODULE_FIRMWARE("radeon/JUNIPER_pfp.bin");
78 MODULE_FIRMWARE("radeon/JUNIPER_me.bin");
79 MODULE_FIRMWARE("radeon/JUNIPER_rlc.bin");
80 MODULE_FIRMWARE("radeon/JUNIPER_smc.bin");
81 MODULE_FIRMWARE("radeon/CYPRESS_pfp.bin");
82 MODULE_FIRMWARE("radeon/CYPRESS_me.bin");
83 MODULE_FIRMWARE("radeon/CYPRESS_rlc.bin");
84 MODULE_FIRMWARE("radeon/CYPRESS_smc.bin");
85 MODULE_FIRMWARE("radeon/PALM_pfp.bin");
86 MODULE_FIRMWARE("radeon/PALM_me.bin");
87 MODULE_FIRMWARE("radeon/SUMO_rlc.bin");
88 MODULE_FIRMWARE("radeon/SUMO_pfp.bin");
89 MODULE_FIRMWARE("radeon/SUMO_me.bin");
90 MODULE_FIRMWARE("radeon/SUMO2_pfp.bin");
91 MODULE_FIRMWARE("radeon/SUMO2_me.bin");
93 static const u32 crtc_offsets[2] =
96 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL
99 int r600_debugfs_mc_info_init(struct radeon_device *rdev);
101 /* r600,rv610,rv630,rv620,rv635,rv670 */
102 static void r600_gpu_init(struct radeon_device *rdev);
103 void r600_irq_disable(struct radeon_device *rdev);
104 static void r600_pcie_gen2_enable(struct radeon_device *rdev);
107 * Indirect registers accessor
109 u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg)
113 spin_lock(&rdev->rcu_idx_lock);
114 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
115 r = RREG32(R600_RCU_DATA);
116 spin_unlock(&rdev->rcu_idx_lock);
120 void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v)
122 spin_lock(&rdev->rcu_idx_lock);
123 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
124 WREG32(R600_RCU_DATA, (v));
125 spin_unlock(&rdev->rcu_idx_lock);
128 u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg)
132 spin_lock(&rdev->uvd_idx_lock);
133 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
134 r = RREG32(R600_UVD_CTX_DATA);
135 spin_unlock(&rdev->uvd_idx_lock);
139 void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v)
141 spin_lock(&rdev->uvd_idx_lock);
142 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
143 WREG32(R600_UVD_CTX_DATA, (v));
144 spin_unlock(&rdev->uvd_idx_lock);
148 * r600_get_allowed_info_register - fetch the register for the info ioctl
150 * @rdev: radeon_device pointer
151 * @reg: register offset in bytes
152 * @val: register value
154 * Returns 0 for success or -EINVAL for an invalid register
157 int r600_get_allowed_info_register(struct radeon_device *rdev,
163 case R_000E50_SRBM_STATUS:
174 * r600_get_xclk - get the xclk
176 * @rdev: radeon_device pointer
178 * Returns the reference clock used by the gfx engine
179 * (r6xx, IGPs, APUs).
181 u32 r600_get_xclk(struct radeon_device *rdev)
183 return rdev->clock.spll.reference_freq;
186 int r600_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
188 unsigned fb_div = 0, ref_div, vclk_div = 0, dclk_div = 0;
191 /* bypass vclk and dclk with bclk */
192 WREG32_P(CG_UPLL_FUNC_CNTL_2,
193 VCLK_SRC_SEL(1) | DCLK_SRC_SEL(1),
194 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK));
196 /* assert BYPASS_EN, deassert UPLL_RESET, UPLL_SLEEP and UPLL_CTLREQ */
197 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~(
198 UPLL_RESET_MASK | UPLL_SLEEP_MASK | UPLL_CTLREQ_MASK));
200 if (rdev->family >= CHIP_RS780)
201 WREG32_P(GFX_MACRO_BYPASS_CNTL, UPLL_BYPASS_CNTL,
204 if (!vclk || !dclk) {
205 /* keep the Bypass mode, put PLL to sleep */
206 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK);
210 if (rdev->clock.spll.reference_freq == 10000)
215 r = radeon_uvd_calc_upll_dividers(rdev, vclk, dclk, 50000, 160000,
216 ref_div + 1, 0xFFF, 2, 30, ~0,
217 &fb_div, &vclk_div, &dclk_div);
221 if (rdev->family >= CHIP_RV670 && rdev->family < CHIP_RS780)
226 r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);
230 /* assert PLL_RESET */
231 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK);
233 /* For RS780 we have to choose ref clk */
234 if (rdev->family >= CHIP_RS780)
235 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_REFCLK_SRC_SEL_MASK,
236 ~UPLL_REFCLK_SRC_SEL_MASK);
238 /* set the required fb, ref and post divder values */
239 WREG32_P(CG_UPLL_FUNC_CNTL,
240 UPLL_FB_DIV(fb_div) |
241 UPLL_REF_DIV(ref_div),
242 ~(UPLL_FB_DIV_MASK | UPLL_REF_DIV_MASK));
243 WREG32_P(CG_UPLL_FUNC_CNTL_2,
244 UPLL_SW_HILEN(vclk_div >> 1) |
245 UPLL_SW_LOLEN((vclk_div >> 1) + (vclk_div & 1)) |
246 UPLL_SW_HILEN2(dclk_div >> 1) |
247 UPLL_SW_LOLEN2((dclk_div >> 1) + (dclk_div & 1)) |
248 UPLL_DIVEN_MASK | UPLL_DIVEN2_MASK,
251 /* give the PLL some time to settle */
254 /* deassert PLL_RESET */
255 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);
259 /* deassert BYPASS EN */
260 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK);
262 if (rdev->family >= CHIP_RS780)
263 WREG32_P(GFX_MACRO_BYPASS_CNTL, 0, ~UPLL_BYPASS_CNTL);
265 r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);
269 /* switch VCLK and DCLK selection */
270 WREG32_P(CG_UPLL_FUNC_CNTL_2,
271 VCLK_SRC_SEL(2) | DCLK_SRC_SEL(2),
272 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK));
279 void dce3_program_fmt(struct drm_encoder *encoder)
281 struct drm_device *dev = encoder->dev;
282 struct radeon_device *rdev = dev->dev_private;
283 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
284 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
285 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
288 enum radeon_connector_dither dither = RADEON_FMT_DITHER_DISABLE;
291 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
292 bpc = radeon_get_monitor_bpc(connector);
293 dither = radeon_connector->dither;
296 /* LVDS FMT is set up by atom */
297 if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
300 /* not needed for analog */
301 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||
302 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))
310 if (dither == RADEON_FMT_DITHER_ENABLE)
311 /* XXX sort out optimal dither settings */
312 tmp |= FMT_SPATIAL_DITHER_EN;
314 tmp |= FMT_TRUNCATE_EN;
317 if (dither == RADEON_FMT_DITHER_ENABLE)
318 /* XXX sort out optimal dither settings */
319 tmp |= (FMT_SPATIAL_DITHER_EN | FMT_SPATIAL_DITHER_DEPTH);
321 tmp |= (FMT_TRUNCATE_EN | FMT_TRUNCATE_DEPTH);
329 WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp);
332 /* get temperature in millidegrees */
333 int rv6xx_get_temp(struct radeon_device *rdev)
335 u32 temp = (RREG32(CG_THERMAL_STATUS) & ASIC_T_MASK) >>
337 int actual_temp = temp & 0xff;
342 return actual_temp * 1000;
345 void r600_pm_get_dynpm_state(struct radeon_device *rdev)
349 rdev->pm.dynpm_can_upclock = true;
350 rdev->pm.dynpm_can_downclock = true;
352 /* power state array is low to high, default is first */
353 if ((rdev->flags & RADEON_IS_IGP) || (rdev->family == CHIP_R600)) {
354 int min_power_state_index = 0;
356 if (rdev->pm.num_power_states > 2)
357 min_power_state_index = 1;
359 switch (rdev->pm.dynpm_planned_action) {
360 case DYNPM_ACTION_MINIMUM:
361 rdev->pm.requested_power_state_index = min_power_state_index;
362 rdev->pm.requested_clock_mode_index = 0;
363 rdev->pm.dynpm_can_downclock = false;
365 case DYNPM_ACTION_DOWNCLOCK:
366 if (rdev->pm.current_power_state_index == min_power_state_index) {
367 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
368 rdev->pm.dynpm_can_downclock = false;
370 if (rdev->pm.active_crtc_count > 1) {
371 for (i = 0; i < rdev->pm.num_power_states; i++) {
372 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
374 else if (i >= rdev->pm.current_power_state_index) {
375 rdev->pm.requested_power_state_index =
376 rdev->pm.current_power_state_index;
379 rdev->pm.requested_power_state_index = i;
384 if (rdev->pm.current_power_state_index == 0)
385 rdev->pm.requested_power_state_index =
386 rdev->pm.num_power_states - 1;
388 rdev->pm.requested_power_state_index =
389 rdev->pm.current_power_state_index - 1;
392 rdev->pm.requested_clock_mode_index = 0;
393 /* don't use the power state if crtcs are active and no display flag is set */
394 if ((rdev->pm.active_crtc_count > 0) &&
395 (rdev->pm.power_state[rdev->pm.requested_power_state_index].
396 clock_info[rdev->pm.requested_clock_mode_index].flags &
397 RADEON_PM_MODE_NO_DISPLAY)) {
398 rdev->pm.requested_power_state_index++;
401 case DYNPM_ACTION_UPCLOCK:
402 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
403 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
404 rdev->pm.dynpm_can_upclock = false;
406 if (rdev->pm.active_crtc_count > 1) {
407 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
408 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
410 else if (i <= rdev->pm.current_power_state_index) {
411 rdev->pm.requested_power_state_index =
412 rdev->pm.current_power_state_index;
415 rdev->pm.requested_power_state_index = i;
420 rdev->pm.requested_power_state_index =
421 rdev->pm.current_power_state_index + 1;
423 rdev->pm.requested_clock_mode_index = 0;
425 case DYNPM_ACTION_DEFAULT:
426 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
427 rdev->pm.requested_clock_mode_index = 0;
428 rdev->pm.dynpm_can_upclock = false;
430 case DYNPM_ACTION_NONE:
432 DRM_ERROR("Requested mode for not defined action\n");
436 /* XXX select a power state based on AC/DC, single/dualhead, etc. */
437 /* for now just select the first power state and switch between clock modes */
438 /* power state array is low to high, default is first (0) */
439 if (rdev->pm.active_crtc_count > 1) {
440 rdev->pm.requested_power_state_index = -1;
441 /* start at 1 as we don't want the default mode */
442 for (i = 1; i < rdev->pm.num_power_states; i++) {
443 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
445 else if ((rdev->pm.power_state[i].type == POWER_STATE_TYPE_PERFORMANCE) ||
446 (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY)) {
447 rdev->pm.requested_power_state_index = i;
451 /* if nothing selected, grab the default state. */
452 if (rdev->pm.requested_power_state_index == -1)
453 rdev->pm.requested_power_state_index = 0;
455 rdev->pm.requested_power_state_index = 1;
457 switch (rdev->pm.dynpm_planned_action) {
458 case DYNPM_ACTION_MINIMUM:
459 rdev->pm.requested_clock_mode_index = 0;
460 rdev->pm.dynpm_can_downclock = false;
462 case DYNPM_ACTION_DOWNCLOCK:
463 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
464 if (rdev->pm.current_clock_mode_index == 0) {
465 rdev->pm.requested_clock_mode_index = 0;
466 rdev->pm.dynpm_can_downclock = false;
468 rdev->pm.requested_clock_mode_index =
469 rdev->pm.current_clock_mode_index - 1;
471 rdev->pm.requested_clock_mode_index = 0;
472 rdev->pm.dynpm_can_downclock = false;
474 /* don't use the power state if crtcs are active and no display flag is set */
475 if ((rdev->pm.active_crtc_count > 0) &&
476 (rdev->pm.power_state[rdev->pm.requested_power_state_index].
477 clock_info[rdev->pm.requested_clock_mode_index].flags &
478 RADEON_PM_MODE_NO_DISPLAY)) {
479 rdev->pm.requested_clock_mode_index++;
482 case DYNPM_ACTION_UPCLOCK:
483 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
484 if (rdev->pm.current_clock_mode_index ==
485 (rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1)) {
486 rdev->pm.requested_clock_mode_index = rdev->pm.current_clock_mode_index;
487 rdev->pm.dynpm_can_upclock = false;
489 rdev->pm.requested_clock_mode_index =
490 rdev->pm.current_clock_mode_index + 1;
492 rdev->pm.requested_clock_mode_index =
493 rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1;
494 rdev->pm.dynpm_can_upclock = false;
497 case DYNPM_ACTION_DEFAULT:
498 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
499 rdev->pm.requested_clock_mode_index = 0;
500 rdev->pm.dynpm_can_upclock = false;
502 case DYNPM_ACTION_NONE:
504 DRM_ERROR("Requested mode for not defined action\n");
509 DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
510 rdev->pm.power_state[rdev->pm.requested_power_state_index].
511 clock_info[rdev->pm.requested_clock_mode_index].sclk,
512 rdev->pm.power_state[rdev->pm.requested_power_state_index].
513 clock_info[rdev->pm.requested_clock_mode_index].mclk,
514 rdev->pm.power_state[rdev->pm.requested_power_state_index].
518 void rs780_pm_init_profile(struct radeon_device *rdev)
520 if (rdev->pm.num_power_states == 2) {
522 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
523 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
524 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
525 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
527 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
528 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
529 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
530 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
532 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
533 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
534 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
535 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
537 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
538 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
539 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
540 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
542 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
543 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
544 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
545 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
547 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
548 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
549 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
550 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
552 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
553 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 1;
554 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
555 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
556 } else if (rdev->pm.num_power_states == 3) {
558 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
559 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
560 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
561 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
563 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
564 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
565 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
566 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
568 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
569 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
570 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
571 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
573 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
574 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 2;
575 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
576 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
578 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 1;
579 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 1;
580 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
581 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
583 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 1;
584 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 1;
585 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
586 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
588 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 1;
589 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
590 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
591 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
594 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
595 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
596 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
597 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
599 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 2;
600 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 2;
601 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
602 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
604 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 2;
605 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 2;
606 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
607 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
609 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 2;
610 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 3;
611 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
612 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
614 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
615 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
616 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
617 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
619 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
620 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
621 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
622 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
624 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
625 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 3;
626 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
627 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
631 void r600_pm_init_profile(struct radeon_device *rdev)
635 if (rdev->family == CHIP_R600) {
638 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
639 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
640 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
641 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
643 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
644 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
645 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
646 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
648 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
649 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
650 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
651 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
653 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
654 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
655 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
656 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
658 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
659 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
660 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
661 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
663 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
664 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
665 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
666 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
668 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
669 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
670 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
671 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
673 if (rdev->pm.num_power_states < 4) {
675 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
676 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
677 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
678 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
680 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
681 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
682 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
683 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
685 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
686 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
687 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
688 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
690 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
691 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
692 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
693 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
695 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
696 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 2;
697 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
698 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
700 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
701 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 2;
702 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
703 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
705 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
706 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
707 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
708 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
711 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
712 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
713 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
714 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
716 if (rdev->flags & RADEON_IS_MOBILITY)
717 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
719 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
720 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx;
721 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx;
722 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
723 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
725 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx;
726 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx;
727 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
728 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
730 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
731 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx;
732 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx;
733 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
734 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
736 if (rdev->flags & RADEON_IS_MOBILITY)
737 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
739 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
740 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx;
741 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx;
742 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
743 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
745 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx;
746 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx;
747 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
748 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
750 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
751 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx;
752 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx;
753 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
754 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
759 void r600_pm_misc(struct radeon_device *rdev)
761 int req_ps_idx = rdev->pm.requested_power_state_index;
762 int req_cm_idx = rdev->pm.requested_clock_mode_index;
763 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
764 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
766 if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
767 /* 0xff01 is a flag rather then an actual voltage */
768 if (voltage->voltage == 0xff01)
770 if (voltage->voltage != rdev->pm.current_vddc) {
771 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
772 rdev->pm.current_vddc = voltage->voltage;
773 DRM_DEBUG_DRIVER("Setting: v: %d\n", voltage->voltage);
778 bool r600_gui_idle(struct radeon_device *rdev)
780 if (RREG32(GRBM_STATUS) & GUI_ACTIVE)
786 /* hpd for digital panel detect/disconnect */
787 bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
789 bool connected = false;
791 if (ASIC_IS_DCE3(rdev)) {
794 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
798 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
802 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
806 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
811 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
815 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
824 if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
828 if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
832 if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
842 void r600_hpd_set_polarity(struct radeon_device *rdev,
843 enum radeon_hpd_id hpd)
846 bool connected = r600_hpd_sense(rdev, hpd);
848 if (ASIC_IS_DCE3(rdev)) {
851 tmp = RREG32(DC_HPD1_INT_CONTROL);
853 tmp &= ~DC_HPDx_INT_POLARITY;
855 tmp |= DC_HPDx_INT_POLARITY;
856 WREG32(DC_HPD1_INT_CONTROL, tmp);
859 tmp = RREG32(DC_HPD2_INT_CONTROL);
861 tmp &= ~DC_HPDx_INT_POLARITY;
863 tmp |= DC_HPDx_INT_POLARITY;
864 WREG32(DC_HPD2_INT_CONTROL, tmp);
867 tmp = RREG32(DC_HPD3_INT_CONTROL);
869 tmp &= ~DC_HPDx_INT_POLARITY;
871 tmp |= DC_HPDx_INT_POLARITY;
872 WREG32(DC_HPD3_INT_CONTROL, tmp);
875 tmp = RREG32(DC_HPD4_INT_CONTROL);
877 tmp &= ~DC_HPDx_INT_POLARITY;
879 tmp |= DC_HPDx_INT_POLARITY;
880 WREG32(DC_HPD4_INT_CONTROL, tmp);
883 tmp = RREG32(DC_HPD5_INT_CONTROL);
885 tmp &= ~DC_HPDx_INT_POLARITY;
887 tmp |= DC_HPDx_INT_POLARITY;
888 WREG32(DC_HPD5_INT_CONTROL, tmp);
892 tmp = RREG32(DC_HPD6_INT_CONTROL);
894 tmp &= ~DC_HPDx_INT_POLARITY;
896 tmp |= DC_HPDx_INT_POLARITY;
897 WREG32(DC_HPD6_INT_CONTROL, tmp);
905 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
907 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
909 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
910 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
913 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
915 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
917 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
918 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
921 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
923 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
925 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
926 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
934 void r600_hpd_init(struct radeon_device *rdev)
936 struct drm_device *dev = rdev->ddev;
937 struct drm_connector *connector;
940 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
941 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
943 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
944 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
945 /* don't try to enable hpd on eDP or LVDS avoid breaking the
946 * aux dp channel on imac and help (but not completely fix)
947 * https://bugzilla.redhat.com/show_bug.cgi?id=726143
951 if (ASIC_IS_DCE3(rdev)) {
952 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa);
953 if (ASIC_IS_DCE32(rdev))
956 switch (radeon_connector->hpd.hpd) {
958 WREG32(DC_HPD1_CONTROL, tmp);
961 WREG32(DC_HPD2_CONTROL, tmp);
964 WREG32(DC_HPD3_CONTROL, tmp);
967 WREG32(DC_HPD4_CONTROL, tmp);
971 WREG32(DC_HPD5_CONTROL, tmp);
974 WREG32(DC_HPD6_CONTROL, tmp);
980 switch (radeon_connector->hpd.hpd) {
982 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN);
985 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN);
988 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN);
994 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
995 enable |= 1 << radeon_connector->hpd.hpd;
996 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
998 radeon_irq_kms_enable_hpd(rdev, enable);
1001 void r600_hpd_fini(struct radeon_device *rdev)
1003 struct drm_device *dev = rdev->ddev;
1004 struct drm_connector *connector;
1005 unsigned disable = 0;
1007 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1008 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1009 if (ASIC_IS_DCE3(rdev)) {
1010 switch (radeon_connector->hpd.hpd) {
1012 WREG32(DC_HPD1_CONTROL, 0);
1015 WREG32(DC_HPD2_CONTROL, 0);
1018 WREG32(DC_HPD3_CONTROL, 0);
1021 WREG32(DC_HPD4_CONTROL, 0);
1025 WREG32(DC_HPD5_CONTROL, 0);
1028 WREG32(DC_HPD6_CONTROL, 0);
1034 switch (radeon_connector->hpd.hpd) {
1036 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0);
1039 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0);
1042 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0);
1048 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
1049 disable |= 1 << radeon_connector->hpd.hpd;
1051 radeon_irq_kms_disable_hpd(rdev, disable);
1057 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
1062 /* flush hdp cache so updates hit vram */
1063 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
1064 !(rdev->flags & RADEON_IS_AGP)) {
1065 void __iomem *ptr = (void *)rdev->gart.ptr;
1068 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read
1069 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL
1070 * This seems to cause problems on some AGP cards. Just use the old
1073 WREG32(HDP_DEBUG1, 0);
1074 tmp = readl((void __iomem *)ptr);
1076 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
1078 WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
1079 WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
1080 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
1081 for (i = 0; i < rdev->usec_timeout; i++) {
1082 /* read MC_STATUS */
1083 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
1084 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
1086 printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
1096 int r600_pcie_gart_init(struct radeon_device *rdev)
1100 if (rdev->gart.robj) {
1101 WARN(1, "R600 PCIE GART already initialized\n");
1104 /* Initialize common gart structure */
1105 r = radeon_gart_init(rdev);
1108 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
1109 return radeon_gart_table_vram_alloc(rdev);
1112 static int r600_pcie_gart_enable(struct radeon_device *rdev)
1117 if (rdev->gart.robj == NULL) {
1118 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
1121 r = radeon_gart_table_vram_pin(rdev);
1125 /* Setup L2 cache */
1126 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
1127 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1128 EFFECTIVE_L2_QUEUE_SIZE(7));
1129 WREG32(VM_L2_CNTL2, 0);
1130 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
1131 /* Setup TLB control */
1132 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1133 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1134 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
1135 ENABLE_WAIT_L2_QUERY;
1136 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
1137 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
1138 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
1139 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
1140 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
1141 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
1142 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
1143 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
1144 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
1145 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
1146 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
1147 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
1148 WREG32(MC_VM_L1_TLB_MCB_RD_UVD_CNTL, tmp);
1149 WREG32(MC_VM_L1_TLB_MCB_WR_UVD_CNTL, tmp);
1150 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1151 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1152 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
1153 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
1154 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
1155 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
1156 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
1157 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
1158 (u32)(rdev->dummy_page.addr >> 12));
1159 for (i = 1; i < 7; i++)
1160 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
1162 r600_pcie_gart_tlb_flush(rdev);
1163 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
1164 (unsigned)(rdev->mc.gtt_size >> 20),
1165 (unsigned long long)rdev->gart.table_addr);
1166 rdev->gart.ready = true;
1170 static void r600_pcie_gart_disable(struct radeon_device *rdev)
1175 /* Disable all tables */
1176 for (i = 0; i < 7; i++)
1177 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
1179 /* Disable L2 cache */
1180 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
1181 EFFECTIVE_L2_QUEUE_SIZE(7));
1182 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
1183 /* Setup L1 TLB control */
1184 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
1185 ENABLE_WAIT_L2_QUERY;
1186 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
1187 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
1188 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
1189 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
1190 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
1191 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
1192 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
1193 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
1194 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp);
1195 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp);
1196 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
1197 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
1198 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
1199 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
1200 WREG32(MC_VM_L1_TLB_MCB_RD_UVD_CNTL, tmp);
1201 WREG32(MC_VM_L1_TLB_MCB_WR_UVD_CNTL, tmp);
1202 radeon_gart_table_vram_unpin(rdev);
1205 static void r600_pcie_gart_fini(struct radeon_device *rdev)
1207 radeon_gart_fini(rdev);
1208 r600_pcie_gart_disable(rdev);
1209 radeon_gart_table_vram_free(rdev);
1212 static void r600_agp_enable(struct radeon_device *rdev)
1217 /* Setup L2 cache */
1218 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
1219 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1220 EFFECTIVE_L2_QUEUE_SIZE(7));
1221 WREG32(VM_L2_CNTL2, 0);
1222 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
1223 /* Setup TLB control */
1224 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1225 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1226 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
1227 ENABLE_WAIT_L2_QUERY;
1228 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
1229 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
1230 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
1231 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
1232 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
1233 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
1234 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
1235 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
1236 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
1237 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
1238 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
1239 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
1240 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1241 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1242 for (i = 0; i < 7; i++)
1243 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
1246 int r600_mc_wait_for_idle(struct radeon_device *rdev)
1251 for (i = 0; i < rdev->usec_timeout; i++) {
1252 /* read MC_STATUS */
1253 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00;
1261 uint32_t rs780_mc_rreg(struct radeon_device *rdev, uint32_t reg)
1265 spin_lock(&rdev->mc_idx_lock);
1266 WREG32(R_0028F8_MC_INDEX, S_0028F8_MC_IND_ADDR(reg));
1267 r = RREG32(R_0028FC_MC_DATA);
1268 WREG32(R_0028F8_MC_INDEX, ~C_0028F8_MC_IND_ADDR);
1269 spin_unlock(&rdev->mc_idx_lock);
1273 void rs780_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1275 spin_lock(&rdev->mc_idx_lock);
1276 WREG32(R_0028F8_MC_INDEX, S_0028F8_MC_IND_ADDR(reg) |
1277 S_0028F8_MC_IND_WR_EN(1));
1278 WREG32(R_0028FC_MC_DATA, v);
1279 WREG32(R_0028F8_MC_INDEX, 0x7F);
1280 spin_unlock(&rdev->mc_idx_lock);
1283 static void r600_mc_program(struct radeon_device *rdev)
1285 struct rv515_mc_save save;
1289 /* Initialize HDP */
1290 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1291 WREG32((0x2c14 + j), 0x00000000);
1292 WREG32((0x2c18 + j), 0x00000000);
1293 WREG32((0x2c1c + j), 0x00000000);
1294 WREG32((0x2c20 + j), 0x00000000);
1295 WREG32((0x2c24 + j), 0x00000000);
1297 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
1299 rv515_mc_stop(rdev, &save);
1300 if (r600_mc_wait_for_idle(rdev)) {
1301 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1303 /* Lockout access through VGA aperture (doesn't exist before R600) */
1304 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
1305 /* Update configuration */
1306 if (rdev->flags & RADEON_IS_AGP) {
1307 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1308 /* VRAM before AGP */
1309 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1310 rdev->mc.vram_start >> 12);
1311 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1312 rdev->mc.gtt_end >> 12);
1314 /* VRAM after AGP */
1315 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1316 rdev->mc.gtt_start >> 12);
1317 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1318 rdev->mc.vram_end >> 12);
1321 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
1322 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12);
1324 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12);
1325 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
1326 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1327 WREG32(MC_VM_FB_LOCATION, tmp);
1328 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1329 WREG32(HDP_NONSURFACE_INFO, (2 << 7));
1330 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
1331 if (rdev->flags & RADEON_IS_AGP) {
1332 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22);
1333 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22);
1334 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1336 WREG32(MC_VM_AGP_BASE, 0);
1337 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1338 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1340 if (r600_mc_wait_for_idle(rdev)) {
1341 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1343 rv515_mc_resume(rdev, &save);
1344 /* we need to own VRAM, so turn off the VGA renderer here
1345 * to stop it overwriting our objects */
1346 rv515_vga_render_disable(rdev);
1350 * r600_vram_gtt_location - try to find VRAM & GTT location
1351 * @rdev: radeon device structure holding all necessary informations
1352 * @mc: memory controller structure holding memory informations
1354 * Function will place try to place VRAM at same place as in CPU (PCI)
1355 * address space as some GPU seems to have issue when we reprogram at
1356 * different address space.
1358 * If there is not enough space to fit the unvisible VRAM after the
1359 * aperture then we limit the VRAM size to the aperture.
1361 * If we are using AGP then place VRAM adjacent to AGP aperture are we need
1362 * them to be in one from GPU point of view so that we can program GPU to
1363 * catch access outside them (weird GPU policy see ??).
1365 * This function will never fails, worst case are limiting VRAM or GTT.
1367 * Note: GTT start, end, size should be initialized before calling this
1368 * function on AGP platform.
1370 static void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
1372 u64 size_bf, size_af;
1374 if (mc->mc_vram_size > 0xE0000000) {
1375 /* leave room for at least 512M GTT */
1376 dev_warn(rdev->dev, "limiting VRAM\n");
1377 mc->real_vram_size = 0xE0000000;
1378 mc->mc_vram_size = 0xE0000000;
1380 if (rdev->flags & RADEON_IS_AGP) {
1381 size_bf = mc->gtt_start;
1382 size_af = mc->mc_mask - mc->gtt_end;
1383 if (size_bf > size_af) {
1384 if (mc->mc_vram_size > size_bf) {
1385 dev_warn(rdev->dev, "limiting VRAM\n");
1386 mc->real_vram_size = size_bf;
1387 mc->mc_vram_size = size_bf;
1389 mc->vram_start = mc->gtt_start - mc->mc_vram_size;
1391 if (mc->mc_vram_size > size_af) {
1392 dev_warn(rdev->dev, "limiting VRAM\n");
1393 mc->real_vram_size = size_af;
1394 mc->mc_vram_size = size_af;
1396 mc->vram_start = mc->gtt_end + 1;
1398 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
1399 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
1400 mc->mc_vram_size >> 20, mc->vram_start,
1401 mc->vram_end, mc->real_vram_size >> 20);
1404 if (rdev->flags & RADEON_IS_IGP) {
1405 base = RREG32(MC_VM_FB_LOCATION) & 0xFFFF;
1408 radeon_vram_location(rdev, &rdev->mc, base);
1409 rdev->mc.gtt_base_align = 0;
1410 radeon_gtt_location(rdev, mc);
1414 static int r600_mc_init(struct radeon_device *rdev)
1417 int chansize, numchan;
1418 uint32_t h_addr, l_addr;
1419 unsigned long long k8_addr;
1421 /* Get VRAM informations */
1422 rdev->mc.vram_is_ddr = true;
1423 tmp = RREG32(RAMCFG);
1424 if (tmp & CHANSIZE_OVERRIDE) {
1426 } else if (tmp & CHANSIZE_MASK) {
1431 tmp = RREG32(CHMAP);
1432 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1447 rdev->mc.vram_width = numchan * chansize;
1448 /* Could aper size report 0 ? */
1449 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
1450 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
1451 /* Setup GPU memory space */
1452 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
1453 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
1454 rdev->mc.visible_vram_size = rdev->mc.aper_size;
1455 r600_vram_gtt_location(rdev, &rdev->mc);
1457 if (rdev->flags & RADEON_IS_IGP) {
1458 rs690_pm_info(rdev);
1459 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
1461 if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) {
1462 /* Use K8 direct mapping for fast fb access. */
1463 rdev->fastfb_working = false;
1464 h_addr = G_000012_K8_ADDR_EXT(RREG32_MC(R_000012_MC_MISC_UMA_CNTL));
1465 l_addr = RREG32_MC(R_000011_K8_FB_LOCATION);
1466 k8_addr = ((unsigned long long)h_addr) << 32 | l_addr;
1467 #if defined(CONFIG_X86_32) && !defined(CONFIG_X86_PAE)
1468 if (k8_addr + rdev->mc.visible_vram_size < 0x100000000ULL)
1471 /* FastFB shall be used with UMA memory. Here it is simply disabled when sideport
1472 * memory is present.
1474 if (rdev->mc.igp_sideport_enabled == false && radeon_fastfb == 1) {
1475 DRM_INFO("Direct mapping: aper base at 0x%llx, replaced by direct mapping base 0x%llx.\n",
1476 (unsigned long long)rdev->mc.aper_base, k8_addr);
1477 rdev->mc.aper_base = (resource_size_t)k8_addr;
1478 rdev->fastfb_working = true;
1484 radeon_update_bandwidth_info(rdev);
1488 int r600_vram_scratch_init(struct radeon_device *rdev)
1491 void *vram_scratch_ptr_ptr = &rdev->vram_scratch.ptr;
1493 if (rdev->vram_scratch.robj == NULL) {
1494 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE,
1495 PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
1496 0, NULL, NULL, &rdev->vram_scratch.robj);
1502 r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
1503 if (unlikely(r != 0))
1505 r = radeon_bo_pin(rdev->vram_scratch.robj,
1506 RADEON_GEM_DOMAIN_VRAM, &rdev->vram_scratch.gpu_addr);
1508 radeon_bo_unreserve(rdev->vram_scratch.robj);
1511 r = radeon_bo_kmap(rdev->vram_scratch.robj,
1512 vram_scratch_ptr_ptr);
1514 radeon_bo_unpin(rdev->vram_scratch.robj);
1515 radeon_bo_unreserve(rdev->vram_scratch.robj);
1520 void r600_vram_scratch_fini(struct radeon_device *rdev)
1524 if (rdev->vram_scratch.robj == NULL) {
1527 r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
1528 if (likely(r == 0)) {
1529 radeon_bo_kunmap(rdev->vram_scratch.robj);
1530 radeon_bo_unpin(rdev->vram_scratch.robj);
1531 radeon_bo_unreserve(rdev->vram_scratch.robj);
1533 radeon_bo_unref(&rdev->vram_scratch.robj);
1536 void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung)
1538 u32 tmp = RREG32(R600_BIOS_3_SCRATCH);
1541 tmp |= ATOM_S3_ASIC_GUI_ENGINE_HUNG;
1543 tmp &= ~ATOM_S3_ASIC_GUI_ENGINE_HUNG;
1545 WREG32(R600_BIOS_3_SCRATCH, tmp);
1548 static void r600_print_gpu_status_regs(struct radeon_device *rdev)
1550 dev_info(rdev->dev, " R_008010_GRBM_STATUS = 0x%08X\n",
1551 RREG32(R_008010_GRBM_STATUS));
1552 dev_info(rdev->dev, " R_008014_GRBM_STATUS2 = 0x%08X\n",
1553 RREG32(R_008014_GRBM_STATUS2));
1554 dev_info(rdev->dev, " R_000E50_SRBM_STATUS = 0x%08X\n",
1555 RREG32(R_000E50_SRBM_STATUS));
1556 dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n",
1557 RREG32(CP_STALLED_STAT1));
1558 dev_info(rdev->dev, " R_008678_CP_STALLED_STAT2 = 0x%08X\n",
1559 RREG32(CP_STALLED_STAT2));
1560 dev_info(rdev->dev, " R_00867C_CP_BUSY_STAT = 0x%08X\n",
1561 RREG32(CP_BUSY_STAT));
1562 dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n",
1564 dev_info(rdev->dev, " R_00D034_DMA_STATUS_REG = 0x%08X\n",
1565 RREG32(DMA_STATUS_REG));
1568 static bool r600_is_display_hung(struct radeon_device *rdev)
1574 for (i = 0; i < rdev->num_crtc; i++) {
1575 if (RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]) & AVIVO_CRTC_EN) {
1576 crtc_status[i] = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT + crtc_offsets[i]);
1577 crtc_hung |= (1 << i);
1581 for (j = 0; j < 10; j++) {
1582 for (i = 0; i < rdev->num_crtc; i++) {
1583 if (crtc_hung & (1 << i)) {
1584 tmp = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT + crtc_offsets[i]);
1585 if (tmp != crtc_status[i])
1586 crtc_hung &= ~(1 << i);
1597 u32 r600_gpu_check_soft_reset(struct radeon_device *rdev)
1603 tmp = RREG32(R_008010_GRBM_STATUS);
1604 if (rdev->family >= CHIP_RV770) {
1605 if (G_008010_PA_BUSY(tmp) | G_008010_SC_BUSY(tmp) |
1606 G_008010_SH_BUSY(tmp) | G_008010_SX_BUSY(tmp) |
1607 G_008010_TA_BUSY(tmp) | G_008010_VGT_BUSY(tmp) |
1608 G_008010_DB03_BUSY(tmp) | G_008010_CB03_BUSY(tmp) |
1609 G_008010_SPI03_BUSY(tmp) | G_008010_VGT_BUSY_NO_DMA(tmp))
1610 reset_mask |= RADEON_RESET_GFX;
1612 if (G_008010_PA_BUSY(tmp) | G_008010_SC_BUSY(tmp) |
1613 G_008010_SH_BUSY(tmp) | G_008010_SX_BUSY(tmp) |
1614 G_008010_TA03_BUSY(tmp) | G_008010_VGT_BUSY(tmp) |
1615 G_008010_DB03_BUSY(tmp) | G_008010_CB03_BUSY(tmp) |
1616 G_008010_SPI03_BUSY(tmp) | G_008010_VGT_BUSY_NO_DMA(tmp))
1617 reset_mask |= RADEON_RESET_GFX;
1620 if (G_008010_CF_RQ_PENDING(tmp) | G_008010_PF_RQ_PENDING(tmp) |
1621 G_008010_CP_BUSY(tmp) | G_008010_CP_COHERENCY_BUSY(tmp))
1622 reset_mask |= RADEON_RESET_CP;
1624 if (G_008010_GRBM_EE_BUSY(tmp))
1625 reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP;
1627 /* DMA_STATUS_REG */
1628 tmp = RREG32(DMA_STATUS_REG);
1629 if (!(tmp & DMA_IDLE))
1630 reset_mask |= RADEON_RESET_DMA;
1633 tmp = RREG32(R_000E50_SRBM_STATUS);
1634 if (G_000E50_RLC_RQ_PENDING(tmp) | G_000E50_RLC_BUSY(tmp))
1635 reset_mask |= RADEON_RESET_RLC;
1637 if (G_000E50_IH_BUSY(tmp))
1638 reset_mask |= RADEON_RESET_IH;
1640 if (G_000E50_SEM_BUSY(tmp))
1641 reset_mask |= RADEON_RESET_SEM;
1643 if (G_000E50_GRBM_RQ_PENDING(tmp))
1644 reset_mask |= RADEON_RESET_GRBM;
1646 if (G_000E50_VMC_BUSY(tmp))
1647 reset_mask |= RADEON_RESET_VMC;
1649 if (G_000E50_MCB_BUSY(tmp) | G_000E50_MCDZ_BUSY(tmp) |
1650 G_000E50_MCDY_BUSY(tmp) | G_000E50_MCDX_BUSY(tmp) |
1651 G_000E50_MCDW_BUSY(tmp))
1652 reset_mask |= RADEON_RESET_MC;
1654 if (r600_is_display_hung(rdev))
1655 reset_mask |= RADEON_RESET_DISPLAY;
1657 /* Skip MC reset as it's mostly likely not hung, just busy */
1658 if (reset_mask & RADEON_RESET_MC) {
1659 DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask);
1660 reset_mask &= ~RADEON_RESET_MC;
1666 static void r600_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
1668 struct rv515_mc_save save;
1669 u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
1672 if (reset_mask == 0)
1675 dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);
1677 r600_print_gpu_status_regs(rdev);
1679 /* Disable CP parsing/prefetching */
1680 if (rdev->family >= CHIP_RV770)
1681 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1) | S_0086D8_CP_PFP_HALT(1));
1683 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1685 /* disable the RLC */
1686 WREG32(RLC_CNTL, 0);
1688 if (reset_mask & RADEON_RESET_DMA) {
1690 tmp = RREG32(DMA_RB_CNTL);
1691 tmp &= ~DMA_RB_ENABLE;
1692 WREG32(DMA_RB_CNTL, tmp);
1697 rv515_mc_stop(rdev, &save);
1698 if (r600_mc_wait_for_idle(rdev)) {
1699 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1702 if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE)) {
1703 if (rdev->family >= CHIP_RV770)
1704 grbm_soft_reset |= S_008020_SOFT_RESET_DB(1) |
1705 S_008020_SOFT_RESET_CB(1) |
1706 S_008020_SOFT_RESET_PA(1) |
1707 S_008020_SOFT_RESET_SC(1) |
1708 S_008020_SOFT_RESET_SPI(1) |
1709 S_008020_SOFT_RESET_SX(1) |
1710 S_008020_SOFT_RESET_SH(1) |
1711 S_008020_SOFT_RESET_TC(1) |
1712 S_008020_SOFT_RESET_TA(1) |
1713 S_008020_SOFT_RESET_VC(1) |
1714 S_008020_SOFT_RESET_VGT(1);
1716 grbm_soft_reset |= S_008020_SOFT_RESET_CR(1) |
1717 S_008020_SOFT_RESET_DB(1) |
1718 S_008020_SOFT_RESET_CB(1) |
1719 S_008020_SOFT_RESET_PA(1) |
1720 S_008020_SOFT_RESET_SC(1) |
1721 S_008020_SOFT_RESET_SMX(1) |
1722 S_008020_SOFT_RESET_SPI(1) |
1723 S_008020_SOFT_RESET_SX(1) |
1724 S_008020_SOFT_RESET_SH(1) |
1725 S_008020_SOFT_RESET_TC(1) |
1726 S_008020_SOFT_RESET_TA(1) |
1727 S_008020_SOFT_RESET_VC(1) |
1728 S_008020_SOFT_RESET_VGT(1);
1731 if (reset_mask & RADEON_RESET_CP) {
1732 grbm_soft_reset |= S_008020_SOFT_RESET_CP(1) |
1733 S_008020_SOFT_RESET_VGT(1);
1735 srbm_soft_reset |= S_000E60_SOFT_RESET_GRBM(1);
1738 if (reset_mask & RADEON_RESET_DMA) {
1739 if (rdev->family >= CHIP_RV770)
1740 srbm_soft_reset |= RV770_SOFT_RESET_DMA;
1742 srbm_soft_reset |= SOFT_RESET_DMA;
1745 if (reset_mask & RADEON_RESET_RLC)
1746 srbm_soft_reset |= S_000E60_SOFT_RESET_RLC(1);
1748 if (reset_mask & RADEON_RESET_SEM)
1749 srbm_soft_reset |= S_000E60_SOFT_RESET_SEM(1);
1751 if (reset_mask & RADEON_RESET_IH)
1752 srbm_soft_reset |= S_000E60_SOFT_RESET_IH(1);
1754 if (reset_mask & RADEON_RESET_GRBM)
1755 srbm_soft_reset |= S_000E60_SOFT_RESET_GRBM(1);
1757 if (!(rdev->flags & RADEON_IS_IGP)) {
1758 if (reset_mask & RADEON_RESET_MC)
1759 srbm_soft_reset |= S_000E60_SOFT_RESET_MC(1);
1762 if (reset_mask & RADEON_RESET_VMC)
1763 srbm_soft_reset |= S_000E60_SOFT_RESET_VMC(1);
1765 if (grbm_soft_reset) {
1766 tmp = RREG32(R_008020_GRBM_SOFT_RESET);
1767 tmp |= grbm_soft_reset;
1768 dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
1769 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
1770 tmp = RREG32(R_008020_GRBM_SOFT_RESET);
1774 tmp &= ~grbm_soft_reset;
1775 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
1776 tmp = RREG32(R_008020_GRBM_SOFT_RESET);
1779 if (srbm_soft_reset) {
1780 tmp = RREG32(SRBM_SOFT_RESET);
1781 tmp |= srbm_soft_reset;
1782 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1783 WREG32(SRBM_SOFT_RESET, tmp);
1784 tmp = RREG32(SRBM_SOFT_RESET);
1788 tmp &= ~srbm_soft_reset;
1789 WREG32(SRBM_SOFT_RESET, tmp);
1790 tmp = RREG32(SRBM_SOFT_RESET);
1793 /* Wait a little for things to settle down */
1796 rv515_mc_resume(rdev, &save);
1799 r600_print_gpu_status_regs(rdev);
1802 static void r600_gpu_pci_config_reset(struct radeon_device *rdev)
1804 struct rv515_mc_save save;
1807 dev_info(rdev->dev, "GPU pci config reset\n");
1811 /* Disable CP parsing/prefetching */
1812 if (rdev->family >= CHIP_RV770)
1813 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1) | S_0086D8_CP_PFP_HALT(1));
1815 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1817 /* disable the RLC */
1818 WREG32(RLC_CNTL, 0);
1821 tmp = RREG32(DMA_RB_CNTL);
1822 tmp &= ~DMA_RB_ENABLE;
1823 WREG32(DMA_RB_CNTL, tmp);
1827 /* set mclk/sclk to bypass */
1828 if (rdev->family >= CHIP_RV770)
1829 rv770_set_clk_bypass_mode(rdev);
1831 pci_clear_master(rdev->pdev);
1832 /* disable mem access */
1833 rv515_mc_stop(rdev, &save);
1834 if (r600_mc_wait_for_idle(rdev)) {
1835 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1838 /* BIF reset workaround. Not sure if this is needed on 6xx */
1839 tmp = RREG32(BUS_CNTL);
1840 tmp |= VGA_COHE_SPEC_TIMER_DIS;
1841 WREG32(BUS_CNTL, tmp);
1843 tmp = RREG32(BIF_SCRATCH0);
1846 radeon_pci_config_reset(rdev);
1849 /* BIF reset workaround. Not sure if this is needed on 6xx */
1850 tmp = SOFT_RESET_BIF;
1851 WREG32(SRBM_SOFT_RESET, tmp);
1853 WREG32(SRBM_SOFT_RESET, 0);
1855 /* wait for asic to come out of reset */
1856 for (i = 0; i < rdev->usec_timeout; i++) {
1857 if (RREG32(CONFIG_MEMSIZE) != 0xffffffff)
1863 int r600_asic_reset(struct radeon_device *rdev, bool hard)
1868 r600_gpu_pci_config_reset(rdev);
1872 reset_mask = r600_gpu_check_soft_reset(rdev);
1875 r600_set_bios_scratch_engine_hung(rdev, true);
1877 /* try soft reset */
1878 r600_gpu_soft_reset(rdev, reset_mask);
1880 reset_mask = r600_gpu_check_soft_reset(rdev);
1882 /* try pci config reset */
1883 if (reset_mask && radeon_hard_reset)
1884 r600_gpu_pci_config_reset(rdev);
1886 reset_mask = r600_gpu_check_soft_reset(rdev);
1889 r600_set_bios_scratch_engine_hung(rdev, false);
1895 * r600_gfx_is_lockup - Check if the GFX engine is locked up
1897 * @rdev: radeon_device pointer
1898 * @ring: radeon_ring structure holding ring information
1900 * Check if the GFX engine is locked up.
1901 * Returns true if the engine appears to be locked up, false if not.
1903 bool r600_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
1905 u32 reset_mask = r600_gpu_check_soft_reset(rdev);
1907 if (!(reset_mask & (RADEON_RESET_GFX |
1908 RADEON_RESET_COMPUTE |
1909 RADEON_RESET_CP))) {
1910 radeon_ring_lockup_update(rdev, ring);
1913 return radeon_ring_test_lockup(rdev, ring);
1916 u32 r6xx_remap_render_backend(struct radeon_device *rdev,
1917 u32 tiling_pipe_num,
1919 u32 total_max_rb_num,
1920 u32 disabled_rb_mask)
1922 u32 rendering_pipe_num, rb_num_width, req_rb_num;
1923 u32 pipe_rb_ratio, pipe_rb_remain, tmp;
1924 u32 data = 0, mask = 1 << (max_rb_num - 1);
1927 /* mask out the RBs that don't exist on that asic */
1928 tmp = disabled_rb_mask | ((0xff << max_rb_num) & 0xff);
1929 /* make sure at least one RB is available */
1930 if ((tmp & 0xff) != 0xff)
1931 disabled_rb_mask = tmp;
1933 rendering_pipe_num = 1 << tiling_pipe_num;
1934 req_rb_num = total_max_rb_num - r600_count_pipe_bits(disabled_rb_mask);
1935 BUG_ON(rendering_pipe_num < req_rb_num);
1937 pipe_rb_ratio = rendering_pipe_num / req_rb_num;
1938 pipe_rb_remain = rendering_pipe_num - pipe_rb_ratio * req_rb_num;
1940 if (rdev->family <= CHIP_RV740) {
1948 for (i = 0; i < max_rb_num; i++) {
1949 if (!(mask & disabled_rb_mask)) {
1950 for (j = 0; j < pipe_rb_ratio; j++) {
1951 data <<= rb_num_width;
1952 data |= max_rb_num - i - 1;
1954 if (pipe_rb_remain) {
1955 data <<= rb_num_width;
1956 data |= max_rb_num - i - 1;
1966 int r600_count_pipe_bits(uint32_t val)
1968 return hweight32(val);
1971 static void r600_gpu_init(struct radeon_device *rdev)
1975 u32 cc_gc_shader_pipe_config;
1979 u32 sq_gpr_resource_mgmt_1 = 0;
1980 u32 sq_gpr_resource_mgmt_2 = 0;
1981 u32 sq_thread_resource_mgmt = 0;
1982 u32 sq_stack_resource_mgmt_1 = 0;
1983 u32 sq_stack_resource_mgmt_2 = 0;
1984 u32 disabled_rb_mask;
1986 rdev->config.r600.tiling_group_size = 256;
1987 switch (rdev->family) {
1989 rdev->config.r600.max_pipes = 4;
1990 rdev->config.r600.max_tile_pipes = 8;
1991 rdev->config.r600.max_simds = 4;
1992 rdev->config.r600.max_backends = 4;
1993 rdev->config.r600.max_gprs = 256;
1994 rdev->config.r600.max_threads = 192;
1995 rdev->config.r600.max_stack_entries = 256;
1996 rdev->config.r600.max_hw_contexts = 8;
1997 rdev->config.r600.max_gs_threads = 16;
1998 rdev->config.r600.sx_max_export_size = 128;
1999 rdev->config.r600.sx_max_export_pos_size = 16;
2000 rdev->config.r600.sx_max_export_smx_size = 128;
2001 rdev->config.r600.sq_num_cf_insts = 2;
2005 rdev->config.r600.max_pipes = 2;
2006 rdev->config.r600.max_tile_pipes = 2;
2007 rdev->config.r600.max_simds = 3;
2008 rdev->config.r600.max_backends = 1;
2009 rdev->config.r600.max_gprs = 128;
2010 rdev->config.r600.max_threads = 192;
2011 rdev->config.r600.max_stack_entries = 128;
2012 rdev->config.r600.max_hw_contexts = 8;
2013 rdev->config.r600.max_gs_threads = 4;
2014 rdev->config.r600.sx_max_export_size = 128;
2015 rdev->config.r600.sx_max_export_pos_size = 16;
2016 rdev->config.r600.sx_max_export_smx_size = 128;
2017 rdev->config.r600.sq_num_cf_insts = 2;
2023 rdev->config.r600.max_pipes = 1;
2024 rdev->config.r600.max_tile_pipes = 1;
2025 rdev->config.r600.max_simds = 2;
2026 rdev->config.r600.max_backends = 1;
2027 rdev->config.r600.max_gprs = 128;
2028 rdev->config.r600.max_threads = 192;
2029 rdev->config.r600.max_stack_entries = 128;
2030 rdev->config.r600.max_hw_contexts = 4;
2031 rdev->config.r600.max_gs_threads = 4;
2032 rdev->config.r600.sx_max_export_size = 128;
2033 rdev->config.r600.sx_max_export_pos_size = 16;
2034 rdev->config.r600.sx_max_export_smx_size = 128;
2035 rdev->config.r600.sq_num_cf_insts = 1;
2038 rdev->config.r600.max_pipes = 4;
2039 rdev->config.r600.max_tile_pipes = 4;
2040 rdev->config.r600.max_simds = 4;
2041 rdev->config.r600.max_backends = 4;
2042 rdev->config.r600.max_gprs = 192;
2043 rdev->config.r600.max_threads = 192;
2044 rdev->config.r600.max_stack_entries = 256;
2045 rdev->config.r600.max_hw_contexts = 8;
2046 rdev->config.r600.max_gs_threads = 16;
2047 rdev->config.r600.sx_max_export_size = 128;
2048 rdev->config.r600.sx_max_export_pos_size = 16;
2049 rdev->config.r600.sx_max_export_smx_size = 128;
2050 rdev->config.r600.sq_num_cf_insts = 2;
2056 /* Initialize HDP */
2057 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
2058 WREG32((0x2c14 + j), 0x00000000);
2059 WREG32((0x2c18 + j), 0x00000000);
2060 WREG32((0x2c1c + j), 0x00000000);
2061 WREG32((0x2c20 + j), 0x00000000);
2062 WREG32((0x2c24 + j), 0x00000000);
2065 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
2069 ramcfg = RREG32(RAMCFG);
2070 switch (rdev->config.r600.max_tile_pipes) {
2072 tiling_config |= PIPE_TILING(0);
2075 tiling_config |= PIPE_TILING(1);
2078 tiling_config |= PIPE_TILING(2);
2081 tiling_config |= PIPE_TILING(3);
2086 rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes;
2087 rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
2088 tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
2089 tiling_config |= GROUP_SIZE((ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
2091 tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
2093 tiling_config |= ROW_TILING(3);
2094 tiling_config |= SAMPLE_SPLIT(3);
2096 tiling_config |= ROW_TILING(tmp);
2097 tiling_config |= SAMPLE_SPLIT(tmp);
2099 tiling_config |= BANK_SWAPS(1);
2101 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0x00ffff00;
2102 tmp = rdev->config.r600.max_simds -
2103 r600_count_pipe_bits((cc_gc_shader_pipe_config >> 16) & R6XX_MAX_SIMDS_MASK);
2104 rdev->config.r600.active_simds = tmp;
2106 disabled_rb_mask = (RREG32(CC_RB_BACKEND_DISABLE) >> 16) & R6XX_MAX_BACKENDS_MASK;
2108 for (i = 0; i < rdev->config.r600.max_backends; i++)
2110 /* if all the backends are disabled, fix it up here */
2111 if ((disabled_rb_mask & tmp) == tmp) {
2112 for (i = 0; i < rdev->config.r600.max_backends; i++)
2113 disabled_rb_mask &= ~(1 << i);
2115 tmp = (tiling_config & PIPE_TILING__MASK) >> PIPE_TILING__SHIFT;
2116 tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.r600.max_backends,
2117 R6XX_MAX_BACKENDS, disabled_rb_mask);
2118 tiling_config |= tmp << 16;
2119 rdev->config.r600.backend_map = tmp;
2121 rdev->config.r600.tile_config = tiling_config;
2122 WREG32(GB_TILING_CONFIG, tiling_config);
2123 WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);
2124 WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff);
2125 WREG32(DMA_TILING_CONFIG, tiling_config & 0xffff);
2127 tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
2128 WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);
2129 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK);
2131 /* Setup some CP states */
2132 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b)));
2133 WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40)));
2135 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT |
2136 SYNC_WALKER | SYNC_ALIGNER));
2137 /* Setup various GPU states */
2138 if (rdev->family == CHIP_RV670)
2139 WREG32(ARB_GDEC_RD_CNTL, 0x00000021);
2141 tmp = RREG32(SX_DEBUG_1);
2142 tmp |= SMX_EVENT_RELEASE;
2143 if ((rdev->family > CHIP_R600))
2144 tmp |= ENABLE_NEW_SMX_ADDRESS;
2145 WREG32(SX_DEBUG_1, tmp);
2147 if (((rdev->family) == CHIP_R600) ||
2148 ((rdev->family) == CHIP_RV630) ||
2149 ((rdev->family) == CHIP_RV610) ||
2150 ((rdev->family) == CHIP_RV620) ||
2151 ((rdev->family) == CHIP_RS780) ||
2152 ((rdev->family) == CHIP_RS880)) {
2153 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE);
2155 WREG32(DB_DEBUG, 0);
2157 WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) |
2158 DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4)));
2160 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
2161 WREG32(VGT_NUM_INSTANCES, 0);
2163 WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
2164 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0));
2166 tmp = RREG32(SQ_MS_FIFO_SIZES);
2167 if (((rdev->family) == CHIP_RV610) ||
2168 ((rdev->family) == CHIP_RV620) ||
2169 ((rdev->family) == CHIP_RS780) ||
2170 ((rdev->family) == CHIP_RS880)) {
2171 tmp = (CACHE_FIFO_SIZE(0xa) |
2172 FETCH_FIFO_HIWATER(0xa) |
2173 DONE_FIFO_HIWATER(0xe0) |
2174 ALU_UPDATE_FIFO_HIWATER(0x8));
2175 } else if (((rdev->family) == CHIP_R600) ||
2176 ((rdev->family) == CHIP_RV630)) {
2177 tmp &= ~DONE_FIFO_HIWATER(0xff);
2178 tmp |= DONE_FIFO_HIWATER(0x4);
2180 WREG32(SQ_MS_FIFO_SIZES, tmp);
2182 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
2183 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
2185 sq_config = RREG32(SQ_CONFIG);
2186 sq_config &= ~(PS_PRIO(3) |
2190 sq_config |= (DX9_CONSTS |
2197 if ((rdev->family) == CHIP_R600) {
2198 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) |
2200 NUM_CLAUSE_TEMP_GPRS(4));
2201 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) |
2203 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) |
2204 NUM_VS_THREADS(48) |
2207 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) |
2208 NUM_VS_STACK_ENTRIES(128));
2209 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) |
2210 NUM_ES_STACK_ENTRIES(0));
2211 } else if (((rdev->family) == CHIP_RV610) ||
2212 ((rdev->family) == CHIP_RV620) ||
2213 ((rdev->family) == CHIP_RS780) ||
2214 ((rdev->family) == CHIP_RS880)) {
2215 /* no vertex cache */
2216 sq_config &= ~VC_ENABLE;
2218 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
2220 NUM_CLAUSE_TEMP_GPRS(2));
2221 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
2223 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
2224 NUM_VS_THREADS(78) |
2226 NUM_ES_THREADS(31));
2227 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
2228 NUM_VS_STACK_ENTRIES(40));
2229 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
2230 NUM_ES_STACK_ENTRIES(16));
2231 } else if (((rdev->family) == CHIP_RV630) ||
2232 ((rdev->family) == CHIP_RV635)) {
2233 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
2235 NUM_CLAUSE_TEMP_GPRS(2));
2236 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) |
2238 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
2239 NUM_VS_THREADS(78) |
2241 NUM_ES_THREADS(31));
2242 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
2243 NUM_VS_STACK_ENTRIES(40));
2244 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
2245 NUM_ES_STACK_ENTRIES(16));
2246 } else if ((rdev->family) == CHIP_RV670) {
2247 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
2249 NUM_CLAUSE_TEMP_GPRS(2));
2250 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
2252 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
2253 NUM_VS_THREADS(78) |
2255 NUM_ES_THREADS(31));
2256 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) |
2257 NUM_VS_STACK_ENTRIES(64));
2258 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) |
2259 NUM_ES_STACK_ENTRIES(64));
2262 WREG32(SQ_CONFIG, sq_config);
2263 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
2264 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
2265 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
2266 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
2267 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
2269 if (((rdev->family) == CHIP_RV610) ||
2270 ((rdev->family) == CHIP_RV620) ||
2271 ((rdev->family) == CHIP_RS780) ||
2272 ((rdev->family) == CHIP_RS880)) {
2273 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY));
2275 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC));
2278 /* More default values. 2D/3D driver should adjust as needed */
2279 WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) |
2280 S1_X(0x4) | S1_Y(0xc)));
2281 WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) |
2282 S1_X(0x2) | S1_Y(0x2) |
2283 S2_X(0xa) | S2_Y(0x6) |
2284 S3_X(0x6) | S3_Y(0xa)));
2285 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) |
2286 S1_X(0x4) | S1_Y(0xc) |
2287 S2_X(0x1) | S2_Y(0x6) |
2288 S3_X(0xa) | S3_Y(0xe)));
2289 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) |
2290 S5_X(0x0) | S5_Y(0x0) |
2291 S6_X(0xb) | S6_Y(0x4) |
2292 S7_X(0x7) | S7_Y(0x8)));
2294 WREG32(VGT_STRMOUT_EN, 0);
2295 tmp = rdev->config.r600.max_pipes * 16;
2296 switch (rdev->family) {
2312 WREG32(VGT_ES_PER_GS, 128);
2313 WREG32(VGT_GS_PER_ES, tmp);
2314 WREG32(VGT_GS_PER_VS, 2);
2315 WREG32(VGT_GS_VERTEX_REUSE, 16);
2317 /* more default values. 2D/3D driver should adjust as needed */
2318 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
2319 WREG32(VGT_STRMOUT_EN, 0);
2321 WREG32(PA_SC_MODE_CNTL, 0);
2322 WREG32(PA_SC_AA_CONFIG, 0);
2323 WREG32(PA_SC_LINE_STIPPLE, 0);
2324 WREG32(SPI_INPUT_Z, 0);
2325 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
2326 WREG32(CB_COLOR7_FRAG, 0);
2328 /* Clear render buffer base addresses */
2329 WREG32(CB_COLOR0_BASE, 0);
2330 WREG32(CB_COLOR1_BASE, 0);
2331 WREG32(CB_COLOR2_BASE, 0);
2332 WREG32(CB_COLOR3_BASE, 0);
2333 WREG32(CB_COLOR4_BASE, 0);
2334 WREG32(CB_COLOR5_BASE, 0);
2335 WREG32(CB_COLOR6_BASE, 0);
2336 WREG32(CB_COLOR7_BASE, 0);
2337 WREG32(CB_COLOR7_FRAG, 0);
2339 switch (rdev->family) {
2344 tmp = TC_L2_SIZE(8);
2348 tmp = TC_L2_SIZE(4);
2351 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT;
2354 tmp = TC_L2_SIZE(0);
2357 WREG32(TC_CNTL, tmp);
2359 tmp = RREG32(HDP_HOST_PATH_CNTL);
2360 WREG32(HDP_HOST_PATH_CNTL, tmp);
2362 tmp = RREG32(ARB_POP);
2363 tmp |= ENABLE_TC128;
2364 WREG32(ARB_POP, tmp);
2366 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
2367 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
2369 WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));
2370 WREG32(VC_ENHANCE, 0);
2375 * Indirect registers accessor
2377 u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg)
2381 spin_lock(&rdev->pciep_idx_lock);
2382 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
2383 (void)RREG32(PCIE_PORT_INDEX);
2384 r = RREG32(PCIE_PORT_DATA);
2385 spin_unlock(&rdev->pciep_idx_lock);
2389 void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2391 spin_lock(&rdev->pciep_idx_lock);
2392 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
2393 (void)RREG32(PCIE_PORT_INDEX);
2394 WREG32(PCIE_PORT_DATA, (v));
2395 (void)RREG32(PCIE_PORT_DATA);
2396 spin_unlock(&rdev->pciep_idx_lock);
2402 void r600_cp_stop(struct radeon_device *rdev)
2404 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
2405 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
2406 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
2407 WREG32(SCRATCH_UMSK, 0);
2408 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
2411 int r600_init_microcode(struct radeon_device *rdev)
2413 const char *chip_name;
2414 const char *rlc_chip_name;
2415 const char *smc_chip_name = "RV770";
2416 size_t pfp_req_size, me_req_size, rlc_req_size, smc_req_size = 0;
2422 switch (rdev->family) {
2425 rlc_chip_name = "R600";
2428 chip_name = "RV610";
2429 rlc_chip_name = "R600";
2432 chip_name = "RV630";
2433 rlc_chip_name = "R600";
2436 chip_name = "RV620";
2437 rlc_chip_name = "R600";
2440 chip_name = "RV635";
2441 rlc_chip_name = "R600";
2444 chip_name = "RV670";
2445 rlc_chip_name = "R600";
2449 chip_name = "RS780";
2450 rlc_chip_name = "R600";
2453 chip_name = "RV770";
2454 rlc_chip_name = "R700";
2455 smc_chip_name = "RV770";
2456 smc_req_size = ALIGN(RV770_SMC_UCODE_SIZE, 4);
2459 chip_name = "RV730";
2460 rlc_chip_name = "R700";
2461 smc_chip_name = "RV730";
2462 smc_req_size = ALIGN(RV730_SMC_UCODE_SIZE, 4);
2465 chip_name = "RV710";
2466 rlc_chip_name = "R700";
2467 smc_chip_name = "RV710";
2468 smc_req_size = ALIGN(RV710_SMC_UCODE_SIZE, 4);
2471 chip_name = "RV730";
2472 rlc_chip_name = "R700";
2473 smc_chip_name = "RV740";
2474 smc_req_size = ALIGN(RV740_SMC_UCODE_SIZE, 4);
2477 chip_name = "CEDAR";
2478 rlc_chip_name = "CEDAR";
2479 smc_chip_name = "CEDAR";
2480 smc_req_size = ALIGN(CEDAR_SMC_UCODE_SIZE, 4);
2483 chip_name = "REDWOOD";
2484 rlc_chip_name = "REDWOOD";
2485 smc_chip_name = "REDWOOD";
2486 smc_req_size = ALIGN(REDWOOD_SMC_UCODE_SIZE, 4);
2489 chip_name = "JUNIPER";
2490 rlc_chip_name = "JUNIPER";
2491 smc_chip_name = "JUNIPER";
2492 smc_req_size = ALIGN(JUNIPER_SMC_UCODE_SIZE, 4);
2496 chip_name = "CYPRESS";
2497 rlc_chip_name = "CYPRESS";
2498 smc_chip_name = "CYPRESS";
2499 smc_req_size = ALIGN(CYPRESS_SMC_UCODE_SIZE, 4);
2503 rlc_chip_name = "SUMO";
2507 rlc_chip_name = "SUMO";
2510 chip_name = "SUMO2";
2511 rlc_chip_name = "SUMO";
2516 if (rdev->family >= CHIP_CEDAR) {
2517 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
2518 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
2519 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
2520 } else if (rdev->family >= CHIP_RV770) {
2521 pfp_req_size = R700_PFP_UCODE_SIZE * 4;
2522 me_req_size = R700_PM4_UCODE_SIZE * 4;
2523 rlc_req_size = R700_RLC_UCODE_SIZE * 4;
2525 pfp_req_size = R600_PFP_UCODE_SIZE * 4;
2526 me_req_size = R600_PM4_UCODE_SIZE * 12;
2527 rlc_req_size = R600_RLC_UCODE_SIZE * 4;
2530 DRM_INFO("Loading %s Microcode\n", chip_name);
2532 ksnprintf(fw_name, sizeof(fw_name), "radeonkmsfw_%s_pfp", chip_name);
2533 err = request_firmware(&rdev->pfp_fw, fw_name, rdev->dev);
2536 if (rdev->pfp_fw->datasize != pfp_req_size) {
2538 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
2539 rdev->pfp_fw->datasize, fw_name);
2544 ksnprintf(fw_name, sizeof(fw_name), "radeonkmsfw_%s_me", chip_name);
2545 err = request_firmware(&rdev->me_fw, fw_name, rdev->dev);
2548 if (rdev->me_fw->datasize != me_req_size) {
2550 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
2551 rdev->me_fw->datasize, fw_name);
2555 ksnprintf(fw_name, sizeof(fw_name), "radeonkmsfw_%s_rlc", rlc_chip_name);
2556 err = request_firmware(&rdev->rlc_fw, fw_name, rdev->dev);
2559 if (rdev->rlc_fw->datasize != rlc_req_size) {
2561 "r600_rlc: Bogus length %zu in firmware \"%s\"\n",
2562 rdev->rlc_fw->datasize, fw_name);
2566 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_HEMLOCK)) {
2567 ksnprintf(fw_name, sizeof(fw_name), "radeonkmsfw_%s_smc", smc_chip_name);
2569 err = request_firmware(&rdev->smc_fw, fw_name, rdev->dev);
2572 "smc: error loading firmware \"%s\"\n",
2574 release_firmware(rdev->smc_fw);
2575 rdev->smc_fw = NULL;
2577 } else if (rdev->smc_fw->datasize != smc_req_size) {
2579 "smc: Bogus length %zu in firmware \"%s\"\n",
2580 rdev->smc_fw->datasize, fw_name);
2589 "r600_cp: Failed to load firmware \"%s\"\n",
2591 release_firmware(rdev->pfp_fw);
2592 rdev->pfp_fw = NULL;
2593 release_firmware(rdev->me_fw);
2595 release_firmware(rdev->rlc_fw);
2596 rdev->rlc_fw = NULL;
2597 release_firmware(rdev->smc_fw);
2598 rdev->smc_fw = NULL;
2603 u32 r600_gfx_get_rptr(struct radeon_device *rdev,
2604 struct radeon_ring *ring)
2608 if (rdev->wb.enabled)
2609 rptr = rdev->wb.wb[ring->rptr_offs/4];
2611 rptr = RREG32(R600_CP_RB_RPTR);
2616 u32 r600_gfx_get_wptr(struct radeon_device *rdev,
2617 struct radeon_ring *ring)
2621 wptr = RREG32(R600_CP_RB_WPTR);
2626 void r600_gfx_set_wptr(struct radeon_device *rdev,
2627 struct radeon_ring *ring)
2629 WREG32(R600_CP_RB_WPTR, ring->wptr);
2630 (void)RREG32(R600_CP_RB_WPTR);
2634 * r600_fini_microcode - drop the firmwares image references
2636 * @rdev: radeon_device pointer
2638 * Drop the pfp, me and rlc firmwares image references.
2639 * Called at driver shutdown.
2641 void r600_fini_microcode(struct radeon_device *rdev)
2643 release_firmware(rdev->pfp_fw);
2644 rdev->pfp_fw = NULL;
2645 release_firmware(rdev->me_fw);
2647 release_firmware(rdev->rlc_fw);
2648 rdev->rlc_fw = NULL;
2649 release_firmware(rdev->smc_fw);
2650 rdev->smc_fw = NULL;
2653 static int r600_cp_load_microcode(struct radeon_device *rdev)
2655 const __be32 *fw_data;
2658 if (!rdev->me_fw || !rdev->pfp_fw)
2667 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
2670 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2671 RREG32(GRBM_SOFT_RESET);
2673 WREG32(GRBM_SOFT_RESET, 0);
2675 WREG32(CP_ME_RAM_WADDR, 0);
2677 fw_data = (const __be32 *)rdev->me_fw->data;
2678 WREG32(CP_ME_RAM_WADDR, 0);
2679 for (i = 0; i < R600_PM4_UCODE_SIZE * 3; i++)
2680 WREG32(CP_ME_RAM_DATA,
2681 be32_to_cpup(fw_data++));
2683 fw_data = (const __be32 *)rdev->pfp_fw->data;
2684 WREG32(CP_PFP_UCODE_ADDR, 0);
2685 for (i = 0; i < R600_PFP_UCODE_SIZE; i++)
2686 WREG32(CP_PFP_UCODE_DATA,
2687 be32_to_cpup(fw_data++));
2689 WREG32(CP_PFP_UCODE_ADDR, 0);
2690 WREG32(CP_ME_RAM_WADDR, 0);
2691 WREG32(CP_ME_RAM_RADDR, 0);
2695 int r600_cp_start(struct radeon_device *rdev)
2697 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2701 r = radeon_ring_lock(rdev, ring, 7);
2703 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
2706 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
2707 radeon_ring_write(ring, 0x1);
2708 if (rdev->family >= CHIP_RV770) {
2709 radeon_ring_write(ring, 0x0);
2710 radeon_ring_write(ring, rdev->config.rv770.max_hw_contexts - 1);
2712 radeon_ring_write(ring, 0x3);
2713 radeon_ring_write(ring, rdev->config.r600.max_hw_contexts - 1);
2715 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
2716 radeon_ring_write(ring, 0);
2717 radeon_ring_write(ring, 0);
2718 radeon_ring_unlock_commit(rdev, ring, false);
2721 WREG32(R_0086D8_CP_ME_CNTL, cp_me);
2725 int r600_cp_resume(struct radeon_device *rdev)
2727 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2733 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2734 RREG32(GRBM_SOFT_RESET);
2736 WREG32(GRBM_SOFT_RESET, 0);
2738 /* Set ring buffer size */
2739 rb_bufsz = order_base_2(ring->ring_size / 8);
2740 tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2742 tmp |= BUF_SWAP_32BIT;
2744 WREG32(CP_RB_CNTL, tmp);
2745 WREG32(CP_SEM_WAIT_TIMER, 0x0);
2747 /* Set the write pointer delay */
2748 WREG32(CP_RB_WPTR_DELAY, 0);
2750 /* Initialize the ring buffer's read and write pointers */
2751 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
2752 WREG32(CP_RB_RPTR_WR, 0);
2754 WREG32(CP_RB_WPTR, ring->wptr);
2756 /* set the wb address whether it's enabled or not */
2757 WREG32(CP_RB_RPTR_ADDR,
2758 ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC));
2759 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
2760 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
2762 if (rdev->wb.enabled)
2763 WREG32(SCRATCH_UMSK, 0xff);
2765 tmp |= RB_NO_UPDATE;
2766 WREG32(SCRATCH_UMSK, 0);
2770 WREG32(CP_RB_CNTL, tmp);
2772 WREG32(CP_RB_BASE, ring->gpu_addr >> 8);
2773 WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
2775 r600_cp_start(rdev);
2777 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
2779 ring->ready = false;
2783 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
2784 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
2789 void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size)
2794 /* Align ring size */
2795 rb_bufsz = order_base_2(ring_size / 8);
2796 ring_size = (1 << (rb_bufsz + 1)) * 4;
2797 ring->ring_size = ring_size;
2798 ring->align_mask = 16 - 1;
2800 if (radeon_ring_supports_scratch_reg(rdev, ring)) {
2801 r = radeon_scratch_get(rdev, &ring->rptr_save_reg);
2803 DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r);
2804 ring->rptr_save_reg = 0;
2809 void r600_cp_fini(struct radeon_device *rdev)
2811 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2813 radeon_ring_fini(rdev, ring);
2814 radeon_scratch_free(rdev, ring->rptr_save_reg);
2818 * GPU scratch registers helpers function.
2820 void r600_scratch_init(struct radeon_device *rdev)
2824 rdev->scratch.num_reg = 7;
2825 rdev->scratch.reg_base = SCRATCH_REG0;
2826 for (i = 0; i < rdev->scratch.num_reg; i++) {
2827 rdev->scratch.free[i] = true;
2828 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
2832 int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
2839 r = radeon_scratch_get(rdev, &scratch);
2841 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
2844 WREG32(scratch, 0xCAFEDEAD);
2845 r = radeon_ring_lock(rdev, ring, 3);
2847 DRM_ERROR("radeon: cp failed to lock ring %d (%d).\n", ring->idx, r);
2848 radeon_scratch_free(rdev, scratch);
2851 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2852 radeon_ring_write(ring, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2853 radeon_ring_write(ring, 0xDEADBEEF);
2854 radeon_ring_unlock_commit(rdev, ring, false);
2855 for (i = 0; i < rdev->usec_timeout; i++) {
2856 tmp = RREG32(scratch);
2857 if (tmp == 0xDEADBEEF)
2861 if (i < rdev->usec_timeout) {
2862 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
2864 DRM_ERROR("radeon: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
2865 ring->idx, scratch, tmp);
2868 radeon_scratch_free(rdev, scratch);
2873 * CP fences/semaphores
2876 void r600_fence_ring_emit(struct radeon_device *rdev,
2877 struct radeon_fence *fence)
2879 struct radeon_ring *ring = &rdev->ring[fence->ring];
2880 u32 cp_coher_cntl = PACKET3_TC_ACTION_ENA | PACKET3_VC_ACTION_ENA |
2881 PACKET3_SH_ACTION_ENA;
2883 if (rdev->family >= CHIP_RV770)
2884 cp_coher_cntl |= PACKET3_FULL_CACHE_ENA;
2886 if (rdev->wb.use_event) {
2887 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
2888 /* flush read cache over gart */
2889 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
2890 radeon_ring_write(ring, cp_coher_cntl);
2891 radeon_ring_write(ring, 0xFFFFFFFF);
2892 radeon_ring_write(ring, 0);
2893 radeon_ring_write(ring, 10); /* poll interval */
2894 /* EVENT_WRITE_EOP - flush caches, send int */
2895 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
2896 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5));
2897 radeon_ring_write(ring, lower_32_bits(addr));
2898 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
2899 radeon_ring_write(ring, fence->seq);
2900 radeon_ring_write(ring, 0);
2902 /* flush read cache over gart */
2903 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
2904 radeon_ring_write(ring, cp_coher_cntl);
2905 radeon_ring_write(ring, 0xFFFFFFFF);
2906 radeon_ring_write(ring, 0);
2907 radeon_ring_write(ring, 10); /* poll interval */
2908 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
2909 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0));
2910 /* wait for 3D idle clean */
2911 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2912 radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2913 radeon_ring_write(ring, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit);
2914 /* Emit fence sequence & fire IRQ */
2915 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2916 radeon_ring_write(ring, ((rdev->fence_drv[fence->ring].scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2917 radeon_ring_write(ring, fence->seq);
2918 /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */
2919 radeon_ring_write(ring, PACKET0(CP_INT_STATUS, 0));
2920 radeon_ring_write(ring, RB_INT_STAT);
2925 * r600_semaphore_ring_emit - emit a semaphore on the CP ring
2927 * @rdev: radeon_device pointer
2928 * @ring: radeon ring buffer object
2929 * @semaphore: radeon semaphore object
2930 * @emit_wait: Is this a sempahore wait?
2932 * Emits a semaphore signal/wait packet to the CP ring and prevents the PFP
2933 * from running ahead of semaphore waits.
2935 bool r600_semaphore_ring_emit(struct radeon_device *rdev,
2936 struct radeon_ring *ring,
2937 struct radeon_semaphore *semaphore,
2940 uint64_t addr = semaphore->gpu_addr;
2941 unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL;
2943 if (rdev->family < CHIP_CAYMAN)
2944 sel |= PACKET3_SEM_WAIT_ON_SIGNAL;
2946 radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1));
2947 radeon_ring_write(ring, lower_32_bits(addr));
2948 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | sel);
2950 /* PFP_SYNC_ME packet only exists on 7xx+, only enable it on eg+ */
2951 if (emit_wait && (rdev->family >= CHIP_CEDAR)) {
2952 /* Prevent the PFP from running ahead of the semaphore wait */
2953 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
2954 radeon_ring_write(ring, 0x0);
2961 * r600_copy_cpdma - copy pages using the CP DMA engine
2963 * @rdev: radeon_device pointer
2964 * @src_offset: src GPU address
2965 * @dst_offset: dst GPU address
2966 * @num_gpu_pages: number of GPU pages to xfer
2967 * @fence: radeon fence object
2969 * Copy GPU paging using the CP DMA engine (r6xx+).
2970 * Used by the radeon ttm implementation to move pages if
2971 * registered as the asic copy callback.
2973 struct radeon_fence *r600_copy_cpdma(struct radeon_device *rdev,
2974 uint64_t src_offset, uint64_t dst_offset,
2975 unsigned num_gpu_pages,
2976 struct reservation_object *resv)
2978 struct radeon_fence *fence;
2979 struct radeon_sync sync;
2980 int ring_index = rdev->asic->copy.blit_ring_index;
2981 struct radeon_ring *ring = &rdev->ring[ring_index];
2982 u32 size_in_bytes, cur_size_in_bytes, tmp;
2986 radeon_sync_create(&sync);
2988 size_in_bytes = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT);
2989 num_loops = DIV_ROUND_UP(size_in_bytes, 0x1fffff);
2990 r = radeon_ring_lock(rdev, ring, num_loops * 6 + 24);
2992 DRM_ERROR("radeon: moving bo (%d).\n", r);
2993 radeon_sync_free(rdev, &sync, NULL);
2997 radeon_sync_resv(rdev, &sync, resv, false);
2998 radeon_sync_rings(rdev, &sync, ring->idx);
3000 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
3001 radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
3002 radeon_ring_write(ring, WAIT_3D_IDLE_bit);
3003 for (i = 0; i < num_loops; i++) {
3004 cur_size_in_bytes = size_in_bytes;
3005 if (cur_size_in_bytes > 0x1fffff)
3006 cur_size_in_bytes = 0x1fffff;
3007 size_in_bytes -= cur_size_in_bytes;
3008 tmp = upper_32_bits(src_offset) & 0xff;
3009 if (size_in_bytes == 0)
3010 tmp |= PACKET3_CP_DMA_CP_SYNC;
3011 radeon_ring_write(ring, PACKET3(PACKET3_CP_DMA, 4));
3012 radeon_ring_write(ring, lower_32_bits(src_offset));
3013 radeon_ring_write(ring, tmp);
3014 radeon_ring_write(ring, lower_32_bits(dst_offset));
3015 radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff);
3016 radeon_ring_write(ring, cur_size_in_bytes);
3017 src_offset += cur_size_in_bytes;
3018 dst_offset += cur_size_in_bytes;
3020 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
3021 radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
3022 radeon_ring_write(ring, WAIT_CP_DMA_IDLE_bit);
3024 r = radeon_fence_emit(rdev, &fence, ring->idx);
3026 radeon_ring_unlock_undo(rdev, ring);
3027 radeon_sync_free(rdev, &sync, NULL);
3031 radeon_ring_unlock_commit(rdev, ring, false);
3032 radeon_sync_free(rdev, &sync, fence);
3037 int r600_set_surface_reg(struct radeon_device *rdev, int reg,
3038 uint32_t tiling_flags, uint32_t pitch,
3039 uint32_t offset, uint32_t obj_size)
3041 /* FIXME: implement */
3045 void r600_clear_surface_reg(struct radeon_device *rdev, int reg)
3047 /* FIXME: implement */
3050 static void r600_uvd_init(struct radeon_device *rdev)
3057 r = radeon_uvd_init(rdev);
3059 dev_err(rdev->dev, "failed UVD (%d) init.\n", r);
3061 * At this point rdev->uvd.vcpu_bo is NULL which trickles down
3062 * to early fails uvd_v1_0_resume() and thus nothing happens
3063 * there. So it is pointless to try to go through that code
3064 * hence why we disable uvd here.
3069 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_obj = NULL;
3070 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX], 4096);
3073 static void r600_uvd_start(struct radeon_device *rdev)
3080 r = uvd_v1_0_resume(rdev);
3082 dev_err(rdev->dev, "failed UVD resume (%d).\n", r);
3085 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_UVD_INDEX);
3087 dev_err(rdev->dev, "failed initializing UVD fences (%d).\n", r);
3093 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0;
3096 static void r600_uvd_resume(struct radeon_device *rdev)
3098 struct radeon_ring *ring;
3101 if (!rdev->has_uvd || !rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size)
3104 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
3105 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, RADEON_CP_PACKET2);
3107 dev_err(rdev->dev, "failed initializing UVD ring (%d).\n", r);
3110 r = uvd_v1_0_init(rdev);
3112 dev_err(rdev->dev, "failed initializing UVD (%d).\n", r);
3117 static int r600_startup(struct radeon_device *rdev)
3119 struct radeon_ring *ring;
3122 /* enable pcie gen2 link */
3123 r600_pcie_gen2_enable(rdev);
3125 /* scratch needs to be initialized before MC */
3126 r = r600_vram_scratch_init(rdev);
3130 r600_mc_program(rdev);
3132 if (rdev->flags & RADEON_IS_AGP) {
3133 r600_agp_enable(rdev);
3135 r = r600_pcie_gart_enable(rdev);
3139 r600_gpu_init(rdev);
3141 /* allocate wb buffer */
3142 r = radeon_wb_init(rdev);
3146 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
3148 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
3152 r600_uvd_start(rdev);
3155 if (!rdev->irq.installed) {
3156 r = radeon_irq_kms_init(rdev);
3161 r = r600_irq_init(rdev);
3163 DRM_ERROR("radeon: IH init failed (%d).\n", r);
3164 radeon_irq_kms_fini(rdev);
3169 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3170 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
3175 r = r600_cp_load_microcode(rdev);
3178 r = r600_cp_resume(rdev);
3182 r600_uvd_resume(rdev);
3184 r = radeon_ib_pool_init(rdev);
3186 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
3190 r = radeon_audio_init(rdev);
3192 DRM_ERROR("radeon: audio init failed\n");
3199 void r600_vga_set_state(struct radeon_device *rdev, bool state)
3203 temp = RREG32(CONFIG_CNTL);
3204 if (state == false) {
3210 WREG32(CONFIG_CNTL, temp);
3213 int r600_resume(struct radeon_device *rdev)
3217 /* Do not reset GPU before posting, on r600 hw unlike on r500 hw,
3218 * posting will perform necessary task to bring back GPU into good
3222 atom_asic_init(rdev->mode_info.atom_context);
3224 if (rdev->pm.pm_method == PM_METHOD_DPM)
3225 radeon_pm_resume(rdev);
3227 rdev->accel_working = true;
3228 r = r600_startup(rdev);
3230 DRM_ERROR("r600 startup failed on resume\n");
3231 rdev->accel_working = false;
3238 int r600_suspend(struct radeon_device *rdev)
3240 radeon_pm_suspend(rdev);
3241 radeon_audio_fini(rdev);
3243 if (rdev->has_uvd) {
3244 uvd_v1_0_fini(rdev);
3245 radeon_uvd_suspend(rdev);
3247 r600_irq_suspend(rdev);
3248 radeon_wb_disable(rdev);
3249 r600_pcie_gart_disable(rdev);
3254 /* Plan is to move initialization in that function and use
3255 * helper function so that radeon_device_init pretty much
3256 * do nothing more than calling asic specific function. This
3257 * should also allow to remove a bunch of callback function
3260 int r600_init(struct radeon_device *rdev)
3264 if (r600_debugfs_mc_info_init(rdev)) {
3265 DRM_ERROR("Failed to register debugfs file for mc !\n");
3268 if (!radeon_get_bios(rdev)) {
3269 if (ASIC_IS_AVIVO(rdev))
3272 /* Must be an ATOMBIOS */
3273 if (!rdev->is_atom_bios) {
3274 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
3277 r = radeon_atombios_init(rdev);
3280 /* Post card if necessary */
3281 if (!radeon_card_posted(rdev)) {
3283 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
3286 DRM_INFO("GPU not posted. posting now...\n");
3287 atom_asic_init(rdev->mode_info.atom_context);
3289 /* Initialize scratch registers */
3290 r600_scratch_init(rdev);
3291 /* Initialize surface registers */
3292 radeon_surface_init(rdev);
3293 /* Initialize clocks */
3294 radeon_get_clock_info(rdev->ddev);
3296 r = radeon_fence_driver_init(rdev);
3299 if (rdev->flags & RADEON_IS_AGP) {
3300 r = radeon_agp_init(rdev);
3302 radeon_agp_disable(rdev);
3304 r = r600_mc_init(rdev);
3307 /* Memory manager */
3308 r = radeon_bo_init(rdev);
3312 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
3313 r = r600_init_microcode(rdev);
3315 DRM_ERROR("Failed to load firmware!\n");
3320 /* Initialize power management */
3321 radeon_pm_init(rdev);
3323 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
3324 r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
3326 r600_uvd_init(rdev);
3328 rdev->ih.ring_obj = NULL;
3329 r600_ih_ring_init(rdev, 64 * 1024);
3331 r = r600_pcie_gart_init(rdev);
3335 rdev->accel_working = true;
3336 r = r600_startup(rdev);
3338 dev_err(rdev->dev, "disabling GPU acceleration\n");
3340 r600_irq_fini(rdev);
3341 radeon_wb_fini(rdev);
3342 radeon_ib_pool_fini(rdev);
3343 radeon_irq_kms_fini(rdev);
3344 r600_pcie_gart_fini(rdev);
3345 rdev->accel_working = false;
3351 void r600_fini(struct radeon_device *rdev)
3353 radeon_pm_fini(rdev);
3354 radeon_audio_fini(rdev);
3356 r600_irq_fini(rdev);
3357 if (rdev->has_uvd) {
3358 uvd_v1_0_fini(rdev);
3359 radeon_uvd_fini(rdev);
3361 radeon_wb_fini(rdev);
3362 radeon_ib_pool_fini(rdev);
3363 radeon_irq_kms_fini(rdev);
3364 r600_pcie_gart_fini(rdev);
3365 r600_vram_scratch_fini(rdev);
3366 radeon_agp_fini(rdev);
3367 radeon_gem_fini(rdev);
3368 radeon_fence_driver_fini(rdev);
3369 radeon_bo_fini(rdev);
3370 radeon_atombios_fini(rdev);
3371 r600_fini_microcode(rdev);
3380 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3382 struct radeon_ring *ring = &rdev->ring[ib->ring];
3385 if (ring->rptr_save_reg) {
3386 next_rptr = ring->wptr + 3 + 4;
3387 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
3388 radeon_ring_write(ring, ((ring->rptr_save_reg -
3389 PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
3390 radeon_ring_write(ring, next_rptr);
3391 } else if (rdev->wb.enabled) {
3392 next_rptr = ring->wptr + 5 + 4;
3393 radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3));
3394 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
3395 radeon_ring_write(ring, (upper_32_bits(ring->next_rptr_gpu_addr) & 0xff) | (1 << 18));
3396 radeon_ring_write(ring, next_rptr);
3397 radeon_ring_write(ring, 0);
3400 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
3401 radeon_ring_write(ring,
3405 (ib->gpu_addr & 0xFFFFFFFC));
3406 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);
3407 radeon_ring_write(ring, ib->length_dw);
3410 int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
3412 struct radeon_ib ib;
3418 r = radeon_scratch_get(rdev, &scratch);
3420 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3423 WREG32(scratch, 0xCAFEDEAD);
3424 r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256);
3426 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
3429 ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
3430 ib.ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
3431 ib.ptr[2] = 0xDEADBEEF;
3433 r = radeon_ib_schedule(rdev, &ib, NULL, false);
3435 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
3438 r = radeon_fence_wait_timeout(ib.fence, false, usecs_to_jiffies(
3439 RADEON_USEC_IB_TEST_TIMEOUT));
3441 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
3443 } else if (r == 0) {
3444 DRM_ERROR("radeon: fence wait timed out.\n");
3449 for (i = 0; i < rdev->usec_timeout; i++) {
3450 tmp = RREG32(scratch);
3451 if (tmp == 0xDEADBEEF)
3455 if (i < rdev->usec_timeout) {
3456 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i);
3458 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
3463 radeon_ib_free(rdev, &ib);
3465 radeon_scratch_free(rdev, scratch);
3472 * Interrupts use a ring buffer on r6xx/r7xx hardware. It works pretty
3473 * the same as the CP ring buffer, but in reverse. Rather than the CPU
3474 * writing to the ring and the GPU consuming, the GPU writes to the ring
3475 * and host consumes. As the host irq handler processes interrupts, it
3476 * increments the rptr. When the rptr catches up with the wptr, all the
3477 * current interrupts have been processed.
3480 void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size)
3484 /* Align ring size */
3485 rb_bufsz = order_base_2(ring_size / 4);
3486 ring_size = (1 << rb_bufsz) * 4;
3487 rdev->ih.ring_size = ring_size;
3488 rdev->ih.ptr_mask = rdev->ih.ring_size - 1;
3492 int r600_ih_ring_alloc(struct radeon_device *rdev)
3495 void *ring_ptr = &rdev->ih.ring;
3497 /* Allocate ring buffer */
3498 if (rdev->ih.ring_obj == NULL) {
3499 r = radeon_bo_create(rdev, rdev->ih.ring_size,
3501 RADEON_GEM_DOMAIN_GTT, 0,
3502 NULL, NULL, &rdev->ih.ring_obj);
3504 DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r);
3507 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
3508 if (unlikely(r != 0))
3510 r = radeon_bo_pin(rdev->ih.ring_obj,
3511 RADEON_GEM_DOMAIN_GTT,
3512 (u64 *)&rdev->ih.gpu_addr);
3514 radeon_bo_unreserve(rdev->ih.ring_obj);
3515 DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r);
3518 r = radeon_bo_kmap(rdev->ih.ring_obj,
3520 radeon_bo_unreserve(rdev->ih.ring_obj);
3522 DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r);
3529 void r600_ih_ring_fini(struct radeon_device *rdev)
3532 if (rdev->ih.ring_obj) {
3533 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
3534 if (likely(r == 0)) {
3535 radeon_bo_kunmap(rdev->ih.ring_obj);
3536 radeon_bo_unpin(rdev->ih.ring_obj);
3537 radeon_bo_unreserve(rdev->ih.ring_obj);
3539 radeon_bo_unref(&rdev->ih.ring_obj);
3540 rdev->ih.ring = NULL;
3541 rdev->ih.ring_obj = NULL;
3545 void r600_rlc_stop(struct radeon_device *rdev)
3548 if ((rdev->family >= CHIP_RV770) &&
3549 (rdev->family <= CHIP_RV740)) {
3550 /* r7xx asics need to soft reset RLC before halting */
3551 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC);
3552 RREG32(SRBM_SOFT_RESET);
3554 WREG32(SRBM_SOFT_RESET, 0);
3555 RREG32(SRBM_SOFT_RESET);
3558 WREG32(RLC_CNTL, 0);
3561 static void r600_rlc_start(struct radeon_device *rdev)
3563 WREG32(RLC_CNTL, RLC_ENABLE);
3566 static int r600_rlc_resume(struct radeon_device *rdev)
3569 const __be32 *fw_data;
3574 r600_rlc_stop(rdev);
3576 WREG32(RLC_HB_CNTL, 0);
3578 WREG32(RLC_HB_BASE, 0);
3579 WREG32(RLC_HB_RPTR, 0);
3580 WREG32(RLC_HB_WPTR, 0);
3581 WREG32(RLC_HB_WPTR_LSB_ADDR, 0);
3582 WREG32(RLC_HB_WPTR_MSB_ADDR, 0);
3583 WREG32(RLC_MC_CNTL, 0);
3584 WREG32(RLC_UCODE_CNTL, 0);
3586 fw_data = (const __be32 *)rdev->rlc_fw->data;
3587 if (rdev->family >= CHIP_RV770) {
3588 for (i = 0; i < R700_RLC_UCODE_SIZE; i++) {
3589 WREG32(RLC_UCODE_ADDR, i);
3590 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
3593 for (i = 0; i < R600_RLC_UCODE_SIZE; i++) {
3594 WREG32(RLC_UCODE_ADDR, i);
3595 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
3598 WREG32(RLC_UCODE_ADDR, 0);
3600 r600_rlc_start(rdev);
3605 static void r600_enable_interrupts(struct radeon_device *rdev)
3607 u32 ih_cntl = RREG32(IH_CNTL);
3608 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
3610 ih_cntl |= ENABLE_INTR;
3611 ih_rb_cntl |= IH_RB_ENABLE;
3612 WREG32(IH_CNTL, ih_cntl);
3613 WREG32(IH_RB_CNTL, ih_rb_cntl);
3614 rdev->ih.enabled = true;
3617 void r600_disable_interrupts(struct radeon_device *rdev)
3619 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
3620 u32 ih_cntl = RREG32(IH_CNTL);
3622 ih_rb_cntl &= ~IH_RB_ENABLE;
3623 ih_cntl &= ~ENABLE_INTR;
3624 WREG32(IH_RB_CNTL, ih_rb_cntl);
3625 WREG32(IH_CNTL, ih_cntl);
3626 /* set rptr, wptr to 0 */
3627 WREG32(IH_RB_RPTR, 0);
3628 WREG32(IH_RB_WPTR, 0);
3629 rdev->ih.enabled = false;
3633 static void r600_disable_interrupt_state(struct radeon_device *rdev)
3637 WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
3638 tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE;
3639 WREG32(DMA_CNTL, tmp);
3640 WREG32(GRBM_INT_CNTL, 0);
3641 WREG32(DxMODE_INT_MASK, 0);
3642 WREG32(D1GRPH_INTERRUPT_CONTROL, 0);
3643 WREG32(D2GRPH_INTERRUPT_CONTROL, 0);
3644 if (ASIC_IS_DCE3(rdev)) {
3645 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0);
3646 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0);
3647 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3648 WREG32(DC_HPD1_INT_CONTROL, tmp);
3649 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3650 WREG32(DC_HPD2_INT_CONTROL, tmp);
3651 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3652 WREG32(DC_HPD3_INT_CONTROL, tmp);
3653 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3654 WREG32(DC_HPD4_INT_CONTROL, tmp);
3655 if (ASIC_IS_DCE32(rdev)) {
3656 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3657 WREG32(DC_HPD5_INT_CONTROL, tmp);
3658 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3659 WREG32(DC_HPD6_INT_CONTROL, tmp);
3660 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3661 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp);
3662 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3663 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp);
3665 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3666 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
3667 tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3668 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp);
3671 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
3672 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
3673 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
3674 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
3675 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
3676 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
3677 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
3678 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
3679 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3680 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
3681 tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3682 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp);
3686 int r600_irq_init(struct radeon_device *rdev)
3690 u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
3693 ret = r600_ih_ring_alloc(rdev);
3698 r600_disable_interrupts(rdev);
3701 if (rdev->family >= CHIP_CEDAR)
3702 ret = evergreen_rlc_resume(rdev);
3704 ret = r600_rlc_resume(rdev);
3706 r600_ih_ring_fini(rdev);
3710 /* setup interrupt control */
3711 /* set dummy read address to ring address */
3712 WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8);
3713 interrupt_cntl = RREG32(INTERRUPT_CNTL);
3714 /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
3715 * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
3717 interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
3718 /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
3719 interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
3720 WREG32(INTERRUPT_CNTL, interrupt_cntl);
3722 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
3723 rb_bufsz = order_base_2(rdev->ih.ring_size / 4);
3725 ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
3726 IH_WPTR_OVERFLOW_CLEAR |
3729 if (rdev->wb.enabled)
3730 ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;
3732 /* set the writeback address whether it's enabled or not */
3733 WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC);
3734 WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF);
3736 WREG32(IH_RB_CNTL, ih_rb_cntl);
3738 /* set rptr, wptr to 0 */
3739 WREG32(IH_RB_RPTR, 0);
3740 WREG32(IH_RB_WPTR, 0);
3742 /* Default settings for IH_CNTL (disabled at first) */
3743 ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10);
3744 /* RPTR_REARM only works if msi's are enabled */
3745 if (rdev->msi_enabled)
3746 ih_cntl |= RPTR_REARM;
3747 WREG32(IH_CNTL, ih_cntl);
3749 /* force the active interrupt state to all disabled */
3750 if (rdev->family >= CHIP_CEDAR)
3751 evergreen_disable_interrupt_state(rdev);
3753 r600_disable_interrupt_state(rdev);
3755 /* at this point everything should be setup correctly to enable master */
3756 pci_set_master(rdev->pdev);
3759 r600_enable_interrupts(rdev);
3764 void r600_irq_suspend(struct radeon_device *rdev)
3766 r600_irq_disable(rdev);
3767 r600_rlc_stop(rdev);
3770 void r600_irq_fini(struct radeon_device *rdev)
3772 r600_irq_suspend(rdev);
3773 r600_ih_ring_fini(rdev);
3776 int r600_irq_set(struct radeon_device *rdev)
3778 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
3780 u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0;
3781 u32 grbm_int_cntl = 0;
3784 u32 thermal_int = 0;
3786 if (!rdev->irq.installed) {
3787 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
3790 /* don't enable anything if the ih is disabled */
3791 if (!rdev->ih.enabled) {
3792 r600_disable_interrupts(rdev);
3793 /* force the active interrupt state to all disabled */
3794 r600_disable_interrupt_state(rdev);
3798 if (ASIC_IS_DCE3(rdev)) {
3799 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3800 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3801 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3802 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
3803 if (ASIC_IS_DCE32(rdev)) {
3804 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
3805 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
3806 hdmi0 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
3807 hdmi1 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
3809 hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3810 hdmi1 = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3813 hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3814 hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3815 hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3816 hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3817 hdmi1 = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3820 dma_cntl = RREG32(DMA_CNTL) & ~TRAP_ENABLE;
3822 if ((rdev->family > CHIP_R600) && (rdev->family < CHIP_RV770)) {
3823 thermal_int = RREG32(CG_THERMAL_INT) &
3824 ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);
3825 } else if (rdev->family >= CHIP_RV770) {
3826 thermal_int = RREG32(RV770_CG_THERMAL_INT) &
3827 ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);
3829 if (rdev->irq.dpm_thermal) {
3830 DRM_DEBUG("dpm thermal\n");
3831 thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW;
3834 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
3835 DRM_DEBUG("r600_irq_set: sw int\n");
3836 cp_int_cntl |= RB_INT_ENABLE;
3837 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
3840 if (atomic_read(&rdev->irq.ring_int[R600_RING_TYPE_DMA_INDEX])) {
3841 DRM_DEBUG("r600_irq_set: sw int dma\n");
3842 dma_cntl |= TRAP_ENABLE;
3845 if (rdev->irq.crtc_vblank_int[0] ||
3846 atomic_read(&rdev->irq.pflip[0])) {
3847 DRM_DEBUG("r600_irq_set: vblank 0\n");
3848 mode_int |= D1MODE_VBLANK_INT_MASK;
3850 if (rdev->irq.crtc_vblank_int[1] ||
3851 atomic_read(&rdev->irq.pflip[1])) {
3852 DRM_DEBUG("r600_irq_set: vblank 1\n");
3853 mode_int |= D2MODE_VBLANK_INT_MASK;
3855 if (rdev->irq.hpd[0]) {
3856 DRM_DEBUG("r600_irq_set: hpd 1\n");
3857 hpd1 |= DC_HPDx_INT_EN;
3859 if (rdev->irq.hpd[1]) {
3860 DRM_DEBUG("r600_irq_set: hpd 2\n");
3861 hpd2 |= DC_HPDx_INT_EN;
3863 if (rdev->irq.hpd[2]) {
3864 DRM_DEBUG("r600_irq_set: hpd 3\n");
3865 hpd3 |= DC_HPDx_INT_EN;
3867 if (rdev->irq.hpd[3]) {
3868 DRM_DEBUG("r600_irq_set: hpd 4\n");
3869 hpd4 |= DC_HPDx_INT_EN;
3871 if (rdev->irq.hpd[4]) {
3872 DRM_DEBUG("r600_irq_set: hpd 5\n");
3873 hpd5 |= DC_HPDx_INT_EN;
3875 if (rdev->irq.hpd[5]) {
3876 DRM_DEBUG("r600_irq_set: hpd 6\n");
3877 hpd6 |= DC_HPDx_INT_EN;
3879 if (rdev->irq.afmt[0]) {
3880 DRM_DEBUG("r600_irq_set: hdmi 0\n");
3881 hdmi0 |= HDMI0_AZ_FORMAT_WTRIG_MASK;
3883 if (rdev->irq.afmt[1]) {
3884 DRM_DEBUG("r600_irq_set: hdmi 0\n");
3885 hdmi1 |= HDMI0_AZ_FORMAT_WTRIG_MASK;
3888 WREG32(CP_INT_CNTL, cp_int_cntl);
3889 WREG32(DMA_CNTL, dma_cntl);
3890 WREG32(DxMODE_INT_MASK, mode_int);
3891 WREG32(D1GRPH_INTERRUPT_CONTROL, DxGRPH_PFLIP_INT_MASK);
3892 WREG32(D2GRPH_INTERRUPT_CONTROL, DxGRPH_PFLIP_INT_MASK);
3893 WREG32(GRBM_INT_CNTL, grbm_int_cntl);
3894 if (ASIC_IS_DCE3(rdev)) {
3895 WREG32(DC_HPD1_INT_CONTROL, hpd1);
3896 WREG32(DC_HPD2_INT_CONTROL, hpd2);
3897 WREG32(DC_HPD3_INT_CONTROL, hpd3);
3898 WREG32(DC_HPD4_INT_CONTROL, hpd4);
3899 if (ASIC_IS_DCE32(rdev)) {
3900 WREG32(DC_HPD5_INT_CONTROL, hpd5);
3901 WREG32(DC_HPD6_INT_CONTROL, hpd6);
3902 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, hdmi0);
3903 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, hdmi1);
3905 WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
3906 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, hdmi1);
3909 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
3910 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
3911 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3);
3912 WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
3913 WREG32(HDMI1_AUDIO_PACKET_CONTROL, hdmi1);
3915 if ((rdev->family > CHIP_R600) && (rdev->family < CHIP_RV770)) {
3916 WREG32(CG_THERMAL_INT, thermal_int);
3917 } else if (rdev->family >= CHIP_RV770) {
3918 WREG32(RV770_CG_THERMAL_INT, thermal_int);
3922 RREG32(R_000E50_SRBM_STATUS);
3927 static void r600_irq_ack(struct radeon_device *rdev)
3931 if (ASIC_IS_DCE3(rdev)) {
3932 rdev->irq.stat_regs.r600.disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS);
3933 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE);
3934 rdev->irq.stat_regs.r600.disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2);
3935 if (ASIC_IS_DCE32(rdev)) {
3936 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET0);
3937 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET1);
3939 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS);
3940 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(DCE3_HDMI1_STATUS);
3943 rdev->irq.stat_regs.r600.disp_int = RREG32(DISP_INTERRUPT_STATUS);
3944 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
3945 rdev->irq.stat_regs.r600.disp_int_cont2 = 0;
3946 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS);
3947 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(HDMI1_STATUS);
3949 rdev->irq.stat_regs.r600.d1grph_int = RREG32(D1GRPH_INTERRUPT_STATUS);
3950 rdev->irq.stat_regs.r600.d2grph_int = RREG32(D2GRPH_INTERRUPT_STATUS);
3952 if (rdev->irq.stat_regs.r600.d1grph_int & DxGRPH_PFLIP_INT_OCCURRED)
3953 WREG32(D1GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR);
3954 if (rdev->irq.stat_regs.r600.d2grph_int & DxGRPH_PFLIP_INT_OCCURRED)
3955 WREG32(D2GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR);
3956 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT)
3957 WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
3958 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT)
3959 WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
3960 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT)
3961 WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
3962 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT)
3963 WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
3964 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) {
3965 if (ASIC_IS_DCE3(rdev)) {
3966 tmp = RREG32(DC_HPD1_INT_CONTROL);
3967 tmp |= DC_HPDx_INT_ACK;
3968 WREG32(DC_HPD1_INT_CONTROL, tmp);
3970 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
3971 tmp |= DC_HPDx_INT_ACK;
3972 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
3975 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) {
3976 if (ASIC_IS_DCE3(rdev)) {
3977 tmp = RREG32(DC_HPD2_INT_CONTROL);
3978 tmp |= DC_HPDx_INT_ACK;
3979 WREG32(DC_HPD2_INT_CONTROL, tmp);
3981 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
3982 tmp |= DC_HPDx_INT_ACK;
3983 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
3986 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) {
3987 if (ASIC_IS_DCE3(rdev)) {
3988 tmp = RREG32(DC_HPD3_INT_CONTROL);
3989 tmp |= DC_HPDx_INT_ACK;
3990 WREG32(DC_HPD3_INT_CONTROL, tmp);
3992 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
3993 tmp |= DC_HPDx_INT_ACK;
3994 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
3997 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) {
3998 tmp = RREG32(DC_HPD4_INT_CONTROL);
3999 tmp |= DC_HPDx_INT_ACK;
4000 WREG32(DC_HPD4_INT_CONTROL, tmp);
4002 if (ASIC_IS_DCE32(rdev)) {
4003 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) {
4004 tmp = RREG32(DC_HPD5_INT_CONTROL);
4005 tmp |= DC_HPDx_INT_ACK;
4006 WREG32(DC_HPD5_INT_CONTROL, tmp);
4008 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) {
4009 tmp = RREG32(DC_HPD6_INT_CONTROL);
4010 tmp |= DC_HPDx_INT_ACK;
4011 WREG32(DC_HPD6_INT_CONTROL, tmp);
4013 if (rdev->irq.stat_regs.r600.hdmi0_status & AFMT_AZ_FORMAT_WTRIG) {
4014 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0);
4015 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
4016 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp);
4018 if (rdev->irq.stat_regs.r600.hdmi1_status & AFMT_AZ_FORMAT_WTRIG) {
4019 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1);
4020 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
4021 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp);
4024 if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG) {
4025 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL);
4026 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK;
4027 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
4029 if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG) {
4030 if (ASIC_IS_DCE3(rdev)) {
4031 tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL);
4032 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK;
4033 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp);
4035 tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL);
4036 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK;
4037 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp);
4043 void r600_irq_disable(struct radeon_device *rdev)
4045 r600_disable_interrupts(rdev);
4046 /* Wait and acknowledge irq */
4049 r600_disable_interrupt_state(rdev);
4052 static u32 r600_get_ih_wptr(struct radeon_device *rdev)
4056 if (rdev->wb.enabled)
4057 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
4059 wptr = RREG32(IH_RB_WPTR);
4061 if (wptr & RB_OVERFLOW) {
4062 wptr &= ~RB_OVERFLOW;
4063 /* When a ring buffer overflow happen start parsing interrupt
4064 * from the last not overwritten vector (wptr + 16). Hopefully
4065 * this should allow us to catchup.
4067 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",
4068 wptr, rdev->ih.rptr, (wptr + 16) & rdev->ih.ptr_mask);
4069 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
4070 tmp = RREG32(IH_RB_CNTL);
4071 tmp |= IH_WPTR_OVERFLOW_CLEAR;
4072 WREG32(IH_RB_CNTL, tmp);
4074 return (wptr & rdev->ih.ptr_mask);
4078 * Each IV ring entry is 128 bits:
4079 * [7:0] - interrupt source id
4081 * [59:32] - interrupt source data
4082 * [127:60] - reserved
4084 * The basic interrupt vector entries
4085 * are decoded as follows:
4086 * src_id src_data description
4091 * 19 0 FP Hot plug detection A
4092 * 19 1 FP Hot plug detection B
4093 * 19 2 DAC A auto-detection
4094 * 19 3 DAC B auto-detection
4100 * 181 - EOP Interrupt
4103 * Note, these are based on r600 and may need to be
4104 * adjusted or added to on newer asics
4107 irqreturn_t r600_irq_process(struct radeon_device *rdev)
4111 u32 src_id, src_data;
4113 bool queue_hotplug = false;
4114 bool queue_hdmi = false;
4115 bool queue_thermal = false;
4117 if (!rdev->ih.enabled || rdev->shutdown)
4120 /* No MSIs, need a dummy read to flush PCI DMAs */
4121 if (!rdev->msi_enabled)
4124 wptr = r600_get_ih_wptr(rdev);
4127 /* is somebody else already processing irqs? */
4128 if (atomic_xchg(&rdev->ih.lock, 1))
4131 rptr = rdev->ih.rptr;
4132 DRM_DEBUG_VBLANK("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
4134 /* Order reading of wptr vs. reading of IH ring data */
4137 /* display interrupts */
4140 while (rptr != wptr) {
4141 /* wptr/rptr are in bytes! */
4142 ring_index = rptr / 4;
4143 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
4144 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
4147 case 1: /* D1 vblank/vline */
4149 case 0: /* D1 vblank */
4150 if (!(rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT))
4151 DRM_DEBUG("IH: D1 vblank - IH event w/o asserted irq bit?\n");
4153 if (rdev->irq.crtc_vblank_int[0]) {
4154 drm_handle_vblank(rdev->ddev, 0);
4155 rdev->pm.vblank_sync = true;
4156 wake_up(&rdev->irq.vblank_queue);
4158 if (atomic_read(&rdev->irq.pflip[0]))
4159 radeon_crtc_handle_vblank(rdev, 0);
4160 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
4161 DRM_DEBUG_VBLANK("IH: D1 vblank\n");
4164 case 1: /* D1 vline */
4165 if (!(rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT))
4166 DRM_DEBUG("IH: D1 vline - IH event w/o asserted irq bit?\n");
4168 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VLINE_INTERRUPT;
4169 DRM_DEBUG_VBLANK("IH: D1 vline\n");
4173 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
4177 case 5: /* D2 vblank/vline */
4179 case 0: /* D2 vblank */
4180 if (!(rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT))
4181 DRM_DEBUG("IH: D2 vblank - IH event w/o asserted irq bit?\n");
4183 if (rdev->irq.crtc_vblank_int[1]) {
4184 drm_handle_vblank(rdev->ddev, 1);
4185 rdev->pm.vblank_sync = true;
4186 wake_up(&rdev->irq.vblank_queue);
4188 if (atomic_read(&rdev->irq.pflip[1]))
4189 radeon_crtc_handle_vblank(rdev, 1);
4190 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VBLANK_INTERRUPT;
4191 DRM_DEBUG_VBLANK("IH: D2 vblank\n");
4194 case 1: /* D1 vline */
4195 if (!(rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT))
4196 DRM_DEBUG("IH: D2 vline - IH event w/o asserted irq bit?\n");
4198 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VLINE_INTERRUPT;
4199 DRM_DEBUG_VBLANK("IH: D2 vline\n");
4203 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
4207 case 9: /* D1 pflip */
4208 DRM_DEBUG_VBLANK("IH: D1 flip\n");
4209 if (radeon_use_pflipirq > 0)
4210 radeon_crtc_handle_flip(rdev, 0);
4212 case 11: /* D2 pflip */
4213 DRM_DEBUG_VBLANK("IH: D2 flip\n");
4214 if (radeon_use_pflipirq > 0)
4215 radeon_crtc_handle_flip(rdev, 1);
4217 case 19: /* HPD/DAC hotplug */
4220 if (!(rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT))
4221 DRM_DEBUG("IH: HPD1 - IH event w/o asserted irq bit?\n");
4223 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD1_INTERRUPT;
4224 queue_hotplug = true;
4225 DRM_DEBUG("IH: HPD1\n");
4228 if (!(rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT))
4229 DRM_DEBUG("IH: HPD2 - IH event w/o asserted irq bit?\n");
4231 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD2_INTERRUPT;
4232 queue_hotplug = true;
4233 DRM_DEBUG("IH: HPD2\n");
4236 if (!(rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT))
4237 DRM_DEBUG("IH: HPD3 - IH event w/o asserted irq bit?\n");
4239 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD3_INTERRUPT;
4240 queue_hotplug = true;
4241 DRM_DEBUG("IH: HPD3\n");
4244 if (!(rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT))
4245 DRM_DEBUG("IH: HPD4 - IH event w/o asserted irq bit?\n");
4247 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD4_INTERRUPT;
4248 queue_hotplug = true;
4249 DRM_DEBUG("IH: HPD4\n");
4252 if (!(rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT))
4253 DRM_DEBUG("IH: HPD5 - IH event w/o asserted irq bit?\n");
4255 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD5_INTERRUPT;
4256 queue_hotplug = true;
4257 DRM_DEBUG("IH: HPD5\n");
4260 if (!(rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT))
4261 DRM_DEBUG("IH: HPD6 - IH event w/o asserted irq bit?\n");
4263 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD6_INTERRUPT;
4264 queue_hotplug = true;
4265 DRM_DEBUG("IH: HPD6\n");
4269 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
4276 if (!(rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG))
4277 DRM_DEBUG("IH: HDMI0 - IH event w/o asserted irq bit?\n");
4279 rdev->irq.stat_regs.r600.hdmi0_status &= ~HDMI0_AZ_FORMAT_WTRIG;
4281 DRM_DEBUG("IH: HDMI0\n");
4285 if (!(rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG))
4286 DRM_DEBUG("IH: HDMI1 - IH event w/o asserted irq bit?\n");
4288 rdev->irq.stat_regs.r600.hdmi1_status &= ~HDMI0_AZ_FORMAT_WTRIG;
4290 DRM_DEBUG("IH: HDMI1\n");
4294 DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data);
4299 DRM_DEBUG("IH: UVD int: 0x%08x\n", src_data);
4300 radeon_fence_process(rdev, R600_RING_TYPE_UVD_INDEX);
4302 case 176: /* CP_INT in ring buffer */
4303 case 177: /* CP_INT in IB1 */
4304 case 178: /* CP_INT in IB2 */
4305 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
4306 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
4308 case 181: /* CP EOP event */
4309 DRM_DEBUG("IH: CP EOP\n");
4310 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
4312 case 224: /* DMA trap event */
4313 DRM_DEBUG("IH: DMA trap\n");
4314 radeon_fence_process(rdev, R600_RING_TYPE_DMA_INDEX);
4316 case 230: /* thermal low to high */
4317 DRM_DEBUG("IH: thermal low to high\n");
4318 rdev->pm.dpm.thermal.high_to_low = false;
4319 queue_thermal = true;
4321 case 231: /* thermal high to low */
4322 DRM_DEBUG("IH: thermal high to low\n");
4323 rdev->pm.dpm.thermal.high_to_low = true;
4324 queue_thermal = true;
4326 case 233: /* GUI IDLE */
4327 DRM_DEBUG("IH: GUI idle\n");
4330 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
4334 /* wptr/rptr are in bytes! */
4336 rptr &= rdev->ih.ptr_mask;
4337 WREG32(IH_RB_RPTR, rptr);
4340 schedule_delayed_work(&rdev->hotplug_work, 0);
4342 schedule_work(&rdev->audio_work);
4343 if (queue_thermal && rdev->pm.dpm_enabled)
4344 schedule_work(&rdev->pm.dpm.thermal.work);
4345 rdev->ih.rptr = rptr;
4346 atomic_set(&rdev->ih.lock, 0);
4348 /* make sure wptr hasn't changed while processing */
4349 wptr = r600_get_ih_wptr(rdev);
4359 #if defined(CONFIG_DEBUG_FS)
4361 static int r600_debugfs_mc_info(struct seq_file *m, void *data)
4363 struct drm_info_node *node = (struct drm_info_node *) m->private;
4364 struct drm_device *dev = node->minor->dev;
4365 struct radeon_device *rdev = dev->dev_private;
4367 DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS);
4368 DREG32_SYS(m, rdev, VM_L2_STATUS);
4372 static struct drm_info_list r600_mc_info_list[] = {
4373 {"r600_mc_info", r600_debugfs_mc_info, 0, NULL},
4377 int r600_debugfs_mc_info_init(struct radeon_device *rdev)
4379 #if defined(CONFIG_DEBUG_FS)
4380 return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list));
4387 * r600_mmio_hdp_flush - flush Host Data Path cache via MMIO
4388 * rdev: radeon device structure
4390 * Some R6XX/R7XX don't seem to take into account HDP flushes performed
4391 * through the ring buffer. This leads to corruption in rendering, see
4392 * http://bugzilla.kernel.org/show_bug.cgi?id=15186 . To avoid this, we
4393 * directly perform the HDP flush by writing the register through MMIO.
4395 void r600_mmio_hdp_flush(struct radeon_device *rdev)
4397 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read
4398 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL.
4399 * This seems to cause problems on some AGP cards. Just use the old
4402 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
4403 rdev->vram_scratch.ptr && !(rdev->flags & RADEON_IS_AGP)) {
4404 volatile void __iomem *ptr = (volatile void *)rdev->vram_scratch.ptr;
4407 WREG32(HDP_DEBUG1, 0);
4408 tmp = readl((volatile void __iomem *)ptr);
4410 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
4413 void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes)
4415 u32 link_width_cntl, mask;
4417 if (rdev->flags & RADEON_IS_IGP)
4420 if (!(rdev->flags & RADEON_IS_PCIE))
4423 /* x2 cards have a special sequence */
4424 if (ASIC_IS_X2(rdev))
4427 radeon_gui_idle(rdev);
4431 mask = RADEON_PCIE_LC_LINK_WIDTH_X0;
4434 mask = RADEON_PCIE_LC_LINK_WIDTH_X1;
4437 mask = RADEON_PCIE_LC_LINK_WIDTH_X2;
4440 mask = RADEON_PCIE_LC_LINK_WIDTH_X4;
4443 mask = RADEON_PCIE_LC_LINK_WIDTH_X8;
4446 /* not actually supported */
4447 mask = RADEON_PCIE_LC_LINK_WIDTH_X12;
4450 mask = RADEON_PCIE_LC_LINK_WIDTH_X16;
4453 DRM_ERROR("invalid pcie lane request: %d\n", lanes);
4457 link_width_cntl = RREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
4458 link_width_cntl &= ~RADEON_PCIE_LC_LINK_WIDTH_MASK;
4459 link_width_cntl |= mask << RADEON_PCIE_LC_LINK_WIDTH_SHIFT;
4460 link_width_cntl |= (RADEON_PCIE_LC_RECONFIG_NOW |
4461 R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE);
4463 WREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4466 int r600_get_pcie_lanes(struct radeon_device *rdev)
4468 u32 link_width_cntl;
4470 if (rdev->flags & RADEON_IS_IGP)
4473 if (!(rdev->flags & RADEON_IS_PCIE))
4476 /* x2 cards have a special sequence */
4477 if (ASIC_IS_X2(rdev))
4480 radeon_gui_idle(rdev);
4482 link_width_cntl = RREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
4484 switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) {
4485 case RADEON_PCIE_LC_LINK_WIDTH_X1:
4487 case RADEON_PCIE_LC_LINK_WIDTH_X2:
4489 case RADEON_PCIE_LC_LINK_WIDTH_X4:
4491 case RADEON_PCIE_LC_LINK_WIDTH_X8:
4493 case RADEON_PCIE_LC_LINK_WIDTH_X12:
4494 /* not actually supported */
4496 case RADEON_PCIE_LC_LINK_WIDTH_X0:
4497 case RADEON_PCIE_LC_LINK_WIDTH_X16:
4503 static void r600_pcie_gen2_enable(struct radeon_device *rdev)
4505 u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp;
4509 if (radeon_pcie_gen2 == 0)
4512 if (rdev->flags & RADEON_IS_IGP)
4515 if (!(rdev->flags & RADEON_IS_PCIE))
4518 /* x2 cards have a special sequence */
4519 if (ASIC_IS_X2(rdev))
4522 /* only RV6xx+ chips are supported */
4523 if (rdev->family <= CHIP_R600)
4526 #ifdef __DragonFly__
4527 if (drm_pcie_get_speed_cap_mask(rdev->ddev, &mask) != 0)
4531 if (!(mask & DRM_PCIE_SPEED_50))
4534 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
4535 if (speed_cntl & LC_CURRENT_DATA_RATE) {
4536 DRM_INFO("PCIE gen 2 link speeds already enabled\n");
4540 DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");
4542 /* 55 nm r6xx asics */
4543 if ((rdev->family == CHIP_RV670) ||
4544 (rdev->family == CHIP_RV620) ||
4545 (rdev->family == CHIP_RV635)) {
4546 /* advertise upconfig capability */
4547 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
4548 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
4549 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4550 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
4551 if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) {
4552 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT;
4553 link_width_cntl &= ~(LC_LINK_WIDTH_MASK |
4554 LC_RECONFIG_ARC_MISSING_ESCAPE);
4555 link_width_cntl |= lanes | LC_RECONFIG_NOW | LC_RENEGOTIATE_EN;
4556 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4558 link_width_cntl |= LC_UPCONFIGURE_DIS;
4559 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4563 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
4564 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
4565 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
4567 /* 55 nm r6xx asics */
4568 if ((rdev->family == CHIP_RV670) ||
4569 (rdev->family == CHIP_RV620) ||
4570 (rdev->family == CHIP_RV635)) {
4571 WREG32(MM_CFGREGS_CNTL, 0x8);
4572 link_cntl2 = RREG32(0x4088);
4573 WREG32(MM_CFGREGS_CNTL, 0);
4574 /* not supported yet */
4575 if (link_cntl2 & SELECTABLE_DEEMPHASIS)
4579 speed_cntl &= ~LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK;
4580 speed_cntl |= (0x3 << LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT);
4581 speed_cntl &= ~LC_VOLTAGE_TIMER_SEL_MASK;
4582 speed_cntl &= ~LC_FORCE_DIS_HW_SPEED_CHANGE;
4583 speed_cntl |= LC_FORCE_EN_HW_SPEED_CHANGE;
4584 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
4586 tmp = RREG32(0x541c);
4587 WREG32(0x541c, tmp | 0x8);
4588 WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN);
4589 link_cntl2 = RREG16(0x4088);
4590 link_cntl2 &= ~TARGET_LINK_SPEED_MASK;
4592 WREG16(0x4088, link_cntl2);
4593 WREG32(MM_CFGREGS_CNTL, 0);
4595 if ((rdev->family == CHIP_RV670) ||
4596 (rdev->family == CHIP_RV620) ||
4597 (rdev->family == CHIP_RV635)) {
4598 training_cntl = RREG32_PCIE_PORT(PCIE_LC_TRAINING_CNTL);
4599 training_cntl &= ~LC_POINT_7_PLUS_EN;
4600 WREG32_PCIE_PORT(PCIE_LC_TRAINING_CNTL, training_cntl);
4602 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
4603 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
4604 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
4607 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
4608 speed_cntl |= LC_GEN2_EN_STRAP;
4609 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
4612 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
4613 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
4615 link_width_cntl |= LC_UPCONFIGURE_DIS;
4617 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
4618 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4623 * r600_get_gpu_clock_counter - return GPU clock counter snapshot
4625 * @rdev: radeon_device pointer
4627 * Fetches a GPU clock counter snapshot (R6xx-cayman).
4628 * Returns the 64 bit clock counter snapshot.
4630 uint64_t r600_get_gpu_clock_counter(struct radeon_device *rdev)
4634 mutex_lock(&rdev->gpu_clock_mutex);
4635 WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1);
4636 clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) |
4637 ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
4638 mutex_unlock(&rdev->gpu_clock_mutex);