sys/dev/drm/i915/intel_uncore.c

   1 /*
   2  * Copyright © 2013 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "i915_drv.h"
  25 #include "intel_drv.h"
  26 #include "i915_vgpu.h"
  27
  28 #define FORCEWAKE_ACK_TIMEOUT_MS 2
  29
  30 #define __raw_i915_read8(dev_priv__, reg__) readb((dev_priv__)->regs + (reg__))
  31 #define __raw_i915_write8(dev_priv__, reg__, val__) DRM_WRITE8(dev_priv__->mmio_map, reg__, val__)
  32
  33 #define __raw_i915_read16(dev_priv__, reg__) readw((dev_priv__)->regs + (reg__))
  34 #define __raw_i915_write16(dev_priv__, reg__, val__) DRM_WRITE16(dev_priv__->mmio_map, reg__, val__)
  35
  36 #define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__))
  37 #define __raw_i915_write32(dev_priv__, reg__, val__) DRM_WRITE32(dev_priv__->mmio_map, reg__, val__)
  38
  39 #define __raw_i915_read64(dev_priv__, reg__) readq((dev_priv__)->regs + (reg__))
  40 #define __raw_i915_write64(dev_priv__, reg__, val__) DRM_WRITE64(dev_priv__->mmio_map, reg__, val__)
  41
  42 #define __raw_posting_read(dev_priv__, reg__) (void)__raw_i915_read32(dev_priv__, reg__)
  43
  44 static const char * const forcewake_domain_names[] = {
  45         "render",
  46         "blitter",
  47         "media",
  48 };
  49
  50 const char *
  51 intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id)
  52 {
  53         BUILD_BUG_ON((sizeof(forcewake_domain_names)/sizeof(const char *)) !=
  54                      FW_DOMAIN_ID_COUNT);
  55
  56         if (id >= 0 && id < FW_DOMAIN_ID_COUNT)
  57                 return forcewake_domain_names[id];
  58
  59         WARN_ON(id);
  60
  61         return "unknown";
  62 }
  63
  64 static void
  65 assert_device_not_suspended(struct drm_i915_private *dev_priv)
  66 {
  67         WARN_ONCE(HAS_RUNTIME_PM(dev_priv->dev) && dev_priv->pm.suspended,
  68                   "Device suspended\n");
  69 }
  70
  71 static inline void
  72 fw_domain_reset(const struct intel_uncore_forcewake_domain *d)
  73 {
  74         WARN_ON(d->reg_set == 0);
  75         __raw_i915_write32(d->i915, d->reg_set, d->val_reset);
  76 }
  77
  78 static inline void
  79 fw_domain_arm_timer(struct intel_uncore_forcewake_domain *d)
  80 {
  81         mod_timer_pinned(&d->timer, jiffies + 1);
  82 }
  83
  84 static inline void
  85 fw_domain_wait_ack_clear(const struct intel_uncore_forcewake_domain *d)
  86 {
  87         if (wait_for_atomic((__raw_i915_read32(d->i915, d->reg_ack) &
  88                              FORCEWAKE_KERNEL) == 0,
  89                             FORCEWAKE_ACK_TIMEOUT_MS))
  90                 DRM_ERROR("%s: timed out waiting for forcewake ack to clear.\n",
  91                           intel_uncore_forcewake_domain_to_str(d->id));
  92 }
  93
  94 static inline void
  95 fw_domain_get(const struct intel_uncore_forcewake_domain *d)
  96 {
  97         __raw_i915_write32(d->i915, d->reg_set, d->val_set);
  98 }
  99
 100 static inline void
 101 fw_domain_wait_ack(const struct intel_uncore_forcewake_domain *d)
 102 {
 103         if (wait_for_atomic((__raw_i915_read32(d->i915, d->reg_ack) &
 104                              FORCEWAKE_KERNEL),
 105                             FORCEWAKE_ACK_TIMEOUT_MS))
 106                 DRM_ERROR("%s: timed out waiting for forcewake ack request.\n",
 107                           intel_uncore_forcewake_domain_to_str(d->id));
 108 }
 109
 110 static inline void
 111 fw_domain_put(const struct intel_uncore_forcewake_domain *d)
 112 {
 113         __raw_i915_write32(d->i915, d->reg_set, d->val_clear);
 114 }
 115
 116 static inline void
 117 fw_domain_posting_read(const struct intel_uncore_forcewake_domain *d)
 118 {
 119         /* something from same cacheline, but not from the set register */
 120         if (d->reg_post)
 121                 __raw_posting_read(d->i915, d->reg_post);
 122 }
 123
 124 static void
 125 fw_domains_get(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains)
 126 {
 127         struct intel_uncore_forcewake_domain *d;
 128         enum forcewake_domain_id id;
 129
 130         for_each_fw_domain_mask(d, fw_domains, dev_priv, id) {
 131                 fw_domain_wait_ack_clear(d);
 132                 fw_domain_get(d);
 133                 fw_domain_wait_ack(d);
 134         }
 135 }
 136
 137 static void
 138 fw_domains_put(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains)
 139 {
 140         struct intel_uncore_forcewake_domain *d;
 141         enum forcewake_domain_id id;
 142
 143         for_each_fw_domain_mask(d, fw_domains, dev_priv, id) {
 144                 fw_domain_put(d);
 145                 fw_domain_posting_read(d);
 146         }
 147 }
 148
 149 static void
 150 fw_domains_posting_read(struct drm_i915_private *dev_priv)
 151 {
 152         struct intel_uncore_forcewake_domain *d;
 153         enum forcewake_domain_id id;
 154
 155         /* No need to do for all, just do for first found */
 156         for_each_fw_domain(d, dev_priv, id) {
 157                 fw_domain_posting_read(d);
 158                 break;
 159         }
 160 }
 161
 162 static void
 163 fw_domains_reset(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains)
 164 {
 165         struct intel_uncore_forcewake_domain *d;
 166         enum forcewake_domain_id id;
 167
 168         if (dev_priv->uncore.fw_domains == 0)
 169                 return;
 170
 171         for_each_fw_domain_mask(d, fw_domains, dev_priv, id)
 172                 fw_domain_reset(d);
 173
 174         fw_domains_posting_read(dev_priv);
 175 }
 176
 177 static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv)
 178 {
 179         /* w/a for a sporadic read returning 0 by waiting for the GT
 180          * thread to wake up.
 181          */
 182         if (wait_for_atomic_us((__raw_i915_read32(dev_priv, GEN6_GT_THREAD_STATUS_REG) &
 183                                 GEN6_GT_THREAD_STATUS_CORE_MASK) == 0, 500))
 184                 DRM_ERROR("GT thread status wait timed out\n");
 185 }
 186
 187 static void fw_domains_get_with_thread_status(struct drm_i915_private *dev_priv,
 188                                               enum forcewake_domains fw_domains)
 189 {
 190         fw_domains_get(dev_priv, fw_domains);
 191
 192         /* WaRsForcewakeWaitTC0:snb,ivb,hsw,bdw,vlv */
 193         __gen6_gt_wait_for_thread_c0(dev_priv);
 194 }
 195
 196 static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
 197 {
 198         u32 gtfifodbg;
 199
 200         gtfifodbg = __raw_i915_read32(dev_priv, GTFIFODBG);
 201         if (WARN(gtfifodbg, "GT wake FIFO error 0x%x\n", gtfifodbg))
 202                 __raw_i915_write32(dev_priv, GTFIFODBG, gtfifodbg);
 203 }
 204
 205 static void fw_domains_put_with_fifo(struct drm_i915_private *dev_priv,
 206                                      enum forcewake_domains fw_domains)
 207 {
 208         fw_domains_put(dev_priv, fw_domains);
 209         gen6_gt_check_fifodbg(dev_priv);
 210 }
 211
 212 static inline u32 fifo_free_entries(struct drm_i915_private *dev_priv)
 213 {
 214         u32 count = __raw_i915_read32(dev_priv, GTFIFOCTL);
 215
 216         return count & GT_FIFO_FREE_ENTRIES_MASK;
 217 }
 218
 219 static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
 220 {
 221         int ret = 0;
 222
 223         /* On VLV, FIFO will be shared by both SW and HW.
 224          * So, we need to read the FREE_ENTRIES everytime */
 225         if (IS_VALLEYVIEW(dev_priv->dev))
 226                 dev_priv->uncore.fifo_count = fifo_free_entries(dev_priv);
 227
 228         if (dev_priv->uncore.fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
 229                 int loop = 500;
 230                 u32 fifo = fifo_free_entries(dev_priv);
 231
 232                 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
 233                         udelay(10);
 234                         fifo = fifo_free_entries(dev_priv);
 235                 }
 236                 if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
 237                         ++ret;
 238                 dev_priv->uncore.fifo_count = fifo;
 239         }
 240         dev_priv->uncore.fifo_count--;
 241
 242         return ret;
 243 }
 244
 245 static void intel_uncore_fw_release_timer(unsigned long arg)
 246 {
 247         struct intel_uncore_forcewake_domain *domain = (void *)arg;
 248         unsigned long irqflags;
 249
 250         assert_device_not_suspended(domain->i915);
 251
 252         spin_lock_irqsave(&domain->i915->uncore.lock, irqflags);
 253         if (WARN_ON(domain->wake_count == 0))
 254                 domain->wake_count++;
 255
 256         if (--domain->wake_count == 0)
 257                 domain->i915->uncore.funcs.force_wake_put(domain->i915,
 258                                                           1 << domain->id);
 259
 260         spin_unlock_irqrestore(&domain->i915->uncore.lock, irqflags);
 261 }
 262
 263 void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore)
 264 {
 265         struct drm_i915_private *dev_priv = dev->dev_private;
 266         unsigned long irqflags;
 267         struct intel_uncore_forcewake_domain *domain;
 268         int retry_count = 100;
 269         enum forcewake_domain_id id;
 270         enum forcewake_domains fw = 0, active_domains;
 271
 272         /* Hold uncore.lock across reset to prevent any register access
 273          * with forcewake not set correctly. Wait until all pending
 274          * timers are run before holding.
 275          */
 276         while (1) {
 277                 active_domains = 0;
 278
 279                 for_each_fw_domain(domain, dev_priv, id) {
 280                         if (del_timer_sync(&domain->timer) == 0)
 281                                 continue;
 282
 283                         intel_uncore_fw_release_timer((unsigned long)domain);
 284                 }
 285
 286                 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 287
 288                 for_each_fw_domain(domain, dev_priv, id) {
 289                         if (timer_pending(&domain->timer))
 290                                 active_domains |= (1 << id);
 291                 }
 292
 293                 if (active_domains == 0)
 294                         break;
 295
 296                 if (--retry_count == 0) {
 297                         DRM_ERROR("Timed out waiting for forcewake timers to finish\n");
 298                         break;
 299                 }
 300
 301                 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 302 #if 0
 303                 cond_resched();
 304 #endif
 305         }
 306
 307         WARN_ON(active_domains);
 308
 309         for_each_fw_domain(domain, dev_priv, id)
 310                 if (domain->wake_count)
 311                         fw |= 1 << id;
 312
 313         if (fw)
 314                 dev_priv->uncore.funcs.force_wake_put(dev_priv, fw);
 315
 316         fw_domains_reset(dev_priv, FORCEWAKE_ALL);
 317
 318         if (restore) { /* If reset with a user forcewake, try to restore */
 319                 if (fw)
 320                         dev_priv->uncore.funcs.force_wake_get(dev_priv, fw);
 321
 322                 if (IS_GEN6(dev) || IS_GEN7(dev))
 323                         dev_priv->uncore.fifo_count =
 324                                 fifo_free_entries(dev_priv);
 325         }
 326
 327         if (!restore)
 328                 assert_forcewakes_inactive(dev_priv);
 329
 330         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 331 }
 332
 333 static void intel_uncore_ellc_detect(struct drm_device *dev)
 334 {
 335         struct drm_i915_private *dev_priv = dev->dev_private;
 336
 337         if ((IS_HASWELL(dev) || IS_BROADWELL(dev) ||
 338              INTEL_INFO(dev)->gen >= 9) &&
 339             (__raw_i915_read32(dev_priv, HSW_EDRAM_PRESENT) & EDRAM_ENABLED)) {
 340                 /* The docs do not explain exactly how the calculation can be
 341                  * made. It is somewhat guessable, but for now, it's always
 342                  * 128MB.
 343                  * NB: We can't write IDICR yet because we do not have gt funcs
 344                  * set up */
 345                 dev_priv->ellc_size = 128;
 346                 DRM_INFO("Found %zuMB of eLLC\n", dev_priv->ellc_size);
 347         }
 348 }
 349
 350 static void __intel_uncore_early_sanitize(struct drm_device *dev,
 351                                           bool restore_forcewake)
 352 {
 353         struct drm_i915_private *dev_priv = dev->dev_private;
 354
 355         if (HAS_FPGA_DBG_UNCLAIMED(dev))
 356                 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
 357
 358         /* clear out old GT FIFO errors */
 359         if (IS_GEN6(dev) || IS_GEN7(dev))
 360                 __raw_i915_write32(dev_priv, GTFIFODBG,
 361                                    __raw_i915_read32(dev_priv, GTFIFODBG));
 362
 363         /* WaDisableShadowRegForCpd:chv */
 364         if (IS_CHERRYVIEW(dev)) {
 365                 __raw_i915_write32(dev_priv, GTFIFOCTL,
 366                                    __raw_i915_read32(dev_priv, GTFIFOCTL) |
 367                                    GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL |
 368                                    GT_FIFO_CTL_RC6_POLICY_STALL);
 369         }
 370
 371         intel_uncore_forcewake_reset(dev, restore_forcewake);
 372 }
 373
 374 void intel_uncore_early_sanitize(struct drm_device *dev, bool restore_forcewake)
 375 {
 376         __intel_uncore_early_sanitize(dev, restore_forcewake);
 377         i915_check_and_clear_faults(dev);
 378 }
 379
 380 void intel_uncore_sanitize(struct drm_device *dev)
 381 {
 382         /* BIOS often leaves RC6 enabled, but disable it for hw init */
 383         intel_disable_gt_powersave(dev);
 384 }
 385
 386 static void __intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
 387                                          enum forcewake_domains fw_domains)
 388 {
 389         struct intel_uncore_forcewake_domain *domain;
 390         enum forcewake_domain_id id;
 391
 392         if (!dev_priv->uncore.funcs.force_wake_get)
 393                 return;
 394
 395         fw_domains &= dev_priv->uncore.fw_domains;
 396
 397         for_each_fw_domain_mask(domain, fw_domains, dev_priv, id) {
 398                 if (domain->wake_count++)
 399                         fw_domains &= ~(1 << id);
 400         }
 401
 402         if (fw_domains)
 403                 dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_domains);
 404 }
 405
 406 /**
 407  * intel_uncore_forcewake_get - grab forcewake domain references
 408  * @dev_priv: i915 device instance
 409  * @fw_domains: forcewake domains to get reference on
 410  *
 411  * This function can be used get GT's forcewake domain references.
 412  * Normal register access will handle the forcewake domains automatically.
 413  * However if some sequence requires the GT to not power down a particular
 414  * forcewake domains this function should be called at the beginning of the
 415  * sequence. And subsequently the reference should be dropped by symmetric
 416  * call to intel_unforce_forcewake_put(). Usually caller wants all the domains
 417  * to be kept awake so the @fw_domains would be then FORCEWAKE_ALL.
 418  */
 419 void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
 420                                 enum forcewake_domains fw_domains)
 421 {
 422         unsigned long irqflags;
 423
 424         if (!dev_priv->uncore.funcs.force_wake_get)
 425                 return;
 426
 427         WARN_ON(dev_priv->pm.suspended);
 428
 429         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 430         __intel_uncore_forcewake_get(dev_priv, fw_domains);
 431         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 432 }
 433
 434 /**
 435  * intel_uncore_forcewake_get__locked - grab forcewake domain references
 436  * @dev_priv: i915 device instance
 437  * @fw_domains: forcewake domains to get reference on
 438  *
 439  * See intel_uncore_forcewake_get(). This variant places the onus
 440  * on the caller to explicitly handle the dev_priv->uncore.lock spinlock.
 441  */
 442 void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
 443                                         enum forcewake_domains fw_domains)
 444 {
 445         assert_spin_locked(&dev_priv->uncore.lock);
 446
 447         if (!dev_priv->uncore.funcs.force_wake_get)
 448                 return;
 449
 450         __intel_uncore_forcewake_get(dev_priv, fw_domains);
 451 }
 452
 453 static void __intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
 454                                          enum forcewake_domains fw_domains)
 455 {
 456         struct intel_uncore_forcewake_domain *domain;
 457         enum forcewake_domain_id id;
 458
 459         if (!dev_priv->uncore.funcs.force_wake_put)
 460                 return;
 461
 462         fw_domains &= dev_priv->uncore.fw_domains;
 463
 464         for_each_fw_domain_mask(domain, fw_domains, dev_priv, id) {
 465                 if (WARN_ON(domain->wake_count == 0))
 466                         continue;
 467
 468                 if (--domain->wake_count)
 469                         continue;
 470
 471                 domain->wake_count++;
 472                 fw_domain_arm_timer(domain);
 473         }
 474 }
 475
 476 /**
 477  * intel_uncore_forcewake_put - release a forcewake domain reference
 478  * @dev_priv: i915 device instance
 479  * @fw_domains: forcewake domains to put references
 480  *
 481  * This function drops the device-level forcewakes for specified
 482  * domains obtained by intel_uncore_forcewake_get().
 483  */
 484 void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
 485                                 enum forcewake_domains fw_domains)
 486 {
 487
 488         if (!dev_priv->uncore.funcs.force_wake_put)
 489                 return;
 490
 491         lockmgr(&dev_priv->uncore.lock, LK_EXCLUSIVE);
 492         __intel_uncore_forcewake_put(dev_priv, fw_domains);
 493         lockmgr(&dev_priv->uncore.lock, LK_RELEASE);
 494 }
 495
 496 /**
 497  * intel_uncore_forcewake_put__locked - grab forcewake domain references
 498  * @dev_priv: i915 device instance
 499  * @fw_domains: forcewake domains to get reference on
 500  *
 501  * See intel_uncore_forcewake_put(). This variant places the onus
 502  * on the caller to explicitly handle the dev_priv->uncore.lock spinlock.
 503  */
 504 void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
 505                                         enum forcewake_domains fw_domains)
 506 {
 507         assert_spin_locked(&dev_priv->uncore.lock);
 508
 509         if (!dev_priv->uncore.funcs.force_wake_put)
 510                 return;
 511
 512         __intel_uncore_forcewake_put(dev_priv, fw_domains);
 513 }
 514
 515 void assert_forcewakes_inactive(struct drm_i915_private *dev_priv)
 516 {
 517         struct intel_uncore_forcewake_domain *domain;
 518         enum forcewake_domain_id id;
 519
 520         if (!dev_priv->uncore.funcs.force_wake_get)
 521                 return;
 522
 523         for_each_fw_domain(domain, dev_priv, id)
 524                 WARN_ON(domain->wake_count);
 525 }
 526
 527 /* We give fast paths for the really cool registers */
 528 #define NEEDS_FORCE_WAKE(dev_priv, reg) \
 529          ((reg) < 0x40000 && (reg) != FORCEWAKE)
 530
 531 #define REG_RANGE(reg, start, end) ((reg) >= (start) && (reg) < (end))
 532
 533 #define FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg) \
 534         (REG_RANGE((reg), 0x2000, 0x4000) || \
 535          REG_RANGE((reg), 0x5000, 0x8000) || \
 536          REG_RANGE((reg), 0xB000, 0x12000) || \
 537          REG_RANGE((reg), 0x2E000, 0x30000))
 538
 539 #define FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg) \
 540         (REG_RANGE((reg), 0x12000, 0x14000) || \
 541          REG_RANGE((reg), 0x22000, 0x24000) || \
 542          REG_RANGE((reg), 0x30000, 0x40000))
 543
 544 #define FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg) \
 545         (REG_RANGE((reg), 0x2000, 0x4000) || \
 546          REG_RANGE((reg), 0x5200, 0x8000) || \
 547          REG_RANGE((reg), 0x8300, 0x8500) || \
 548          REG_RANGE((reg), 0xB000, 0xB480) || \
 549          REG_RANGE((reg), 0xE000, 0xE800))
 550
 551 #define FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg) \
 552         (REG_RANGE((reg), 0x8800, 0x8900) || \
 553          REG_RANGE((reg), 0xD000, 0xD800) || \
 554          REG_RANGE((reg), 0x12000, 0x14000) || \
 555          REG_RANGE((reg), 0x1A000, 0x1C000) || \
 556          REG_RANGE((reg), 0x1E800, 0x1EA00) || \
 557          REG_RANGE((reg), 0x30000, 0x38000))
 558
 559 #define FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg) \
 560         (REG_RANGE((reg), 0x4000, 0x5000) || \
 561          REG_RANGE((reg), 0x8000, 0x8300) || \
 562          REG_RANGE((reg), 0x8500, 0x8600) || \
 563          REG_RANGE((reg), 0x9000, 0xB000) || \
 564          REG_RANGE((reg), 0xF000, 0x10000))
 565
 566 #define FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg) \
 567         REG_RANGE((reg), 0xB00,  0x2000)
 568
 569 #define FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg) \
 570         (REG_RANGE((reg), 0x2000, 0x2700) || \
 571          REG_RANGE((reg), 0x3000, 0x4000) || \
 572          REG_RANGE((reg), 0x5200, 0x8000) || \
 573          REG_RANGE((reg), 0x8140, 0x8160) || \
 574          REG_RANGE((reg), 0x8300, 0x8500) || \
 575          REG_RANGE((reg), 0x8C00, 0x8D00) || \
 576          REG_RANGE((reg), 0xB000, 0xB480) || \
 577          REG_RANGE((reg), 0xE000, 0xE900) || \
 578          REG_RANGE((reg), 0x24400, 0x24800))
 579
 580 #define FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg) \
 581         (REG_RANGE((reg), 0x8130, 0x8140) || \
 582          REG_RANGE((reg), 0x8800, 0x8A00) || \
 583          REG_RANGE((reg), 0xD000, 0xD800) || \
 584          REG_RANGE((reg), 0x12000, 0x14000) || \
 585          REG_RANGE((reg), 0x1A000, 0x1EA00) || \
 586          REG_RANGE((reg), 0x30000, 0x40000))
 587
 588 #define FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg) \
 589         REG_RANGE((reg), 0x9400, 0x9800)
 590
 591 #define FORCEWAKE_GEN9_BLITTER_RANGE_OFFSET(reg) \
 592         ((reg) < 0x40000 &&\
 593          !FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg) && \
 594          !FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg) && \
 595          !FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg) && \
 596          !FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg))
 597
 598 static void
 599 ilk_dummy_write(struct drm_i915_private *dev_priv)
 600 {
 601         /* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up
 602          * the chip from rc6 before touching it for real. MI_MODE is masked,
 603          * hence harmless to write 0 into. */
 604         __raw_i915_write32(dev_priv, MI_MODE, 0);
 605 }
 606
 607 static void
 608 hsw_unclaimed_reg_debug(struct drm_i915_private *dev_priv, u32 reg, bool read,
 609                         bool before)
 610 {
 611         const char *op = read ? "reading" : "writing to";
 612         const char *when = before ? "before" : "after";
 613
 614         if (!i915.mmio_debug)
 615                 return;
 616
 617         if (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM) {
 618                 WARN(1, "Unclaimed register detected %s %s register 0x%x\n",
 619                      when, op, reg);
 620                 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
 621                 i915.mmio_debug--; /* Only report the first N failures */
 622         }
 623 }
 624
 625 static void
 626 hsw_unclaimed_reg_detect(struct drm_i915_private *dev_priv)
 627 {
 628         static bool mmio_debug_once = true;
 629
 630         if (i915.mmio_debug || !mmio_debug_once)
 631                 return;
 632
 633         if (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM) {
 634                 DRM_DEBUG("Unclaimed register detected, "
 635                           "enabling oneshot unclaimed register reporting. "
 636                           "Please use i915.mmio_debug=N for more information.\n");
 637                 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
 638                 i915.mmio_debug = mmio_debug_once--;
 639         }
 640 }
 641
 642 #define GEN2_READ_HEADER(x) \
 643         u##x val = 0; \
 644         assert_device_not_suspended(dev_priv);
 645
 646 #define GEN2_READ_FOOTER \
 647         trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
 648         return val
 649
 650 #define __gen2_read(x) \
 651 static u##x \
 652 gen2_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
 653         GEN2_READ_HEADER(x); \
 654         val = __raw_i915_read##x(dev_priv, reg); \
 655         GEN2_READ_FOOTER; \
 656 }
 657
 658 #define __gen5_read(x) \
 659 static u##x \
 660 gen5_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
 661         GEN2_READ_HEADER(x); \
 662         ilk_dummy_write(dev_priv); \
 663         val = __raw_i915_read##x(dev_priv, reg); \
 664         GEN2_READ_FOOTER; \
 665 }
 666
 667 __gen5_read(8)
 668 __gen5_read(16)
 669 __gen5_read(32)
 670 __gen5_read(64)
 671 __gen2_read(8)
 672 __gen2_read(16)
 673 __gen2_read(32)
 674 __gen2_read(64)
 675
 676 #undef __gen5_read
 677 #undef __gen2_read
 678
 679 #undef GEN2_READ_FOOTER
 680 #undef GEN2_READ_HEADER
 681
 682 #define GEN6_READ_HEADER(x) \
 683         unsigned long irqflags; \
 684         u##x val = 0; \
 685         assert_device_not_suspended(dev_priv); \
 686         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
 687
 688 #define GEN6_READ_FOOTER \
 689         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \
 690         trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
 691         return val
 692
 693 static inline void __force_wake_get(struct drm_i915_private *dev_priv,
 694                                     enum forcewake_domains fw_domains)
 695 {
 696         struct intel_uncore_forcewake_domain *domain;
 697         enum forcewake_domain_id id;
 698
 699         if (WARN_ON(!fw_domains))
 700                 return;
 701
 702         /* Ideally GCC would be constant-fold and eliminate this loop */
 703         for_each_fw_domain_mask(domain, fw_domains, dev_priv, id) {
 704                 if (domain->wake_count) {
 705                         fw_domains &= ~(1 << id);
 706                         continue;
 707                 }
 708
 709                 domain->wake_count++;
 710                 fw_domain_arm_timer(domain);
 711         }
 712
 713         if (fw_domains)
 714                 dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_domains);
 715 }
 716
 717 #define __vgpu_read(x) \
 718 static u##x \
 719 vgpu_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
 720         GEN6_READ_HEADER(x); \
 721         val = __raw_i915_read##x(dev_priv, reg); \
 722         GEN6_READ_FOOTER; \
 723 }
 724
 725 #define __gen6_read(x) \
 726 static u##x \
 727 gen6_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
 728         GEN6_READ_HEADER(x); \
 729         hsw_unclaimed_reg_debug(dev_priv, reg, true, true); \
 730         if (NEEDS_FORCE_WAKE((dev_priv), (reg))) \
 731                 __force_wake_get(dev_priv, FORCEWAKE_RENDER); \
 732         val = __raw_i915_read##x(dev_priv, reg); \
 733         hsw_unclaimed_reg_debug(dev_priv, reg, true, false); \
 734         GEN6_READ_FOOTER; \
 735 }
 736
 737 #define __vlv_read(x) \
 738 static u##x \
 739 vlv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
 740         GEN6_READ_HEADER(x); \
 741         if (FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg)) \
 742                 __force_wake_get(dev_priv, FORCEWAKE_RENDER); \
 743         else if (FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg)) \
 744                 __force_wake_get(dev_priv, FORCEWAKE_MEDIA); \
 745         val = __raw_i915_read##x(dev_priv, reg); \
 746         GEN6_READ_FOOTER; \
 747 }
 748
 749 #define __chv_read(x) \
 750 static u##x \
 751 chv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
 752         GEN6_READ_HEADER(x); \
 753         if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) \
 754                 __force_wake_get(dev_priv, FORCEWAKE_RENDER); \
 755         else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) \
 756                 __force_wake_get(dev_priv, FORCEWAKE_MEDIA); \
 757         else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) \
 758                 __force_wake_get(dev_priv, \
 759                                  FORCEWAKE_RENDER | FORCEWAKE_MEDIA); \
 760         val = __raw_i915_read##x(dev_priv, reg); \
 761         GEN6_READ_FOOTER; \
 762 }
 763
 764 #define SKL_NEEDS_FORCE_WAKE(dev_priv, reg)     \
 765          ((reg) < 0x40000 && !FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg))
 766
 767 #define __gen9_read(x) \
 768 static u##x \
 769 gen9_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
 770         enum forcewake_domains fw_engine; \
 771         GEN6_READ_HEADER(x); \
 772         if (!SKL_NEEDS_FORCE_WAKE((dev_priv), (reg)))   \
 773                 fw_engine = 0; \
 774         else if (FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg))       \
 775                 fw_engine = FORCEWAKE_RENDER; \
 776         else if (FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg)) \
 777                 fw_engine = FORCEWAKE_MEDIA; \
 778         else if (FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg)) \
 779                 fw_engine = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \
 780         else \
 781                 fw_engine = FORCEWAKE_BLITTER; \
 782         if (fw_engine) \
 783                 __force_wake_get(dev_priv, fw_engine); \
 784         val = __raw_i915_read##x(dev_priv, reg); \
 785         GEN6_READ_FOOTER; \
 786 }
 787
 788 __vgpu_read(8)
 789 __vgpu_read(16)
 790 __vgpu_read(32)
 791 __vgpu_read(64)
 792 __gen9_read(8)
 793 __gen9_read(16)
 794 __gen9_read(32)
 795 __gen9_read(64)
 796 __chv_read(8)
 797 __chv_read(16)
 798 __chv_read(32)
 799 __chv_read(64)
 800 __vlv_read(8)
 801 __vlv_read(16)
 802 __vlv_read(32)
 803 __vlv_read(64)
 804 __gen6_read(8)
 805 __gen6_read(16)
 806 __gen6_read(32)
 807 __gen6_read(64)
 808
 809 #undef __gen9_read
 810 #undef __chv_read
 811 #undef __vlv_read
 812 #undef __gen6_read
 813 #undef __vgpu_read
 814 #undef GEN6_READ_FOOTER
 815 #undef GEN6_READ_HEADER
 816
 817 #define GEN2_WRITE_HEADER \
 818         trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
 819         assert_device_not_suspended(dev_priv); \
 820
 821 #define GEN2_WRITE_FOOTER
 822
 823 #define __gen2_write(x) \
 824 static void \
 825 gen2_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
 826         GEN2_WRITE_HEADER; \
 827         __raw_i915_write##x(dev_priv, reg, val); \
 828         GEN2_WRITE_FOOTER; \
 829 }
 830
 831 #define __gen5_write(x) \
 832 static void \
 833 gen5_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
 834         GEN2_WRITE_HEADER; \
 835         ilk_dummy_write(dev_priv); \
 836         __raw_i915_write##x(dev_priv, reg, val); \
 837         GEN2_WRITE_FOOTER; \
 838 }
 839
 840 __gen5_write(8)
 841 __gen5_write(16)
 842 __gen5_write(32)
 843 __gen5_write(64)
 844 __gen2_write(8)
 845 __gen2_write(16)
 846 __gen2_write(32)
 847 __gen2_write(64)
 848
 849 #undef __gen5_write
 850 #undef __gen2_write
 851
 852 #undef GEN2_WRITE_FOOTER
 853 #undef GEN2_WRITE_HEADER
 854
 855 #define GEN6_WRITE_HEADER \
 856         unsigned long irqflags; \
 857         trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
 858         assert_device_not_suspended(dev_priv); \
 859         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
 860
 861 #define GEN6_WRITE_FOOTER \
 862         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags)
 863
 864 #define __gen6_write(x) \
 865 static void \
 866 gen6_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
 867         u32 __fifo_ret = 0; \
 868         GEN6_WRITE_HEADER; \
 869         if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
 870                 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
 871         } \
 872         __raw_i915_write##x(dev_priv, reg, val); \
 873         if (unlikely(__fifo_ret)) { \
 874                 gen6_gt_check_fifodbg(dev_priv); \
 875         } \
 876         GEN6_WRITE_FOOTER; \
 877 }
 878
 879 #define __hsw_write(x) \
 880 static void \
 881 hsw_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
 882         u32 __fifo_ret = 0; \
 883         GEN6_WRITE_HEADER; \
 884         if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
 885                 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
 886         } \
 887         hsw_unclaimed_reg_debug(dev_priv, reg, false, true); \
 888         __raw_i915_write##x(dev_priv, reg, val); \
 889         if (unlikely(__fifo_ret)) { \
 890                 gen6_gt_check_fifodbg(dev_priv); \
 891         } \
 892         hsw_unclaimed_reg_debug(dev_priv, reg, false, false); \
 893         hsw_unclaimed_reg_detect(dev_priv); \
 894         GEN6_WRITE_FOOTER; \
 895 }
 896
 897 #define __vgpu_write(x) \
 898 static void vgpu_write##x(struct drm_i915_private *dev_priv, \
 899                           off_t reg, u##x val, bool trace) { \
 900         GEN6_WRITE_HEADER; \
 901         __raw_i915_write##x(dev_priv, reg, val); \
 902         GEN6_WRITE_FOOTER; \
 903 }
 904
 905 static const u32 gen8_shadowed_regs[] = {
 906         FORCEWAKE_MT,
 907         GEN6_RPNSWREQ,
 908         GEN6_RC_VIDEO_FREQ,
 909         RING_TAIL(RENDER_RING_BASE),
 910         RING_TAIL(GEN6_BSD_RING_BASE),
 911         RING_TAIL(VEBOX_RING_BASE),
 912         RING_TAIL(BLT_RING_BASE),
 913         /* TODO: Other registers are not yet used */
 914 };
 915
 916 static bool is_gen8_shadowed(struct drm_i915_private *dev_priv, u32 reg)
 917 {
 918         int i;
 919         for (i = 0; i < ARRAY_SIZE(gen8_shadowed_regs); i++)
 920                 if (reg == gen8_shadowed_regs[i])
 921                         return true;
 922
 923         return false;
 924 }
 925
 926 #define __gen8_write(x) \
 927 static void \
 928 gen8_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
 929         GEN6_WRITE_HEADER; \
 930         hsw_unclaimed_reg_debug(dev_priv, reg, false, true); \
 931         if (reg < 0x40000 && !is_gen8_shadowed(dev_priv, reg)) \
 932                 __force_wake_get(dev_priv, FORCEWAKE_RENDER); \
 933         __raw_i915_write##x(dev_priv, reg, val); \
 934         hsw_unclaimed_reg_debug(dev_priv, reg, false, false); \
 935         hsw_unclaimed_reg_detect(dev_priv); \
 936         GEN6_WRITE_FOOTER; \
 937 }
 938
 939 #define __chv_write(x) \
 940 static void \
 941 chv_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
 942         bool shadowed = is_gen8_shadowed(dev_priv, reg); \
 943         GEN6_WRITE_HEADER; \
 944         if (!shadowed) { \
 945                 if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) \
 946                         __force_wake_get(dev_priv, FORCEWAKE_RENDER); \
 947                 else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) \
 948                         __force_wake_get(dev_priv, FORCEWAKE_MEDIA); \
 949                 else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) \
 950                         __force_wake_get(dev_priv, FORCEWAKE_RENDER | FORCEWAKE_MEDIA); \
 951         } \
 952         __raw_i915_write##x(dev_priv, reg, val); \
 953         GEN6_WRITE_FOOTER; \
 954 }
 955
 956 static const u32 gen9_shadowed_regs[] = {
 957         RING_TAIL(RENDER_RING_BASE),
 958         RING_TAIL(GEN6_BSD_RING_BASE),
 959         RING_TAIL(VEBOX_RING_BASE),
 960         RING_TAIL(BLT_RING_BASE),
 961         FORCEWAKE_BLITTER_GEN9,
 962         FORCEWAKE_RENDER_GEN9,
 963         FORCEWAKE_MEDIA_GEN9,
 964         GEN6_RPNSWREQ,
 965         GEN6_RC_VIDEO_FREQ,
 966         /* TODO: Other registers are not yet used */
 967 };
 968
 969 static bool is_gen9_shadowed(struct drm_i915_private *dev_priv, u32 reg)
 970 {
 971         int i;
 972         for (i = 0; i < ARRAY_SIZE(gen9_shadowed_regs); i++)
 973                 if (reg == gen9_shadowed_regs[i])
 974                         return true;
 975
 976         return false;
 977 }
 978
 979 #define __gen9_write(x) \
 980 static void \
 981 gen9_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, \
 982                 bool trace) { \
 983         enum forcewake_domains fw_engine; \
 984         GEN6_WRITE_HEADER; \
 985         if (!SKL_NEEDS_FORCE_WAKE((dev_priv), (reg)) || \
 986             is_gen9_shadowed(dev_priv, reg)) \
 987                 fw_engine = 0; \
 988         else if (FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg)) \
 989                 fw_engine = FORCEWAKE_RENDER; \
 990         else if (FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg)) \
 991                 fw_engine = FORCEWAKE_MEDIA; \
 992         else if (FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg)) \
 993                 fw_engine = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \
 994         else \
 995                 fw_engine = FORCEWAKE_BLITTER; \
 996         if (fw_engine) \
 997                 __force_wake_get(dev_priv, fw_engine); \
 998         __raw_i915_write##x(dev_priv, reg, val); \
 999         GEN6_WRITE_FOOTER; \
1000 }
1001
1002 __gen9_write(8)
1003 __gen9_write(16)
1004 __gen9_write(32)
1005 __gen9_write(64)
1006 __chv_write(8)
1007 __chv_write(16)
1008 __chv_write(32)
1009 __chv_write(64)
1010 __gen8_write(8)
1011 __gen8_write(16)
1012 __gen8_write(32)
1013 __gen8_write(64)
1014 __hsw_write(8)
1015 __hsw_write(16)
1016 __hsw_write(32)
1017 __hsw_write(64)
1018 __gen6_write(8)
1019 __gen6_write(16)
1020 __gen6_write(32)
1021 __gen6_write(64)
1022 __vgpu_write(8)
1023 __vgpu_write(16)
1024 __vgpu_write(32)
1025 __vgpu_write(64)
1026
1027 #undef __gen9_write
1028 #undef __chv_write
1029 #undef __gen8_write
1030 #undef __hsw_write
1031 #undef __gen6_write
1032 #undef __vgpu_write
1033 #undef GEN6_WRITE_FOOTER
1034 #undef GEN6_WRITE_HEADER
1035
1036 #define ASSIGN_WRITE_MMIO_VFUNCS(x) \
1037 do { \
1038         dev_priv->uncore.funcs.mmio_writeb = x##_write8; \
1039         dev_priv->uncore.funcs.mmio_writew = x##_write16; \
1040         dev_priv->uncore.funcs.mmio_writel = x##_write32; \
1041         dev_priv->uncore.funcs.mmio_writeq = x##_write64; \
1042 } while (0)
1043
1044 #define ASSIGN_READ_MMIO_VFUNCS(x) \
1045 do { \
1046         dev_priv->uncore.funcs.mmio_readb = x##_read8; \
1047         dev_priv->uncore.funcs.mmio_readw = x##_read16; \
1048         dev_priv->uncore.funcs.mmio_readl = x##_read32; \
1049         dev_priv->uncore.funcs.mmio_readq = x##_read64; \
1050 } while (0)
1051
1052
1053 static void fw_domain_init(struct drm_i915_private *dev_priv,
1054                            enum forcewake_domain_id domain_id,
1055                            u32 reg_set, u32 reg_ack)
1056 {
1057         struct intel_uncore_forcewake_domain *d;
1058
1059         if (WARN_ON(domain_id >= FW_DOMAIN_ID_COUNT))
1060                 return;
1061
1062         d = &dev_priv->uncore.fw_domain[domain_id];
1063
1064         WARN_ON(d->wake_count);
1065
1066         d->wake_count = 0;
1067         d->reg_set = reg_set;
1068         d->reg_ack = reg_ack;
1069
1070         if (IS_GEN6(dev_priv)) {
1071                 d->val_reset = 0;
1072                 d->val_set = FORCEWAKE_KERNEL;
1073                 d->val_clear = 0;
1074         } else {
1075                 /* WaRsClearFWBitsAtReset:bdw,skl */
1076                 d->val_reset = _MASKED_BIT_DISABLE(0xffff);
1077                 d->val_set = _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL);
1078                 d->val_clear = _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL);
1079         }
1080
1081         if (IS_VALLEYVIEW(dev_priv))
1082                 d->reg_post = FORCEWAKE_ACK_VLV;
1083         else if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv) || IS_GEN8(dev_priv))
1084                 d->reg_post = ECOBUS;
1085         else
1086                 d->reg_post = 0;
1087
1088         d->i915 = dev_priv;
1089         d->id = domain_id;
1090
1091         setup_timer(&d->timer, intel_uncore_fw_release_timer, (unsigned long)d);
1092
1093         dev_priv->uncore.fw_domains |= (1 << domain_id);
1094
1095         fw_domain_reset(d);
1096 }
1097
1098 static void intel_uncore_fw_domains_init(struct drm_device *dev)
1099 {
1100         struct drm_i915_private *dev_priv = dev->dev_private;
1101
1102         if (INTEL_INFO(dev_priv->dev)->gen <= 5)
1103                 return;
1104
1105         if (IS_GEN9(dev)) {
1106                 dev_priv->uncore.funcs.force_wake_get = fw_domains_get;
1107                 dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
1108                 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1109                                FORCEWAKE_RENDER_GEN9,
1110                                FORCEWAKE_ACK_RENDER_GEN9);
1111                 fw_domain_init(dev_priv, FW_DOMAIN_ID_BLITTER,
1112                                FORCEWAKE_BLITTER_GEN9,
1113                                FORCEWAKE_ACK_BLITTER_GEN9);
1114                 fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA,
1115                                FORCEWAKE_MEDIA_GEN9, FORCEWAKE_ACK_MEDIA_GEN9);
1116         } else if (IS_VALLEYVIEW(dev)) {
1117                 dev_priv->uncore.funcs.force_wake_get = fw_domains_get;
1118                 if (!IS_CHERRYVIEW(dev))
1119                         dev_priv->uncore.funcs.force_wake_put =
1120                                 fw_domains_put_with_fifo;
1121                 else
1122                         dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
1123                 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1124                                FORCEWAKE_VLV, FORCEWAKE_ACK_VLV);
1125                 fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA,
1126                                FORCEWAKE_MEDIA_VLV, FORCEWAKE_ACK_MEDIA_VLV);
1127         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1128                 dev_priv->uncore.funcs.force_wake_get =
1129                         fw_domains_get_with_thread_status;
1130                 dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
1131                 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1132                                FORCEWAKE_MT, FORCEWAKE_ACK_HSW);
1133         } else if (IS_IVYBRIDGE(dev)) {
1134                 u32 ecobus;
1135
1136                 /* IVB configs may use multi-threaded forcewake */
1137
1138                 /* A small trick here - if the bios hasn't configured
1139                  * MT forcewake, and if the device is in RC6, then
1140                  * force_wake_mt_get will not wake the device and the
1141                  * ECOBUS read will return zero. Which will be
1142                  * (correctly) interpreted by the test below as MT
1143                  * forcewake being disabled.
1144                  */
1145                 dev_priv->uncore.funcs.force_wake_get =
1146                         fw_domains_get_with_thread_status;
1147                 dev_priv->uncore.funcs.force_wake_put =
1148                         fw_domains_put_with_fifo;
1149
1150                 /* We need to init first for ECOBUS access and then
1151                  * determine later if we want to reinit, in case of MT access is
1152                  * not working. In this stage we don't know which flavour this
1153                  * ivb is, so it is better to reset also the gen6 fw registers
1154                  * before the ecobus check.
1155                  */
1156
1157                 __raw_i915_write32(dev_priv, FORCEWAKE, 0);
1158                 __raw_posting_read(dev_priv, ECOBUS);
1159
1160                 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1161                                FORCEWAKE_MT, FORCEWAKE_MT_ACK);
1162
1163                 mutex_lock(&dev->struct_mutex);
1164                 fw_domains_get_with_thread_status(dev_priv, FORCEWAKE_ALL);
1165                 ecobus = __raw_i915_read32(dev_priv, ECOBUS);
1166                 fw_domains_put_with_fifo(dev_priv, FORCEWAKE_ALL);
1167                 mutex_unlock(&dev->struct_mutex);
1168
1169                 if (!(ecobus & FORCEWAKE_MT_ENABLE)) {
1170                         DRM_INFO("No MT forcewake available on Ivybridge, this can result in issues\n");
1171                         DRM_INFO("when using vblank-synced partial screen updates.\n");
1172                         fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1173                                        FORCEWAKE, FORCEWAKE_ACK);
1174                 }
1175         } else if (IS_GEN6(dev)) {
1176                 dev_priv->uncore.funcs.force_wake_get =
1177                         fw_domains_get_with_thread_status;
1178                 dev_priv->uncore.funcs.force_wake_put =
1179                         fw_domains_put_with_fifo;
1180                 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1181                                FORCEWAKE, FORCEWAKE_ACK);
1182         }
1183
1184         /* All future platforms are expected to require complex power gating */
1185         WARN_ON(dev_priv->uncore.fw_domains == 0);
1186 }
1187
1188 void intel_uncore_init(struct drm_device *dev)
1189 {
1190         struct drm_i915_private *dev_priv = dev->dev_private;
1191
1192         i915_check_vgpu(dev);
1193
1194         intel_uncore_ellc_detect(dev);
1195         intel_uncore_fw_domains_init(dev);
1196         __intel_uncore_early_sanitize(dev, false);
1197
1198         switch (INTEL_INFO(dev)->gen) {
1199         default:
1200                 MISSING_CASE(INTEL_INFO(dev)->gen);
1201                 return;
1202         case 9:
1203                 ASSIGN_WRITE_MMIO_VFUNCS(gen9);
1204                 ASSIGN_READ_MMIO_VFUNCS(gen9);
1205                 break;
1206         case 8:
1207                 if (IS_CHERRYVIEW(dev)) {
1208                         ASSIGN_WRITE_MMIO_VFUNCS(chv);
1209                         ASSIGN_READ_MMIO_VFUNCS(chv);
1210
1211                 } else {
1212                         ASSIGN_WRITE_MMIO_VFUNCS(gen8);
1213                         ASSIGN_READ_MMIO_VFUNCS(gen6);
1214                 }
1215                 break;
1216         case 7:
1217         case 6:
1218                 if (IS_HASWELL(dev)) {
1219                         ASSIGN_WRITE_MMIO_VFUNCS(hsw);
1220                 } else {
1221                         ASSIGN_WRITE_MMIO_VFUNCS(gen6);
1222                 }
1223
1224                 if (IS_VALLEYVIEW(dev)) {
1225                         ASSIGN_READ_MMIO_VFUNCS(vlv);
1226                 } else {
1227                         ASSIGN_READ_MMIO_VFUNCS(gen6);
1228                 }
1229                 break;
1230         case 5:
1231                 ASSIGN_WRITE_MMIO_VFUNCS(gen5);
1232                 ASSIGN_READ_MMIO_VFUNCS(gen5);
1233                 break;
1234         case 4:
1235         case 3:
1236         case 2:
1237                 ASSIGN_WRITE_MMIO_VFUNCS(gen2);
1238                 ASSIGN_READ_MMIO_VFUNCS(gen2);
1239                 break;
1240         }
1241
1242         if (intel_vgpu_active(dev)) {
1243                 ASSIGN_WRITE_MMIO_VFUNCS(vgpu);
1244                 ASSIGN_READ_MMIO_VFUNCS(vgpu);
1245         }
1246
1247         i915_check_and_clear_faults(dev);
1248 }
1249 #undef ASSIGN_WRITE_MMIO_VFUNCS
1250 #undef ASSIGN_READ_MMIO_VFUNCS
1251
1252 void intel_uncore_fini(struct drm_device *dev)
1253 {
1254         /* Paranoia: make sure we have disabled everything before we exit. */
1255         intel_uncore_sanitize(dev);
1256         intel_uncore_forcewake_reset(dev, false);
1257 }
1258
1259 #define GEN_RANGE(l, h) GENMASK(h, l)
1260
1261 static const struct register_whitelist {
1262         uint64_t offset;
1263         uint32_t size;
1264         /* supported gens, 0x10 for 4, 0x30 for 4 and 5, etc. */
1265         uint32_t gen_bitmask;
1266 } whitelist[] = {
1267         { RING_TIMESTAMP(RENDER_RING_BASE), 8, GEN_RANGE(4, 9) },
1268 };
1269
1270 int i915_reg_read_ioctl(struct drm_device *dev,
1271                         void *data, struct drm_file *file)
1272 {
1273         struct drm_i915_private *dev_priv = dev->dev_private;
1274         struct drm_i915_reg_read *reg = data;
1275         struct register_whitelist const *entry = whitelist;
1276         unsigned size;
1277         u64 offset;
1278         int i, ret = 0;
1279
1280         for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) {
1281                 if (entry->offset == (reg->offset & -entry->size) &&
1282                     (1 << INTEL_INFO(dev)->gen & entry->gen_bitmask))
1283                         break;
1284         }
1285
1286         if (i == ARRAY_SIZE(whitelist))
1287                 return -EINVAL;
1288
1289         /* We use the low bits to encode extra flags as the register should
1290          * be naturally aligned (and those that are not so aligned merely
1291          * limit the available flags for that register).
1292          */
1293         offset = entry->offset;
1294         size = entry->size;
1295         size |= reg->offset ^ offset;
1296
1297         intel_runtime_pm_get(dev_priv);
1298
1299         switch (size) {
1300         case 8 | 1:
1301                 reg->val = I915_READ64_2x32(offset, offset+4);
1302                 break;
1303         case 8:
1304                 reg->val = I915_READ64(offset);
1305                 break;
1306         case 4:
1307                 reg->val = I915_READ(offset);
1308                 break;
1309         case 2:
1310                 reg->val = I915_READ16(offset);
1311                 break;
1312         case 1:
1313                 reg->val = I915_READ8(offset);
1314                 break;
1315         default:
1316                 ret = -EINVAL;
1317                 goto out;
1318         }
1319
1320 out:
1321         intel_runtime_pm_put(dev_priv);
1322         return ret;
1323 }
1324
1325 int i915_get_reset_stats_ioctl(struct drm_device *dev,
1326                                void *data, struct drm_file *file)
1327 {
1328         struct drm_i915_private *dev_priv = dev->dev_private;
1329         struct drm_i915_reset_stats *args = data;
1330         struct i915_ctx_hang_stats *hs;
1331         struct intel_context *ctx;
1332         int ret;
1333
1334         if (args->flags || args->pad)
1335                 return -EINVAL;
1336
1337         if (args->ctx_id == DEFAULT_CONTEXT_HANDLE && !capable(CAP_SYS_ADMIN))
1338                 return -EPERM;
1339
1340         ret = mutex_lock_interruptible(&dev->struct_mutex);
1341         if (ret)
1342                 return ret;
1343
1344         ctx = i915_gem_context_get(file->driver_priv, args->ctx_id);
1345         if (IS_ERR(ctx)) {
1346                 mutex_unlock(&dev->struct_mutex);
1347                 return PTR_ERR(ctx);
1348         }
1349         hs = &ctx->hang_stats;
1350
1351         if (capable(CAP_SYS_ADMIN))
1352                 args->reset_count = i915_reset_count(&dev_priv->gpu_error);
1353         else
1354                 args->reset_count = 0;
1355
1356         args->batch_active = hs->batch_active;
1357         args->batch_pending = hs->batch_pending;
1358
1359         mutex_unlock(&dev->struct_mutex);
1360
1361         return 0;
1362 }
1363
1364 static int i915_reset_complete(struct drm_device *dev)
1365 {
1366         u8 gdrst;
1367         pci_read_config_byte(dev->pdev, I915_GDRST, &gdrst);
1368         return (gdrst & GRDOM_RESET_STATUS) == 0;
1369 }
1370
1371 static int i915_do_reset(struct drm_device *dev)
1372 {
1373         /* assert reset for at least 20 usec */
1374         pci_write_config_byte(dev->pdev, I915_GDRST, GRDOM_RESET_ENABLE);
1375         udelay(20);
1376         pci_write_config_byte(dev->pdev, I915_GDRST, 0);
1377
1378         return wait_for(i915_reset_complete(dev), 500);
1379 }
1380
1381 static int g4x_reset_complete(struct drm_device *dev)
1382 {
1383         u8 gdrst;
1384         pci_read_config_byte(dev->pdev, I915_GDRST, &gdrst);
1385         return (gdrst & GRDOM_RESET_ENABLE) == 0;
1386 }
1387
1388 static int g33_do_reset(struct drm_device *dev)
1389 {
1390         pci_write_config_byte(dev->pdev, I915_GDRST, GRDOM_RESET_ENABLE);
1391         return wait_for(g4x_reset_complete(dev), 500);
1392 }
1393
1394 static int g4x_do_reset(struct drm_device *dev)
1395 {
1396         struct drm_i915_private *dev_priv = dev->dev_private;
1397         int ret;
1398
1399         pci_write_config_byte(dev->pdev, I915_GDRST,
1400                               GRDOM_RENDER | GRDOM_RESET_ENABLE);
1401         ret =  wait_for(g4x_reset_complete(dev), 500);
1402         if (ret)
1403                 return ret;
1404
1405         /* WaVcpClkGateDisableForMediaReset:ctg,elk */
1406         I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) | VCP_UNIT_CLOCK_GATE_DISABLE);
1407         POSTING_READ(VDECCLK_GATE_D);
1408
1409         pci_write_config_byte(dev->pdev, I915_GDRST,
1410                               GRDOM_MEDIA | GRDOM_RESET_ENABLE);
1411         ret =  wait_for(g4x_reset_complete(dev), 500);
1412         if (ret)
1413                 return ret;
1414
1415         /* WaVcpClkGateDisableForMediaReset:ctg,elk */
1416         I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) & ~VCP_UNIT_CLOCK_GATE_DISABLE);
1417         POSTING_READ(VDECCLK_GATE_D);
1418
1419         pci_write_config_byte(dev->pdev, I915_GDRST, 0);
1420
1421         return 0;
1422 }
1423
1424 static int ironlake_do_reset(struct drm_device *dev)
1425 {
1426         struct drm_i915_private *dev_priv = dev->dev_private;
1427         int ret;
1428
1429         I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
1430                    ILK_GRDOM_RENDER | ILK_GRDOM_RESET_ENABLE);
1431         ret = wait_for((I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) &
1432                         ILK_GRDOM_RESET_ENABLE) == 0, 500);
1433         if (ret)
1434                 return ret;
1435
1436         I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
1437                    ILK_GRDOM_MEDIA | ILK_GRDOM_RESET_ENABLE);
1438         ret = wait_for((I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) &
1439                         ILK_GRDOM_RESET_ENABLE) == 0, 500);
1440         if (ret)
1441                 return ret;
1442
1443         I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, 0);
1444
1445         return 0;
1446 }
1447
1448 static int gen6_do_reset(struct drm_device *dev)
1449 {
1450         struct drm_i915_private *dev_priv = dev->dev_private;
1451         int     ret;
1452
1453         /* Reset the chip */
1454
1455         /* GEN6_GDRST is not in the gt power well, no need to check
1456          * for fifo space for the write or forcewake the chip for
1457          * the read
1458          */
1459         __raw_i915_write32(dev_priv, GEN6_GDRST, GEN6_GRDOM_FULL);
1460
1461         /* Spin waiting for the device to ack the reset request */
1462         ret = wait_for((__raw_i915_read32(dev_priv, GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500);
1463
1464         intel_uncore_forcewake_reset(dev, true);
1465
1466         return ret;
1467 }
1468
1469 static int wait_for_register(struct drm_i915_private *dev_priv,
1470                              const u32 reg,
1471                              const u32 mask,
1472                              const u32 value,
1473                              const unsigned long timeout_ms)
1474 {
1475         return wait_for((I915_READ(reg) & mask) == value, timeout_ms);
1476 }
1477
1478 static int gen8_do_reset(struct drm_device *dev)
1479 {
1480         struct drm_i915_private *dev_priv = dev->dev_private;
1481         struct intel_engine_cs *engine;
1482         int i;
1483
1484         for_each_ring(engine, dev_priv, i) {
1485                 I915_WRITE(RING_RESET_CTL(engine->mmio_base),
1486                            _MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET));
1487
1488                 if (wait_for_register(dev_priv,
1489                                       RING_RESET_CTL(engine->mmio_base),
1490                                       RESET_CTL_READY_TO_RESET,
1491                                       RESET_CTL_READY_TO_RESET,
1492                                       700)) {
1493                         DRM_ERROR("%s: reset request timeout\n", engine->name);
1494                         goto not_ready;
1495                 }
1496         }
1497
1498         return gen6_do_reset(dev);
1499
1500 not_ready:
1501         for_each_ring(engine, dev_priv, i)
1502                 I915_WRITE(RING_RESET_CTL(engine->mmio_base),
1503                            _MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET));
1504
1505         return -EIO;
1506 }
1507
1508 static int (*intel_get_gpu_reset(struct drm_device *dev))(struct drm_device *)
1509 {
1510         if (!i915.reset)
1511                 return NULL;
1512
1513         if (INTEL_INFO(dev)->gen >= 8)
1514                 return gen8_do_reset;
1515         else if (INTEL_INFO(dev)->gen >= 6)
1516                 return gen6_do_reset;
1517         else if (IS_GEN5(dev))
1518                 return ironlake_do_reset;
1519         else if (IS_G4X(dev))
1520                 return g4x_do_reset;
1521         else if (IS_G33(dev))
1522                 return g33_do_reset;
1523         else if (INTEL_INFO(dev)->gen >= 3)
1524                 return i915_do_reset;
1525         else
1526                 return NULL;
1527 }
1528
1529 int intel_gpu_reset(struct drm_device *dev)
1530 {
1531         int (*reset)(struct drm_device *);
1532
1533         reset = intel_get_gpu_reset(dev);
1534         if (reset == NULL)
1535                 return -ENODEV;
1536
1537         return reset(dev);
1538 }
1539
1540 bool intel_has_gpu_reset(struct drm_device *dev)
1541 {
1542         return intel_get_gpu_reset(dev) != NULL;
1543 }
1544
1545 void intel_uncore_check_errors(struct drm_device *dev)
1546 {
1547         struct drm_i915_private *dev_priv = dev->dev_private;
1548
1549         if (HAS_FPGA_DBG_UNCLAIMED(dev) &&
1550             (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) {
1551                 DRM_ERROR("Unclaimed register before interrupt\n");
1552                 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
1553         }
1554 }