2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
26 * Copyright (c) 2011 The FreeBSD Foundation
27 * All rights reserved.
29 * This software was developed by Konstantin Belousov under sponsorship from
30 * the FreeBSD Foundation.
32 * Redistribution and use in source and binary forms, with or without
33 * modification, are permitted provided that the following conditions
35 * 1. Redistributions of source code must retain the above copyright
36 * notice, this list of conditions and the following disclaimer.
37 * 2. Redistributions in binary form must reproduce the above copyright
38 * notice, this list of conditions and the following disclaimer in the
39 * documentation and/or other materials provided with the distribution.
41 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
42 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
43 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
44 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
45 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
46 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
47 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
48 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
49 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
50 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
55 #include <sys/resourcevar.h>
56 #include <sys/sfbuf.h>
57 #include <machine/md_var.h>
60 #include <drm/i915_drm.h>
62 #include "i915_trace.h"
63 #include "intel_drv.h"
64 #include <linux/shmem_fs.h>
65 #include <linux/slab.h>
66 #include <linux/swap.h>
67 #include <linux/pci.h>
69 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
70 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
71 static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
73 bool map_and_fenceable,
75 static int i915_gem_phys_pwrite(struct drm_device *dev,
76 struct drm_i915_gem_object *obj,
77 struct drm_i915_gem_pwrite *args,
78 struct drm_file *file);
80 static void i915_gem_write_fence(struct drm_device *dev, int reg,
81 struct drm_i915_gem_object *obj);
82 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
83 struct drm_i915_fence_reg *fence,
86 static long i915_gem_purge(struct drm_i915_private *dev_priv, long target);
87 static void i915_gem_object_truncate(struct drm_i915_gem_object *obj);
89 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
92 i915_gem_release_mmap(obj);
94 /* As we do not have an associated fence register, we will force
95 * a tiling change if we ever need to acquire one.
97 obj->fence_dirty = false;
98 obj->fence_reg = I915_FENCE_REG_NONE;
101 static bool i915_gem_object_is_inactive(struct drm_i915_gem_object *obj);
102 static void i915_gem_lowmem(void *arg);
104 /* some bookkeeping */
105 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
108 dev_priv->mm.object_count++;
109 dev_priv->mm.object_memory += size;
112 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
115 dev_priv->mm.object_count--;
116 dev_priv->mm.object_memory -= size;
120 i915_gem_wait_for_error(struct i915_gpu_error *error)
124 #define EXIT_COND (!i915_reset_in_progress(error) || \
125 i915_terminally_wedged(error))
130 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
131 * userspace. If it takes that long something really bad is going on and
132 * we should simply try to bail out and fail as gracefully as possible.
134 ret = wait_event_interruptible_timeout(error->reset_queue,
138 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
140 } else if (ret < 0) {
148 int i915_mutex_lock_interruptible(struct drm_device *dev)
150 struct drm_i915_private *dev_priv = dev->dev_private;
153 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
157 ret = lockmgr(&dev->struct_mutex, LK_EXCLUSIVE|LK_SLEEPFAIL);
161 WARN_ON(i915_verify_lists(dev));
166 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
172 i915_gem_init_ioctl(struct drm_device *dev, void *data,
173 struct drm_file *file)
175 struct drm_i915_private *dev_priv = dev->dev_private;
176 struct drm_i915_gem_init *args = data;
178 if (drm_core_check_feature(dev, DRIVER_MODESET))
181 if (args->gtt_start >= args->gtt_end ||
182 (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
185 /* GEM with user mode setting was never supported on ilk and later. */
186 if (INTEL_INFO(dev)->gen >= 5)
189 mutex_lock(&dev->struct_mutex);
190 i915_gem_setup_global_gtt(dev, args->gtt_start, args->gtt_end,
192 dev_priv->gtt.mappable_end = args->gtt_end;
193 mutex_unlock(&dev->struct_mutex);
199 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
200 struct drm_file *file)
202 struct drm_i915_private *dev_priv = dev->dev_private;
203 struct drm_i915_gem_get_aperture *args = data;
204 struct drm_i915_gem_object *obj;
208 mutex_lock(&dev->struct_mutex);
209 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
211 pinned += obj->gtt_space->size;
212 mutex_unlock(&dev->struct_mutex);
214 args->aper_size = dev_priv->gtt.total;
215 args->aper_available_size = args->aper_size - pinned;
220 void i915_gem_object_free(struct drm_i915_gem_object *obj)
226 i915_gem_create(struct drm_file *file,
227 struct drm_device *dev,
231 struct drm_i915_gem_object *obj;
235 size = roundup(size, PAGE_SIZE);
239 /* Allocate the new object */
240 obj = i915_gem_alloc_object(dev, size);
244 ret = drm_gem_handle_create(file, &obj->base, &handle);
246 drm_gem_object_release(&obj->base);
247 i915_gem_info_remove_obj(dev->dev_private, obj->base.size);
248 i915_gem_object_free(obj);
252 /* drop reference from allocate - handle holds it now */
253 drm_gem_object_unreference(&obj->base);
254 trace_i915_gem_object_create(obj);
261 i915_gem_dumb_create(struct drm_file *file,
262 struct drm_device *dev,
263 struct drm_mode_create_dumb *args)
266 /* have to work out size/pitch and return them */
267 args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64);
268 args->size = args->pitch * args->height;
269 return i915_gem_create(file, dev,
270 args->size, &args->handle);
273 int i915_gem_dumb_destroy(struct drm_file *file,
274 struct drm_device *dev,
278 return drm_gem_handle_delete(file, handle);
282 * Creates a new mm object and returns a handle to it.
285 i915_gem_create_ioctl(struct drm_device *dev, void *data,
286 struct drm_file *file)
288 struct drm_i915_gem_create *args = data;
290 return i915_gem_create(file, dev,
291 args->size, &args->handle);
295 __copy_to_user_swizzled(char __user *cpu_vaddr,
296 const char *gpu_vaddr, int gpu_offset,
299 int ret, cpu_offset = 0;
302 int cacheline_end = ALIGN(gpu_offset + 1, 64);
303 int this_length = min(cacheline_end - gpu_offset, length);
304 int swizzled_gpu_offset = gpu_offset ^ 64;
306 ret = __copy_to_user(cpu_vaddr + cpu_offset,
307 gpu_vaddr + swizzled_gpu_offset,
312 cpu_offset += this_length;
313 gpu_offset += this_length;
314 length -= this_length;
321 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
322 const char __user *cpu_vaddr,
325 int ret, cpu_offset = 0;
328 int cacheline_end = ALIGN(gpu_offset + 1, 64);
329 int this_length = min(cacheline_end - gpu_offset, length);
330 int swizzled_gpu_offset = gpu_offset ^ 64;
332 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
333 cpu_vaddr + cpu_offset,
338 cpu_offset += this_length;
339 gpu_offset += this_length;
340 length -= this_length;
346 /* Per-page copy function for the shmem pread fastpath.
347 * Flushes invalid cachelines before reading the target if
348 * needs_clflush is set. */
350 shmem_pread_fast(struct vm_page *page, int shmem_page_offset, int page_length,
351 char __user *user_data,
352 bool page_do_bit17_swizzling, bool needs_clflush)
357 if (unlikely(page_do_bit17_swizzling))
360 vaddr = kmap_atomic(page);
362 drm_clflush_virt_range(vaddr + shmem_page_offset,
364 ret = __copy_to_user_inatomic(user_data,
365 vaddr + shmem_page_offset,
367 kunmap_atomic(vaddr);
369 return ret ? -EFAULT : 0;
373 shmem_clflush_swizzled_range(char *addr, unsigned long length,
376 if (unlikely(swizzled)) {
377 unsigned long start = (unsigned long) addr;
378 unsigned long end = (unsigned long) addr + length;
380 /* For swizzling simply ensure that we always flush both
381 * channels. Lame, but simple and it works. Swizzled
382 * pwrite/pread is far from a hotpath - current userspace
383 * doesn't use it at all. */
384 start = round_down(start, 128);
385 end = round_up(end, 128);
387 drm_clflush_virt_range((void *)start, end - start);
389 drm_clflush_virt_range(addr, length);
394 /* Only difference to the fast-path function is that this can handle bit17
395 * and uses non-atomic copy and kmap functions. */
397 shmem_pread_slow(struct vm_page *page, int shmem_page_offset, int page_length,
398 char __user *user_data,
399 bool page_do_bit17_swizzling, bool needs_clflush)
406 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
408 page_do_bit17_swizzling);
410 if (page_do_bit17_swizzling)
411 ret = __copy_to_user_swizzled(user_data,
412 vaddr, shmem_page_offset,
415 ret = __copy_to_user(user_data,
416 vaddr + shmem_page_offset,
420 return ret ? - EFAULT : 0;
423 static inline void vm_page_reference(vm_page_t m)
425 vm_page_flag_set(m, PG_REFERENCED);
429 i915_gem_shmem_pread(struct drm_device *dev,
430 struct drm_i915_gem_object *obj,
431 struct drm_i915_gem_pread *args,
432 struct drm_file *file)
434 char __user *user_data;
437 int shmem_page_offset, page_length, ret = 0;
438 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
439 int needs_clflush = 0;
442 user_data = to_user_ptr(args->data_ptr);
445 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
447 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
448 /* If we're not in the cpu read domain, set ourself into the gtt
449 * read domain and manually flush cachelines (if required). This
450 * optimizes for the case when the gpu will dirty the data
451 * anyway again before the next pread happens. */
452 if (obj->cache_level == I915_CACHE_NONE)
454 if (obj->gtt_space) {
455 ret = i915_gem_object_set_to_gtt_domain(obj, false);
461 ret = i915_gem_object_get_pages(obj);
465 i915_gem_object_pin_pages(obj);
467 offset = args->offset;
469 for (i = 0; i < (obj->base.size >> PAGE_SHIFT); i++) {
470 struct vm_page *page = obj->pages[i];
472 if (i < offset >> PAGE_SHIFT)
478 /* Operation in this page
480 * shmem_page_offset = offset within page in shmem file
481 * page_length = bytes to copy for this page
483 shmem_page_offset = offset_in_page(offset);
484 page_length = remain;
485 if ((shmem_page_offset + page_length) > PAGE_SIZE)
486 page_length = PAGE_SIZE - shmem_page_offset;
488 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
489 (VM_PAGE_TO_PHYS(page) & (1 << 17)) != 0;
491 ret = shmem_pread_fast(page, shmem_page_offset, page_length,
492 user_data, page_do_bit17_swizzling,
497 mutex_unlock(&dev->struct_mutex);
501 ret = fault_in_multipages_writeable(user_data, remain);
502 /* Userspace is tricking us, but we've already clobbered
503 * its pages with the prefault and promised to write the
504 * data up to the first fault. Hence ignore any errors
505 * and just continue. */
511 ret = shmem_pread_slow(page, shmem_page_offset, page_length,
512 user_data, page_do_bit17_swizzling,
515 mutex_lock(&dev->struct_mutex);
518 mark_page_accessed(page);
523 remain -= page_length;
524 user_data += page_length;
525 offset += page_length;
529 i915_gem_object_unpin_pages(obj);
535 * Reads data from the object referenced by handle.
537 * On error, the contents of *data are undefined.
540 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
541 struct drm_file *file)
543 struct drm_i915_gem_pread *args = data;
544 struct drm_i915_gem_object *obj;
550 ret = i915_mutex_lock_interruptible(dev);
554 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
555 if (&obj->base == NULL) {
560 /* Bounds check source. */
561 if (args->offset > obj->base.size ||
562 args->size > obj->base.size - args->offset) {
567 trace_i915_gem_object_pread(obj, args->offset, args->size);
569 ret = i915_gem_shmem_pread(dev, obj, args, file);
572 drm_gem_object_unreference(&obj->base);
574 mutex_unlock(&dev->struct_mutex);
579 /* This is the fast write path which cannot handle
580 * page faults in the source data
584 fast_user_write(struct io_mapping *mapping,
585 loff_t page_base, int page_offset,
586 char __user *user_data,
589 void __iomem *vaddr_atomic;
591 unsigned long unwritten;
593 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
594 /* We can use the cpu mem copy function because this is X86. */
595 vaddr = (void __force*)vaddr_atomic + page_offset;
596 unwritten = __copy_from_user_inatomic_nocache(vaddr,
598 io_mapping_unmap_atomic(vaddr_atomic);
603 * This is the fast pwrite path, where we copy the data directly from the
604 * user into the GTT, uncached.
607 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
608 struct drm_i915_gem_object *obj,
609 struct drm_i915_gem_pwrite *args,
610 struct drm_file *file)
612 drm_i915_private_t *dev_priv = dev->dev_private;
614 loff_t offset, page_base;
615 char __user *user_data;
616 int page_offset, page_length, ret;
618 ret = i915_gem_object_pin(obj, 0, true, true);
622 ret = i915_gem_object_set_to_gtt_domain(obj, true);
626 ret = i915_gem_object_put_fence(obj);
630 user_data = to_user_ptr(args->data_ptr);
633 offset = obj->gtt_offset + args->offset;
636 /* Operation in this page
638 * page_base = page offset within aperture
639 * page_offset = offset within page
640 * page_length = bytes to copy for this page
642 page_base = offset & PAGE_MASK;
643 page_offset = offset_in_page(offset);
644 page_length = remain;
645 if ((page_offset + remain) > PAGE_SIZE)
646 page_length = PAGE_SIZE - page_offset;
648 /* If we get a fault while copying data, then (presumably) our
649 * source page isn't available. Return the error and we'll
650 * retry in the slow path.
652 if (fast_user_write(dev_priv->gtt.mappable, page_base,
653 page_offset, user_data, page_length)) {
658 remain -= page_length;
659 user_data += page_length;
660 offset += page_length;
664 i915_gem_object_unpin(obj);
671 i915_gem_gtt_write(struct drm_device *dev, struct drm_i915_gem_object *obj,
672 uint64_t data_ptr, uint64_t size, uint64_t offset, struct drm_file *file)
678 * Pass the unaligned physical address and size to pmap_mapdev_attr()
679 * so it can properly calculate whether an extra page needs to be
680 * mapped or not to cover the requested range. The function will
681 * add the page offset into the returned mkva for us.
683 mkva = (vm_offset_t)pmap_mapdev_attr(dev->agp->base + obj->gtt_offset +
684 offset, size, PAT_WRITE_COMBINING);
685 ret = -copyin_nofault((void *)(uintptr_t)data_ptr, (char *)mkva, size);
686 pmap_unmapdev(mkva, size);
691 /* Per-page copy function for the shmem pwrite fastpath.
692 * Flushes invalid cachelines before writing to the target if
693 * needs_clflush_before is set and flushes out any written cachelines after
694 * writing if needs_clflush is set. */
696 shmem_pwrite_fast(struct vm_page *page, int shmem_page_offset, int page_length,
697 char __user *user_data,
698 bool page_do_bit17_swizzling,
699 bool needs_clflush_before,
700 bool needs_clflush_after)
705 if (unlikely(page_do_bit17_swizzling))
708 vaddr = kmap_atomic(page);
709 if (needs_clflush_before)
710 drm_clflush_virt_range(vaddr + shmem_page_offset,
712 ret = __copy_from_user_inatomic_nocache(vaddr + shmem_page_offset,
715 if (needs_clflush_after)
716 drm_clflush_virt_range(vaddr + shmem_page_offset,
718 kunmap_atomic(vaddr);
720 return ret ? -EFAULT : 0;
723 /* Only difference to the fast-path function is that this can handle bit17
724 * and uses non-atomic copy and kmap functions. */
726 shmem_pwrite_slow(struct vm_page *page, int shmem_page_offset, int page_length,
727 char __user *user_data,
728 bool page_do_bit17_swizzling,
729 bool needs_clflush_before,
730 bool needs_clflush_after)
736 if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
737 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
739 page_do_bit17_swizzling);
740 if (page_do_bit17_swizzling)
741 ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
745 ret = __copy_from_user(vaddr + shmem_page_offset,
748 if (needs_clflush_after)
749 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
751 page_do_bit17_swizzling);
754 return ret ? -EFAULT : 0;
759 i915_gem_shmem_pwrite(struct drm_device *dev,
760 struct drm_i915_gem_object *obj,
761 struct drm_i915_gem_pwrite *args,
762 struct drm_file *file)
769 int cnt, do_bit17_swizzling, length, obj_po, ret, swizzled_po;
771 do_bit17_swizzling = 0;
774 vm_obj = obj->base.vm_obj;
777 VM_OBJECT_LOCK(vm_obj);
778 vm_object_pip_add(vm_obj, 1);
779 while (args->size > 0) {
780 obj_pi = OFF_TO_IDX(args->offset);
781 obj_po = args->offset & PAGE_MASK;
783 m = shmem_read_mapping_page(vm_obj, obj_pi);
784 VM_OBJECT_UNLOCK(vm_obj);
786 sf = sf_buf_alloc(m);
787 mkva = sf_buf_kva(sf);
788 length = min(args->size, PAGE_SIZE - obj_po);
790 if (do_bit17_swizzling &&
791 (VM_PAGE_TO_PHYS(m) & (1 << 17)) != 0) {
792 cnt = roundup2(obj_po + 1, 64);
793 cnt = min(cnt - obj_po, length);
794 swizzled_po = obj_po ^ 64;
797 swizzled_po = obj_po;
799 ret = -copyin_nofault(
800 (void *)(uintptr_t)args->data_ptr,
801 (char *)mkva + swizzled_po, cnt);
804 args->data_ptr += cnt;
811 VM_OBJECT_LOCK(vm_obj);
813 vm_page_reference(m);
814 vm_page_busy_wait(m, FALSE, "i915gem");
815 vm_page_unwire(m, 1);
821 vm_object_pip_wakeup(vm_obj);
822 VM_OBJECT_UNLOCK(vm_obj);
828 * Writes data to the object referenced by handle.
830 * On error, the contents of the buffer that were to be modified are undefined.
833 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
834 struct drm_file *file)
836 struct drm_i915_gem_pwrite *args = data;
837 struct drm_i915_gem_object *obj;
839 vm_offset_t start, end;
845 start = trunc_page(args->data_ptr);
846 end = round_page(args->data_ptr + args->size);
847 npages = howmany(end - start, PAGE_SIZE);
848 ma = kmalloc(npages * sizeof(vm_page_t), M_DRM, M_WAITOK |
850 npages = vm_fault_quick_hold_pages(&curproc->p_vmspace->vm_map,
851 (vm_offset_t)args->data_ptr, args->size,
852 VM_PROT_READ, ma, npages);
858 ret = i915_mutex_lock_interruptible(dev);
862 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
863 if (&obj->base == NULL) {
868 /* Bounds check destination. */
869 if (args->offset > obj->base.size ||
870 args->size > obj->base.size - args->offset) {
875 trace_i915_gem_object_pwrite(obj, args->offset, args->size);
878 ret = i915_gem_phys_pwrite(dev, obj, args, file);
879 } else if (obj->gtt_space &&
880 obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
881 ret = i915_gem_object_pin(obj, 0, true, false);
884 ret = i915_gem_object_set_to_gtt_domain(obj, true);
887 ret = i915_gem_object_put_fence(obj);
890 ret = i915_gem_gtt_write(dev, obj, args->data_ptr, args->size,
893 i915_gem_object_unpin(obj);
895 ret = i915_gem_object_set_to_cpu_domain(obj, true);
898 ret = i915_gem_shmem_pwrite(dev, obj, args, file);
901 drm_gem_object_unreference(&obj->base);
903 mutex_unlock(&dev->struct_mutex);
905 vm_page_unhold_pages(ma, npages);
912 i915_gem_check_wedge(struct i915_gpu_error *error,
915 if (i915_reset_in_progress(error)) {
916 /* Non-interruptible callers can't handle -EAGAIN, hence return
917 * -EIO unconditionally for these. */
921 /* Recovery complete, but the reset failed ... */
922 if (i915_terminally_wedged(error))
932 * Compare seqno against outstanding lazy request. Emit a request if they are
936 i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno)
940 DRM_LOCK_ASSERT(ring->dev);
943 if (seqno == ring->outstanding_lazy_request)
944 ret = i915_add_request(ring, NULL);
950 * __wait_seqno - wait until execution of seqno has finished
951 * @ring: the ring expected to report seqno
953 * @reset_counter: reset sequence associated with the given seqno
954 * @interruptible: do an interruptible wait (normally yes)
955 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
957 * Note: It is of utmost importance that the passed in seqno and reset_counter
958 * values have been read by the caller in an smp safe manner. Where read-side
959 * locks are involved, it is sufficient to read the reset_counter before
960 * unlocking the lock that protects the seqno. For lockless tricks, the
961 * reset_counter _must_ be read before, and an appropriate smp_rmb must be
964 * Returns 0 if the seqno was found within the alloted time. Else returns the
965 * errno with remaining time filled in timeout argument.
967 static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno,
968 unsigned reset_counter,
969 bool interruptible, struct timespec *timeout)
971 drm_i915_private_t *dev_priv = ring->dev->dev_private;
972 struct timespec before, now, wait_time={1,0};
973 unsigned long timeout_jiffies;
975 bool wait_forever = true;
978 if (i915_seqno_passed(ring->get_seqno(ring, true), seqno))
981 trace_i915_gem_request_wait_begin(ring, seqno);
983 if (timeout != NULL) {
984 wait_time = *timeout;
985 wait_forever = false;
988 timeout_jiffies = timespec_to_jiffies_timeout(&wait_time);
990 if (WARN_ON(!ring->irq_get(ring)))
993 /* Record current time in case interrupted by signal, or wedged * */
994 getrawmonotonic(&before);
997 (i915_seqno_passed(ring->get_seqno(ring, false), seqno) || \
998 i915_reset_in_progress(&dev_priv->gpu_error) || \
999 reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
1002 end = wait_event_interruptible_timeout(ring->irq_queue,
1006 end = wait_event_timeout(ring->irq_queue, EXIT_COND,
1009 /* We need to check whether any gpu reset happened in between
1010 * the caller grabbing the seqno and now ... */
1011 if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
1014 /* ... but upgrade the -EGAIN to an -EIO if the gpu is truely
1016 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1019 } while (end == 0 && wait_forever);
1021 getrawmonotonic(&now);
1023 ring->irq_put(ring);
1024 trace_i915_gem_request_wait_end(ring, seqno);
1028 struct timespec sleep_time = timespec_sub(now, before);
1029 *timeout = timespec_sub(*timeout, sleep_time);
1030 if (!timespec_valid(timeout)) /* i.e. negative time remains */
1031 set_normalized_timespec(timeout, 0, 0);
1036 case -EAGAIN: /* Wedged */
1037 case -ERESTARTSYS: /* Signal */
1039 case 0: /* Timeout */
1040 return -ETIMEDOUT; /* -ETIME on Linux */
1041 default: /* Completed */
1042 WARN_ON(end < 0); /* We're not aware of other errors */
1048 * Waits for a sequence number to be signaled, and cleans up the
1049 * request and object lists appropriately for that event.
1052 i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno)
1054 struct drm_device *dev = ring->dev;
1055 struct drm_i915_private *dev_priv = dev->dev_private;
1056 bool interruptible = dev_priv->mm.interruptible;
1059 DRM_LOCK_ASSERT(dev);
1062 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1066 ret = i915_gem_check_olr(ring, seqno);
1070 return __wait_seqno(ring, seqno,
1071 atomic_read(&dev_priv->gpu_error.reset_counter),
1072 interruptible, NULL);
1076 i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object *obj,
1077 struct intel_ring_buffer *ring)
1079 i915_gem_retire_requests_ring(ring);
1081 /* Manually manage the write flush as we may have not yet
1082 * retired the buffer.
1084 * Note that the last_write_seqno is always the earlier of
1085 * the two (read/write) seqno, so if we haved successfully waited,
1086 * we know we have passed the last write.
1088 obj->last_write_seqno = 0;
1089 obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
1095 * Ensures that all rendering to the object has completed and the object is
1096 * safe to unbind from the GTT or access from the CPU.
1098 static __must_check int
1099 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
1102 struct intel_ring_buffer *ring = obj->ring;
1106 seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1110 ret = i915_wait_seqno(ring, seqno);
1114 return i915_gem_object_wait_rendering__tail(obj, ring);
1117 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1118 * as the object state may change during this call.
1120 static __must_check int
1121 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
1124 struct drm_device *dev = obj->base.dev;
1125 struct drm_i915_private *dev_priv = dev->dev_private;
1126 struct intel_ring_buffer *ring = obj->ring;
1127 unsigned reset_counter;
1131 DRM_LOCK_ASSERT(dev);
1132 BUG_ON(!dev_priv->mm.interruptible);
1134 seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1138 ret = i915_gem_check_wedge(&dev_priv->gpu_error, true);
1142 ret = i915_gem_check_olr(ring, seqno);
1146 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
1147 mutex_unlock(&dev->struct_mutex);
1148 ret = __wait_seqno(ring, seqno, reset_counter, true, NULL);
1149 mutex_lock(&dev->struct_mutex);
1153 return i915_gem_object_wait_rendering__tail(obj, ring);
1157 * Called when user space prepares to use an object with the CPU, either
1158 * through the mmap ioctl's mapping or a GTT mapping.
1161 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1162 struct drm_file *file)
1164 struct drm_i915_gem_set_domain *args = data;
1165 struct drm_i915_gem_object *obj;
1166 uint32_t read_domains = args->read_domains;
1167 uint32_t write_domain = args->write_domain;
1170 /* Only handle setting domains to types used by the CPU. */
1171 if (write_domain & I915_GEM_GPU_DOMAINS)
1174 if (read_domains & I915_GEM_GPU_DOMAINS)
1177 /* Having something in the write domain implies it's in the read
1178 * domain, and only that read domain. Enforce that in the request.
1180 if (write_domain != 0 && read_domains != write_domain)
1183 ret = i915_mutex_lock_interruptible(dev);
1187 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1188 if (&obj->base == NULL) {
1193 /* Try to flush the object off the GPU without holding the lock.
1194 * We will repeat the flush holding the lock in the normal manner
1195 * to catch cases where we are gazumped.
1197 ret = i915_gem_object_wait_rendering__nonblocking(obj, !write_domain);
1201 if (read_domains & I915_GEM_DOMAIN_GTT) {
1202 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1204 /* Silently promote "you're not bound, there was nothing to do"
1205 * to success, since the client was just asking us to
1206 * make sure everything was done.
1211 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1215 drm_gem_object_unreference(&obj->base);
1217 mutex_unlock(&dev->struct_mutex);
1222 * Called when user space has done writes to this buffer
1225 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1226 struct drm_file *file)
1228 struct drm_i915_gem_sw_finish *args = data;
1229 struct drm_i915_gem_object *obj;
1232 ret = i915_mutex_lock_interruptible(dev);
1236 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1237 if (&obj->base == NULL) {
1242 /* Pinned buffers may be scanout, so flush the cache */
1244 i915_gem_object_flush_cpu_write_domain(obj);
1246 drm_gem_object_unreference(&obj->base);
1248 mutex_unlock(&dev->struct_mutex);
1253 * Maps the contents of an object, returning the address it is mapped
1256 * While the mapping holds a reference on the contents of the object, it doesn't
1257 * imply a ref on the object itself.
1260 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1261 struct drm_file *file)
1263 struct drm_i915_gem_mmap *args = data;
1264 struct drm_gem_object *obj;
1265 struct proc *p = curproc;
1266 vm_map_t map = &p->p_vmspace->vm_map;
1271 obj = drm_gem_object_lookup(dev, file, args->handle);
1275 if (args->size == 0)
1278 size = round_page(args->size);
1279 if (map->size + size > p->p_rlimit[RLIMIT_VMEM].rlim_cur) {
1285 vm_object_hold(obj->vm_obj);
1286 vm_object_reference_locked(obj->vm_obj);
1287 vm_object_drop(obj->vm_obj);
1288 rv = vm_map_find(map, obj->vm_obj, NULL,
1289 args->offset, &addr, args->size,
1290 PAGE_SIZE, /* align */
1292 VM_MAPTYPE_NORMAL, /* maptype */
1293 VM_PROT_READ | VM_PROT_WRITE, /* prot */
1294 VM_PROT_READ | VM_PROT_WRITE, /* max */
1295 MAP_SHARED /* cow */);
1296 if (rv != KERN_SUCCESS) {
1297 vm_object_deallocate(obj->vm_obj);
1298 error = -vm_mmap_to_errno(rv);
1300 args->addr_ptr = (uint64_t)addr;
1303 drm_gem_object_unreference(obj);
1310 * i915_gem_fault - fault a page into the GTT
1311 * vma: VMA in question
1314 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1315 * from userspace. The fault handler takes care of binding the object to
1316 * the GTT (if needed), allocating and programming a fence register (again,
1317 * only if needed based on whether the old reg is still valid or the object
1318 * is tiled) and inserting a new PTE into the faulting process.
1320 * Note that the faulting process may involve evicting existing objects
1321 * from the GTT and/or fence registers to make room. So performance may
1322 * suffer if the GTT working set is large or there are few fence registers
1326 i915_gem_fault(vm_object_t vm_obj, vm_ooffset_t offset, int prot,
1329 struct drm_gem_object *gem_obj;
1330 struct drm_i915_gem_object *obj;
1331 struct drm_device *dev;
1332 drm_i915_private_t *dev_priv;
1337 gem_obj = vm_obj->handle;
1338 obj = to_intel_bo(gem_obj);
1339 dev = obj->base.dev;
1340 dev_priv = dev->dev_private;
1342 write = (prot & VM_PROT_WRITE) != 0;
1346 vm_object_pip_add(vm_obj, 1);
1349 * Remove the placeholder page inserted by vm_fault() from the
1350 * object before dropping the object lock. If
1351 * i915_gem_release_mmap() is active in parallel on this gem
1352 * object, then it owns the drm device sx and might find the
1353 * placeholder already. Then, since the page is busy,
1354 * i915_gem_release_mmap() sleeps waiting for the busy state
1355 * of the page cleared. We will be not able to acquire drm
1356 * device lock until i915_gem_release_mmap() is able to make a
1359 if (*mres != NULL) {
1361 vm_page_remove(oldm);
1366 VM_OBJECT_UNLOCK(vm_obj);
1372 ret = i915_mutex_lock_interruptible(dev);
1378 mutex_lock(&dev->struct_mutex);
1381 * Since the object lock was dropped, other thread might have
1382 * faulted on the same GTT address and instantiated the
1383 * mapping for the page. Recheck.
1385 VM_OBJECT_LOCK(vm_obj);
1386 m = vm_page_lookup(vm_obj, OFF_TO_IDX(offset));
1388 if ((m->flags & PG_BUSY) != 0) {
1389 mutex_unlock(&dev->struct_mutex);
1391 vm_page_sleep(m, "915pee");
1397 VM_OBJECT_UNLOCK(vm_obj);
1399 trace_i915_gem_object_fault(obj, page_offset, true, write);
1401 /* Access to snoopable pages through the GTT is incoherent. */
1402 if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) {
1407 /* Now bind it into the GTT if needed */
1408 if (!obj->map_and_fenceable) {
1409 ret = i915_gem_object_unbind(obj);
1415 if (!obj->gtt_space) {
1416 ret = i915_gem_object_bind_to_gtt(obj, 0, true, false);
1422 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1429 if (obj->tiling_mode == I915_TILING_NONE)
1430 ret = i915_gem_object_put_fence(obj);
1432 ret = i915_gem_object_get_fence(obj);
1438 if (i915_gem_object_is_inactive(obj))
1439 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
1441 obj->fault_mappable = true;
1442 VM_OBJECT_LOCK(vm_obj);
1443 m = vm_phys_fictitious_to_vm_page(dev->agp->base + obj->gtt_offset +
1450 KASSERT((m->flags & PG_FICTITIOUS) != 0,
1451 ("not fictitious %p", m));
1452 KASSERT(m->wire_count == 1, ("wire_count not 1 %p", m));
1454 if ((m->flags & PG_BUSY) != 0) {
1455 mutex_unlock(&dev->struct_mutex);
1457 vm_page_sleep(m, "915pbs");
1461 m->valid = VM_PAGE_BITS_ALL;
1462 vm_page_insert(m, vm_obj, OFF_TO_IDX(offset));
1465 vm_page_busy_try(m, false);
1467 mutex_unlock(&dev->struct_mutex);
1471 vm_object_pip_wakeup(vm_obj);
1472 return (VM_PAGER_OK);
1475 mutex_unlock(&dev->struct_mutex);
1477 KASSERT(ret != 0, ("i915_gem_pager_fault: wrong return"));
1478 if (ret == -EAGAIN || ret == -EIO || ret == -EINTR) {
1479 goto unlocked_vmobj;
1481 VM_OBJECT_LOCK(vm_obj);
1482 vm_object_pip_wakeup(vm_obj);
1483 return (VM_PAGER_ERROR);
1487 * i915_gem_release_mmap - remove physical page mappings
1488 * @obj: obj in question
1490 * Preserve the reservation of the mmapping with the DRM core code, but
1491 * relinquish ownership of the pages back to the system.
1493 * It is vital that we remove the page mapping if we have mapped a tiled
1494 * object through the GTT and then lose the fence register due to
1495 * resource pressure. Similarly if the object has been moved out of the
1496 * aperture, than pages mapped into userspace must be revoked. Removing the
1497 * mapping will then trigger a page fault on the next user access, allowing
1498 * fixup by i915_gem_fault().
1501 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1507 if (!obj->fault_mappable)
1510 devobj = cdev_pager_lookup(obj);
1511 if (devobj != NULL) {
1512 page_count = OFF_TO_IDX(obj->base.size);
1514 VM_OBJECT_LOCK(devobj);
1515 for (i = 0; i < page_count; i++) {
1516 m = vm_page_lookup_busy_wait(devobj, i, TRUE, "915unm");
1519 cdev_pager_free_page(devobj, m);
1521 VM_OBJECT_UNLOCK(devobj);
1522 vm_object_deallocate(devobj);
1525 obj->fault_mappable = false;
1529 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1533 if (INTEL_INFO(dev)->gen >= 4 ||
1534 tiling_mode == I915_TILING_NONE)
1537 /* Previous chips need a power-of-two fence region when tiling */
1538 if (INTEL_INFO(dev)->gen == 3)
1539 gtt_size = 1024*1024;
1541 gtt_size = 512*1024;
1543 while (gtt_size < size)
1550 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1551 * @obj: object to check
1553 * Return the required GTT alignment for an object, taking into account
1554 * potential fence register mapping.
1557 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
1558 int tiling_mode, bool fenced)
1561 * Minimum alignment is 4k (GTT page size), but might be greater
1562 * if a fence register is needed for the object.
1564 if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) ||
1565 tiling_mode == I915_TILING_NONE)
1569 * Previous chips need to be aligned to the size of the smallest
1570 * fence register that can contain the object.
1572 return i915_gem_get_gtt_size(dev, size, tiling_mode);
1576 i915_gem_mmap_gtt(struct drm_file *file,
1577 struct drm_device *dev,
1581 struct drm_i915_private *dev_priv = dev->dev_private;
1582 struct drm_i915_gem_object *obj;
1585 ret = i915_mutex_lock_interruptible(dev);
1589 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1590 if (&obj->base == NULL) {
1595 if (obj->base.size > dev_priv->gtt.mappable_end) {
1600 if (obj->madv != I915_MADV_WILLNEED) {
1601 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1606 ret = drm_gem_create_mmap_offset(&obj->base);
1610 *offset = DRM_GEM_MAPPING_OFF(obj->base.map_list.key) |
1611 DRM_GEM_MAPPING_KEY;
1613 drm_gem_object_unreference(&obj->base);
1615 mutex_unlock(&dev->struct_mutex);
1620 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1622 * @data: GTT mapping ioctl data
1623 * @file: GEM object info
1625 * Simply returns the fake offset to userspace so it can mmap it.
1626 * The mmap call will end up in drm_gem_mmap(), which will set things
1627 * up so we can get faults in the handler above.
1629 * The fault handler will take care of binding the object into the GTT
1630 * (since it may have been evicted to make room for something), allocating
1631 * a fence register, and mapping the appropriate aperture address into
1635 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1636 struct drm_file *file)
1638 struct drm_i915_gem_mmap_gtt *args = data;
1640 return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
1643 /* Immediately discard the backing storage */
1645 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
1649 vm_obj = obj->base.vm_obj;
1650 VM_OBJECT_LOCK(vm_obj);
1651 vm_object_page_remove(vm_obj, 0, 0, false);
1652 VM_OBJECT_UNLOCK(vm_obj);
1654 obj->madv = __I915_MADV_PURGED;
1658 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
1660 return obj->madv == I915_MADV_DONTNEED;
1664 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
1666 int page_count = obj->base.size / PAGE_SIZE;
1672 BUG_ON(obj->madv == __I915_MADV_PURGED);
1674 ret = i915_gem_object_set_to_cpu_domain(obj, true);
1676 /* In the event of a disaster, abandon all caches and
1677 * hope for the best.
1679 WARN_ON(ret != -EIO);
1680 i915_gem_clflush_object(obj);
1681 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
1684 if (i915_gem_object_needs_bit17_swizzle(obj))
1685 i915_gem_object_save_bit_17_swizzle(obj);
1687 if (obj->madv == I915_MADV_DONTNEED)
1690 for (i = 0; i < page_count; i++) {
1692 set_page_dirty(obj->pages[i]);
1694 if (obj->madv == I915_MADV_WILLNEED)
1695 mark_page_accessed(obj->pages[i]);
1697 vm_page_busy_wait(obj->pages[i], FALSE, "i915gem");
1698 vm_page_unwire(obj->pages[i], 1);
1699 vm_page_wakeup(obj->pages[i]);
1708 i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
1710 const struct drm_i915_gem_object_ops *ops = obj->ops;
1712 if (obj->pages == NULL)
1715 BUG_ON(obj->gtt_space);
1717 if (obj->pages_pin_count)
1720 /* ->put_pages might need to allocate memory for the bit17 swizzle
1721 * array, hence protect them from being reaped by removing them from gtt
1723 list_del(&obj->global_list);
1725 ops->put_pages(obj);
1728 if (i915_gem_object_is_purgeable(obj))
1729 i915_gem_object_truncate(obj);
1735 __i915_gem_shrink(struct drm_i915_private *dev_priv, long target,
1736 bool purgeable_only)
1738 struct drm_i915_gem_object *obj, *next;
1741 list_for_each_entry_safe(obj, next,
1742 &dev_priv->mm.unbound_list,
1745 if ((i915_gem_object_is_purgeable(obj) || !purgeable_only) &&
1746 i915_gem_object_put_pages(obj) == 0) {
1747 count += obj->base.size >> PAGE_SHIFT;
1748 if (count >= target)
1754 list_for_each_entry_safe(obj, next,
1755 &dev_priv->mm.inactive_list,
1758 if ((i915_gem_object_is_purgeable(obj) || !purgeable_only) &&
1759 i915_gem_object_unbind(obj) == 0 &&
1760 i915_gem_object_put_pages(obj) == 0) {
1761 count += obj->base.size >> PAGE_SHIFT;
1762 if (count >= target)
1772 i915_gem_purge(struct drm_i915_private *dev_priv, long target)
1774 return __i915_gem_shrink(dev_priv, target, true);
1778 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
1780 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1781 struct drm_device *dev;
1783 int page_count, i, j;
1784 struct vm_page *page;
1786 dev = obj->base.dev;
1787 KASSERT(obj->pages == NULL, ("Obj already has pages"));
1788 page_count = obj->base.size / PAGE_SIZE;
1789 obj->pages = kmalloc(page_count * sizeof(vm_page_t), M_DRM,
1792 vm_obj = obj->base.vm_obj;
1793 VM_OBJECT_LOCK(vm_obj);
1795 for (i = 0; i < page_count; i++) {
1796 page = shmem_read_mapping_page(vm_obj, i);
1798 i915_gem_purge(dev_priv, page_count);
1802 obj->pages[i] = page;
1805 VM_OBJECT_UNLOCK(vm_obj);
1806 if (i915_gem_object_needs_bit17_swizzle(obj))
1807 i915_gem_object_do_bit_17_swizzle(obj);
1812 for (j = 0; j < i; j++) {
1813 page = obj->pages[j];
1814 vm_page_busy_wait(page, FALSE, "i915gem");
1815 vm_page_unwire(page, 0);
1816 vm_page_wakeup(page);
1818 VM_OBJECT_UNLOCK(vm_obj);
1819 drm_free(obj->pages, M_DRM);
1824 /* Ensure that the associated pages are gathered from the backing storage
1825 * and pinned into our object. i915_gem_object_get_pages() may be called
1826 * multiple times before they are released by a single call to
1827 * i915_gem_object_put_pages() - once the pages are no longer referenced
1828 * either as a result of memory pressure (reaping pages under the shrinker)
1829 * or as the object is itself released.
1832 i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
1834 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1835 const struct drm_i915_gem_object_ops *ops = obj->ops;
1841 if (obj->madv != I915_MADV_WILLNEED) {
1842 DRM_ERROR("Attempting to obtain a purgeable object\n");
1846 BUG_ON(obj->pages_pin_count);
1848 ret = ops->get_pages(obj);
1852 list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list);
1857 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1858 struct intel_ring_buffer *ring)
1860 struct drm_device *dev = obj->base.dev;
1861 struct drm_i915_private *dev_priv = dev->dev_private;
1862 u32 seqno = intel_ring_get_seqno(ring);
1864 BUG_ON(ring == NULL);
1865 if (obj->ring != ring && obj->last_write_seqno) {
1866 /* Keep the seqno relative to the current ring */
1867 obj->last_write_seqno = seqno;
1871 /* Add a reference if we're newly entering the active list. */
1873 drm_gem_object_reference(&obj->base);
1877 /* Move from whatever list we were on to the tail of execution. */
1878 list_move_tail(&obj->mm_list, &dev_priv->mm.active_list);
1879 list_move_tail(&obj->ring_list, &ring->active_list);
1881 obj->last_read_seqno = seqno;
1883 if (obj->fenced_gpu_access) {
1884 obj->last_fenced_seqno = seqno;
1886 /* Bump MRU to take account of the delayed flush */
1887 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1888 struct drm_i915_fence_reg *reg;
1890 reg = &dev_priv->fence_regs[obj->fence_reg];
1891 list_move_tail(®->lru_list,
1892 &dev_priv->mm.fence_list);
1898 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
1900 struct drm_device *dev = obj->base.dev;
1901 struct drm_i915_private *dev_priv = dev->dev_private;
1903 BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS);
1904 BUG_ON(!obj->active);
1906 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
1908 list_del_init(&obj->ring_list);
1911 obj->last_read_seqno = 0;
1912 obj->last_write_seqno = 0;
1913 obj->base.write_domain = 0;
1915 obj->last_fenced_seqno = 0;
1916 obj->fenced_gpu_access = false;
1919 drm_gem_object_unreference(&obj->base);
1921 WARN_ON(i915_verify_lists(dev));
1925 i915_gem_init_seqno(struct drm_device *dev, u32 seqno)
1927 struct drm_i915_private *dev_priv = dev->dev_private;
1928 struct intel_ring_buffer *ring;
1931 /* Carefully retire all requests without writing to the rings */
1932 for_each_ring(ring, dev_priv, i) {
1933 ret = intel_ring_idle(ring);
1937 i915_gem_retire_requests(dev);
1939 /* Finally reset hw state */
1940 for_each_ring(ring, dev_priv, i) {
1941 intel_ring_init_seqno(ring, seqno);
1943 for (j = 0; j < ARRAY_SIZE(ring->sync_seqno); j++)
1944 ring->sync_seqno[j] = 0;
1950 int i915_gem_set_seqno(struct drm_device *dev, u32 seqno)
1952 struct drm_i915_private *dev_priv = dev->dev_private;
1958 /* HWS page needs to be set less than what we
1959 * will inject to ring
1961 ret = i915_gem_init_seqno(dev, seqno - 1);
1965 /* Carefully set the last_seqno value so that wrap
1966 * detection still works
1968 dev_priv->next_seqno = seqno;
1969 dev_priv->last_seqno = seqno - 1;
1970 if (dev_priv->last_seqno == 0)
1971 dev_priv->last_seqno--;
1977 i915_gem_get_seqno(struct drm_device *dev, u32 *seqno)
1979 struct drm_i915_private *dev_priv = dev->dev_private;
1981 /* reserve 0 for non-seqno */
1982 if (dev_priv->next_seqno == 0) {
1983 int ret = i915_gem_init_seqno(dev, 0);
1987 dev_priv->next_seqno = 1;
1990 *seqno = dev_priv->last_seqno = dev_priv->next_seqno++;
1994 int __i915_add_request(struct intel_ring_buffer *ring,
1995 struct drm_file *file,
1996 struct drm_i915_gem_object *obj,
1999 drm_i915_private_t *dev_priv = ring->dev->dev_private;
2000 struct drm_i915_gem_request *request;
2001 u32 request_ring_position, request_start;
2005 request_start = intel_ring_get_tail(ring);
2007 * Emit any outstanding flushes - execbuf can fail to emit the flush
2008 * after having emitted the batchbuffer command. Hence we need to fix
2009 * things up similar to emitting the lazy request. The difference here
2010 * is that the flush _must_ happen before the next request, no matter
2013 ret = intel_ring_flush_all_caches(ring);
2017 request = kmalloc(sizeof(*request), M_DRM, M_WAITOK);
2018 if (request == NULL)
2022 /* Record the position of the start of the request so that
2023 * should we detect the updated seqno part-way through the
2024 * GPU processing the request, we never over-estimate the
2025 * position of the head.
2027 request_ring_position = intel_ring_get_tail(ring);
2029 ret = ring->add_request(ring);
2035 request->seqno = intel_ring_get_seqno(ring);
2036 request->ring = ring;
2037 request->head = request_start;
2038 request->tail = request_ring_position;
2039 request->ctx = ring->last_context;
2040 request->batch_obj = obj;
2042 /* Whilst this request exists, batch_obj will be on the
2043 * active_list, and so will hold the active reference. Only when this
2044 * request is retired will the the batch_obj be moved onto the
2045 * inactive_list and lose its active reference. Hence we do not need
2046 * to explicitly hold another reference here.
2050 i915_gem_context_reference(request->ctx);
2052 request->emitted_jiffies = jiffies;
2053 was_empty = list_empty(&ring->request_list);
2054 list_add_tail(&request->list, &ring->request_list);
2055 request->file_priv = NULL;
2058 struct drm_i915_file_private *file_priv = file->driver_priv;
2060 spin_lock(&file_priv->mm.lock);
2061 request->file_priv = file_priv;
2062 list_add_tail(&request->client_list,
2063 &file_priv->mm.request_list);
2064 spin_unlock(&file_priv->mm.lock);
2067 trace_i915_gem_request_add(ring, request->seqno);
2068 ring->outstanding_lazy_request = 0;
2070 if (!dev_priv->mm.suspended) {
2071 if (i915_enable_hangcheck) {
2072 mod_timer(&dev_priv->gpu_error.hangcheck_timer,
2073 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
2076 queue_delayed_work(dev_priv->wq,
2077 &dev_priv->mm.retire_work,
2078 round_jiffies_up_relative(hz));
2079 intel_mark_busy(dev_priv->dev);
2084 *out_seqno = request->seqno;
2089 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
2091 struct drm_i915_file_private *file_priv = request->file_priv;
2096 spin_lock(&file_priv->mm.lock);
2097 if (request->file_priv) {
2098 list_del(&request->client_list);
2099 request->file_priv = NULL;
2101 spin_unlock(&file_priv->mm.lock);
2104 static bool i915_head_inside_object(u32 acthd, struct drm_i915_gem_object *obj)
2106 if (acthd >= obj->gtt_offset &&
2107 acthd < obj->gtt_offset + obj->base.size)
2113 static bool i915_head_inside_request(const u32 acthd_unmasked,
2114 const u32 request_start,
2115 const u32 request_end)
2117 const u32 acthd = acthd_unmasked & HEAD_ADDR;
2119 if (request_start < request_end) {
2120 if (acthd >= request_start && acthd < request_end)
2122 } else if (request_start > request_end) {
2123 if (acthd >= request_start || acthd < request_end)
2130 static bool i915_request_guilty(struct drm_i915_gem_request *request,
2131 const u32 acthd, bool *inside)
2133 /* There is a possibility that unmasked head address
2134 * pointing inside the ring, matches the batch_obj address range.
2135 * However this is extremely unlikely.
2138 if (request->batch_obj) {
2139 if (i915_head_inside_object(acthd, request->batch_obj)) {
2145 if (i915_head_inside_request(acthd, request->head, request->tail)) {
2153 static void i915_set_reset_status(struct intel_ring_buffer *ring,
2154 struct drm_i915_gem_request *request,
2157 struct i915_ctx_hang_stats *hs = NULL;
2158 bool inside, guilty;
2160 /* Innocent until proven guilty */
2163 if (ring->hangcheck.action != wait &&
2164 i915_request_guilty(request, acthd, &inside)) {
2165 DRM_ERROR("%s hung %s bo (0x%x ctx %d) at 0x%x\n",
2167 inside ? "inside" : "flushing",
2168 request->batch_obj ?
2169 request->batch_obj->gtt_offset : 0,
2170 request->ctx ? request->ctx->id : 0,
2176 /* If contexts are disabled or this is the default context, use
2177 * file_priv->reset_state
2179 if (request->ctx && request->ctx->id != DEFAULT_CONTEXT_ID)
2180 hs = &request->ctx->hang_stats;
2181 else if (request->file_priv)
2182 hs = &request->file_priv->hang_stats;
2188 hs->batch_pending++;
2192 static void i915_gem_free_request(struct drm_i915_gem_request *request)
2194 list_del(&request->list);
2195 i915_gem_request_remove_from_client(request);
2198 i915_gem_context_unreference(request->ctx);
2203 static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv,
2204 struct intel_ring_buffer *ring)
2206 u32 completed_seqno;
2209 acthd = intel_ring_get_active_head(ring);
2210 completed_seqno = ring->get_seqno(ring, false);
2212 while (!list_empty(&ring->request_list)) {
2213 struct drm_i915_gem_request *request;
2215 request = list_first_entry(&ring->request_list,
2216 struct drm_i915_gem_request,
2219 if (request->seqno > completed_seqno)
2220 i915_set_reset_status(ring, request, acthd);
2222 i915_gem_free_request(request);
2225 while (!list_empty(&ring->active_list)) {
2226 struct drm_i915_gem_object *obj;
2228 obj = list_first_entry(&ring->active_list,
2229 struct drm_i915_gem_object,
2232 i915_gem_object_move_to_inactive(obj);
2236 void i915_gem_restore_fences(struct drm_device *dev)
2238 struct drm_i915_private *dev_priv = dev->dev_private;
2241 for (i = 0; i < dev_priv->num_fence_regs; i++) {
2242 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
2245 * Commit delayed tiling changes if we have an object still
2246 * attached to the fence, otherwise just clear the fence.
2249 i915_gem_object_update_fence(reg->obj, reg,
2250 reg->obj->tiling_mode);
2252 i915_gem_write_fence(dev, i, NULL);
2257 void i915_gem_reset(struct drm_device *dev)
2259 struct drm_i915_private *dev_priv = dev->dev_private;
2260 struct drm_i915_gem_object *obj;
2261 struct intel_ring_buffer *ring;
2264 for_each_ring(ring, dev_priv, i)
2265 i915_gem_reset_ring_lists(dev_priv, ring);
2267 /* Move everything out of the GPU domains to ensure we do any
2268 * necessary invalidation upon reuse.
2270 list_for_each_entry(obj,
2271 &dev_priv->mm.inactive_list,
2274 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
2277 i915_gem_restore_fences(dev);
2281 * This function clears the request list as sequence numbers are passed.
2284 i915_gem_retire_requests_ring(struct intel_ring_buffer *ring)
2288 if (list_empty(&ring->request_list))
2291 WARN_ON(i915_verify_lists(ring->dev));
2293 seqno = ring->get_seqno(ring, true);
2295 while (!list_empty(&ring->request_list)) {
2296 struct drm_i915_gem_request *request;
2298 request = list_first_entry(&ring->request_list,
2299 struct drm_i915_gem_request,
2302 if (!i915_seqno_passed(seqno, request->seqno))
2305 trace_i915_gem_request_retire(ring, request->seqno);
2306 /* We know the GPU must have read the request to have
2307 * sent us the seqno + interrupt, so use the position
2308 * of tail of the request to update the last known position
2311 ring->last_retired_head = request->tail;
2313 i915_gem_free_request(request);
2316 /* Move any buffers on the active list that are no longer referenced
2317 * by the ringbuffer to the flushing/inactive lists as appropriate.
2319 while (!list_empty(&ring->active_list)) {
2320 struct drm_i915_gem_object *obj;
2322 obj = list_first_entry(&ring->active_list,
2323 struct drm_i915_gem_object,
2326 if (!i915_seqno_passed(seqno, obj->last_read_seqno))
2329 i915_gem_object_move_to_inactive(obj);
2332 if (unlikely(ring->trace_irq_seqno &&
2333 i915_seqno_passed(seqno, ring->trace_irq_seqno))) {
2334 ring->irq_put(ring);
2335 ring->trace_irq_seqno = 0;
2341 i915_gem_retire_requests(struct drm_device *dev)
2343 drm_i915_private_t *dev_priv = dev->dev_private;
2344 struct intel_ring_buffer *ring;
2347 for_each_ring(ring, dev_priv, i)
2348 i915_gem_retire_requests_ring(ring);
2352 i915_gem_retire_work_handler(struct work_struct *work)
2354 drm_i915_private_t *dev_priv;
2355 struct drm_device *dev;
2356 struct intel_ring_buffer *ring;
2360 dev_priv = container_of(work, drm_i915_private_t,
2361 mm.retire_work.work);
2362 dev = dev_priv->dev;
2364 /* Come back later if the device is busy... */
2365 if (lockmgr(&dev->struct_mutex, LK_EXCLUSIVE|LK_NOWAIT)) {
2366 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2367 round_jiffies_up_relative(hz));
2371 i915_gem_retire_requests(dev);
2373 /* Send a periodic flush down the ring so we don't hold onto GEM
2374 * objects indefinitely.
2377 for_each_ring(ring, dev_priv, i) {
2378 if (ring->gpu_caches_dirty)
2379 i915_add_request(ring, NULL);
2381 idle &= list_empty(&ring->request_list);
2384 if (!dev_priv->mm.suspended && !idle)
2385 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2386 round_jiffies_up_relative(hz));
2388 intel_mark_idle(dev);
2390 mutex_unlock(&dev->struct_mutex);
2393 * Ensures that an object will eventually get non-busy by flushing any required
2394 * write domains, emitting any outstanding lazy request and retiring and
2395 * completed requests.
2398 i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
2403 ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno);
2407 i915_gem_retire_requests_ring(obj->ring);
2414 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2415 * @DRM_IOCTL_ARGS: standard ioctl arguments
2417 * Returns 0 if successful, else an error is returned with the remaining time in
2418 * the timeout parameter.
2419 * -ETIME: object is still busy after timeout
2420 * -ERESTARTSYS: signal interrupted the wait
2421 * -ENONENT: object doesn't exist
2422 * Also possible, but rare:
2423 * -EAGAIN: GPU wedged
2425 * -ENODEV: Internal IRQ fail
2426 * -E?: The add request failed
2428 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2429 * non-zero timeout parameter the wait ioctl will wait for the given number of
2430 * nanoseconds on an object becoming unbusy. Since the wait itself does so
2431 * without holding struct_mutex the object may become re-busied before this
2432 * function completes. A similar but shorter * race condition exists in the busy
2436 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
2438 drm_i915_private_t *dev_priv = dev->dev_private;
2439 struct drm_i915_gem_wait *args = data;
2440 struct drm_i915_gem_object *obj;
2441 struct intel_ring_buffer *ring = NULL;
2442 struct timespec timeout_stack, *timeout = NULL;
2443 unsigned reset_counter;
2447 if (args->timeout_ns >= 0) {
2448 timeout_stack = ns_to_timespec(args->timeout_ns);
2449 timeout = &timeout_stack;
2452 ret = i915_mutex_lock_interruptible(dev);
2456 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle));
2457 if (&obj->base == NULL) {
2458 mutex_unlock(&dev->struct_mutex);
2462 /* Need to make sure the object gets inactive eventually. */
2463 ret = i915_gem_object_flush_active(obj);
2468 seqno = obj->last_read_seqno;
2475 /* Do this after OLR check to make sure we make forward progress polling
2476 * on this IOCTL with a 0 timeout (like busy ioctl)
2478 if (!args->timeout_ns) {
2483 drm_gem_object_unreference(&obj->base);
2484 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
2485 mutex_unlock(&dev->struct_mutex);
2487 ret = __wait_seqno(ring, seqno, reset_counter, true, timeout);
2489 args->timeout_ns = timespec_to_ns(timeout);
2493 drm_gem_object_unreference(&obj->base);
2494 mutex_unlock(&dev->struct_mutex);
2499 * i915_gem_object_sync - sync an object to a ring.
2501 * @obj: object which may be in use on another ring.
2502 * @to: ring we wish to use the object on. May be NULL.
2504 * This code is meant to abstract object synchronization with the GPU.
2505 * Calling with NULL implies synchronizing the object with the CPU
2506 * rather than a particular GPU ring.
2508 * Returns 0 if successful, else propagates up the lower layer error.
2511 i915_gem_object_sync(struct drm_i915_gem_object *obj,
2512 struct intel_ring_buffer *to)
2514 struct intel_ring_buffer *from = obj->ring;
2518 if (from == NULL || to == from)
2521 if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev))
2522 return i915_gem_object_wait_rendering(obj, false);
2524 idx = intel_ring_sync_index(from, to);
2526 seqno = obj->last_read_seqno;
2527 if (seqno <= from->sync_seqno[idx])
2530 ret = i915_gem_check_olr(obj->ring, seqno);
2534 ret = to->sync_to(to, from, seqno);
2536 /* We use last_read_seqno because sync_to()
2537 * might have just caused seqno wrap under
2540 from->sync_seqno[idx] = obj->last_read_seqno;
2545 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
2547 u32 old_write_domain, old_read_domains;
2549 /* Force a pagefault for domain tracking on next user access */
2550 i915_gem_release_mmap(obj);
2552 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
2555 /* Wait for any direct GTT access to complete */
2558 old_read_domains = obj->base.read_domains;
2559 old_write_domain = obj->base.write_domain;
2561 obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
2562 obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
2564 trace_i915_gem_object_change_domain(obj,
2570 * Unbinds an object from the GTT aperture.
2573 i915_gem_object_unbind(struct drm_i915_gem_object *obj)
2575 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
2578 if (obj->gtt_space == NULL)
2584 BUG_ON(obj->pages == NULL);
2586 ret = i915_gem_object_finish_gpu(obj);
2589 /* Continue on if we fail due to EIO, the GPU is hung so we
2590 * should be safe and we need to cleanup or else we might
2591 * cause memory corruption through use-after-free.
2594 i915_gem_object_finish_gtt(obj);
2596 /* Move the object to the CPU domain to ensure that
2597 * any possible CPU writes while it's not in the GTT
2598 * are flushed when we go to remap it.
2601 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
2602 if (ret == -ERESTARTSYS)
2605 /* In the event of a disaster, abandon all caches and
2606 * hope for the best.
2608 i915_gem_clflush_object(obj);
2609 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
2612 /* release the fence reg _after_ flushing */
2613 ret = i915_gem_object_put_fence(obj);
2617 trace_i915_gem_object_unbind(obj);
2619 if (obj->has_global_gtt_mapping)
2620 i915_gem_gtt_unbind_object(obj);
2621 if (obj->has_aliasing_ppgtt_mapping) {
2622 i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj);
2623 obj->has_aliasing_ppgtt_mapping = 0;
2625 i915_gem_gtt_finish_object(obj);
2627 i915_gem_object_put_pages_gtt(obj);
2629 list_del_init(&obj->global_list);
2630 list_del_init(&obj->mm_list);
2631 /* Avoid an unnecessary call to unbind on rebind. */
2632 obj->map_and_fenceable = true;
2634 drm_mm_put_block(obj->gtt_space);
2635 obj->gtt_space = NULL;
2636 obj->gtt_offset = 0;
2638 if (i915_gem_object_is_purgeable(obj))
2639 i915_gem_object_truncate(obj);
2644 int i915_gpu_idle(struct drm_device *dev)
2646 drm_i915_private_t *dev_priv = dev->dev_private;
2647 struct intel_ring_buffer *ring;
2650 /* Flush everything onto the inactive list. */
2651 for_each_ring(ring, dev_priv, i) {
2652 ret = i915_switch_context(ring, NULL, DEFAULT_CONTEXT_ID);
2656 ret = intel_ring_idle(ring);
2664 static void i965_write_fence_reg(struct drm_device *dev, int reg,
2665 struct drm_i915_gem_object *obj)
2667 drm_i915_private_t *dev_priv = dev->dev_private;
2669 int fence_pitch_shift;
2671 if (INTEL_INFO(dev)->gen >= 6) {
2672 fence_reg = FENCE_REG_SANDYBRIDGE_0;
2673 fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT;
2675 fence_reg = FENCE_REG_965_0;
2676 fence_pitch_shift = I965_FENCE_PITCH_SHIFT;
2679 fence_reg += reg * 8;
2681 /* To w/a incoherency with non-atomic 64-bit register updates,
2682 * we split the 64-bit update into two 32-bit writes. In order
2683 * for a partial fence not to be evaluated between writes, we
2684 * precede the update with write to turn off the fence register,
2685 * and only enable the fence as the last step.
2687 * For extra levels of paranoia, we make sure each step lands
2688 * before applying the next step.
2690 I915_WRITE(fence_reg, 0);
2691 POSTING_READ(fence_reg);
2694 u32 size = obj->gtt_space->size;
2697 val = (uint64_t)((obj->gtt_offset + size - 4096) &
2699 val |= obj->gtt_offset & 0xfffff000;
2700 val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift;
2701 if (obj->tiling_mode == I915_TILING_Y)
2702 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2703 val |= I965_FENCE_REG_VALID;
2705 I915_WRITE(fence_reg + 4, val >> 32);
2706 POSTING_READ(fence_reg + 4);
2708 I915_WRITE(fence_reg + 0, val);
2709 POSTING_READ(fence_reg);
2711 I915_WRITE(fence_reg + 4, 0);
2712 POSTING_READ(fence_reg + 4);
2716 static void i915_write_fence_reg(struct drm_device *dev, int reg,
2717 struct drm_i915_gem_object *obj)
2719 drm_i915_private_t *dev_priv = dev->dev_private;
2723 u32 size = obj->gtt_space->size;
2727 WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) ||
2728 (size & -size) != size ||
2729 (obj->gtt_offset & (size - 1)),
2730 "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2731 obj->gtt_offset, obj->map_and_fenceable, size);
2733 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
2738 /* Note: pitch better be a power of two tile widths */
2739 pitch_val = obj->stride / tile_width;
2740 pitch_val = ffs(pitch_val) - 1;
2742 val = obj->gtt_offset;
2743 if (obj->tiling_mode == I915_TILING_Y)
2744 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2745 val |= I915_FENCE_SIZE_BITS(size);
2746 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2747 val |= I830_FENCE_REG_VALID;
2752 reg = FENCE_REG_830_0 + reg * 4;
2754 reg = FENCE_REG_945_8 + (reg - 8) * 4;
2756 I915_WRITE(reg, val);
2760 static void i830_write_fence_reg(struct drm_device *dev, int reg,
2761 struct drm_i915_gem_object *obj)
2763 drm_i915_private_t *dev_priv = dev->dev_private;
2767 u32 size = obj->gtt_space->size;
2770 WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) ||
2771 (size & -size) != size ||
2772 (obj->gtt_offset & (size - 1)),
2773 "object 0x%08x not 512K or pot-size 0x%08x aligned\n",
2774 obj->gtt_offset, size);
2776 pitch_val = obj->stride / 128;
2777 pitch_val = ffs(pitch_val) - 1;
2779 val = obj->gtt_offset;
2780 if (obj->tiling_mode == I915_TILING_Y)
2781 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2782 val |= I830_FENCE_SIZE_BITS(size);
2783 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2784 val |= I830_FENCE_REG_VALID;
2788 I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
2789 POSTING_READ(FENCE_REG_830_0 + reg * 4);
2792 inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj)
2794 return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT;
2797 static void i915_gem_write_fence(struct drm_device *dev, int reg,
2798 struct drm_i915_gem_object *obj)
2800 struct drm_i915_private *dev_priv = dev->dev_private;
2802 /* Ensure that all CPU reads are completed before installing a fence
2803 * and all writes before removing the fence.
2805 if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj))
2808 WARN(obj && (!obj->stride || !obj->tiling_mode),
2809 "bogus fence setup with stride: 0x%x, tiling mode: %i\n",
2810 obj->stride, obj->tiling_mode);
2812 switch (INTEL_INFO(dev)->gen) {
2816 case 4: i965_write_fence_reg(dev, reg, obj); break;
2817 case 3: i915_write_fence_reg(dev, reg, obj); break;
2818 case 2: i830_write_fence_reg(dev, reg, obj); break;
2822 /* And similarly be paranoid that no direct access to this region
2823 * is reordered to before the fence is installed.
2825 if (i915_gem_object_needs_mb(obj))
2829 static inline int fence_number(struct drm_i915_private *dev_priv,
2830 struct drm_i915_fence_reg *fence)
2832 return fence - dev_priv->fence_regs;
2835 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
2836 struct drm_i915_fence_reg *fence,
2839 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2840 int reg = fence_number(dev_priv, fence);
2842 i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL);
2845 obj->fence_reg = reg;
2847 list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
2849 obj->fence_reg = I915_FENCE_REG_NONE;
2851 list_del_init(&fence->lru_list);
2853 obj->fence_dirty = false;
2857 i915_gem_object_wait_fence(struct drm_i915_gem_object *obj)
2859 if (obj->last_fenced_seqno) {
2860 int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno);
2864 obj->last_fenced_seqno = 0;
2867 obj->fenced_gpu_access = false;
2872 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
2874 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2875 struct drm_i915_fence_reg *fence;
2878 ret = i915_gem_object_wait_fence(obj);
2882 if (obj->fence_reg == I915_FENCE_REG_NONE)
2885 fence = &dev_priv->fence_regs[obj->fence_reg];
2887 i915_gem_object_fence_lost(obj);
2888 i915_gem_object_update_fence(obj, fence, false);
2893 static struct drm_i915_fence_reg *
2894 i915_find_fence_reg(struct drm_device *dev)
2896 struct drm_i915_private *dev_priv = dev->dev_private;
2897 struct drm_i915_fence_reg *reg, *avail;
2900 /* First try to find a free reg */
2902 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2903 reg = &dev_priv->fence_regs[i];
2907 if (!reg->pin_count)
2914 /* None available, try to steal one or wait for a user to finish */
2915 list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
2926 * i915_gem_object_get_fence - set up fencing for an object
2927 * @obj: object to map through a fence reg
2929 * When mapping objects through the GTT, userspace wants to be able to write
2930 * to them without having to worry about swizzling if the object is tiled.
2931 * This function walks the fence regs looking for a free one for @obj,
2932 * stealing one if it can't find any.
2934 * It then sets up the reg based on the object's properties: address, pitch
2935 * and tiling format.
2937 * For an untiled surface, this removes any existing fence.
2940 i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
2942 struct drm_device *dev = obj->base.dev;
2943 struct drm_i915_private *dev_priv = dev->dev_private;
2944 bool enable = obj->tiling_mode != I915_TILING_NONE;
2945 struct drm_i915_fence_reg *reg;
2948 /* Have we updated the tiling parameters upon the object and so
2949 * will need to serialise the write to the associated fence register?
2951 if (obj->fence_dirty) {
2952 ret = i915_gem_object_wait_fence(obj);
2957 /* Just update our place in the LRU if our fence is getting reused. */
2958 if (obj->fence_reg != I915_FENCE_REG_NONE) {
2959 reg = &dev_priv->fence_regs[obj->fence_reg];
2960 if (!obj->fence_dirty) {
2961 list_move_tail(®->lru_list,
2962 &dev_priv->mm.fence_list);
2965 } else if (enable) {
2966 reg = i915_find_fence_reg(dev);
2971 struct drm_i915_gem_object *old = reg->obj;
2973 ret = i915_gem_object_wait_fence(old);
2977 i915_gem_object_fence_lost(old);
2982 i915_gem_object_update_fence(obj, reg, enable);
2987 static bool i915_gem_valid_gtt_space(struct drm_device *dev,
2988 struct drm_mm_node *gtt_space,
2989 unsigned long cache_level)
2991 struct drm_mm_node *other;
2993 /* On non-LLC machines we have to be careful when putting differing
2994 * types of snoopable memory together to avoid the prefetcher
2995 * crossing memory domains and dying.
3000 if (gtt_space == NULL)
3003 if (list_empty(>t_space->node_list))
3006 other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list);
3007 if (other->allocated && !other->hole_follows && other->color != cache_level)
3010 other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list);
3011 if (other->allocated && !gtt_space->hole_follows && other->color != cache_level)
3017 static void i915_gem_verify_gtt(struct drm_device *dev)
3020 struct drm_i915_private *dev_priv = dev->dev_private;
3021 struct drm_i915_gem_object *obj;
3024 list_for_each_entry(obj, &dev_priv->mm.global_list, global_list) {
3025 if (obj->gtt_space == NULL) {
3026 printk(KERN_ERR "object found on GTT list with no space reserved\n");
3031 if (obj->cache_level != obj->gtt_space->color) {
3032 printk(KERN_ERR "object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n",
3033 obj->gtt_space->start,
3034 obj->gtt_space->start + obj->gtt_space->size,
3036 obj->gtt_space->color);
3041 if (!i915_gem_valid_gtt_space(dev,
3043 obj->cache_level)) {
3044 printk(KERN_ERR "invalid GTT space found at [%08lx, %08lx] - color=%x\n",
3045 obj->gtt_space->start,
3046 obj->gtt_space->start + obj->gtt_space->size,
3058 * Finds free space in the GTT aperture and binds the object there.
3061 i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
3063 bool map_and_fenceable,
3066 struct drm_device *dev = obj->base.dev;
3067 drm_i915_private_t *dev_priv = dev->dev_private;
3068 struct drm_mm_node *node;
3069 u32 size, fence_size, fence_alignment, unfenced_alignment;
3070 bool mappable, fenceable;
3071 size_t gtt_max = map_and_fenceable ?
3072 dev_priv->gtt.mappable_end : dev_priv->gtt.total;
3075 fence_size = i915_gem_get_gtt_size(dev,
3078 fence_alignment = i915_gem_get_gtt_alignment(dev,
3080 obj->tiling_mode, true);
3081 unfenced_alignment =
3082 i915_gem_get_gtt_alignment(dev,
3084 obj->tiling_mode, false);
3087 alignment = map_and_fenceable ? fence_alignment :
3089 if (map_and_fenceable && alignment & (fence_alignment - 1)) {
3090 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
3094 size = map_and_fenceable ? fence_size : obj->base.size;
3096 /* If the object is bigger than the entire aperture, reject it early
3097 * before evicting everything in a vain attempt to find space.
3099 if (obj->base.size > gtt_max) {
3100 DRM_ERROR("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%zu\n",
3102 map_and_fenceable ? "mappable" : "total",
3108 if (map_and_fenceable)
3109 node = drm_mm_search_free_in_range_color(&dev_priv->mm.gtt_space,
3110 size, alignment, obj->cache_level,
3111 0, dev_priv->gtt.mappable_end,
3114 node = drm_mm_search_free_color(&dev_priv->mm.gtt_space,
3115 size, alignment, obj->cache_level,
3118 if (map_and_fenceable)
3120 drm_mm_get_block_range_generic(node,
3121 size, alignment, obj->cache_level,
3122 0, dev_priv->gtt.mappable_end,
3126 drm_mm_get_block_generic(node,
3127 size, alignment, obj->cache_level,
3130 if (obj->gtt_space == NULL) {
3131 ret = i915_gem_evict_something(dev, size, alignment,
3142 * NOTE: i915_gem_object_get_pages_gtt() cannot
3143 * return ENOMEM, since we used VM_ALLOC_RETRY.
3145 ret = i915_gem_object_get_pages_gtt(obj);
3147 drm_mm_put_block(obj->gtt_space);
3148 obj->gtt_space = NULL;
3152 i915_gem_gtt_bind_object(obj, obj->cache_level);
3154 i915_gem_object_put_pages_gtt(obj);
3155 drm_mm_put_block(obj->gtt_space);
3156 obj->gtt_space = NULL;
3157 if (i915_gem_evict_everything(dev))
3162 list_add_tail(&obj->global_list, &dev_priv->mm.bound_list);
3163 list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
3165 obj->gtt_offset = obj->gtt_space->start;
3168 obj->gtt_space->size == fence_size &&
3169 (obj->gtt_space->start & (fence_alignment - 1)) == 0;
3172 obj->gtt_offset + obj->base.size <= dev_priv->gtt.mappable_end;
3174 obj->map_and_fenceable = mappable && fenceable;
3176 trace_i915_gem_object_bind(obj, map_and_fenceable);
3177 i915_gem_verify_gtt(dev);
3182 i915_gem_clflush_object(struct drm_i915_gem_object *obj)
3185 /* If we don't have a page list set up, then we're not pinned
3186 * to GPU, and we can ignore the cache flush because it'll happen
3187 * again at bind time.
3189 if (obj->pages == NULL)
3193 * Stolen memory is always coherent with the GPU as it is explicitly
3194 * marked as wc by the system, or the system is cache-coherent.
3199 /* If the GPU is snooping the contents of the CPU cache,
3200 * we do not need to manually clear the CPU cache lines. However,
3201 * the caches are only snooped when the render cache is
3202 * flushed/invalidated. As we always have to emit invalidations
3203 * and flushes when moving into and out of the RENDER domain, correct
3204 * snooping behaviour occurs naturally as the result of our domain
3207 if (obj->cache_level != I915_CACHE_NONE)
3210 trace_i915_gem_object_clflush(obj);
3212 drm_clflush_pages(obj->pages, obj->base.size / PAGE_SIZE);
3215 /** Flushes the GTT write domain for the object if it's dirty. */
3217 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
3219 uint32_t old_write_domain;
3221 if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
3224 /* No actual flushing is required for the GTT write domain. Writes
3225 * to it immediately go to main memory as far as we know, so there's
3226 * no chipset flush. It also doesn't land in render cache.
3228 * However, we do have to enforce the order so that all writes through
3229 * the GTT land before any writes to the device, such as updates to
3234 old_write_domain = obj->base.write_domain;
3235 obj->base.write_domain = 0;
3237 trace_i915_gem_object_change_domain(obj,
3238 obj->base.read_domains,
3242 /** Flushes the CPU write domain for the object if it's dirty. */
3244 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
3246 uint32_t old_write_domain;
3248 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
3251 i915_gem_clflush_object(obj);
3252 i915_gem_chipset_flush(obj->base.dev);
3253 old_write_domain = obj->base.write_domain;
3254 obj->base.write_domain = 0;
3256 trace_i915_gem_object_change_domain(obj,
3257 obj->base.read_domains,
3262 * Moves a single object to the GTT read, and possibly write domain.
3264 * This function returns when the move is complete, including waiting on
3268 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
3270 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
3271 uint32_t old_write_domain, old_read_domains;
3274 /* Not valid to be called on unbound objects. */
3275 if (obj->gtt_space == NULL)
3278 if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
3281 ret = i915_gem_object_wait_rendering(obj, !write);
3285 i915_gem_object_flush_cpu_write_domain(obj);
3287 /* Serialise direct access to this object with the barriers for
3288 * coherent writes from the GPU, by effectively invalidating the
3289 * GTT domain upon first access.
3291 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3294 old_write_domain = obj->base.write_domain;
3295 old_read_domains = obj->base.read_domains;
3297 /* It should now be out of any other write domains, and we can update
3298 * the domain values for our changes.
3300 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3301 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3303 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3304 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3308 trace_i915_gem_object_change_domain(obj,
3312 /* And bump the LRU for this access */
3313 if (i915_gem_object_is_inactive(obj))
3314 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
3319 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3320 enum i915_cache_level cache_level)
3322 struct drm_device *dev = obj->base.dev;
3323 drm_i915_private_t *dev_priv = dev->dev_private;
3326 if (obj->cache_level == cache_level)
3329 if (obj->pin_count) {
3330 DRM_DEBUG("can not change the cache level of pinned objects\n");
3334 if (!i915_gem_valid_gtt_space(dev, obj->gtt_space, cache_level)) {
3335 ret = i915_gem_object_unbind(obj);
3340 if (obj->gtt_space) {
3341 ret = i915_gem_object_finish_gpu(obj);
3345 i915_gem_object_finish_gtt(obj);
3347 /* Before SandyBridge, you could not use tiling or fence
3348 * registers with snooped memory, so relinquish any fences
3349 * currently pointing to our region in the aperture.
3351 if (INTEL_INFO(dev)->gen < 6) {
3352 ret = i915_gem_object_put_fence(obj);
3357 if (obj->has_global_gtt_mapping)
3358 i915_gem_gtt_bind_object(obj, cache_level);
3359 if (obj->has_aliasing_ppgtt_mapping)
3360 i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt,
3363 obj->gtt_space->color = cache_level;
3366 if (cache_level == I915_CACHE_NONE) {
3367 u32 old_read_domains, old_write_domain;
3369 /* If we're coming from LLC cached, then we haven't
3370 * actually been tracking whether the data is in the
3371 * CPU cache or not, since we only allow one bit set
3372 * in obj->write_domain and have been skipping the clflushes.
3373 * Just set it to the CPU cache for now.
3375 WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU);
3376 WARN_ON(obj->base.read_domains & ~I915_GEM_DOMAIN_CPU);
3378 old_read_domains = obj->base.read_domains;
3379 old_write_domain = obj->base.write_domain;
3381 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3382 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3384 trace_i915_gem_object_change_domain(obj,
3389 obj->cache_level = cache_level;
3390 i915_gem_verify_gtt(dev);
3394 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3395 struct drm_file *file)
3397 struct drm_i915_gem_caching *args = data;
3398 struct drm_i915_gem_object *obj;
3401 ret = i915_mutex_lock_interruptible(dev);
3405 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3406 if (&obj->base == NULL) {
3411 args->caching = obj->cache_level != I915_CACHE_NONE;
3413 drm_gem_object_unreference(&obj->base);
3415 mutex_unlock(&dev->struct_mutex);
3419 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3420 struct drm_file *file)
3422 struct drm_i915_gem_caching *args = data;
3423 struct drm_i915_gem_object *obj;
3424 enum i915_cache_level level;
3427 switch (args->caching) {
3428 case I915_CACHING_NONE:
3429 level = I915_CACHE_NONE;
3431 case I915_CACHING_CACHED:
3432 level = I915_CACHE_LLC;
3438 ret = i915_mutex_lock_interruptible(dev);
3442 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3443 if (&obj->base == NULL) {
3448 ret = i915_gem_object_set_cache_level(obj, level);
3450 drm_gem_object_unreference(&obj->base);
3452 mutex_unlock(&dev->struct_mutex);
3457 * Prepare buffer for display plane (scanout, cursors, etc).
3458 * Can be called from an uninterruptible phase (modesetting) and allows
3459 * any flushes to be pipelined (for pageflips).
3462 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3464 struct intel_ring_buffer *pipelined)
3466 u32 old_read_domains, old_write_domain;
3469 if (pipelined != obj->ring) {
3470 ret = i915_gem_object_sync(obj, pipelined);
3475 /* The display engine is not coherent with the LLC cache on gen6. As
3476 * a result, we make sure that the pinning that is about to occur is
3477 * done with uncached PTEs. This is lowest common denominator for all
3480 * However for gen6+, we could do better by using the GFDT bit instead
3481 * of uncaching, which would allow us to flush all the LLC-cached data
3482 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3484 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE);
3488 /* As the user may map the buffer once pinned in the display plane
3489 * (e.g. libkms for the bootup splash), we have to ensure that we
3490 * always use map_and_fenceable for all scanout buffers.
3492 ret = i915_gem_object_pin(obj, alignment, true, false);
3496 i915_gem_object_flush_cpu_write_domain(obj);
3498 old_write_domain = obj->base.write_domain;
3499 old_read_domains = obj->base.read_domains;
3501 /* It should now be out of any other write domains, and we can update
3502 * the domain values for our changes.
3504 obj->base.write_domain = 0;
3505 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3507 trace_i915_gem_object_change_domain(obj,
3515 i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
3519 if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
3522 ret = i915_gem_object_wait_rendering(obj, false);
3526 /* Ensure that we invalidate the GPU's caches and TLBs. */
3527 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
3532 * Moves a single object to the CPU read, and possibly write domain.
3534 * This function returns when the move is complete, including waiting on
3538 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
3540 uint32_t old_write_domain, old_read_domains;
3543 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
3546 ret = i915_gem_object_wait_rendering(obj, !write);
3550 i915_gem_object_flush_gtt_write_domain(obj);
3552 old_write_domain = obj->base.write_domain;
3553 old_read_domains = obj->base.read_domains;
3555 /* Flush the CPU cache if it's still invalid. */
3556 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
3557 i915_gem_clflush_object(obj);
3559 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3562 /* It should now be out of any other write domains, and we can update
3563 * the domain values for our changes.
3565 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3567 /* If we're writing through the CPU, then the GPU read domains will
3568 * need to be invalidated at next use.
3571 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3572 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3575 trace_i915_gem_object_change_domain(obj,
3582 /* Throttle our rendering by waiting until the ring has completed our requests
3583 * emitted over 20 msec ago.
3585 * Note that if we were to use the current jiffies each time around the loop,
3586 * we wouldn't escape the function with any frames outstanding if the time to
3587 * render a frame was over 20ms.
3589 * This should get us reasonable parallelism between CPU and GPU but also
3590 * relatively low latency when blocking on a particular request to finish.
3593 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
3595 struct drm_i915_private *dev_priv = dev->dev_private;
3596 struct drm_i915_file_private *file_priv = file->driver_priv;
3597 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3598 struct drm_i915_gem_request *request;
3599 struct intel_ring_buffer *ring = NULL;
3600 unsigned reset_counter;
3604 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
3608 ret = i915_gem_check_wedge(&dev_priv->gpu_error, false);
3612 spin_lock(&file_priv->mm.lock);
3613 list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
3614 if (time_after_eq(request->emitted_jiffies, recent_enough))
3617 ring = request->ring;
3618 seqno = request->seqno;
3620 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
3621 spin_unlock(&file_priv->mm.lock);
3626 ret = __wait_seqno(ring, seqno, reset_counter, true, NULL);
3628 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
3634 i915_gem_object_pin(struct drm_i915_gem_object *obj,
3636 bool map_and_fenceable,
3641 if (WARN_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT))
3644 if (obj->gtt_space != NULL) {
3645 if ((alignment && obj->gtt_offset & (alignment - 1)) ||
3646 (map_and_fenceable && !obj->map_and_fenceable)) {
3647 WARN(obj->pin_count,
3648 "bo is already pinned with incorrect alignment:"
3649 " offset=%x, req.alignment=%x, req.map_and_fenceable=%d,"
3650 " obj->map_and_fenceable=%d\n",
3651 obj->gtt_offset, alignment,
3653 obj->map_and_fenceable);
3654 ret = i915_gem_object_unbind(obj);
3660 if (obj->gtt_space == NULL) {
3661 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3663 ret = i915_gem_object_bind_to_gtt(obj, alignment,
3669 if (!dev_priv->mm.aliasing_ppgtt)
3670 i915_gem_gtt_bind_object(obj, obj->cache_level);
3673 if (!obj->has_global_gtt_mapping && map_and_fenceable)
3674 i915_gem_gtt_bind_object(obj, obj->cache_level);
3677 obj->pin_mappable |= map_and_fenceable;
3683 i915_gem_object_unpin(struct drm_i915_gem_object *obj)
3685 BUG_ON(obj->pin_count == 0);
3686 BUG_ON(obj->gtt_space == NULL);
3688 if (--obj->pin_count == 0)
3689 obj->pin_mappable = false;
3693 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
3694 struct drm_file *file)
3696 struct drm_i915_gem_pin *args = data;
3697 struct drm_i915_gem_object *obj;
3700 ret = i915_mutex_lock_interruptible(dev);
3704 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3705 if (&obj->base == NULL) {
3710 if (obj->madv != I915_MADV_WILLNEED) {
3711 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3716 if (obj->pin_filp != NULL && obj->pin_filp != file) {
3717 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3723 if (obj->user_pin_count == 0) {
3724 ret = i915_gem_object_pin(obj, args->alignment, true, false);
3729 obj->user_pin_count++;
3730 obj->pin_filp = file;
3732 /* XXX - flush the CPU caches for pinned objects
3733 * as the X server doesn't manage domains yet
3735 i915_gem_object_flush_cpu_write_domain(obj);
3736 args->offset = obj->gtt_offset;
3738 drm_gem_object_unreference(&obj->base);
3740 mutex_unlock(&dev->struct_mutex);
3745 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
3746 struct drm_file *file)
3748 struct drm_i915_gem_pin *args = data;
3749 struct drm_i915_gem_object *obj;
3752 ret = i915_mutex_lock_interruptible(dev);
3756 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3757 if (&obj->base == NULL) {
3762 if (obj->pin_filp != file) {
3763 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3768 obj->user_pin_count--;
3769 if (obj->user_pin_count == 0) {
3770 obj->pin_filp = NULL;
3771 i915_gem_object_unpin(obj);
3775 drm_gem_object_unreference(&obj->base);
3777 mutex_unlock(&dev->struct_mutex);
3782 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3783 struct drm_file *file)
3785 struct drm_i915_gem_busy *args = data;
3786 struct drm_i915_gem_object *obj;
3789 ret = i915_mutex_lock_interruptible(dev);
3793 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3794 if (&obj->base == NULL) {
3799 /* Count all active objects as busy, even if they are currently not used
3800 * by the gpu. Users of this interface expect objects to eventually
3801 * become non-busy without any further actions, therefore emit any
3802 * necessary flushes here.
3804 ret = i915_gem_object_flush_active(obj);
3806 args->busy = obj->active;
3808 args->busy |= intel_ring_flag(obj->ring) << 16;
3811 drm_gem_object_unreference(&obj->base);
3813 mutex_unlock(&dev->struct_mutex);
3818 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3819 struct drm_file *file_priv)
3821 return i915_gem_ring_throttle(dev, file_priv);
3825 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
3826 struct drm_file *file_priv)
3828 struct drm_i915_gem_madvise *args = data;
3829 struct drm_i915_gem_object *obj;
3832 switch (args->madv) {
3833 case I915_MADV_DONTNEED:
3834 case I915_MADV_WILLNEED:
3840 ret = i915_mutex_lock_interruptible(dev);
3844 obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
3845 if (&obj->base == NULL) {
3850 if (obj->pin_count) {
3855 if (obj->madv != __I915_MADV_PURGED)
3856 obj->madv = args->madv;
3858 /* if the object is no longer attached, discard its backing storage */
3859 if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL)
3860 i915_gem_object_truncate(obj);
3862 args->retained = obj->madv != __I915_MADV_PURGED;
3865 drm_gem_object_unreference(&obj->base);
3867 mutex_unlock(&dev->struct_mutex);
3871 void i915_gem_object_init(struct drm_i915_gem_object *obj,
3872 const struct drm_i915_gem_object_ops *ops)
3874 INIT_LIST_HEAD(&obj->mm_list);
3875 INIT_LIST_HEAD(&obj->global_list);
3876 INIT_LIST_HEAD(&obj->ring_list);
3877 INIT_LIST_HEAD(&obj->exec_list);
3881 obj->fence_reg = I915_FENCE_REG_NONE;
3882 obj->madv = I915_MADV_WILLNEED;
3883 /* Avoid an unnecessary call to unbind on the first bind. */
3884 obj->map_and_fenceable = true;
3886 i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size);
3889 static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
3890 .get_pages = i915_gem_object_get_pages_gtt,
3891 .put_pages = i915_gem_object_put_pages_gtt,
3894 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
3897 struct drm_i915_gem_object *obj;
3899 struct address_space *mapping;
3903 obj = kmalloc(sizeof(*obj), M_DRM, M_WAITOK | M_ZERO);
3907 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
3913 mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
3914 if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
3915 /* 965gm cannot relocate objects above 4GiB. */
3916 mask &= ~__GFP_HIGHMEM;
3917 mask |= __GFP_DMA32;
3920 mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
3921 mapping_set_gfp_mask(mapping, mask);
3924 i915_gem_object_init(obj, &i915_gem_object_ops);
3926 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3927 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3930 /* On some devices, we can have the GPU use the LLC (the CPU
3931 * cache) for about a 10% performance improvement
3932 * compared to uncached. Graphics requests other than
3933 * display scanout are coherent with the CPU in
3934 * accessing this cache. This means in this mode we
3935 * don't need to clflush on the CPU side, and on the
3936 * GPU side we only need to flush internal caches to
3937 * get data visible to the CPU.
3939 * However, we maintain the display planes as UC, and so
3940 * need to rebind when first used as such.
3942 obj->cache_level = I915_CACHE_LLC;
3944 obj->cache_level = I915_CACHE_NONE;
3949 int i915_gem_init_object(struct drm_gem_object *obj)
3956 void i915_gem_free_object(struct drm_gem_object *gem_obj)
3958 struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
3959 struct drm_device *dev = obj->base.dev;
3960 drm_i915_private_t *dev_priv = dev->dev_private;
3962 trace_i915_gem_object_destroy(obj);
3965 i915_gem_detach_phys_object(dev, obj);
3968 if (WARN_ON(i915_gem_object_unbind(obj) == -ERESTARTSYS)) {
3969 bool was_interruptible;
3971 was_interruptible = dev_priv->mm.interruptible;
3972 dev_priv->mm.interruptible = false;
3974 WARN_ON(i915_gem_object_unbind(obj));
3976 dev_priv->mm.interruptible = was_interruptible;
3979 /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
3980 * before progressing. */
3982 i915_gem_object_unpin_pages(obj);
3984 if (WARN_ON(obj->pages_pin_count))
3985 obj->pages_pin_count = 0;
3986 i915_gem_object_put_pages(obj);
3987 drm_gem_free_mmap_offset(&obj->base);
3991 drm_gem_object_release(&obj->base);
3992 i915_gem_info_remove_obj(dev_priv, obj->base.size);
3995 i915_gem_object_free(obj);
3999 i915_gem_idle(struct drm_device *dev)
4001 drm_i915_private_t *dev_priv = dev->dev_private;
4004 mutex_lock(&dev->struct_mutex);
4006 if (dev_priv->mm.suspended) {
4007 mutex_unlock(&dev->struct_mutex);
4011 ret = i915_gpu_idle(dev);
4013 mutex_unlock(&dev->struct_mutex);
4016 i915_gem_retire_requests(dev);
4018 /* Under UMS, be paranoid and evict. */
4019 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4020 i915_gem_evict_everything(dev);
4022 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4023 * We need to replace this with a semaphore, or something.
4024 * And not confound mm.suspended!
4026 dev_priv->mm.suspended = 1;
4027 del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
4029 i915_kernel_lost_context(dev);
4030 i915_gem_cleanup_ringbuffer(dev);
4032 mutex_unlock(&dev->struct_mutex);
4034 /* Cancel the retire work handler, which should be idle now. */
4035 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4040 void i915_gem_l3_remap(struct drm_device *dev)
4042 drm_i915_private_t *dev_priv = dev->dev_private;
4046 if (!HAS_L3_GPU_CACHE(dev))
4049 if (!dev_priv->l3_parity.remap_info)
4052 misccpctl = I915_READ(GEN7_MISCCPCTL);
4053 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
4054 POSTING_READ(GEN7_MISCCPCTL);
4056 for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
4057 u32 remap = I915_READ(GEN7_L3LOG_BASE + i);
4058 if (remap && remap != dev_priv->l3_parity.remap_info[i/4])
4059 DRM_DEBUG("0x%x was already programmed to %x\n",
4060 GEN7_L3LOG_BASE + i, remap);
4061 if (remap && !dev_priv->l3_parity.remap_info[i/4])
4062 DRM_DEBUG_DRIVER("Clearing remapped register\n");
4063 I915_WRITE(GEN7_L3LOG_BASE + i, dev_priv->l3_parity.remap_info[i/4]);
4066 /* Make sure all the writes land before disabling dop clock gating */
4067 POSTING_READ(GEN7_L3LOG_BASE);
4069 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
4072 void i915_gem_init_swizzling(struct drm_device *dev)
4074 drm_i915_private_t *dev_priv = dev->dev_private;
4076 if (INTEL_INFO(dev)->gen < 5 ||
4077 dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
4080 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
4081 DISP_TILE_SURFACE_SWIZZLING);
4086 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
4088 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
4089 else if (IS_GEN7(dev))
4090 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
4096 intel_enable_blt(struct drm_device *dev)
4103 /* The blitter was dysfunctional on early prototypes */
4104 revision = pci_read_config(dev->dev, PCIR_REVID, 1);
4105 if (IS_GEN6(dev) && revision < 8) {
4106 DRM_INFO("BLT not supported on this pre-production hardware;"
4107 " graphics performance will be degraded.\n");
4114 static int i915_gem_init_rings(struct drm_device *dev)
4116 struct drm_i915_private *dev_priv = dev->dev_private;
4119 ret = intel_init_render_ring_buffer(dev);
4124 ret = intel_init_bsd_ring_buffer(dev);
4126 goto cleanup_render_ring;
4129 if (intel_enable_blt(dev)) {
4130 ret = intel_init_blt_ring_buffer(dev);
4132 goto cleanup_bsd_ring;
4135 if (HAS_VEBOX(dev)) {
4136 ret = intel_init_vebox_ring_buffer(dev);
4138 goto cleanup_blt_ring;
4142 ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000));
4144 goto cleanup_vebox_ring;
4149 intel_cleanup_ring_buffer(&dev_priv->ring[VECS]);
4151 intel_cleanup_ring_buffer(&dev_priv->ring[BCS]);
4153 intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
4154 cleanup_render_ring:
4155 intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
4161 i915_gem_init_hw(struct drm_device *dev)
4163 drm_i915_private_t *dev_priv = dev->dev_private;
4167 if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt())
4171 if (IS_HASWELL(dev) && (I915_READ(0x120010) == 1))
4172 I915_WRITE(0x9008, I915_READ(0x9008) | 0xf0000);
4174 if (HAS_PCH_NOP(dev)) {
4175 u32 temp = I915_READ(GEN7_MSG_CTL);
4176 temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
4177 I915_WRITE(GEN7_MSG_CTL, temp);
4180 i915_gem_l3_remap(dev);
4182 i915_gem_init_swizzling(dev);
4184 ret = i915_gem_init_rings(dev);
4189 * XXX: There was some w/a described somewhere suggesting loading
4190 * contexts before PPGTT.
4192 i915_gem_context_init(dev);
4193 if (dev_priv->mm.aliasing_ppgtt) {
4194 ret = dev_priv->mm.aliasing_ppgtt->enable(dev);
4196 i915_gem_cleanup_aliasing_ppgtt(dev);
4197 DRM_INFO("PPGTT enable failed. This is not fatal, but unexpected\n");
4204 int i915_gem_init(struct drm_device *dev)
4206 struct drm_i915_private *dev_priv = dev->dev_private;
4209 mutex_lock(&dev->struct_mutex);
4211 if (IS_VALLEYVIEW(dev)) {
4212 /* VLVA0 (potential hack), BIOS isn't actually waking us */
4213 I915_WRITE(VLV_GTLC_WAKE_CTRL, 1);
4214 if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) & 1) == 1, 10))
4215 DRM_DEBUG_DRIVER("allow wake ack timed out\n");
4218 i915_gem_init_global_gtt(dev);
4220 ret = i915_gem_init_hw(dev);
4221 mutex_unlock(&dev->struct_mutex);
4223 i915_gem_cleanup_aliasing_ppgtt(dev);
4227 /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */
4228 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4229 dev_priv->dri1.allow_batchbuffer = 1;
4234 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4236 drm_i915_private_t *dev_priv = dev->dev_private;
4237 struct intel_ring_buffer *ring;
4240 for_each_ring(ring, dev_priv, i)
4241 intel_cleanup_ring_buffer(ring);
4245 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4246 struct drm_file *file_priv)
4248 drm_i915_private_t *dev_priv = dev->dev_private;
4251 if (drm_core_check_feature(dev, DRIVER_MODESET))
4254 if (i915_reset_in_progress(&dev_priv->gpu_error)) {
4255 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4256 atomic_set(&dev_priv->gpu_error.reset_counter, 0);
4259 mutex_lock(&dev->struct_mutex);
4260 dev_priv->mm.suspended = 0;
4262 ret = i915_gem_init_hw(dev);
4264 mutex_unlock(&dev->struct_mutex);
4268 KASSERT(list_empty(&dev_priv->mm.active_list), ("active list"));
4269 mutex_unlock(&dev->struct_mutex);
4271 ret = drm_irq_install(dev);
4273 goto cleanup_ringbuffer;
4278 mutex_lock(&dev->struct_mutex);
4279 i915_gem_cleanup_ringbuffer(dev);
4280 dev_priv->mm.suspended = 1;
4281 mutex_unlock(&dev->struct_mutex);
4287 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4288 struct drm_file *file_priv)
4290 if (drm_core_check_feature(dev, DRIVER_MODESET))
4293 drm_irq_uninstall(dev);
4294 return i915_gem_idle(dev);
4298 i915_gem_lastclose(struct drm_device *dev)
4302 if (drm_core_check_feature(dev, DRIVER_MODESET))
4305 ret = i915_gem_idle(dev);
4307 DRM_ERROR("failed to idle hardware: %d\n", ret);
4311 init_ring_lists(struct intel_ring_buffer *ring)
4313 INIT_LIST_HEAD(&ring->active_list);
4314 INIT_LIST_HEAD(&ring->request_list);
4318 i915_gem_load(struct drm_device *dev)
4321 drm_i915_private_t *dev_priv = dev->dev_private;
4323 INIT_LIST_HEAD(&dev_priv->mm.active_list);
4324 INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
4325 INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
4326 INIT_LIST_HEAD(&dev_priv->mm.bound_list);
4327 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4328 for (i = 0; i < I915_NUM_RINGS; i++)
4329 init_ring_lists(&dev_priv->ring[i]);
4330 for (i = 0; i < I915_MAX_NUM_FENCES; i++)
4331 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
4332 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4333 i915_gem_retire_work_handler);
4334 init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
4336 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4338 I915_WRITE(MI_ARB_STATE,
4339 _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
4342 dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
4344 /* Old X drivers will take 0-2 for front, back, depth buffers */
4345 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4346 dev_priv->fence_reg_start = 3;
4348 if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev))
4349 dev_priv->num_fence_regs = 32;
4350 else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4351 dev_priv->num_fence_regs = 16;
4353 dev_priv->num_fence_regs = 8;
4355 /* Initialize fence registers to zero */
4356 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4357 i915_gem_restore_fences(dev);
4359 i915_gem_detect_bit_6_swizzle(dev);
4360 init_waitqueue_head(&dev_priv->pending_flip_queue);
4362 dev_priv->mm.interruptible = true;
4365 dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink;
4366 dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS;
4367 register_shrinker(&dev_priv->mm.inactive_shrinker);
4369 dev_priv->mm.inactive_shrinker = EVENTHANDLER_REGISTER(vm_lowmem,
4370 i915_gem_lowmem, dev, EVENTHANDLER_PRI_ANY);
4375 * Create a physically contiguous memory object for this object
4376 * e.g. for cursor + overlay regs
4378 static int i915_gem_init_phys_object(struct drm_device *dev,
4379 int id, int size, int align)
4381 drm_i915_private_t *dev_priv = dev->dev_private;
4382 struct drm_i915_gem_phys_object *phys_obj;
4385 if (dev_priv->mm.phys_objs[id - 1] || !size)
4388 phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
4394 phys_obj->handle = drm_pci_alloc(dev, size, align);
4395 if (!phys_obj->handle) {
4399 pmap_change_attr((vm_offset_t)phys_obj->handle->vaddr,
4400 size / PAGE_SIZE, PAT_WRITE_COMBINING);
4402 dev_priv->mm.phys_objs[id - 1] = phys_obj;
4411 static void i915_gem_free_phys_object(struct drm_device *dev, int id)
4413 drm_i915_private_t *dev_priv = dev->dev_private;
4414 struct drm_i915_gem_phys_object *phys_obj;
4416 if (!dev_priv->mm.phys_objs[id - 1])
4419 phys_obj = dev_priv->mm.phys_objs[id - 1];
4420 if (phys_obj->cur_obj) {
4421 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4424 drm_pci_free(dev, phys_obj->handle);
4426 dev_priv->mm.phys_objs[id - 1] = NULL;
4429 void i915_gem_free_all_phys_object(struct drm_device *dev)
4433 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
4434 i915_gem_free_phys_object(dev, i);
4437 void i915_gem_detach_phys_object(struct drm_device *dev,
4438 struct drm_i915_gem_object *obj)
4440 struct vm_object *mapping = obj->base.vm_obj;
4447 vaddr = obj->phys_obj->handle->vaddr;
4449 page_count = obj->base.size / PAGE_SIZE;
4450 VM_OBJECT_LOCK(obj->base.vm_obj);
4451 for (i = 0; i < page_count; i++) {
4452 struct vm_page *page = shmem_read_mapping_page(mapping, i);
4453 if (!IS_ERR(page)) {
4454 VM_OBJECT_UNLOCK(obj->base.vm_obj);
4455 char *dst = kmap_atomic(page);
4456 memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE);
4459 drm_clflush_pages(&page, 1);
4462 set_page_dirty(page);
4463 mark_page_accessed(page);
4464 page_cache_release(page);
4466 VM_OBJECT_LOCK(obj->base.vm_obj);
4467 vm_page_reference(page);
4468 vm_page_dirty(page);
4469 vm_page_busy_wait(page, FALSE, "i915gem");
4470 vm_page_unwire(page, 0);
4471 vm_page_wakeup(page);
4474 VM_OBJECT_UNLOCK(obj->base.vm_obj);
4475 intel_gtt_chipset_flush();
4477 obj->phys_obj->cur_obj = NULL;
4478 obj->phys_obj = NULL;
4482 i915_gem_attach_phys_object(struct drm_device *dev,
4483 struct drm_i915_gem_object *obj,
4487 struct vm_object *mapping = obj->base.vm_obj;
4488 drm_i915_private_t *dev_priv = dev->dev_private;
4493 if (id > I915_MAX_PHYS_OBJECT)
4496 if (obj->phys_obj) {
4497 if (obj->phys_obj->id == id)
4499 i915_gem_detach_phys_object(dev, obj);
4502 /* create a new object */
4503 if (!dev_priv->mm.phys_objs[id - 1]) {
4504 ret = i915_gem_init_phys_object(dev, id,
4505 obj->base.size, align);
4507 DRM_ERROR("failed to init phys object %d size: %zu\n",
4508 id, obj->base.size);
4513 /* bind to the object */
4514 obj->phys_obj = dev_priv->mm.phys_objs[id - 1];
4515 obj->phys_obj->cur_obj = obj;
4517 page_count = obj->base.size / PAGE_SIZE;
4519 VM_OBJECT_LOCK(obj->base.vm_obj);
4520 for (i = 0; i < page_count; i++) {
4521 struct vm_page *page;
4524 page = shmem_read_mapping_page(mapping, i);
4525 VM_OBJECT_UNLOCK(obj->base.vm_obj);
4527 return PTR_ERR(page);
4529 src = kmap_atomic(page);
4530 dst = (char*)obj->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4531 memcpy(dst, src, PAGE_SIZE);
4535 mark_page_accessed(page);
4536 page_cache_release(page);
4538 VM_OBJECT_LOCK(obj->base.vm_obj);
4539 vm_page_reference(page);
4540 vm_page_busy_wait(page, FALSE, "i915gem");
4541 vm_page_unwire(page, 0);
4542 vm_page_wakeup(page);
4544 VM_OBJECT_UNLOCK(obj->base.vm_obj);
4550 i915_gem_phys_pwrite(struct drm_device *dev,
4551 struct drm_i915_gem_object *obj,
4552 struct drm_i915_gem_pwrite *args,
4553 struct drm_file *file_priv)
4555 void *vaddr = (char *)obj->phys_obj->handle->vaddr + args->offset;
4556 char __user *user_data = to_user_ptr(args->data_ptr);
4558 if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
4559 unsigned long unwritten;
4561 /* The physical object once assigned is fixed for the lifetime
4562 * of the obj, so we can safely drop the lock and continue
4565 mutex_unlock(&dev->struct_mutex);
4566 unwritten = copy_from_user(vaddr, user_data, args->size);
4567 mutex_lock(&dev->struct_mutex);
4572 i915_gem_chipset_flush(dev);
4576 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
4578 struct drm_i915_file_private *file_priv = file->driver_priv;
4580 /* Clean up our request list when the client is going away, so that
4581 * later retire_requests won't dereference our soon-to-be-gone
4584 spin_lock(&file_priv->mm.lock);
4585 while (!list_empty(&file_priv->mm.request_list)) {
4586 struct drm_i915_gem_request *request;
4588 request = list_first_entry(&file_priv->mm.request_list,
4589 struct drm_i915_gem_request,
4591 list_del(&request->client_list);
4592 request->file_priv = NULL;
4594 spin_unlock(&file_priv->mm.lock);
4598 i915_gem_pager_ctor(void *handle, vm_ooffset_t size, vm_prot_t prot,
4599 vm_ooffset_t foff, struct ucred *cred, u_short *color)
4602 *color = 0; /* XXXKIB */
4607 i915_gem_pager_dtor(void *handle)
4609 struct drm_gem_object *obj;
4610 struct drm_device *dev;
4615 mutex_lock(&dev->struct_mutex);
4616 drm_gem_free_mmap_offset(obj);
4617 i915_gem_release_mmap(to_intel_bo(obj));
4618 drm_gem_object_unreference(obj);
4619 mutex_unlock(&dev->struct_mutex);
4622 #define GEM_PARANOID_CHECK_GTT 0
4623 #if GEM_PARANOID_CHECK_GTT
4625 i915_gem_assert_pages_not_mapped(struct drm_device *dev, vm_page_t *ma,
4628 struct drm_i915_private *dev_priv;
4630 unsigned long start, end;
4634 dev_priv = dev->dev_private;
4635 start = OFF_TO_IDX(dev_priv->mm.gtt_start);
4636 end = OFF_TO_IDX(dev_priv->mm.gtt_end);
4637 for (i = start; i < end; i++) {
4638 pa = intel_gtt_read_pte_paddr(i);
4639 for (j = 0; j < page_count; j++) {
4640 if (pa == VM_PAGE_TO_PHYS(ma[j])) {
4641 panic("Page %p in GTT pte index %d pte %x",
4642 ma[i], i, intel_gtt_read_pte(i));
4646 obj->fence_dirty = false;
4651 i915_gpu_is_active(struct drm_device *dev)
4653 drm_i915_private_t *dev_priv = dev->dev_private;
4655 return !list_empty(&dev_priv->mm.active_list);
4659 i915_gem_lowmem(void *arg)
4661 struct drm_device *dev;
4662 struct drm_i915_private *dev_priv;
4663 struct drm_i915_gem_object *obj, *next;
4664 int cnt, cnt_fail, cnt_total;
4667 dev_priv = dev->dev_private;
4669 if (lockmgr(&dev->struct_mutex, LK_EXCLUSIVE|LK_NOWAIT))
4673 /* first scan for clean buffers */
4674 i915_gem_retire_requests(dev);
4676 cnt_total = cnt_fail = cnt = 0;
4678 list_for_each_entry_safe(obj, next, &dev_priv->mm.inactive_list,
4680 if (i915_gem_object_is_purgeable(obj)) {
4681 if (i915_gem_object_unbind(obj) != 0)
4687 /* second pass, evict/count anything still on the inactive list */
4688 list_for_each_entry_safe(obj, next, &dev_priv->mm.inactive_list,
4690 if (i915_gem_object_unbind(obj) == 0)
4696 if (cnt_fail > cnt_total / 100 && i915_gpu_is_active(dev)) {
4698 * We are desperate for pages, so as a last resort, wait
4699 * for the GPU to finish and discard whatever we can.
4700 * This has a dramatic impact to reduce the number of
4701 * OOM-killer events whilst running the GPU aggressively.
4703 if (i915_gpu_idle(dev) == 0)
4706 mutex_unlock(&dev->struct_mutex);