sys/dev/netif/ig_hal/e1000_82571.c

   1 /******************************************************************************
   2
   3   Copyright (c) 2001-2009, Intel Corporation
   4   All rights reserved.
   5
   6   Redistribution and use in source and binary forms, with or without
   7   modification, are permitted provided that the following conditions are met:
   8
   9    1. Redistributions of source code must retain the above copyright notice,
  10       this list of conditions and the following disclaimer.
  11
  12    2. Redistributions in binary form must reproduce the above copyright
  13       notice, this list of conditions and the following disclaimer in the
  14       documentation and/or other materials provided with the distribution.
  15
  16    3. Neither the name of the Intel Corporation nor the names of its
  17       contributors may be used to endorse or promote products derived from
  18       this software without specific prior written permission.
  19
  20   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30   POSSIBILITY OF SUCH DAMAGE.
  31
  32 ******************************************************************************/
  33 /*$FreeBSD: $*/
  34
  35 /*
  36  * 82571EB Gigabit Ethernet Controller
  37  * 82571EB Gigabit Ethernet Controller (Copper)
  38  * 82571EB Gigabit Ethernet Controller (Fiber)
  39  * 82571EB Dual Port Gigabit Mezzanine Adapter
  40  * 82571EB Quad Port Gigabit Mezzanine Adapter
  41  * 82571PT Gigabit PT Quad Port Server ExpressModule
  42  * 82572EI Gigabit Ethernet Controller (Copper)
  43  * 82572EI Gigabit Ethernet Controller (Fiber)
  44  * 82572EI Gigabit Ethernet Controller
  45  * 82573V Gigabit Ethernet Controller (Copper)
  46  * 82573E Gigabit Ethernet Controller (Copper)
  47  * 82573L Gigabit Ethernet Controller
  48  * 82574L Gigabit Network Connection
  49  * 82583V Gigabit Network Connection
  50  */
  51
  52 #include "e1000_api.h"
  53
  54 static s32  e1000_init_phy_params_82571(struct e1000_hw *hw);
  55 static s32  e1000_init_nvm_params_82571(struct e1000_hw *hw);
  56 static s32  e1000_init_mac_params_82571(struct e1000_hw *hw);
  57 static s32  e1000_acquire_nvm_82571(struct e1000_hw *hw);
  58 static void e1000_release_nvm_82571(struct e1000_hw *hw);
  59 static s32  e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset,
  60                                   u16 words, u16 *data);
  61 static s32  e1000_update_nvm_checksum_82571(struct e1000_hw *hw);
  62 static s32  e1000_validate_nvm_checksum_82571(struct e1000_hw *hw);
  63 static s32  e1000_get_cfg_done_82571(struct e1000_hw *hw);
  64 static s32  e1000_set_d0_lplu_state_82571(struct e1000_hw *hw,
  65                                           bool active);
  66 static s32  e1000_reset_hw_82571(struct e1000_hw *hw);
  67 static s32  e1000_init_hw_82571(struct e1000_hw *hw);
  68 static void e1000_clear_vfta_82571(struct e1000_hw *hw);
  69 static bool e1000_check_mng_mode_82574(struct e1000_hw *hw);
  70 static s32 e1000_led_on_82574(struct e1000_hw *hw);
  71 static s32  e1000_setup_link_82571(struct e1000_hw *hw);
  72 static s32  e1000_setup_copper_link_82571(struct e1000_hw *hw);
  73 static s32  e1000_check_for_serdes_link_82571(struct e1000_hw *hw);
  74 static s32  e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw);
  75 static s32  e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data);
  76 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw);
  77 static s32  e1000_get_hw_semaphore_82571(struct e1000_hw *hw);
  78 static s32  e1000_fix_nvm_checksum_82571(struct e1000_hw *hw);
  79 static s32  e1000_get_phy_id_82571(struct e1000_hw *hw);
  80 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw);
  81 static s32  e1000_get_hw_semaphore_82573(struct e1000_hw *hw);
  82 static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw);
  83 static s32  e1000_get_hw_semaphore_82574(struct e1000_hw *hw);
  84 static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw);
  85 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw);
  86 static s32  e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
  87                                        u16 words, u16 *data);
  88 static s32  e1000_read_mac_addr_82571(struct e1000_hw *hw);
  89 static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw);
  90
  91 /**
  92  *  e1000_init_phy_params_82571 - Init PHY func ptrs.
  93  *  @hw: pointer to the HW structure
  94  **/
  95 static s32 e1000_init_phy_params_82571(struct e1000_hw *hw)
  96 {
  97         struct e1000_phy_info *phy = &hw->phy;
  98         s32 ret_val = E1000_SUCCESS;
  99
 100         DEBUGFUNC("e1000_init_phy_params_82571");
 101
 102         if (hw->phy.media_type != e1000_media_type_copper) {
 103                 phy->type = e1000_phy_none;
 104                 goto out;
 105         }
 106
 107         phy->addr                        = 1;
 108         phy->autoneg_mask                = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 109         phy->reset_delay_us              = 100;
 110
 111         phy->ops.check_reset_block       = e1000_check_reset_block_generic;
 112         phy->ops.reset                   = e1000_phy_hw_reset_generic;
 113         phy->ops.set_d0_lplu_state       = e1000_set_d0_lplu_state_82571;
 114         phy->ops.set_d3_lplu_state       = e1000_set_d3_lplu_state_generic;
 115         phy->ops.power_up                = e1000_power_up_phy_copper;
 116         phy->ops.power_down              = e1000_power_down_phy_copper_82571;
 117
 118         switch (hw->mac.type) {
 119         case e1000_82571:
 120         case e1000_82572:
 121                 phy->type                   = e1000_phy_igp_2;
 122                 phy->ops.get_cfg_done       = e1000_get_cfg_done_82571;
 123                 phy->ops.get_info           = e1000_get_phy_info_igp;
 124                 phy->ops.check_polarity     = e1000_check_polarity_igp;
 125                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
 126                 phy->ops.get_cable_length   = e1000_get_cable_length_igp_2;
 127                 phy->ops.read_reg           = e1000_read_phy_reg_igp;
 128                 phy->ops.write_reg          = e1000_write_phy_reg_igp;
 129                 phy->ops.acquire            = e1000_get_hw_semaphore_82571;
 130                 phy->ops.release            = e1000_put_hw_semaphore_82571;
 131
 132                 /* This uses above function pointers */
 133                 ret_val = e1000_get_phy_id_82571(hw);
 134
 135                 /* Verify PHY ID */
 136                 if (phy->id != IGP01E1000_I_PHY_ID) {
 137                         ret_val = -E1000_ERR_PHY;
 138                         DEBUGOUT1("PHY ID unknown: type = 0x%08x\n", phy->id);
 139                         goto out;
 140                 }
 141                 break;
 142         case e1000_82573:
 143                 phy->type                   = e1000_phy_m88;
 144                 phy->ops.get_cfg_done       = e1000_get_cfg_done_generic;
 145                 phy->ops.get_info           = e1000_get_phy_info_m88;
 146                 phy->ops.check_polarity     = e1000_check_polarity_m88;
 147                 phy->ops.commit             = e1000_phy_sw_reset_generic;
 148                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
 149                 phy->ops.get_cable_length   = e1000_get_cable_length_m88;
 150                 phy->ops.read_reg           = e1000_read_phy_reg_m88;
 151                 phy->ops.write_reg          = e1000_write_phy_reg_m88;
 152                 phy->ops.acquire            = e1000_get_hw_semaphore_82571;
 153                 phy->ops.release            = e1000_put_hw_semaphore_82571;
 154
 155                 /* This uses above function pointers */
 156                 ret_val = e1000_get_phy_id_82571(hw);
 157
 158                 /* Verify PHY ID */
 159                 if (phy->id != M88E1111_I_PHY_ID) {
 160                         ret_val = -E1000_ERR_PHY;
 161                         DEBUGOUT1("PHY ID unknown: type = 0x%08x\n", phy->id);
 162                         goto out;
 163                 }
 164                 break;
 165         case e1000_82574:
 166         case e1000_82583:
 167                 phy->type                   = e1000_phy_bm;
 168                 phy->ops.get_cfg_done       = e1000_get_cfg_done_generic;
 169                 phy->ops.get_info           = e1000_get_phy_info_m88;
 170                 phy->ops.check_polarity     = e1000_check_polarity_m88;
 171                 phy->ops.commit             = e1000_phy_sw_reset_generic;
 172                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
 173                 phy->ops.get_cable_length   = e1000_get_cable_length_m88;
 174                 phy->ops.read_reg           = e1000_read_phy_reg_bm2;
 175                 phy->ops.write_reg          = e1000_write_phy_reg_bm2;
 176                 phy->ops.acquire            = e1000_get_hw_semaphore_82574;
 177                 phy->ops.release            = e1000_put_hw_semaphore_82574;
 178
 179                 /* This uses above function pointers */
 180                 ret_val = e1000_get_phy_id_82571(hw);
 181                 /* Verify PHY ID */
 182                 if (phy->id != BME1000_E_PHY_ID_R2) {
 183                         ret_val = -E1000_ERR_PHY;
 184                         DEBUGOUT1("PHY ID unknown: type = 0x%08x\n", phy->id);
 185                         goto out;
 186                 }
 187                 break;
 188         default:
 189                 ret_val = -E1000_ERR_PHY;
 190                 goto out;
 191                 break;
 192         }
 193
 194 out:
 195         return ret_val;
 196 }
 197
 198 /**
 199  *  e1000_init_nvm_params_82571 - Init NVM func ptrs.
 200  *  @hw: pointer to the HW structure
 201  **/
 202 static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw)
 203 {
 204         struct e1000_nvm_info *nvm = &hw->nvm;
 205         u32 eecd = E1000_READ_REG(hw, E1000_EECD);
 206         u16 size;
 207
 208         DEBUGFUNC("e1000_init_nvm_params_82571");
 209
 210         nvm->opcode_bits = 8;
 211         nvm->delay_usec = 1;
 212         switch (nvm->override) {
 213         case e1000_nvm_override_spi_large:
 214                 nvm->page_size = 32;
 215                 nvm->address_bits = 16;
 216                 break;
 217         case e1000_nvm_override_spi_small:
 218                 nvm->page_size = 8;
 219                 nvm->address_bits = 8;
 220                 break;
 221         default:
 222                 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
 223                 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
 224                 break;
 225         }
 226
 227         switch (hw->mac.type) {
 228         case e1000_82573:
 229         case e1000_82574:
 230         case e1000_82583:
 231                 if (((eecd >> 15) & 0x3) == 0x3) {
 232                         nvm->type = e1000_nvm_flash_hw;
 233                         nvm->word_size = 2048;
 234                         /*
 235                          * Autonomous Flash update bit must be cleared due
 236                          * to Flash update issue.
 237                          */
 238                         eecd &= ~E1000_EECD_AUPDEN;
 239                         E1000_WRITE_REG(hw, E1000_EECD, eecd);
 240                         break;
 241                 }
 242                 /* Fall Through */
 243         default:
 244                 nvm->type = e1000_nvm_eeprom_spi;
 245                 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
 246                                   E1000_EECD_SIZE_EX_SHIFT);
 247                 /*
 248                  * Added to a constant, "size" becomes the left-shift value
 249                  * for setting word_size.
 250                  */
 251                 size += NVM_WORD_SIZE_BASE_SHIFT;
 252
 253                 /* EEPROM access above 16k is unsupported */
 254                 if (size > 14)
 255                         size = 14;
 256                 nvm->word_size  = 1 << size;
 257                 break;
 258         }
 259
 260         /* Function Pointers */
 261         switch (hw->mac.type) {
 262         case e1000_82574:
 263         case e1000_82583:
 264                 nvm->ops.acquire = e1000_get_hw_semaphore_82574;
 265                 nvm->ops.release = e1000_put_hw_semaphore_82574;
 266                 break;
 267         default:
 268                 nvm->ops.acquire = e1000_acquire_nvm_82571;
 269                 nvm->ops.release = e1000_release_nvm_82571;
 270                 break;
 271         }
 272         nvm->ops.read          = e1000_read_nvm_eerd;
 273         nvm->ops.update        = e1000_update_nvm_checksum_82571;
 274         nvm->ops.validate      = e1000_validate_nvm_checksum_82571;
 275         nvm->ops.valid_led_default = e1000_valid_led_default_82571;
 276         nvm->ops.write         = e1000_write_nvm_82571;
 277
 278         return E1000_SUCCESS;
 279 }
 280
 281 /**
 282  *  e1000_init_mac_params_82571 - Init MAC func ptrs.
 283  *  @hw: pointer to the HW structure
 284  **/
 285 static s32 e1000_init_mac_params_82571(struct e1000_hw *hw)
 286 {
 287         struct e1000_mac_info *mac = &hw->mac;
 288         u32 swsm = 0;
 289         u32 swsm2 = 0;
 290         bool force_clear_smbi = FALSE;
 291
 292         DEBUGFUNC("e1000_init_mac_params_82571");
 293
 294         /* Set media type and media-dependent function pointers */
 295         switch (hw->device_id) {
 296         case E1000_DEV_ID_82571EB_FIBER:
 297         case E1000_DEV_ID_82572EI_FIBER:
 298         case E1000_DEV_ID_82571EB_QUAD_FIBER:
 299                 hw->phy.media_type = e1000_media_type_fiber;
 300                 mac->ops.setup_physical_interface =
 301                         e1000_setup_fiber_serdes_link_82571;
 302                 mac->ops.check_for_link = e1000_check_for_fiber_link_generic;
 303                 mac->ops.get_link_up_info =
 304                         e1000_get_speed_and_duplex_fiber_serdes_generic;
 305                 break;
 306         case E1000_DEV_ID_82571EB_SERDES:
 307         case E1000_DEV_ID_82571EB_SERDES_DUAL:
 308         case E1000_DEV_ID_82571EB_SERDES_QUAD:
 309         case E1000_DEV_ID_82572EI_SERDES:
 310                 hw->phy.media_type = e1000_media_type_internal_serdes;
 311                 mac->ops.setup_physical_interface =
 312                         e1000_setup_fiber_serdes_link_82571;
 313                 mac->ops.check_for_link = e1000_check_for_serdes_link_82571;
 314                 mac->ops.get_link_up_info =
 315                         e1000_get_speed_and_duplex_fiber_serdes_generic;
 316                 break;
 317         default:
 318                 hw->phy.media_type = e1000_media_type_copper;
 319                 mac->ops.setup_physical_interface =
 320                         e1000_setup_copper_link_82571;
 321                 mac->ops.check_for_link = e1000_check_for_copper_link_generic;
 322                 mac->ops.get_link_up_info =
 323                         e1000_get_speed_and_duplex_copper_generic;
 324                 break;
 325         }
 326
 327         /* Set mta register count */
 328         mac->mta_reg_count = 128;
 329         /* Set rar entry count */
 330         mac->rar_entry_count = E1000_RAR_ENTRIES;
 331         /* Set if part includes ASF firmware */
 332         mac->asf_firmware_present = TRUE;
 333         /* Adaptive IFS supported */
 334         mac->adaptive_ifs = TRUE;
 335
 336         /* Function pointers */
 337
 338         /* bus type/speed/width */
 339         mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic;
 340         /* reset */
 341         mac->ops.reset_hw = e1000_reset_hw_82571;
 342         /* hw initialization */
 343         mac->ops.init_hw = e1000_init_hw_82571;
 344         /* link setup */
 345         mac->ops.setup_link = e1000_setup_link_82571;
 346         /* multicast address update */
 347         mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
 348         /* writing VFTA */
 349         mac->ops.write_vfta = e1000_write_vfta_generic;
 350         /* clearing VFTA */
 351         mac->ops.clear_vfta = e1000_clear_vfta_82571;
 352         /* read mac address */
 353         mac->ops.read_mac_addr = e1000_read_mac_addr_82571;
 354         /* ID LED init */
 355         mac->ops.id_led_init = e1000_id_led_init_generic;
 356         /* blink LED */
 357         mac->ops.blink_led = e1000_blink_led_generic;
 358         /* setup LED */
 359         mac->ops.setup_led = e1000_setup_led_generic;
 360         /* cleanup LED */
 361         mac->ops.cleanup_led = e1000_cleanup_led_generic;
 362         /* turn off LED */
 363         mac->ops.led_off = e1000_led_off_generic;
 364         /* clear hardware counters */
 365         mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82571;
 366
 367         /* MAC-specific function pointers */
 368         switch (hw->mac.type) {
 369         case e1000_82573:
 370                 mac->ops.set_lan_id = e1000_set_lan_id_single_port;
 371                 mac->ops.check_mng_mode = e1000_check_mng_mode_generic;
 372                 mac->ops.led_on = e1000_led_on_generic;
 373
 374                 /* FWSM register */
 375                 mac->has_fwsm = TRUE;
 376                 /*
 377                  * ARC supported; valid only if manageability features are
 378                  * enabled.
 379                  */
 380                 mac->arc_subsystem_valid =
 381                         (E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK)
 382                         ? TRUE : FALSE;
 383                 break;
 384         case e1000_82574:
 385         case e1000_82583:
 386                 mac->ops.set_lan_id = e1000_set_lan_id_single_port;
 387                 mac->ops.check_mng_mode = e1000_check_mng_mode_82574;
 388                 mac->ops.led_on = e1000_led_on_82574;
 389                 break;
 390         default:
 391                 mac->ops.check_mng_mode = e1000_check_mng_mode_generic;
 392                 mac->ops.led_on = e1000_led_on_generic;
 393
 394                 /* FWSM register */
 395                 mac->has_fwsm = TRUE;
 396                 break;
 397         }
 398
 399         /*
 400          * Ensure that the inter-port SWSM.SMBI lock bit is clear before
 401          * first NVM or PHY acess. This should be done for single-port
 402          * devices, and for one port only on dual-port devices so that
 403          * for those devices we can still use the SMBI lock to synchronize
 404          * inter-port accesses to the PHY & NVM.
 405          */
 406         switch (hw->mac.type) {
 407         case e1000_82571:
 408         case e1000_82572:
 409                 swsm2 = E1000_READ_REG(hw, E1000_SWSM2);
 410
 411                 if (!(swsm2 & E1000_SWSM2_LOCK)) {
 412                         /* Only do this for the first interface on this card */
 413                         E1000_WRITE_REG(hw, E1000_SWSM2,
 414                             swsm2 | E1000_SWSM2_LOCK);
 415                         force_clear_smbi = TRUE;
 416                 } else
 417                         force_clear_smbi = FALSE;
 418                 break;
 419         default:
 420                 force_clear_smbi = TRUE;
 421                 break;
 422         }
 423
 424         if (force_clear_smbi) {
 425                 /* Make sure SWSM.SMBI is clear */
 426                 swsm = E1000_READ_REG(hw, E1000_SWSM);
 427                 if (swsm & E1000_SWSM_SMBI) {
 428                         /* This bit should not be set on a first interface, and
 429                          * indicates that the bootagent or EFI code has
 430                          * improperly left this bit enabled
 431                          */
 432                         DEBUGOUT("Please update your 82571 Bootagent\n");
 433                 }
 434                 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_SMBI);
 435         }
 436
 437         /*
 438          * Initialze device specific counter of SMBI acquisition
 439          * timeouts.
 440          */
 441          hw->dev_spec._82571.smb_counter = 0;
 442
 443         return E1000_SUCCESS;
 444 }
 445
 446 /**
 447  *  e1000_init_function_pointers_82571 - Init func ptrs.
 448  *  @hw: pointer to the HW structure
 449  *
 450  *  Called to initialize all function pointers and parameters.
 451  **/
 452 void e1000_init_function_pointers_82571(struct e1000_hw *hw)
 453 {
 454         DEBUGFUNC("e1000_init_function_pointers_82571");
 455
 456         hw->mac.ops.init_params = e1000_init_mac_params_82571;
 457         hw->nvm.ops.init_params = e1000_init_nvm_params_82571;
 458         hw->phy.ops.init_params = e1000_init_phy_params_82571;
 459 }
 460
 461 /**
 462  *  e1000_get_phy_id_82571 - Retrieve the PHY ID and revision
 463  *  @hw: pointer to the HW structure
 464  *
 465  *  Reads the PHY registers and stores the PHY ID and possibly the PHY
 466  *  revision in the hardware structure.
 467  **/
 468 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw)
 469 {
 470         struct e1000_phy_info *phy = &hw->phy;
 471         s32 ret_val = E1000_SUCCESS;
 472         u16 phy_id = 0;
 473
 474         DEBUGFUNC("e1000_get_phy_id_82571");
 475
 476         switch (hw->mac.type) {
 477         case e1000_82571:
 478         case e1000_82572:
 479                 /*
 480                  * The 82571 firmware may still be configuring the PHY.
 481                  * In this case, we cannot access the PHY until the
 482                  * configuration is done.  So we explicitly set the
 483                  * PHY ID.
 484                  */
 485                 phy->id = IGP01E1000_I_PHY_ID;
 486                 break;
 487         case e1000_82573:
 488                 ret_val = e1000_get_phy_id(hw);
 489                 break;
 490         case e1000_82574:
 491         case e1000_82583:
 492                 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
 493                 if (ret_val)
 494                         goto out;
 495
 496                 phy->id = (u32)(phy_id << 16);
 497                 usec_delay(20);
 498                 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);
 499                 if (ret_val)
 500                         goto out;
 501
 502                 phy->id |= (u32)(phy_id);
 503                 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
 504                 break;
 505         default:
 506                 ret_val = -E1000_ERR_PHY;
 507                 break;
 508         }
 509 out:
 510         return ret_val;
 511 }
 512
 513 /**
 514  *  e1000_get_hw_semaphore_82571 - Acquire hardware semaphore
 515  *  @hw: pointer to the HW structure
 516  *
 517  *  Acquire the HW semaphore to access the PHY or NVM
 518  **/
 519 static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw)
 520 {
 521         u32 swsm;
 522         s32 ret_val = E1000_SUCCESS;
 523         s32 sw_timeout = hw->nvm.word_size + 1;
 524         s32 fw_timeout = hw->nvm.word_size + 1;
 525         s32 i = 0;
 526
 527         DEBUGFUNC("e1000_get_hw_semaphore_82571");
 528
 529         /*
 530          * If we have timedout 3 times on trying to acquire
 531          * the inter-port SMBI semaphore, there is old code
 532          * operating on the other port, and it is not
 533          * releasing SMBI. Modify the number of times that
 534          * we try for the semaphore to interwork with this
 535          * older code.
 536          */
 537         if (hw->dev_spec._82571.smb_counter > 2)
 538                 sw_timeout = 1;
 539
 540         /* Get the SW semaphore */
 541         while (i < sw_timeout) {
 542                 swsm = E1000_READ_REG(hw, E1000_SWSM);
 543                 if (!(swsm & E1000_SWSM_SMBI))
 544                         break;
 545
 546                 usec_delay(50);
 547                 i++;
 548         }
 549
 550         if (i == sw_timeout) {
 551                 DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
 552                 hw->dev_spec._82571.smb_counter++;
 553         }
 554         /* Get the FW semaphore. */
 555         for (i = 0; i < fw_timeout; i++) {
 556                 swsm = E1000_READ_REG(hw, E1000_SWSM);
 557                 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI);
 558
 559                 /* Semaphore acquired if bit latched */
 560                 if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI)
 561                         break;
 562
 563                 usec_delay(50);
 564         }
 565
 566         if (i == fw_timeout) {
 567                 /* Release semaphores */
 568                 e1000_put_hw_semaphore_82571(hw);
 569                 DEBUGOUT("Driver can't access the NVM\n");
 570                 ret_val = -E1000_ERR_NVM;
 571                 goto out;
 572         }
 573
 574 out:
 575         return ret_val;
 576 }
 577
 578 /**
 579  *  e1000_put_hw_semaphore_82571 - Release hardware semaphore
 580  *  @hw: pointer to the HW structure
 581  *
 582  *  Release hardware semaphore used to access the PHY or NVM
 583  **/
 584 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw)
 585 {
 586         u32 swsm;
 587
 588         DEBUGFUNC("e1000_put_hw_semaphore_generic");
 589
 590         swsm = E1000_READ_REG(hw, E1000_SWSM);
 591
 592         swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
 593
 594         E1000_WRITE_REG(hw, E1000_SWSM, swsm);
 595 }
 596
 597 /**
 598  *  e1000_get_hw_semaphore_82573 - Acquire hardware semaphore
 599  *  @hw: pointer to the HW structure
 600  *
 601  *  Acquire the HW semaphore during reset.
 602  *
 603  **/
 604 static s32 e1000_get_hw_semaphore_82573(struct e1000_hw *hw)
 605 {
 606         u32 extcnf_ctrl;
 607         s32 ret_val = E1000_SUCCESS;
 608         s32 i = 0;
 609
 610         DEBUGFUNC("e1000_get_hw_semaphore_82573");
 611
 612         extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
 613         extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
 614         do {
 615                 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
 616                 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
 617
 618                 if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
 619                         break;
 620
 621                 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
 622
 623                 msec_delay(2);
 624                 i++;
 625         } while (i < MDIO_OWNERSHIP_TIMEOUT);
 626
 627         if (i == MDIO_OWNERSHIP_TIMEOUT) {
 628                 /* Release semaphores */
 629                 e1000_put_hw_semaphore_82573(hw);
 630                 DEBUGOUT("Driver can't access the PHY\n");
 631                 ret_val = -E1000_ERR_PHY;
 632                 goto out;
 633         }
 634
 635 out:
 636         return ret_val;
 637 }
 638
 639 /**
 640  *  e1000_put_hw_semaphore_82573 - Release hardware semaphore
 641  *  @hw: pointer to the HW structure
 642  *
 643  *  Release hardware semaphore used during reset.
 644  *
 645  **/
 646 static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw)
 647 {
 648         u32 extcnf_ctrl;
 649
 650         DEBUGFUNC("e1000_put_hw_semaphore_82573");
 651
 652         extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
 653         extcnf_ctrl &= ~E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
 654         E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
 655 }
 656
 657 /**
 658  *  e1000_get_hw_semaphore_82574 - Acquire hardware semaphore
 659  *  @hw: pointer to the HW structure
 660  *
 661  *  Acquire the HW semaphore to access the PHY or NVM.
 662  *
 663  **/
 664 static s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw)
 665 {
 666         s32 ret_val;
 667
 668         DEBUGFUNC("e1000_get_hw_semaphore_82574");
 669
 670         ret_val = e1000_get_hw_semaphore_82573(hw);
 671         return ret_val;
 672 }
 673
 674 /**
 675  *  e1000_put_hw_semaphore_82574 - Release hardware semaphore
 676  *  @hw: pointer to the HW structure
 677  *
 678  *  Release hardware semaphore used to access the PHY or NVM
 679  *
 680  **/
 681 static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw)
 682 {
 683         DEBUGFUNC("e1000_put_hw_semaphore_82574");
 684
 685         e1000_put_hw_semaphore_82573(hw);
 686 }
 687
 688 /**
 689  *  e1000_acquire_nvm_82571 - Request for access to the EEPROM
 690  *  @hw: pointer to the HW structure
 691  *
 692  *  To gain access to the EEPROM, first we must obtain a hardware semaphore.
 693  *  Then for non-82573 hardware, set the EEPROM access request bit and wait
 694  *  for EEPROM access grant bit.  If the access grant bit is not set, release
 695  *  hardware semaphore.
 696  **/
 697 static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw)
 698 {
 699         s32 ret_val;
 700
 701         DEBUGFUNC("e1000_acquire_nvm_82571");
 702
 703         ret_val = e1000_get_hw_semaphore_82571(hw);
 704         if (ret_val)
 705                 goto out;
 706
 707         switch (hw->mac.type) {
 708         case e1000_82573:
 709                 break;
 710         default:
 711                 ret_val = e1000_acquire_nvm_generic(hw);
 712                 break;
 713         }
 714
 715         if (ret_val)
 716                 e1000_put_hw_semaphore_82571(hw);
 717
 718 out:
 719         return ret_val;
 720 }
 721
 722 /**
 723  *  e1000_release_nvm_82571 - Release exclusive access to EEPROM
 724  *  @hw: pointer to the HW structure
 725  *
 726  *  Stop any current commands to the EEPROM and clear the EEPROM request bit.
 727  **/
 728 static void e1000_release_nvm_82571(struct e1000_hw *hw)
 729 {
 730         DEBUGFUNC("e1000_release_nvm_82571");
 731
 732         e1000_release_nvm_generic(hw);
 733         e1000_put_hw_semaphore_82571(hw);
 734 }
 735
 736 /**
 737  *  e1000_write_nvm_82571 - Write to EEPROM using appropriate interface
 738  *  @hw: pointer to the HW structure
 739  *  @offset: offset within the EEPROM to be written to
 740  *  @words: number of words to write
 741  *  @data: 16 bit word(s) to be written to the EEPROM
 742  *
 743  *  For non-82573 silicon, write data to EEPROM at offset using SPI interface.
 744  *
 745  *  If e1000_update_nvm_checksum is not called after this function, the
 746  *  EEPROM will most likely contain an invalid checksum.
 747  **/
 748 static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words,
 749                                  u16 *data)
 750 {
 751         s32 ret_val = E1000_SUCCESS;
 752
 753         DEBUGFUNC("e1000_write_nvm_82571");
 754
 755         switch (hw->mac.type) {
 756         case e1000_82573:
 757         case e1000_82574:
 758         case e1000_82583:
 759                 ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data);
 760                 break;
 761         case e1000_82571:
 762         case e1000_82572:
 763                 ret_val = e1000_write_nvm_spi(hw, offset, words, data);
 764                 break;
 765         default:
 766                 ret_val = -E1000_ERR_NVM;
 767                 break;
 768         }
 769
 770         return ret_val;
 771 }
 772
 773 /**
 774  *  e1000_update_nvm_checksum_82571 - Update EEPROM checksum
 775  *  @hw: pointer to the HW structure
 776  *
 777  *  Updates the EEPROM checksum by reading/adding each word of the EEPROM
 778  *  up to the checksum.  Then calculates the EEPROM checksum and writes the
 779  *  value to the EEPROM.
 780  **/
 781 static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw)
 782 {
 783         u32 eecd;
 784         s32 ret_val;
 785         u16 i;
 786
 787         DEBUGFUNC("e1000_update_nvm_checksum_82571");
 788
 789         ret_val = e1000_update_nvm_checksum_generic(hw);
 790         if (ret_val)
 791                 goto out;
 792
 793         /*
 794          * If our nvm is an EEPROM, then we're done
 795          * otherwise, commit the checksum to the flash NVM.
 796          */
 797         if (hw->nvm.type != e1000_nvm_flash_hw)
 798                 goto out;
 799
 800         /* Check for pending operations. */
 801         for (i = 0; i < E1000_FLASH_UPDATES; i++) {
 802                 msec_delay(1);
 803                 if ((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD) == 0)
 804                         break;
 805         }
 806
 807         if (i == E1000_FLASH_UPDATES) {
 808                 ret_val = -E1000_ERR_NVM;
 809                 goto out;
 810         }
 811
 812         /* Reset the firmware if using STM opcode. */
 813         if ((E1000_READ_REG(hw, E1000_FLOP) & 0xFF00) == E1000_STM_OPCODE) {
 814                 /*
 815                  * The enabling of and the actual reset must be done
 816                  * in two write cycles.
 817                  */
 818                 E1000_WRITE_REG(hw, E1000_HICR, E1000_HICR_FW_RESET_ENABLE);
 819                 E1000_WRITE_FLUSH(hw);
 820                 E1000_WRITE_REG(hw, E1000_HICR, E1000_HICR_FW_RESET);
 821         }
 822
 823         /* Commit the write to flash */
 824         eecd = E1000_READ_REG(hw, E1000_EECD) | E1000_EECD_FLUPD;
 825         E1000_WRITE_REG(hw, E1000_EECD, eecd);
 826
 827         for (i = 0; i < E1000_FLASH_UPDATES; i++) {
 828                 msec_delay(1);
 829                 if ((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD) == 0)
 830                         break;
 831         }
 832
 833         if (i == E1000_FLASH_UPDATES) {
 834                 ret_val = -E1000_ERR_NVM;
 835                 goto out;
 836         }
 837
 838 out:
 839         return ret_val;
 840 }
 841
 842 /**
 843  *  e1000_validate_nvm_checksum_82571 - Validate EEPROM checksum
 844  *  @hw: pointer to the HW structure
 845  *
 846  *  Calculates the EEPROM checksum by reading/adding each word of the EEPROM
 847  *  and then verifies that the sum of the EEPROM is equal to 0xBABA.
 848  **/
 849 static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw)
 850 {
 851         DEBUGFUNC("e1000_validate_nvm_checksum_82571");
 852
 853         if (hw->nvm.type == e1000_nvm_flash_hw)
 854                 e1000_fix_nvm_checksum_82571(hw);
 855
 856         return e1000_validate_nvm_checksum_generic(hw);
 857 }
 858
 859 /**
 860  *  e1000_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon
 861  *  @hw: pointer to the HW structure
 862  *  @offset: offset within the EEPROM to be written to
 863  *  @words: number of words to write
 864  *  @data: 16 bit word(s) to be written to the EEPROM
 865  *
 866  *  After checking for invalid values, poll the EEPROM to ensure the previous
 867  *  command has completed before trying to write the next word.  After write
 868  *  poll for completion.
 869  *
 870  *  If e1000_update_nvm_checksum is not called after this function, the
 871  *  EEPROM will most likely contain an invalid checksum.
 872  **/
 873 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
 874                                       u16 words, u16 *data)
 875 {
 876         struct e1000_nvm_info *nvm = &hw->nvm;
 877         u32 i, eewr = 0;
 878         s32 ret_val = 0;
 879
 880         DEBUGFUNC("e1000_write_nvm_eewr_82571");
 881
 882         /*
 883          * A check for invalid values:  offset too large, too many words,
 884          * and not enough words.
 885          */
 886         if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
 887             (words == 0)) {
 888                 DEBUGOUT("nvm parameter(s) out of bounds\n");
 889                 ret_val = -E1000_ERR_NVM;
 890                 goto out;
 891         }
 892
 893         for (i = 0; i < words; i++) {
 894                 eewr = (data[i] << E1000_NVM_RW_REG_DATA) |
 895                        ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) |
 896                        E1000_NVM_RW_REG_START;
 897
 898                 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
 899                 if (ret_val)
 900                         break;
 901
 902                 E1000_WRITE_REG(hw, E1000_EEWR, eewr);
 903
 904                 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
 905                 if (ret_val)
 906                         break;
 907         }
 908
 909 out:
 910         return ret_val;
 911 }
 912
 913 /**
 914  *  e1000_get_cfg_done_82571 - Poll for configuration done
 915  *  @hw: pointer to the HW structure
 916  *
 917  *  Reads the management control register for the config done bit to be set.
 918  **/
 919 static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw)
 920 {
 921         s32 timeout = PHY_CFG_TIMEOUT;
 922         s32 ret_val = E1000_SUCCESS;
 923
 924         DEBUGFUNC("e1000_get_cfg_done_82571");
 925
 926         while (timeout) {
 927                 if (E1000_READ_REG(hw, E1000_EEMNGCTL) &
 928                     E1000_NVM_CFG_DONE_PORT_0)
 929                         break;
 930                 msec_delay(1);
 931                 timeout--;
 932         }
 933         if (!timeout) {
 934                 DEBUGOUT("MNG configuration cycle has not completed.\n");
 935                 ret_val = -E1000_ERR_RESET;
 936                 goto out;
 937         }
 938
 939 out:
 940         return ret_val;
 941 }
 942
 943 /**
 944  *  e1000_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state
 945  *  @hw: pointer to the HW structure
 946  *  @active: TRUE to enable LPLU, FALSE to disable
 947  *
 948  *  Sets the LPLU D0 state according to the active flag.  When activating LPLU
 949  *  this function also disables smart speed and vice versa.  LPLU will not be
 950  *  activated unless the device autonegotiation advertisement meets standards
 951  *  of either 10 or 10/100 or 10/100/1000 at all duplexes.  This is a function
 952  *  pointer entry point only called by PHY setup routines.
 953  **/
 954 static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active)
 955 {
 956         struct e1000_phy_info *phy = &hw->phy;
 957         s32 ret_val = E1000_SUCCESS;
 958         u16 data;
 959
 960         DEBUGFUNC("e1000_set_d0_lplu_state_82571");
 961
 962         if (!(phy->ops.read_reg))
 963                 goto out;
 964
 965         ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
 966         if (ret_val)
 967                 goto out;
 968
 969         if (active) {
 970                 data |= IGP02E1000_PM_D0_LPLU;
 971                 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
 972                                              data);
 973                 if (ret_val)
 974                         goto out;
 975
 976                 /* When LPLU is enabled, we should disable SmartSpeed */
 977                 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
 978                                             &data);
 979                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 980                 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
 981                                              data);
 982                 if (ret_val)
 983                         goto out;
 984         } else {
 985                 data &= ~IGP02E1000_PM_D0_LPLU;
 986                 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
 987                                              data);
 988                 /*
 989                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
 990                  * during Dx states where the power conservation is most
 991                  * important.  During driver activity we should enable
 992                  * SmartSpeed, so performance is maintained.
 993                  */
 994                 if (phy->smart_speed == e1000_smart_speed_on) {
 995                         ret_val = phy->ops.read_reg(hw,
 996                                                     IGP01E1000_PHY_PORT_CONFIG,
 997                                                     &data);
 998                         if (ret_val)
 999                                 goto out;
1000
1001                         data |= IGP01E1000_PSCFR_SMART_SPEED;
1002                         ret_val = phy->ops.write_reg(hw,
1003                                                      IGP01E1000_PHY_PORT_CONFIG,
1004                                                      data);
1005                         if (ret_val)
1006                                 goto out;
1007                 } else if (phy->smart_speed == e1000_smart_speed_off) {
1008                         ret_val = phy->ops.read_reg(hw,
1009                                                     IGP01E1000_PHY_PORT_CONFIG,
1010                                                     &data);
1011                         if (ret_val)
1012                                 goto out;
1013
1014                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1015                         ret_val = phy->ops.write_reg(hw,
1016                                                      IGP01E1000_PHY_PORT_CONFIG,
1017                                                      data);
1018                         if (ret_val)
1019                                 goto out;
1020                 }
1021         }
1022
1023 out:
1024         return ret_val;
1025 }
1026
1027 /**
1028  *  e1000_reset_hw_82571 - Reset hardware
1029  *  @hw: pointer to the HW structure
1030  *
1031  *  This resets the hardware into a known state.
1032  **/
1033 static s32 e1000_reset_hw_82571(struct e1000_hw *hw)
1034 {
1035         u32 ctrl, ctrl_ext, icr;
1036         s32 ret_val;
1037
1038         DEBUGFUNC("e1000_reset_hw_82571");
1039
1040         /*
1041          * Prevent the PCI-E bus from sticking if there is no TLP connection
1042          * on the last TLP read/write transaction when MAC is reset.
1043          */
1044         ret_val = e1000_disable_pcie_master_generic(hw);
1045         if (ret_val)
1046                 DEBUGOUT("PCI-E Master disable polling has failed.\n");
1047
1048         DEBUGOUT("Masking off all interrupts\n");
1049         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1050
1051         E1000_WRITE_REG(hw, E1000_RCTL, 0);
1052         E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
1053         E1000_WRITE_FLUSH(hw);
1054
1055         msec_delay(10);
1056
1057         /*
1058          * Must acquire the MDIO ownership before MAC reset.
1059          * Ownership defaults to firmware after a reset.
1060          */
1061         switch (hw->mac.type) {
1062         case e1000_82573:
1063                 ret_val = e1000_get_hw_semaphore_82573(hw);
1064                 break;
1065         case e1000_82574:
1066         case e1000_82583:
1067                 ret_val = e1000_get_hw_semaphore_82574(hw);
1068                 break;
1069         default:
1070                 break;
1071         }
1072         if (ret_val)
1073                 DEBUGOUT("Cannot acquire MDIO ownership\n");
1074
1075         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1076
1077         DEBUGOUT("Issuing a global reset to MAC\n");
1078         E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
1079
1080         /* Must release MDIO ownership and mutex after MAC reset. */
1081         switch (hw->mac.type) {
1082         case e1000_82574:
1083         case e1000_82583:
1084                 e1000_put_hw_semaphore_82574(hw);
1085                 break;
1086         default:
1087                 break;
1088         }
1089
1090         if (hw->nvm.type == e1000_nvm_flash_hw) {
1091                 usec_delay(10);
1092                 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1093                 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
1094                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1095                 E1000_WRITE_FLUSH(hw);
1096         }
1097
1098         ret_val = e1000_get_auto_rd_done_generic(hw);
1099         if (ret_val)
1100                 /* We don't want to continue accessing MAC registers. */
1101                 goto out;
1102
1103         /*
1104          * Phy configuration from NVM just starts after EECD_AUTO_RD is set.
1105          * Need to wait for Phy configuration completion before accessing
1106          * NVM and Phy.
1107          */
1108
1109         switch (hw->mac.type) {
1110         case e1000_82573:
1111         case e1000_82574:
1112         case e1000_82583:
1113                 msec_delay(25);
1114                 break;
1115         default:
1116                 break;
1117         }
1118
1119         /* Clear any pending interrupt events. */
1120         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1121         icr = E1000_READ_REG(hw, E1000_ICR);
1122
1123         if (hw->mac.type == e1000_82571) {
1124                 /* Install any alternate MAC address into RAR0 */
1125                 ret_val = e1000_check_alt_mac_addr_generic(hw);
1126                 if (ret_val)
1127                         goto out;
1128
1129                 e1000_set_laa_state_82571(hw, TRUE);
1130         }
1131
1132         /* Reinitialize the 82571 serdes link state machine */
1133         if (hw->phy.media_type == e1000_media_type_internal_serdes)
1134                 hw->mac.serdes_link_state = e1000_serdes_link_down;
1135
1136 out:
1137         return ret_val;
1138 }
1139
1140 /**
1141  *  e1000_init_hw_82571 - Initialize hardware
1142  *  @hw: pointer to the HW structure
1143  *
1144  *  This inits the hardware readying it for operation.
1145  **/
1146 static s32 e1000_init_hw_82571(struct e1000_hw *hw)
1147 {
1148         struct e1000_mac_info *mac = &hw->mac;
1149         u32 reg_data;
1150         s32 ret_val;
1151         u16 i, rar_count = mac->rar_entry_count;
1152
1153         DEBUGFUNC("e1000_init_hw_82571");
1154
1155         e1000_initialize_hw_bits_82571(hw);
1156
1157         /* Initialize identification LED */
1158         ret_val = mac->ops.id_led_init(hw);
1159         if (ret_val)
1160                 DEBUGOUT("Error initializing identification LED\n");
1161                 /* This is not fatal and we should not stop init due to this */
1162
1163         /* Disabling VLAN filtering */
1164         DEBUGOUT("Initializing the IEEE VLAN\n");
1165         mac->ops.clear_vfta(hw);
1166
1167         /* Setup the receive address. */
1168         /*
1169          * If, however, a locally administered address was assigned to the
1170          * 82571, we must reserve a RAR for it to work around an issue where
1171          * resetting one port will reload the MAC on the other port.
1172          */
1173         if (e1000_get_laa_state_82571(hw))
1174                 rar_count--;
1175         e1000_init_rx_addrs_generic(hw, rar_count);
1176
1177         /* Zero out the Multicast HASH table */
1178         DEBUGOUT("Zeroing the MTA\n");
1179         for (i = 0; i < mac->mta_reg_count; i++)
1180                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
1181
1182         /* Setup link and flow control */
1183         ret_val = mac->ops.setup_link(hw);
1184
1185         /* Set the transmit descriptor write-back policy */
1186         reg_data = E1000_READ_REG(hw, E1000_TXDCTL(0));
1187         reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
1188                    E1000_TXDCTL_FULL_TX_DESC_WB |
1189                    E1000_TXDCTL_COUNT_DESC;
1190         E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg_data);
1191
1192         /* ...for both queues. */
1193         switch (mac->type) {
1194         case e1000_82573:
1195                 e1000_enable_tx_pkt_filtering_generic(hw);
1196                 /* fall through */
1197         case e1000_82574:
1198         case e1000_82583:
1199                 reg_data = E1000_READ_REG(hw, E1000_GCR);
1200                 reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
1201                 E1000_WRITE_REG(hw, E1000_GCR, reg_data);
1202                 break;
1203         default:
1204                 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(1));
1205                 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
1206                            E1000_TXDCTL_FULL_TX_DESC_WB |
1207                            E1000_TXDCTL_COUNT_DESC;
1208                 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg_data);
1209                 break;
1210         }
1211
1212         /*
1213          * Clear all of the statistics registers (clear on read).  It is
1214          * important that we do this after we have tried to establish link
1215          * because the symbol error count will increment wildly if there
1216          * is no link.
1217          */
1218         e1000_clear_hw_cntrs_82571(hw);
1219
1220         return ret_val;
1221 }
1222
1223 /**
1224  *  e1000_initialize_hw_bits_82571 - Initialize hardware-dependent bits
1225  *  @hw: pointer to the HW structure
1226  *
1227  *  Initializes required hardware-dependent bits needed for normal operation.
1228  **/
1229 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw)
1230 {
1231         u32 reg;
1232
1233         DEBUGFUNC("e1000_initialize_hw_bits_82571");
1234
1235         /* Transmit Descriptor Control 0 */
1236         reg = E1000_READ_REG(hw, E1000_TXDCTL(0));
1237         reg |= (1 << 22);
1238         E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg);
1239
1240         /* Transmit Descriptor Control 1 */
1241         reg = E1000_READ_REG(hw, E1000_TXDCTL(1));
1242         reg |= (1 << 22);
1243         E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg);
1244
1245         /* Transmit Arbitration Control 0 */
1246         reg = E1000_READ_REG(hw, E1000_TARC(0));
1247         reg &= ~(0xF << 27); /* 30:27 */
1248         switch (hw->mac.type) {
1249         case e1000_82571:
1250         case e1000_82572:
1251                 reg |= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26);
1252                 break;
1253         default:
1254                 break;
1255         }
1256         E1000_WRITE_REG(hw, E1000_TARC(0), reg);
1257
1258         /* Transmit Arbitration Control 1 */
1259         reg = E1000_READ_REG(hw, E1000_TARC(1));
1260         switch (hw->mac.type) {
1261         case e1000_82571:
1262         case e1000_82572:
1263                 reg &= ~((1 << 29) | (1 << 30));
1264                 reg |= (1 << 22) | (1 << 24) | (1 << 25) | (1 << 26);
1265                 if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR)
1266                         reg &= ~(1 << 28);
1267                 else
1268                         reg |= (1 << 28);
1269                 E1000_WRITE_REG(hw, E1000_TARC(1), reg);
1270                 break;
1271         default:
1272                 break;
1273         }
1274
1275         /* Device Control */
1276         switch (hw->mac.type) {
1277         case e1000_82573:
1278         case e1000_82574:
1279         case e1000_82583:
1280                 reg = E1000_READ_REG(hw, E1000_CTRL);
1281                 reg &= ~(1 << 29);
1282                 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1283                 break;
1284         default:
1285                 break;
1286         }
1287
1288         /* Extended Device Control */
1289         switch (hw->mac.type) {
1290         case e1000_82573:
1291         case e1000_82574:
1292         case e1000_82583:
1293                 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1294                 reg &= ~(1 << 23);
1295                 reg |= (1 << 22);
1296                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1297                 break;
1298         default:
1299                 break;
1300         }
1301
1302         if (hw->mac.type == e1000_82571) {
1303                 reg = E1000_READ_REG(hw, E1000_PBA_ECC);
1304                 reg |= E1000_PBA_ECC_CORR_EN;
1305                 E1000_WRITE_REG(hw, E1000_PBA_ECC, reg);
1306         }
1307
1308         /*
1309          * Workaround for hardware errata.
1310          * Ensure that DMA Dynamic Clock gating is disabled on 82571 and 82572
1311          */
1312         if ((hw->mac.type == e1000_82571) ||
1313            (hw->mac.type == e1000_82572)) {
1314                 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1315                 reg &= ~E1000_CTRL_EXT_DMA_DYN_CLK_EN;
1316                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1317         }
1318
1319         /* PCI-Ex Control Registers */
1320         switch (hw->mac.type) {
1321         case e1000_82574:
1322         case e1000_82583:
1323                 reg = E1000_READ_REG(hw, E1000_GCR);
1324                 reg |= (1 << 22);
1325                 E1000_WRITE_REG(hw, E1000_GCR, reg);
1326
1327                 /*
1328                  * Workaround for hardware errata.
1329                  * apply workaround for hardware errata documented in errata
1330                  * docs Fixes issue where some error prone or unreliable PCIe
1331                  * completions are occurring, particularly with ASPM enabled.
1332                  * Without fix, issue can cause tx timeouts.
1333                  */
1334                 reg = E1000_READ_REG(hw, E1000_GCR2);
1335                 reg |= 1;
1336                 E1000_WRITE_REG(hw, E1000_GCR2, reg);
1337                 break;
1338         default:
1339                 break;
1340         }
1341
1342         return;
1343 }
1344
1345 /**
1346  *  e1000_clear_vfta_82571 - Clear VLAN filter table
1347  *  @hw: pointer to the HW structure
1348  *
1349  *  Clears the register array which contains the VLAN filter table by
1350  *  setting all the values to 0.
1351  **/
1352 static void e1000_clear_vfta_82571(struct e1000_hw *hw)
1353 {
1354         u32 offset;
1355         u32 vfta_value = 0;
1356         u32 vfta_offset = 0;
1357         u32 vfta_bit_in_reg = 0;
1358
1359         DEBUGFUNC("e1000_clear_vfta_82571");
1360
1361         switch (hw->mac.type) {
1362         case e1000_82573:
1363         case e1000_82574:
1364         case e1000_82583:
1365                 if (hw->mng_cookie.vlan_id != 0) {
1366                         /*
1367                          * The VFTA is a 4096b bit-field, each identifying
1368                          * a single VLAN ID.  The following operations
1369                          * determine which 32b entry (i.e. offset) into the
1370                          * array we want to set the VLAN ID (i.e. bit) of
1371                          * the manageability unit.
1372                          */
1373                         vfta_offset = (hw->mng_cookie.vlan_id >>
1374                                 E1000_VFTA_ENTRY_SHIFT) & E1000_VFTA_ENTRY_MASK;
1375                         vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id &
1376                                 E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
1377                 }
1378                 break;
1379         default:
1380                 break;
1381         }
1382         for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
1383                 /*
1384                  * If the offset we want to clear is the same offset of the
1385                  * manageability VLAN ID, then clear all bits except that of
1386                  * the manageability unit.
1387                  */
1388                 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
1389                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, vfta_value);
1390                 E1000_WRITE_FLUSH(hw);
1391         }
1392 }
1393
1394 /**
1395  *  e1000_check_mng_mode_82574 - Check manageability is enabled
1396  *  @hw: pointer to the HW structure
1397  *
1398  *  Reads the NVM Initialization Control Word 2 and returns TRUE
1399  *  (>0) if any manageability is enabled, else FALSE (0).
1400  **/
1401 static bool e1000_check_mng_mode_82574(struct e1000_hw *hw)
1402 {
1403         u16 data;
1404
1405         DEBUGFUNC("e1000_check_mng_mode_82574");
1406
1407         hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &data);
1408         return (data & E1000_NVM_INIT_CTRL2_MNGM) != 0;
1409 }
1410
1411 /**
1412  *  e1000_led_on_82574 - Turn LED on
1413  *  @hw: pointer to the HW structure
1414  *
1415  *  Turn LED on.
1416  **/
1417 static s32 e1000_led_on_82574(struct e1000_hw *hw)
1418 {
1419         u32 ctrl;
1420         u32 i;
1421
1422         DEBUGFUNC("e1000_led_on_82574");
1423
1424         ctrl = hw->mac.ledctl_mode2;
1425         if (!(E1000_STATUS_LU & E1000_READ_REG(hw, E1000_STATUS))) {
1426                 /*
1427                  * If no link, then turn LED on by setting the invert bit
1428                  * for each LED that's "on" (0x0E) in ledctl_mode2.
1429                  */
1430                 for (i = 0; i < 4; i++)
1431                         if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
1432                             E1000_LEDCTL_MODE_LED_ON)
1433                                 ctrl |= (E1000_LEDCTL_LED0_IVRT << (i * 8));
1434         }
1435         E1000_WRITE_REG(hw, E1000_LEDCTL, ctrl);
1436
1437         return E1000_SUCCESS;
1438 }
1439
1440 /**
1441  *  e1000_check_phy_82574 - check 82574 phy hung state
1442  *  @hw: pointer to the HW structure
1443  *
1444  *  Returns whether phy is hung or not
1445  **/
1446 bool e1000_check_phy_82574(struct e1000_hw *hw)
1447 {
1448         u16 status_1kbt = 0;
1449         u16 receive_errors = 0;
1450         bool phy_hung = FALSE;
1451         s32 ret_val = E1000_SUCCESS;
1452
1453         DEBUGFUNC("e1000_check_phy_82574");
1454
1455         /*
1456          * Read PHY Receive Error counter first, if its is max - all F's then
1457          * read the Base1000T status register If both are max then PHY is hung.
1458          */
1459         ret_val = hw->phy.ops.read_reg(hw, E1000_RECEIVE_ERROR_COUNTER,
1460                                        &receive_errors);
1461         if (ret_val)
1462                 goto out;
1463         if (receive_errors == E1000_RECEIVE_ERROR_MAX)  {
1464                 ret_val = hw->phy.ops.read_reg(hw, E1000_BASE1000T_STATUS,
1465                                                &status_1kbt);
1466                 if (ret_val)
1467                         goto out;
1468                 if ((status_1kbt & E1000_IDLE_ERROR_COUNT_MASK) ==
1469                     E1000_IDLE_ERROR_COUNT_MASK)
1470                         phy_hung = TRUE;
1471         }
1472 out:
1473         return phy_hung;
1474 }
1475
1476
1477 /**
1478  *  e1000_setup_link_82571 - Setup flow control and link settings
1479  *  @hw: pointer to the HW structure
1480  *
1481  *  Determines which flow control settings to use, then configures flow
1482  *  control.  Calls the appropriate media-specific link configuration
1483  *  function.  Assuming the adapter has a valid link partner, a valid link
1484  *  should be established.  Assumes the hardware has previously been reset
1485  *  and the transmitter and receiver are not enabled.
1486  **/
1487 static s32 e1000_setup_link_82571(struct e1000_hw *hw)
1488 {
1489         DEBUGFUNC("e1000_setup_link_82571");
1490
1491         /*
1492          * 82573 does not have a word in the NVM to determine
1493          * the default flow control setting, so we explicitly
1494          * set it to full.
1495          */
1496         switch (hw->mac.type) {
1497         case e1000_82573:
1498         case e1000_82574:
1499         case e1000_82583:
1500                 if (hw->fc.requested_mode == e1000_fc_default)
1501                         hw->fc.requested_mode = e1000_fc_full;
1502                 break;
1503         default:
1504                 break;
1505         }
1506         return e1000_setup_link_generic(hw);
1507 }
1508
1509 /**
1510  *  e1000_setup_copper_link_82571 - Configure copper link settings
1511  *  @hw: pointer to the HW structure
1512  *
1513  *  Configures the link for auto-neg or forced speed and duplex.  Then we check
1514  *  for link, once link is established calls to configure collision distance
1515  *  and flow control are called.
1516  **/
1517 static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw)
1518 {
1519         u32 ctrl;
1520         s32 ret_val;
1521
1522         DEBUGFUNC("e1000_setup_copper_link_82571");
1523
1524         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1525         ctrl |= E1000_CTRL_SLU;
1526         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1527         E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1528
1529         switch (hw->phy.type) {
1530         case e1000_phy_m88:
1531         case e1000_phy_bm:
1532                 ret_val = e1000_copper_link_setup_m88(hw);
1533                 break;
1534         case e1000_phy_igp_2:
1535                 ret_val = e1000_copper_link_setup_igp(hw);
1536                 break;
1537         default:
1538                 ret_val = -E1000_ERR_PHY;
1539                 break;
1540         }
1541
1542         if (ret_val)
1543                 goto out;
1544
1545         ret_val = e1000_setup_copper_link_generic(hw);
1546
1547 out:
1548         return ret_val;
1549 }
1550
1551 /**
1552  *  e1000_setup_fiber_serdes_link_82571 - Setup link for fiber/serdes
1553  *  @hw: pointer to the HW structure
1554  *
1555  *  Configures collision distance and flow control for fiber and serdes links.
1556  *  Upon successful setup, poll for link.
1557  **/
1558 static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw)
1559 {
1560         DEBUGFUNC("e1000_setup_fiber_serdes_link_82571");
1561
1562         switch (hw->mac.type) {
1563         case e1000_82571:
1564         case e1000_82572:
1565                 /*
1566                  * If SerDes loopback mode is entered, there is no form
1567                  * of reset to take the adapter out of that mode.  So we
1568                  * have to explicitly take the adapter out of loopback
1569                  * mode.  This prevents drivers from twiddling their thumbs
1570                  * if another tool failed to take it out of loopback mode.
1571                  */
1572                 E1000_WRITE_REG(hw, E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1573                 break;
1574         default:
1575                 break;
1576         }
1577
1578         return e1000_setup_fiber_serdes_link_generic(hw);
1579 }
1580
1581 /**
1582  *  e1000_check_for_serdes_link_82571 - Check for link (Serdes)
1583  *  @hw: pointer to the HW structure
1584  *
1585  *  Reports the link state as up or down.
1586  *
1587  *  If autonegotiation is supported by the link partner, the link state is
1588  *  determined by the result of autonegotiation. This is the most likely case.
1589  *  If autonegotiation is not supported by the link partner, and the link
1590  *  has a valid signal, force the link up.
1591  *
1592  *  The link state is represented internally here by 4 states:
1593  *
1594  *  1) down
1595  *  2) autoneg_progress
1596  *  3) autoneg_complete (the link sucessfully autonegotiated)
1597  *  4) forced_up (the link has been forced up, it did not autonegotiate)
1598  *
1599  **/
1600 static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw)
1601 {
1602         struct e1000_mac_info *mac = &hw->mac;
1603         u32 rxcw;
1604         u32 ctrl;
1605         u32 status;
1606         u32 txcw;
1607         u32 i;
1608         s32 ret_val = E1000_SUCCESS;
1609
1610         DEBUGFUNC("e1000_check_for_serdes_link_82571");
1611
1612         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1613         status = E1000_READ_REG(hw, E1000_STATUS);
1614         rxcw = E1000_READ_REG(hw, E1000_RXCW);
1615
1616         if ((rxcw & E1000_RXCW_SYNCH) && !(rxcw & E1000_RXCW_IV)) {
1617
1618                 /* Receiver is synchronized with no invalid bits.  */
1619                 switch (mac->serdes_link_state) {
1620                 case e1000_serdes_link_autoneg_complete:
1621                         if (!(status & E1000_STATUS_LU)) {
1622                                 /*
1623                                  * We have lost link, retry autoneg before
1624                                  * reporting link failure
1625                                  */
1626                                 mac->serdes_link_state =
1627                                     e1000_serdes_link_autoneg_progress;
1628                                 mac->serdes_has_link = FALSE;
1629                                 DEBUGOUT("AN_UP     -> AN_PROG\n");
1630                         } else {
1631                                 mac->serdes_has_link = TRUE;
1632                         }
1633                         break;
1634
1635                 case e1000_serdes_link_forced_up:
1636                         /*
1637                          * If we are receiving /C/ ordered sets, re-enable
1638                          * auto-negotiation in the TXCW register and disable
1639                          * forced link in the Device Control register in an
1640                          * attempt to auto-negotiate with our link partner.
1641                          * If the partner code word is null, stop forcing
1642                          * and restart auto negotiation.
1643                          */
1644                         if ((rxcw & E1000_RXCW_C) || !(rxcw & E1000_RXCW_CW))  {
1645                                 /* Enable autoneg, and unforce link up */
1646                                 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
1647                                 E1000_WRITE_REG(hw, E1000_CTRL,
1648                                     (ctrl & ~E1000_CTRL_SLU));
1649                                 mac->serdes_link_state =
1650                                     e1000_serdes_link_autoneg_progress;
1651                                 mac->serdes_has_link = FALSE;
1652                                 DEBUGOUT("FORCED_UP -> AN_PROG\n");
1653                         } else {
1654                                 mac->serdes_has_link = TRUE;
1655                         }
1656                         break;
1657
1658                 case e1000_serdes_link_autoneg_progress:
1659                         if (rxcw & E1000_RXCW_C) {
1660                                 /*
1661                                  * We received /C/ ordered sets, meaning the
1662                                  * link partner has autonegotiated, and we can
1663                                  * trust the Link Up (LU) status bit.
1664                                  */
1665                                 if (status & E1000_STATUS_LU) {
1666                                         mac->serdes_link_state =
1667                                             e1000_serdes_link_autoneg_complete;
1668                                         DEBUGOUT("AN_PROG   -> AN_UP\n");
1669                                         mac->serdes_has_link = TRUE;
1670                                 } else {
1671                                         /* Autoneg completed, but failed. */
1672                                         mac->serdes_link_state =
1673                                             e1000_serdes_link_down;
1674                                         DEBUGOUT("AN_PROG   -> DOWN\n");
1675                                 }
1676                         } else {
1677                                 /*
1678                                  * The link partner did not autoneg.
1679                                  * Force link up and full duplex, and change
1680                                  * state to forced.
1681                                  */
1682                                 E1000_WRITE_REG(hw, E1000_TXCW,
1683                                 (mac->txcw & ~E1000_TXCW_ANE));
1684                                 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
1685                                 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1686
1687                                 /* Configure Flow Control after link up. */
1688                                 ret_val =
1689                                     e1000_config_fc_after_link_up_generic(hw);
1690                                 if (ret_val) {
1691                                         DEBUGOUT("Error config flow control\n");
1692                                         break;
1693                                 }
1694                                 mac->serdes_link_state =
1695                                 e1000_serdes_link_forced_up;
1696                                 mac->serdes_has_link = TRUE;
1697                                 DEBUGOUT("AN_PROG   -> FORCED_UP\n");
1698                         }
1699                         break;
1700
1701                 case e1000_serdes_link_down:
1702                 default:
1703                         /*
1704                          * The link was down but the receiver has now gained
1705                          * valid sync, so lets see if we can bring the link
1706                          * up.
1707                          */
1708                         E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
1709                         E1000_WRITE_REG(hw, E1000_CTRL,
1710                             (ctrl & ~E1000_CTRL_SLU));
1711                         mac->serdes_link_state =
1712                             e1000_serdes_link_autoneg_progress;
1713                         mac->serdes_has_link = FALSE;
1714                         DEBUGOUT("DOWN      -> AN_PROG\n");
1715                         break;
1716                 }
1717         } else {
1718                 if (!(rxcw & E1000_RXCW_SYNCH)) {
1719                         mac->serdes_has_link = FALSE;
1720                         mac->serdes_link_state = e1000_serdes_link_down;
1721                         DEBUGOUT("ANYSTATE  -> DOWN\n");
1722                 } else {
1723                         /*
1724                          * Check several times, if Sync and Config
1725                          * both are consistently 1 then simply ignore
1726                          * the Invalid bit and restart Autoneg
1727                          */
1728                         for (i = 0; i < AN_RETRY_COUNT; i++) {
1729                                 usec_delay(10);
1730                                 rxcw = E1000_READ_REG(hw, E1000_RXCW);
1731                                 if ((rxcw & E1000_RXCW_IV) &&
1732                                     !((rxcw & E1000_RXCW_SYNCH) &&
1733                                       (rxcw & E1000_RXCW_C))) {
1734                                         mac->serdes_has_link = FALSE;
1735                                         mac->serdes_link_state =
1736                                             e1000_serdes_link_down;
1737                                         DEBUGOUT("ANYSTATE  -> DOWN\n");
1738                                         break;
1739                                 }
1740                         }
1741
1742                         if (i == AN_RETRY_COUNT) {
1743                                 txcw = E1000_READ_REG(hw, E1000_TXCW);
1744                                 txcw |= E1000_TXCW_ANE;
1745                                 E1000_WRITE_REG(hw, E1000_TXCW, txcw);
1746                                 mac->serdes_link_state =
1747                                     e1000_serdes_link_autoneg_progress;
1748                                 mac->serdes_has_link = FALSE;
1749                                 DEBUGOUT("ANYSTATE  -> AN_PROG\n");
1750                         }
1751                 }
1752         }
1753
1754         return ret_val;
1755 }
1756
1757 /**
1758  *  e1000_valid_led_default_82571 - Verify a valid default LED config
1759  *  @hw: pointer to the HW structure
1760  *  @data: pointer to the NVM (EEPROM)
1761  *
1762  *  Read the EEPROM for the current default LED configuration.  If the
1763  *  LED configuration is not valid, set to a valid LED configuration.
1764  **/
1765 static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data)
1766 {
1767         s32 ret_val;
1768
1769         DEBUGFUNC("e1000_valid_led_default_82571");
1770
1771         ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1772         if (ret_val) {
1773                 DEBUGOUT("NVM Read Error\n");
1774                 goto out;
1775         }
1776
1777         switch (hw->mac.type) {
1778         case e1000_82573:
1779         case e1000_82574:
1780         case e1000_82583:
1781                 if (*data == ID_LED_RESERVED_F746)
1782                         *data = ID_LED_DEFAULT_82573;
1783                 break;
1784         default:
1785                 if (*data == ID_LED_RESERVED_0000 ||
1786                     *data == ID_LED_RESERVED_FFFF)
1787                         *data = ID_LED_DEFAULT;
1788                 break;
1789         }
1790
1791 out:
1792         return ret_val;
1793 }
1794
1795 /**
1796  *  e1000_get_laa_state_82571 - Get locally administered address state
1797  *  @hw: pointer to the HW structure
1798  *
1799  *  Retrieve and return the current locally administered address state.
1800  **/
1801 bool e1000_get_laa_state_82571(struct e1000_hw *hw)
1802 {
1803         DEBUGFUNC("e1000_get_laa_state_82571");
1804
1805         if (hw->mac.type != e1000_82571)
1806                 return FALSE;
1807
1808         return hw->dev_spec._82571.laa_is_present;
1809 }
1810
1811 /**
1812  *  e1000_set_laa_state_82571 - Set locally administered address state
1813  *  @hw: pointer to the HW structure
1814  *  @state: enable/disable locally administered address
1815  *
1816  *  Enable/Disable the current locally administered address state.
1817  **/
1818 void e1000_set_laa_state_82571(struct e1000_hw *hw, bool state)
1819 {
1820         DEBUGFUNC("e1000_set_laa_state_82571");
1821
1822         if (hw->mac.type != e1000_82571)
1823                 return;
1824
1825         hw->dev_spec._82571.laa_is_present = state;
1826
1827         /* If workaround is activated... */
1828         if (state)
1829                 /*
1830                  * Hold a copy of the LAA in RAR[14] This is done so that
1831                  * between the time RAR[0] gets clobbered and the time it
1832                  * gets fixed, the actual LAA is in one of the RARs and no
1833                  * incoming packets directed to this port are dropped.
1834                  * Eventually the LAA will be in RAR[0] and RAR[14].
1835                  */
1836                 e1000_rar_set_generic(hw, hw->mac.addr,
1837                                       hw->mac.rar_entry_count - 1);
1838         return;
1839 }
1840
1841 /**
1842  *  e1000_fix_nvm_checksum_82571 - Fix EEPROM checksum
1843  *  @hw: pointer to the HW structure
1844  *
1845  *  Verifies that the EEPROM has completed the update.  After updating the
1846  *  EEPROM, we need to check bit 15 in work 0x23 for the checksum fix.  If
1847  *  the checksum fix is not implemented, we need to set the bit and update
1848  *  the checksum.  Otherwise, if bit 15 is set and the checksum is incorrect,
1849  *  we need to return bad checksum.
1850  **/
1851 static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw)
1852 {
1853         struct e1000_nvm_info *nvm = &hw->nvm;
1854         s32 ret_val = E1000_SUCCESS;
1855         u16 data;
1856
1857         DEBUGFUNC("e1000_fix_nvm_checksum_82571");
1858
1859         if (nvm->type != e1000_nvm_flash_hw)
1860                 goto out;
1861
1862         /*
1863          * Check bit 4 of word 10h.  If it is 0, firmware is done updating
1864          * 10h-12h.  Checksum may need to be fixed.
1865          */
1866         ret_val = nvm->ops.read(hw, 0x10, 1, &data);
1867         if (ret_val)
1868                 goto out;
1869
1870         if (!(data & 0x10)) {
1871                 /*
1872                  * Read 0x23 and check bit 15.  This bit is a 1
1873                  * when the checksum has already been fixed.  If
1874                  * the checksum is still wrong and this bit is a
1875                  * 1, we need to return bad checksum.  Otherwise,
1876                  * we need to set this bit to a 1 and update the
1877                  * checksum.
1878                  */
1879                 ret_val = nvm->ops.read(hw, 0x23, 1, &data);
1880                 if (ret_val)
1881                         goto out;
1882
1883                 if (!(data & 0x8000)) {
1884                         data |= 0x8000;
1885                         ret_val = nvm->ops.write(hw, 0x23, 1, &data);
1886                         if (ret_val)
1887                                 goto out;
1888                         ret_val = nvm->ops.update(hw);
1889                 }
1890         }
1891
1892 out:
1893         return ret_val;
1894 }
1895
1896
1897 /**
1898  *  e1000_read_mac_addr_82571 - Read device MAC address
1899  *  @hw: pointer to the HW structure
1900  **/
1901 static s32 e1000_read_mac_addr_82571(struct e1000_hw *hw)
1902 {
1903         s32 ret_val = E1000_SUCCESS;
1904
1905         DEBUGFUNC("e1000_read_mac_addr_82571");
1906
1907         if (hw->mac.type == e1000_82571) {
1908                 /*
1909                  * If there's an alternate MAC address place it in RAR0
1910                  * so that it will override the Si installed default perm
1911                  * address.
1912                  */
1913                 ret_val = e1000_check_alt_mac_addr_generic(hw);
1914                 if (ret_val)
1915                         goto out;
1916         }
1917
1918         ret_val = e1000_read_mac_addr_generic(hw);
1919
1920 out:
1921         return ret_val;
1922 }
1923
1924 /**
1925  * e1000_power_down_phy_copper_82571 - Remove link during PHY power down
1926  * @hw: pointer to the HW structure
1927  *
1928  * In the case of a PHY power down to save power, or to turn off link during a
1929  * driver unload, or wake on lan is not enabled, remove the link.
1930  **/
1931 static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw)
1932 {
1933         struct e1000_phy_info *phy = &hw->phy;
1934         struct e1000_mac_info *mac = &hw->mac;
1935
1936         if (!(phy->ops.check_reset_block))
1937                 return;
1938
1939         /* If the management interface is not enabled, then power down */
1940         if (!(mac->ops.check_mng_mode(hw) || phy->ops.check_reset_block(hw)))
1941                 e1000_power_down_phy_copper(hw);
1942
1943         return;
1944 }
1945
1946 /**
1947  *  e1000_clear_hw_cntrs_82571 - Clear device specific hardware counters
1948  *  @hw: pointer to the HW structure
1949  *
1950  *  Clears the hardware counters by reading the counter registers.
1951  **/
1952 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw)
1953 {
1954         DEBUGFUNC("e1000_clear_hw_cntrs_82571");
1955
1956         e1000_clear_hw_cntrs_base_generic(hw);
1957
1958         E1000_READ_REG(hw, E1000_PRC64);
1959         E1000_READ_REG(hw, E1000_PRC127);
1960         E1000_READ_REG(hw, E1000_PRC255);
1961         E1000_READ_REG(hw, E1000_PRC511);
1962         E1000_READ_REG(hw, E1000_PRC1023);
1963         E1000_READ_REG(hw, E1000_PRC1522);
1964         E1000_READ_REG(hw, E1000_PTC64);
1965         E1000_READ_REG(hw, E1000_PTC127);
1966         E1000_READ_REG(hw, E1000_PTC255);
1967         E1000_READ_REG(hw, E1000_PTC511);
1968         E1000_READ_REG(hw, E1000_PTC1023);
1969         E1000_READ_REG(hw, E1000_PTC1522);
1970
1971         E1000_READ_REG(hw, E1000_ALGNERRC);
1972         E1000_READ_REG(hw, E1000_RXERRC);
1973         E1000_READ_REG(hw, E1000_TNCRS);
1974         E1000_READ_REG(hw, E1000_CEXTERR);
1975         E1000_READ_REG(hw, E1000_TSCTC);
1976         E1000_READ_REG(hw, E1000_TSCTFC);
1977
1978         E1000_READ_REG(hw, E1000_MGTPRC);
1979         E1000_READ_REG(hw, E1000_MGTPDC);
1980         E1000_READ_REG(hw, E1000_MGTPTC);
1981
1982         E1000_READ_REG(hw, E1000_IAC);
1983         E1000_READ_REG(hw, E1000_ICRXOC);
1984
1985         E1000_READ_REG(hw, E1000_ICRXPTC);
1986         E1000_READ_REG(hw, E1000_ICRXATC);
1987         E1000_READ_REG(hw, E1000_ICTXPTC);
1988         E1000_READ_REG(hw, E1000_ICTXATC);
1989         E1000_READ_REG(hw, E1000_ICTXQEC);
1990         E1000_READ_REG(hw, E1000_ICTXQMTC);
1991         E1000_READ_REG(hw, E1000_ICRXDMTC);
1992 }