1 /* $OpenBSD: if_txp.c,v 1.48 2001/06/27 06:34:50 kjc Exp $ */
2 /* $FreeBSD: src/sys/dev/txp/if_txp.c,v 1.4.2.4 2001/12/14 19:50:43 jlemon Exp $ */
3 /* $DragonFly: src/sys/dev/netif/txp/if_txp.c,v 1.28 2005/06/20 13:51:54 joerg Exp $ */
7 * Jason L. Wright <jason@thought.net>, Theo de Raadt, and
8 * Aaron Campbell <aaron@monkey.org>. All rights reserved.
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 * must display the following acknowledgement:
20 * This product includes software developed by Jason L. Wright,
21 * Theo de Raadt and Aaron Campbell.
22 * 4. Neither the name of the author nor the names of any co-contributors
23 * may be used to endorse or promote products derived from this software
24 * without specific prior written permission.
26 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR
27 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
28 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
29 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
36 * THE POSSIBILITY OF SUCH DAMAGE.
40 * Driver for 3c990 (Typhoon) Ethernet ASIC
43 #include <sys/param.h>
44 #include <sys/systm.h>
45 #include <sys/sockio.h>
47 #include <sys/malloc.h>
48 #include <sys/kernel.h>
49 #include <sys/socket.h>
50 #include <sys/thread2.h>
53 #include <net/ifq_var.h>
54 #include <net/if_arp.h>
55 #include <net/ethernet.h>
56 #include <net/if_dl.h>
57 #include <net/if_types.h>
58 #include <net/vlan/if_vlan_var.h>
60 #include <netinet/in.h>
61 #include <netinet/in_systm.h>
62 #include <netinet/in_var.h>
63 #include <netinet/ip.h>
64 #include <netinet/if_ether.h>
65 #include <sys/in_cksum.h>
67 #include <net/if_media.h>
71 #include <vm/vm.h> /* for vtophys */
72 #include <vm/pmap.h> /* for vtophys */
73 #include <machine/bus_pio.h>
74 #include <machine/bus_memio.h>
75 #include <machine/bus.h>
76 #include <machine/resource.h>
80 #include "../mii_layer/mii.h"
81 #include "../mii_layer/miivar.h"
82 #include <bus/pci/pcireg.h>
83 #include <bus/pci/pcivar.h>
85 #define TXP_USEIOSPACE
86 #define __STRICT_ALIGNMENT
88 #include "if_txpreg.h"
92 * Various supported device vendors/types and their names.
94 static struct txp_type txp_devs[] = {
95 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990_TX_95,
96 "3Com 3cR990-TX-95 Etherlink with 3XP Processor" },
97 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990_TX_97,
98 "3Com 3cR990-TX-97 Etherlink with 3XP Processor" },
99 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990B_TXM,
100 "3Com 3cR990B-TXM Etherlink with 3XP Processor" },
101 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990_SRV_95,
102 "3Com 3cR990-SRV-95 Etherlink Server with 3XP Processor" },
103 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990_SRV_97,
104 "3Com 3cR990-SRV-97 Etherlink Server with 3XP Processor" },
105 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990B_SRV,
106 "3Com 3cR990B-SRV Etherlink Server with 3XP Processor" },
110 static int txp_probe (device_t);
111 static int txp_attach (device_t);
112 static int txp_detach (device_t);
113 static void txp_intr (void *);
114 static void txp_tick (void *);
115 static int txp_shutdown (device_t);
116 static int txp_ioctl (struct ifnet *, u_long, caddr_t, struct ucred *);
117 static void txp_start (struct ifnet *);
118 static void txp_stop (struct txp_softc *);
119 static void txp_init (void *);
120 static void txp_watchdog (struct ifnet *);
122 static void txp_release_resources (device_t);
123 static int txp_chip_init (struct txp_softc *);
124 static int txp_reset_adapter (struct txp_softc *);
125 static int txp_download_fw (struct txp_softc *);
126 static int txp_download_fw_wait (struct txp_softc *);
127 static int txp_download_fw_section (struct txp_softc *,
128 struct txp_fw_section_header *, int);
129 static int txp_alloc_rings (struct txp_softc *);
130 static int txp_rxring_fill (struct txp_softc *);
131 static void txp_rxring_empty (struct txp_softc *);
132 static void txp_set_filter (struct txp_softc *);
134 static int txp_cmd_desc_numfree (struct txp_softc *);
135 static int txp_command (struct txp_softc *, u_int16_t, u_int16_t, u_int32_t,
136 u_int32_t, u_int16_t *, u_int32_t *, u_int32_t *, int);
137 static int txp_command2 (struct txp_softc *, u_int16_t, u_int16_t,
138 u_int32_t, u_int32_t, struct txp_ext_desc *, u_int8_t,
139 struct txp_rsp_desc **, int);
140 static int txp_response (struct txp_softc *, u_int32_t, u_int16_t, u_int16_t,
141 struct txp_rsp_desc **);
142 static void txp_rsp_fixup (struct txp_softc *, struct txp_rsp_desc *,
143 struct txp_rsp_desc *);
144 static void txp_capabilities (struct txp_softc *);
146 static void txp_ifmedia_sts (struct ifnet *, struct ifmediareq *);
147 static int txp_ifmedia_upd (struct ifnet *);
149 static void txp_show_descriptor (void *);
151 static void txp_tx_reclaim (struct txp_softc *, struct txp_tx_ring *);
152 static void txp_rxbuf_reclaim (struct txp_softc *);
153 static void txp_rx_reclaim (struct txp_softc *, struct txp_rx_ring *);
155 #ifdef TXP_USEIOSPACE
156 #define TXP_RES SYS_RES_IOPORT
157 #define TXP_RID TXP_PCI_LOIO
159 #define TXP_RES SYS_RES_MEMORY
160 #define TXP_RID TXP_PCI_LOMEM
163 static device_method_t txp_methods[] = {
164 /* Device interface */
165 DEVMETHOD(device_probe, txp_probe),
166 DEVMETHOD(device_attach, txp_attach),
167 DEVMETHOD(device_detach, txp_detach),
168 DEVMETHOD(device_shutdown, txp_shutdown),
172 static driver_t txp_driver = {
175 sizeof(struct txp_softc)
178 static devclass_t txp_devclass;
180 DECLARE_DUMMY_MODULE(if_txp);
181 DRIVER_MODULE(if_txp, pci, txp_driver, txp_devclass, 0, 0);
190 vid = pci_get_vendor(dev);
191 did = pci_get_device(dev);
193 for (t = txp_devs; t->txp_name != NULL; ++t) {
194 if ((vid == t->txp_vid) && (did == t->txp_did)) {
195 device_set_desc(dev, t->txp_name);
207 struct txp_softc *sc;
211 uint8_t enaddr[ETHER_ADDR_LEN];
214 sc = device_get_softc(dev);
215 callout_init(&sc->txp_stat_timer);
217 ifp = &sc->sc_arpcom.ac_if;
218 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
220 pci_enable_busmaster(dev);
223 sc->sc_res = bus_alloc_resource_any(dev, TXP_RES, &rid, RF_ACTIVE);
225 if (sc->sc_res == NULL) {
226 device_printf(dev, "couldn't map ports/memory\n");
230 sc->sc_bt = rman_get_bustag(sc->sc_res);
231 sc->sc_bh = rman_get_bushandle(sc->sc_res);
233 /* Allocate interrupt */
235 sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
236 RF_SHAREABLE | RF_ACTIVE);
238 if (sc->sc_irq == NULL) {
239 device_printf(dev, "couldn't map interrupt\n");
244 error = bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_NET,
245 txp_intr, sc, &sc->sc_intrhand, NULL);
248 device_printf(dev, "couldn't set up irq\n");
252 if (txp_chip_init(sc)) {
257 sc->sc_fwbuf = contigmalloc(32768, M_DEVBUF,
258 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
259 error = txp_download_fw(sc);
260 contigfree(sc->sc_fwbuf, 32768, M_DEVBUF);
266 sc->sc_ldata = contigmalloc(sizeof(struct txp_ldata), M_DEVBUF,
267 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
268 bzero(sc->sc_ldata, sizeof(struct txp_ldata));
270 if (txp_alloc_rings(sc)) {
275 if (txp_command(sc, TXP_CMD_MAX_PKT_SIZE_WRITE, TXP_MAX_PKTLEN, 0, 0,
276 NULL, NULL, NULL, 1)) {
281 if (txp_command(sc, TXP_CMD_STATION_ADDRESS_READ, 0, 0, 0,
282 &p1, &p2, NULL, 1)) {
289 enaddr[0] = ((uint8_t *)&p1)[1];
290 enaddr[1] = ((uint8_t *)&p1)[0];
291 enaddr[2] = ((uint8_t *)&p2)[3];
292 enaddr[3] = ((uint8_t *)&p2)[2];
293 enaddr[4] = ((uint8_t *)&p2)[1];
294 enaddr[5] = ((uint8_t *)&p2)[0];
296 ifmedia_init(&sc->sc_ifmedia, 0, txp_ifmedia_upd, txp_ifmedia_sts);
297 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
298 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL);
299 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
300 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL);
301 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX|IFM_HDX, 0, NULL);
302 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL);
303 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
305 sc->sc_xcvr = TXP_XCVR_AUTO;
306 txp_command(sc, TXP_CMD_XCVR_SELECT, TXP_XCVR_AUTO, 0, 0,
307 NULL, NULL, NULL, 0);
308 ifmedia_set(&sc->sc_ifmedia, IFM_ETHER|IFM_AUTO);
311 ifp->if_mtu = ETHERMTU;
312 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
313 ifp->if_ioctl = txp_ioctl;
314 ifp->if_start = txp_start;
315 ifp->if_watchdog = txp_watchdog;
316 ifp->if_init = txp_init;
317 ifp->if_baudrate = 100000000;
318 ifq_set_maxlen(&ifp->if_snd, TX_ENTRIES);
319 ifq_set_ready(&ifp->if_snd);
320 ifp->if_hwassist = 0;
321 txp_capabilities(sc);
324 * Attach us everywhere
326 ether_ifattach(ifp, enaddr);
330 txp_release_resources(dev);
338 struct txp_softc *sc;
342 sc = device_get_softc(dev);
343 ifp = &sc->sc_arpcom.ac_if;
348 ifmedia_removeall(&sc->sc_ifmedia);
351 for (i = 0; i < RXBUF_ENTRIES; i++)
352 free(sc->sc_rxbufs[i].rb_sd, M_DEVBUF);
354 txp_release_resources(dev);
360 txp_release_resources(device_t dev)
362 struct txp_softc *sc;
364 sc = device_get_softc(dev);
366 if (sc->sc_intrhand != NULL)
367 bus_teardown_intr(dev, sc->sc_irq, sc->sc_intrhand);
369 if (sc->sc_irq != NULL)
370 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq);
372 if (sc->sc_res != NULL)
373 bus_release_resource(dev, TXP_RES, TXP_RID, sc->sc_res);
375 if (sc->sc_ldata != NULL)
376 contigfree(sc->sc_ldata, sizeof(struct txp_ldata), M_DEVBUF);
383 struct txp_softc *sc;
385 /* disable interrupts */
386 WRITE_REG(sc, TXP_IER, 0);
387 WRITE_REG(sc, TXP_IMR,
388 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT |
389 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 |
392 /* ack all interrupts */
393 WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH |
394 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 |
395 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT |
396 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 |
397 TXP_INT_A2H_3 | TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0);
399 if (txp_reset_adapter(sc))
402 /* disable interrupts */
403 WRITE_REG(sc, TXP_IER, 0);
404 WRITE_REG(sc, TXP_IMR,
405 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT |
406 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 |
409 /* ack all interrupts */
410 WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH |
411 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 |
412 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT |
413 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 |
414 TXP_INT_A2H_3 | TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0);
420 txp_reset_adapter(sc)
421 struct txp_softc *sc;
426 WRITE_REG(sc, TXP_SRR, TXP_SRR_ALL);
428 WRITE_REG(sc, TXP_SRR, 0);
430 /* Should wait max 6 seconds */
431 for (i = 0; i < 6000; i++) {
432 r = READ_REG(sc, TXP_A2H_0);
433 if (r == STAT_WAITING_FOR_HOST_REQUEST)
438 if (r != STAT_WAITING_FOR_HOST_REQUEST) {
439 if_printf(&sc->sc_arpcom.ac_if, "reset hung\n");
448 struct txp_softc *sc;
450 struct txp_fw_file_header *fileheader;
451 struct txp_fw_section_header *secthead;
453 u_int32_t r, i, ier, imr;
455 ier = READ_REG(sc, TXP_IER);
456 WRITE_REG(sc, TXP_IER, ier | TXP_INT_A2H_0);
458 imr = READ_REG(sc, TXP_IMR);
459 WRITE_REG(sc, TXP_IMR, imr | TXP_INT_A2H_0);
461 for (i = 0; i < 10000; i++) {
462 r = READ_REG(sc, TXP_A2H_0);
463 if (r == STAT_WAITING_FOR_HOST_REQUEST)
467 if (r != STAT_WAITING_FOR_HOST_REQUEST) {
468 if_printf(&sc->sc_arpcom.ac_if,
469 "not waiting for host request\n");
474 WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0);
476 fileheader = (struct txp_fw_file_header *)tc990image;
477 if (bcmp("TYPHOON", fileheader->magicid, sizeof(fileheader->magicid))) {
478 if_printf(&sc->sc_arpcom.ac_if, "fw invalid magic\n");
482 /* Tell boot firmware to get ready for image */
483 WRITE_REG(sc, TXP_H2A_1, fileheader->addr);
484 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_RUNTIME_IMAGE);
486 if (txp_download_fw_wait(sc)) {
487 if_printf(&sc->sc_arpcom.ac_if, "fw wait failed, initial\n");
491 secthead = (struct txp_fw_section_header *)(((u_int8_t *)tc990image) +
492 sizeof(struct txp_fw_file_header));
494 for (sect = 0; sect < fileheader->nsections; sect++) {
495 if (txp_download_fw_section(sc, secthead, sect))
497 secthead = (struct txp_fw_section_header *)
498 (((u_int8_t *)secthead) + secthead->nbytes +
502 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_DOWNLOAD_COMPLETE);
504 for (i = 0; i < 10000; i++) {
505 r = READ_REG(sc, TXP_A2H_0);
506 if (r == STAT_WAITING_FOR_BOOT)
510 if (r != STAT_WAITING_FOR_BOOT) {
511 if_printf(&sc->sc_arpcom.ac_if, "not waiting for boot\n");
515 WRITE_REG(sc, TXP_IER, ier);
516 WRITE_REG(sc, TXP_IMR, imr);
522 txp_download_fw_wait(sc)
523 struct txp_softc *sc;
527 for (i = 0; i < 10000; i++) {
528 r = READ_REG(sc, TXP_ISR);
529 if (r & TXP_INT_A2H_0)
534 if (!(r & TXP_INT_A2H_0)) {
535 if_printf(&sc->sc_arpcom.ac_if, "fw wait failed comm0\n");
539 WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0);
541 r = READ_REG(sc, TXP_A2H_0);
542 if (r != STAT_WAITING_FOR_SEGMENT) {
543 if_printf(&sc->sc_arpcom.ac_if, "fw not waiting for segment\n");
550 txp_download_fw_section(sc, sect, sectnum)
551 struct txp_softc *sc;
552 struct txp_fw_section_header *sect;
560 /* Skip zero length sections */
561 if (sect->nbytes == 0)
564 /* Make sure we aren't past the end of the image */
565 rseg = ((u_int8_t *)sect) - ((u_int8_t *)tc990image);
566 if (rseg >= sizeof(tc990image)) {
567 if_printf(&sc->sc_arpcom.ac_if, "fw invalid section address, "
568 "section %d\n", sectnum);
572 /* Make sure this section doesn't go past the end */
573 rseg += sect->nbytes;
574 if (rseg >= sizeof(tc990image)) {
575 if_printf(&sc->sc_arpcom.ac_if, "fw truncated section %d\n",
580 bcopy(((u_int8_t *)sect) + sizeof(*sect), sc->sc_fwbuf, sect->nbytes);
581 dma = vtophys(sc->sc_fwbuf);
584 * dummy up mbuf and verify section checksum
587 m.m_next = m.m_nextpkt = NULL;
588 m.m_len = sect->nbytes;
589 m.m_data = sc->sc_fwbuf;
591 csum = in_cksum(&m, sect->nbytes);
592 if (csum != sect->cksum) {
593 if_printf(&sc->sc_arpcom.ac_if, "fw section %d, bad "
594 "cksum (expected 0x%x got 0x%x)\n",
595 sectnum, sect->cksum, csum);
600 WRITE_REG(sc, TXP_H2A_1, sect->nbytes);
601 WRITE_REG(sc, TXP_H2A_2, sect->cksum);
602 WRITE_REG(sc, TXP_H2A_3, sect->addr);
603 WRITE_REG(sc, TXP_H2A_4, 0);
604 WRITE_REG(sc, TXP_H2A_5, dma & 0xffffffff);
605 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_SEGMENT_AVAILABLE);
607 if (txp_download_fw_wait(sc)) {
608 if_printf(&sc->sc_arpcom.ac_if, "fw wait failed, "
609 "section %d\n", sectnum);
621 struct txp_softc *sc = vsc;
622 struct txp_hostvar *hv = sc->sc_hostvar;
625 /* mask all interrupts */
626 WRITE_REG(sc, TXP_IMR, TXP_INT_RESERVED | TXP_INT_SELF |
627 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 |
628 TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0 |
629 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 |
630 TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | TXP_INT_LATCH);
632 isr = READ_REG(sc, TXP_ISR);
634 WRITE_REG(sc, TXP_ISR, isr);
636 if ((*sc->sc_rxhir.r_roff) != (*sc->sc_rxhir.r_woff))
637 txp_rx_reclaim(sc, &sc->sc_rxhir);
638 if ((*sc->sc_rxlor.r_roff) != (*sc->sc_rxlor.r_woff))
639 txp_rx_reclaim(sc, &sc->sc_rxlor);
641 if (hv->hv_rx_buf_write_idx == hv->hv_rx_buf_read_idx)
642 txp_rxbuf_reclaim(sc);
644 if (sc->sc_txhir.r_cnt && (sc->sc_txhir.r_cons !=
645 TXP_OFFSET2IDX(*(sc->sc_txhir.r_off))))
646 txp_tx_reclaim(sc, &sc->sc_txhir);
648 if (sc->sc_txlor.r_cnt && (sc->sc_txlor.r_cons !=
649 TXP_OFFSET2IDX(*(sc->sc_txlor.r_off))))
650 txp_tx_reclaim(sc, &sc->sc_txlor);
652 isr = READ_REG(sc, TXP_ISR);
655 /* unmask all interrupts */
656 WRITE_REG(sc, TXP_IMR, TXP_INT_A2H_3);
658 txp_start(&sc->sc_arpcom.ac_if);
664 txp_rx_reclaim(sc, r)
665 struct txp_softc *sc;
666 struct txp_rx_ring *r;
668 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
669 struct txp_rx_desc *rxd;
671 struct txp_swdesc *sd = NULL;
672 u_int32_t roff, woff;
676 rxd = r->r_desc + (roff / sizeof(struct txp_rx_desc));
678 while (roff != woff) {
680 if (rxd->rx_flags & RX_FLAGS_ERROR) {
681 if_printf(ifp, "error 0x%x\n", rxd->rx_stat);
686 /* retrieve stashed pointer */
692 m->m_pkthdr.len = m->m_len = rxd->rx_len;
694 #ifdef __STRICT_ALIGNMENT
697 * XXX Nice chip, except it won't accept "off by 2"
698 * buffers, so we're force to copy. Supposedly
699 * this will be fixed in a newer firmware rev
700 * and this will be temporary.
704 MGETHDR(mnew, MB_DONTWAIT, MT_DATA);
709 if (m->m_len > (MHLEN - 2)) {
710 MCLGET(mnew, MB_DONTWAIT);
711 if (!(mnew->m_flags & M_EXT)) {
717 mnew->m_pkthdr.rcvif = ifp;
719 mnew->m_pkthdr.len = mnew->m_len = m->m_len;
720 m_copydata(m, 0, m->m_pkthdr.len, mtod(mnew, caddr_t));
726 if (rxd->rx_stat & RX_STAT_IPCKSUMBAD)
727 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
728 else if (rxd->rx_stat & RX_STAT_IPCKSUMGOOD)
729 m->m_pkthdr.csum_flags |=
730 CSUM_IP_CHECKED|CSUM_IP_VALID;
732 if ((rxd->rx_stat & RX_STAT_TCPCKSUMGOOD) ||
733 (rxd->rx_stat & RX_STAT_UDPCKSUMGOOD)) {
734 m->m_pkthdr.csum_flags |=
735 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
736 m->m_pkthdr.csum_data = 0xffff;
739 if (rxd->rx_stat & RX_STAT_VLAN)
740 VLAN_INPUT_TAG(m, htons(rxd->rx_vlan >> 16));
742 (*ifp->if_input)(ifp, m);
746 roff += sizeof(struct txp_rx_desc);
747 if (roff == (RX_ENTRIES * sizeof(struct txp_rx_desc))) {
761 txp_rxbuf_reclaim(sc)
762 struct txp_softc *sc;
764 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
765 struct txp_hostvar *hv = sc->sc_hostvar;
766 struct txp_rxbuf_desc *rbd;
767 struct txp_swdesc *sd;
770 if (!(ifp->if_flags & IFF_RUNNING))
773 i = sc->sc_rxbufprod;
774 rbd = sc->sc_rxbufs + i;
778 if (sd->sd_mbuf != NULL)
781 MGETHDR(sd->sd_mbuf, MB_DONTWAIT, MT_DATA);
782 if (sd->sd_mbuf == NULL)
785 MCLGET(sd->sd_mbuf, MB_DONTWAIT);
786 if ((sd->sd_mbuf->m_flags & M_EXT) == 0)
788 sd->sd_mbuf->m_pkthdr.rcvif = ifp;
789 sd->sd_mbuf->m_pkthdr.len = sd->sd_mbuf->m_len = MCLBYTES;
791 rbd->rb_paddrlo = vtophys(mtod(sd->sd_mbuf, vm_offset_t))
795 hv->hv_rx_buf_write_idx = TXP_IDX2OFFSET(i);
797 if (++i == RXBUF_ENTRIES) {
804 sc->sc_rxbufprod = i;
809 m_freem(sd->sd_mbuf);
815 * Reclaim mbufs and entries from a transmit ring.
818 txp_tx_reclaim(sc, r)
819 struct txp_softc *sc;
820 struct txp_tx_ring *r;
822 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
823 u_int32_t idx = TXP_OFFSET2IDX(*(r->r_off));
824 u_int32_t cons = r->r_cons, cnt = r->r_cnt;
825 struct txp_tx_desc *txd = r->r_desc + cons;
826 struct txp_swdesc *sd = sc->sc_txd + cons;
829 while (cons != idx) {
833 if ((txd->tx_flags & TX_FLAGS_TYPE_M) ==
834 TX_FLAGS_TYPE_DATA) {
843 ifp->if_flags &= ~IFF_OACTIVE;
845 if (++cons == TX_ENTRIES) {
867 struct txp_softc *sc;
869 sc = device_get_softc(dev);
871 /* mask all interrupts */
872 WRITE_REG(sc, TXP_IMR,
873 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT |
874 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 |
877 txp_command(sc, TXP_CMD_TX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 0);
878 txp_command(sc, TXP_CMD_RX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 0);
879 txp_command(sc, TXP_CMD_HALT, 0, 0, 0, NULL, NULL, NULL, 0);
886 struct txp_softc *sc;
888 struct txp_boot_record *boot;
889 struct txp_ldata *ld;
894 boot = &ld->txp_boot;
900 bzero(&ld->txp_hostvar, sizeof(struct txp_hostvar));
901 boot->br_hostvar_lo = vtophys(&ld->txp_hostvar);
902 boot->br_hostvar_hi = 0;
903 sc->sc_hostvar = (struct txp_hostvar *)&ld->txp_hostvar;
905 /* hi priority tx ring */
906 boot->br_txhipri_lo = vtophys(&ld->txp_txhiring);;
907 boot->br_txhipri_hi = 0;
908 boot->br_txhipri_siz = TX_ENTRIES * sizeof(struct txp_tx_desc);
909 sc->sc_txhir.r_reg = TXP_H2A_1;
910 sc->sc_txhir.r_desc = (struct txp_tx_desc *)&ld->txp_txhiring;
911 sc->sc_txhir.r_cons = sc->sc_txhir.r_prod = sc->sc_txhir.r_cnt = 0;
912 sc->sc_txhir.r_off = &sc->sc_hostvar->hv_tx_hi_desc_read_idx;
914 /* lo priority tx ring */
915 boot->br_txlopri_lo = vtophys(&ld->txp_txloring);
916 boot->br_txlopri_hi = 0;
917 boot->br_txlopri_siz = TX_ENTRIES * sizeof(struct txp_tx_desc);
918 sc->sc_txlor.r_reg = TXP_H2A_3;
919 sc->sc_txlor.r_desc = (struct txp_tx_desc *)&ld->txp_txloring;
920 sc->sc_txlor.r_cons = sc->sc_txlor.r_prod = sc->sc_txlor.r_cnt = 0;
921 sc->sc_txlor.r_off = &sc->sc_hostvar->hv_tx_lo_desc_read_idx;
923 /* high priority rx ring */
924 boot->br_rxhipri_lo = vtophys(&ld->txp_rxhiring);
925 boot->br_rxhipri_hi = 0;
926 boot->br_rxhipri_siz = RX_ENTRIES * sizeof(struct txp_rx_desc);
927 sc->sc_rxhir.r_desc = (struct txp_rx_desc *)&ld->txp_rxhiring;
928 sc->sc_rxhir.r_roff = &sc->sc_hostvar->hv_rx_hi_read_idx;
929 sc->sc_rxhir.r_woff = &sc->sc_hostvar->hv_rx_hi_write_idx;
931 /* low priority rx ring */
932 boot->br_rxlopri_lo = vtophys(&ld->txp_rxloring);
933 boot->br_rxlopri_hi = 0;
934 boot->br_rxlopri_siz = RX_ENTRIES * sizeof(struct txp_rx_desc);
935 sc->sc_rxlor.r_desc = (struct txp_rx_desc *)&ld->txp_rxloring;
936 sc->sc_rxlor.r_roff = &sc->sc_hostvar->hv_rx_lo_read_idx;
937 sc->sc_rxlor.r_woff = &sc->sc_hostvar->hv_rx_lo_write_idx;
940 bzero(&ld->txp_cmdring, sizeof(struct txp_cmd_desc) * CMD_ENTRIES);
941 boot->br_cmd_lo = vtophys(&ld->txp_cmdring);
943 boot->br_cmd_siz = CMD_ENTRIES * sizeof(struct txp_cmd_desc);
944 sc->sc_cmdring.base = (struct txp_cmd_desc *)&ld->txp_cmdring;
945 sc->sc_cmdring.size = CMD_ENTRIES * sizeof(struct txp_cmd_desc);
946 sc->sc_cmdring.lastwrite = 0;
949 bzero(&ld->txp_rspring, sizeof(struct txp_rsp_desc) * RSP_ENTRIES);
950 boot->br_resp_lo = vtophys(&ld->txp_rspring);
951 boot->br_resp_hi = 0;
952 boot->br_resp_siz = CMD_ENTRIES * sizeof(struct txp_rsp_desc);
953 sc->sc_rspring.base = (struct txp_rsp_desc *)&ld->txp_rspring;
954 sc->sc_rspring.size = RSP_ENTRIES * sizeof(struct txp_rsp_desc);
955 sc->sc_rspring.lastwrite = 0;
957 /* receive buffer ring */
958 boot->br_rxbuf_lo = vtophys(&ld->txp_rxbufs);
959 boot->br_rxbuf_hi = 0;
960 boot->br_rxbuf_siz = RXBUF_ENTRIES * sizeof(struct txp_rxbuf_desc);
961 sc->sc_rxbufs = (struct txp_rxbuf_desc *)&ld->txp_rxbufs;
963 for (i = 0; i < RXBUF_ENTRIES; i++) {
964 struct txp_swdesc *sd;
965 if (sc->sc_rxbufs[i].rb_sd != NULL)
967 sc->sc_rxbufs[i].rb_sd = malloc(sizeof(struct txp_swdesc),
969 if (sc->sc_rxbufs[i].rb_sd == NULL)
971 sd = sc->sc_rxbufs[i].rb_sd;
974 sc->sc_rxbufprod = 0;
977 bzero(&ld->txp_zero, sizeof(u_int32_t));
978 boot->br_zero_lo = vtophys(&ld->txp_zero);
979 boot->br_zero_hi = 0;
981 /* See if it's waiting for boot, and try to boot it */
982 for (i = 0; i < 10000; i++) {
983 r = READ_REG(sc, TXP_A2H_0);
984 if (r == STAT_WAITING_FOR_BOOT)
989 if (r != STAT_WAITING_FOR_BOOT) {
990 if_printf(&sc->sc_arpcom.ac_if, "not waiting for boot\n");
994 WRITE_REG(sc, TXP_H2A_2, 0);
995 WRITE_REG(sc, TXP_H2A_1, vtophys(sc->sc_boot));
996 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_REGISTER_BOOT_RECORD);
998 /* See if it booted */
999 for (i = 0; i < 10000; i++) {
1000 r = READ_REG(sc, TXP_A2H_0);
1001 if (r == STAT_RUNNING)
1005 if (r != STAT_RUNNING) {
1006 if_printf(&sc->sc_arpcom.ac_if, "fw not running\n");
1010 /* Clear TX and CMD ring write registers */
1011 WRITE_REG(sc, TXP_H2A_1, TXP_BOOTCMD_NULL);
1012 WRITE_REG(sc, TXP_H2A_2, TXP_BOOTCMD_NULL);
1013 WRITE_REG(sc, TXP_H2A_3, TXP_BOOTCMD_NULL);
1014 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_NULL);
1020 txp_ioctl(ifp, command, data, cr)
1026 struct txp_softc *sc = ifp->if_softc;
1027 struct ifreq *ifr = (struct ifreq *)data;
1034 if (ifp->if_flags & IFF_UP) {
1037 if (ifp->if_flags & IFF_RUNNING)
1044 * Multicast list has changed; set the hardware
1045 * filter accordingly.
1052 error = ifmedia_ioctl(ifp, ifr, &sc->sc_ifmedia, command);
1055 error = ether_ioctl(ifp, command, data);
1066 struct txp_softc *sc;
1070 struct txp_swdesc *sd;
1072 ifp = &sc->sc_arpcom.ac_if;
1074 for (i = 0; i < RXBUF_ENTRIES; i++) {
1075 sd = sc->sc_rxbufs[i].rb_sd;
1076 MGETHDR(sd->sd_mbuf, MB_DONTWAIT, MT_DATA);
1077 if (sd->sd_mbuf == NULL)
1080 MCLGET(sd->sd_mbuf, MB_DONTWAIT);
1081 if ((sd->sd_mbuf->m_flags & M_EXT) == 0) {
1082 m_freem(sd->sd_mbuf);
1085 sd->sd_mbuf->m_pkthdr.len = sd->sd_mbuf->m_len = MCLBYTES;
1086 sd->sd_mbuf->m_pkthdr.rcvif = ifp;
1088 sc->sc_rxbufs[i].rb_paddrlo =
1089 vtophys(mtod(sd->sd_mbuf, vm_offset_t));
1090 sc->sc_rxbufs[i].rb_paddrhi = 0;
1093 sc->sc_hostvar->hv_rx_buf_write_idx = (RXBUF_ENTRIES - 1) *
1094 sizeof(struct txp_rxbuf_desc);
1100 txp_rxring_empty(sc)
1101 struct txp_softc *sc;
1104 struct txp_swdesc *sd;
1106 if (sc->sc_rxbufs == NULL)
1109 for (i = 0; i < RXBUF_ENTRIES; i++) {
1110 if (&sc->sc_rxbufs[i] == NULL)
1112 sd = sc->sc_rxbufs[i].rb_sd;
1115 if (sd->sd_mbuf != NULL) {
1116 m_freem(sd->sd_mbuf);
1128 struct txp_softc *sc;
1134 ifp = &sc->sc_arpcom.ac_if;
1136 if (ifp->if_flags & IFF_RUNNING)
1143 txp_command(sc, TXP_CMD_MAX_PKT_SIZE_WRITE, TXP_MAX_PKTLEN, 0, 0,
1144 NULL, NULL, NULL, 1);
1146 /* Set station address. */
1147 ((u_int8_t *)&p1)[1] = sc->sc_arpcom.ac_enaddr[0];
1148 ((u_int8_t *)&p1)[0] = sc->sc_arpcom.ac_enaddr[1];
1149 ((u_int8_t *)&p2)[3] = sc->sc_arpcom.ac_enaddr[2];
1150 ((u_int8_t *)&p2)[2] = sc->sc_arpcom.ac_enaddr[3];
1151 ((u_int8_t *)&p2)[1] = sc->sc_arpcom.ac_enaddr[4];
1152 ((u_int8_t *)&p2)[0] = sc->sc_arpcom.ac_enaddr[5];
1153 txp_command(sc, TXP_CMD_STATION_ADDRESS_WRITE, p1, p2, 0,
1154 NULL, NULL, NULL, 1);
1158 txp_rxring_fill(sc);
1160 txp_command(sc, TXP_CMD_TX_ENABLE, 0, 0, 0, NULL, NULL, NULL, 1);
1161 txp_command(sc, TXP_CMD_RX_ENABLE, 0, 0, 0, NULL, NULL, NULL, 1);
1163 WRITE_REG(sc, TXP_IER, TXP_INT_RESERVED | TXP_INT_SELF |
1164 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 |
1165 TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0 |
1166 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 |
1167 TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | TXP_INT_LATCH);
1168 WRITE_REG(sc, TXP_IMR, TXP_INT_A2H_3);
1170 ifp->if_flags |= IFF_RUNNING;
1171 ifp->if_flags &= ~IFF_OACTIVE;
1174 callout_reset(&sc->txp_stat_timer, hz, txp_tick, sc);
1183 struct txp_softc *sc = vsc;
1184 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
1185 struct txp_rsp_desc *rsp = NULL;
1186 struct txp_ext_desc *ext;
1189 txp_rxbuf_reclaim(sc);
1191 if (txp_command2(sc, TXP_CMD_READ_STATISTICS, 0, 0, 0, NULL, 0,
1194 if (rsp->rsp_numdesc != 6)
1196 if (txp_command(sc, TXP_CMD_CLEAR_STATISTICS, 0, 0, 0,
1197 NULL, NULL, NULL, 1))
1199 ext = (struct txp_ext_desc *)(rsp + 1);
1201 ifp->if_ierrors += ext[3].ext_2 + ext[3].ext_3 + ext[3].ext_4 +
1202 ext[4].ext_1 + ext[4].ext_4;
1203 ifp->if_oerrors += ext[0].ext_1 + ext[1].ext_1 + ext[1].ext_4 +
1205 ifp->if_collisions += ext[0].ext_2 + ext[0].ext_3 + ext[1].ext_2 +
1207 ifp->if_opackets += rsp->rsp_par2;
1208 ifp->if_ipackets += ext[2].ext_3;
1212 free(rsp, M_DEVBUF);
1214 callout_reset(&sc->txp_stat_timer, hz, txp_tick, sc);
1222 struct txp_softc *sc = ifp->if_softc;
1223 struct txp_tx_ring *r = &sc->sc_txhir;
1224 struct txp_tx_desc *txd;
1225 struct txp_frag_desc *fxd;
1226 struct mbuf *m, *m0;
1227 struct txp_swdesc *sd;
1228 u_int32_t firstprod, firstcnt, prod, cnt;
1231 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
1238 m = ifq_poll(&ifp->if_snd);
1245 sd = sc->sc_txd + prod;
1248 if ((TX_ENTRIES - cnt) < 4)
1251 txd = r->r_desc + prod;
1253 txd->tx_flags = TX_FLAGS_TYPE_DATA;
1254 txd->tx_numdesc = 0;
1260 if (++prod == TX_ENTRIES)
1263 if (++cnt >= (TX_ENTRIES - 4))
1266 if ((m->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) &&
1267 m->m_pkthdr.rcvif != NULL) {
1268 ifv = m->m_pkthdr.rcvif->if_softc;
1269 txd->tx_pflags = TX_PFLAGS_VLAN |
1270 (htons(ifv->ifv_tag) << TX_PFLAGS_VLANTAG_S);
1273 if (m->m_pkthdr.csum_flags & CSUM_IP)
1274 txd->tx_pflags |= TX_PFLAGS_IPCKSUM;
1277 if (m->m_pkthdr.csum_flags & CSUM_TCP)
1278 txd->tx_pflags |= TX_PFLAGS_TCPCKSUM;
1279 if (m->m_pkthdr.csum_flags & CSUM_UDP)
1280 txd->tx_pflags |= TX_PFLAGS_UDPCKSUM;
1283 fxd = (struct txp_frag_desc *)(r->r_desc + prod);
1284 for (m0 = m; m0 != NULL; m0 = m0->m_next) {
1287 if (++cnt >= (TX_ENTRIES - 4))
1292 fxd->frag_flags = FRAG_FLAGS_TYPE_FRAG;
1293 fxd->frag_rsvd1 = 0;
1294 fxd->frag_len = m0->m_len;
1295 fxd->frag_addrlo = vtophys(mtod(m0, vm_offset_t));
1296 fxd->frag_addrhi = 0;
1297 fxd->frag_rsvd2 = 0;
1299 if (++prod == TX_ENTRIES) {
1300 fxd = (struct txp_frag_desc *)r->r_desc;
1309 m = ifq_dequeue(&ifp->if_snd);
1311 WRITE_REG(sc, r->r_reg, TXP_IDX2OFFSET(prod));
1319 ifp->if_flags |= IFF_OACTIVE;
1320 r->r_prod = firstprod;
1321 r->r_cnt = firstcnt;
1326 * Handle simple commands sent to the typhoon
1329 txp_command(sc, id, in1, in2, in3, out1, out2, out3, wait)
1330 struct txp_softc *sc;
1331 u_int16_t id, in1, *out1;
1332 u_int32_t in2, in3, *out2, *out3;
1335 struct txp_rsp_desc *rsp = NULL;
1337 if (txp_command2(sc, id, in1, in2, in3, NULL, 0, &rsp, wait))
1344 *out1 = rsp->rsp_par1;
1346 *out2 = rsp->rsp_par2;
1348 *out3 = rsp->rsp_par3;
1349 free(rsp, M_DEVBUF);
1354 txp_command2(sc, id, in1, in2, in3, in_extp, in_extn, rspp, wait)
1355 struct txp_softc *sc;
1358 struct txp_ext_desc *in_extp;
1360 struct txp_rsp_desc **rspp;
1363 struct txp_hostvar *hv = sc->sc_hostvar;
1364 struct txp_cmd_desc *cmd;
1365 struct txp_ext_desc *ext;
1369 if (txp_cmd_desc_numfree(sc) < (in_extn + 1)) {
1370 if_printf(&sc->sc_arpcom.ac_if, "no free cmd descriptors\n");
1374 idx = sc->sc_cmdring.lastwrite;
1375 cmd = (struct txp_cmd_desc *)(((u_int8_t *)sc->sc_cmdring.base) + idx);
1376 bzero(cmd, sizeof(*cmd));
1378 cmd->cmd_numdesc = in_extn;
1379 cmd->cmd_seq = seq = sc->sc_seq++;
1381 cmd->cmd_par1 = in1;
1382 cmd->cmd_par2 = in2;
1383 cmd->cmd_par3 = in3;
1384 cmd->cmd_flags = CMD_FLAGS_TYPE_CMD |
1385 (wait ? CMD_FLAGS_RESP : 0) | CMD_FLAGS_VALID;
1387 idx += sizeof(struct txp_cmd_desc);
1388 if (idx == sc->sc_cmdring.size)
1391 for (i = 0; i < in_extn; i++) {
1392 ext = (struct txp_ext_desc *)(((u_int8_t *)sc->sc_cmdring.base) + idx);
1393 bcopy(in_extp, ext, sizeof(struct txp_ext_desc));
1395 idx += sizeof(struct txp_cmd_desc);
1396 if (idx == sc->sc_cmdring.size)
1400 sc->sc_cmdring.lastwrite = idx;
1402 WRITE_REG(sc, TXP_H2A_2, sc->sc_cmdring.lastwrite);
1407 for (i = 0; i < 10000; i++) {
1408 idx = hv->hv_resp_read_idx;
1409 if (idx != hv->hv_resp_write_idx) {
1411 if (txp_response(sc, idx, id, seq, rspp))
1418 if (i == 1000 || (*rspp) == NULL) {
1419 if_printf(&sc->sc_arpcom.ac_if, "0x%x command failed\n", id);
1427 txp_response(sc, ridx, id, seq, rspp)
1428 struct txp_softc *sc;
1432 struct txp_rsp_desc **rspp;
1434 struct txp_hostvar *hv = sc->sc_hostvar;
1435 struct txp_rsp_desc *rsp;
1437 while (ridx != hv->hv_resp_write_idx) {
1438 rsp = (struct txp_rsp_desc *)(((u_int8_t *)sc->sc_rspring.base) + ridx);
1440 if (id == rsp->rsp_id && rsp->rsp_seq == seq) {
1441 *rspp = (struct txp_rsp_desc *)malloc(
1442 sizeof(struct txp_rsp_desc) * (rsp->rsp_numdesc + 1),
1443 M_DEVBUF, M_INTWAIT);
1444 if ((*rspp) == NULL)
1446 txp_rsp_fixup(sc, rsp, *rspp);
1450 if (rsp->rsp_flags & RSP_FLAGS_ERROR) {
1451 if_printf(&sc->sc_arpcom.ac_if, "response error!\n");
1452 txp_rsp_fixup(sc, rsp, NULL);
1453 ridx = hv->hv_resp_read_idx;
1457 switch (rsp->rsp_id) {
1458 case TXP_CMD_CYCLE_STATISTICS:
1459 case TXP_CMD_MEDIA_STATUS_READ:
1461 case TXP_CMD_HELLO_RESPONSE:
1462 if_printf(&sc->sc_arpcom.ac_if, "hello\n");
1465 if_printf(&sc->sc_arpcom.ac_if, "unknown id(0x%x)\n",
1469 txp_rsp_fixup(sc, rsp, NULL);
1470 ridx = hv->hv_resp_read_idx;
1471 hv->hv_resp_read_idx = ridx;
1478 txp_rsp_fixup(sc, rsp, dst)
1479 struct txp_softc *sc;
1480 struct txp_rsp_desc *rsp, *dst;
1482 struct txp_rsp_desc *src = rsp;
1483 struct txp_hostvar *hv = sc->sc_hostvar;
1486 ridx = hv->hv_resp_read_idx;
1488 for (i = 0; i < rsp->rsp_numdesc + 1; i++) {
1490 bcopy(src, dst++, sizeof(struct txp_rsp_desc));
1491 ridx += sizeof(struct txp_rsp_desc);
1492 if (ridx == sc->sc_rspring.size) {
1493 src = sc->sc_rspring.base;
1497 sc->sc_rspring.lastwrite = hv->hv_resp_read_idx = ridx;
1500 hv->hv_resp_read_idx = ridx;
1504 txp_cmd_desc_numfree(sc)
1505 struct txp_softc *sc;
1507 struct txp_hostvar *hv = sc->sc_hostvar;
1508 struct txp_boot_record *br = sc->sc_boot;
1509 u_int32_t widx, ridx, nfree;
1511 widx = sc->sc_cmdring.lastwrite;
1512 ridx = hv->hv_cmd_read_idx;
1515 /* Ring is completely free */
1516 nfree = br->br_cmd_siz - sizeof(struct txp_cmd_desc);
1519 nfree = br->br_cmd_siz -
1520 (widx - ridx + sizeof(struct txp_cmd_desc));
1522 nfree = ridx - widx - sizeof(struct txp_cmd_desc);
1525 return (nfree / sizeof(struct txp_cmd_desc));
1530 struct txp_softc *sc;
1534 ifp = &sc->sc_arpcom.ac_if;
1536 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1538 callout_stop(&sc->txp_stat_timer);
1540 txp_command(sc, TXP_CMD_TX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 1);
1541 txp_command(sc, TXP_CMD_RX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 1);
1543 txp_rxring_empty(sc);
1556 txp_ifmedia_upd(ifp)
1559 struct txp_softc *sc = ifp->if_softc;
1560 struct ifmedia *ifm = &sc->sc_ifmedia;
1563 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1566 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_10_T) {
1567 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1568 new_xcvr = TXP_XCVR_10_FDX;
1570 new_xcvr = TXP_XCVR_10_HDX;
1571 } else if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) {
1572 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1573 new_xcvr = TXP_XCVR_100_FDX;
1575 new_xcvr = TXP_XCVR_100_HDX;
1576 } else if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) {
1577 new_xcvr = TXP_XCVR_AUTO;
1582 if (sc->sc_xcvr == new_xcvr)
1585 txp_command(sc, TXP_CMD_XCVR_SELECT, new_xcvr, 0, 0,
1586 NULL, NULL, NULL, 0);
1587 sc->sc_xcvr = new_xcvr;
1593 txp_ifmedia_sts(ifp, ifmr)
1595 struct ifmediareq *ifmr;
1597 struct txp_softc *sc = ifp->if_softc;
1598 struct ifmedia *ifm = &sc->sc_ifmedia;
1599 u_int16_t bmsr, bmcr, anlpar;
1601 ifmr->ifm_status = IFM_AVALID;
1602 ifmr->ifm_active = IFM_ETHER;
1604 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMSR, 0,
1605 &bmsr, NULL, NULL, 1))
1607 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMSR, 0,
1608 &bmsr, NULL, NULL, 1))
1611 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMCR, 0,
1612 &bmcr, NULL, NULL, 1))
1615 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_ANLPAR, 0,
1616 &anlpar, NULL, NULL, 1))
1619 if (bmsr & BMSR_LINK)
1620 ifmr->ifm_status |= IFM_ACTIVE;
1622 if (bmcr & BMCR_ISO) {
1623 ifmr->ifm_active |= IFM_NONE;
1624 ifmr->ifm_status = 0;
1628 if (bmcr & BMCR_LOOP)
1629 ifmr->ifm_active |= IFM_LOOP;
1631 if (bmcr & BMCR_AUTOEN) {
1632 if ((bmsr & BMSR_ACOMP) == 0) {
1633 ifmr->ifm_active |= IFM_NONE;
1637 if (anlpar & ANLPAR_T4)
1638 ifmr->ifm_active |= IFM_100_T4;
1639 else if (anlpar & ANLPAR_TX_FD)
1640 ifmr->ifm_active |= IFM_100_TX|IFM_FDX;
1641 else if (anlpar & ANLPAR_TX)
1642 ifmr->ifm_active |= IFM_100_TX;
1643 else if (anlpar & ANLPAR_10_FD)
1644 ifmr->ifm_active |= IFM_10_T|IFM_FDX;
1645 else if (anlpar & ANLPAR_10)
1646 ifmr->ifm_active |= IFM_10_T;
1648 ifmr->ifm_active |= IFM_NONE;
1650 ifmr->ifm_active = ifm->ifm_cur->ifm_media;
1654 ifmr->ifm_active |= IFM_NONE;
1655 ifmr->ifm_status &= ~IFM_AVALID;
1660 txp_show_descriptor(d)
1663 struct txp_cmd_desc *cmd = d;
1664 struct txp_rsp_desc *rsp = d;
1665 struct txp_tx_desc *txd = d;
1666 struct txp_frag_desc *frgd = d;
1668 switch (cmd->cmd_flags & CMD_FLAGS_TYPE_M) {
1669 case CMD_FLAGS_TYPE_CMD:
1670 /* command descriptor */
1671 printf("[cmd flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n",
1672 cmd->cmd_flags, cmd->cmd_numdesc, cmd->cmd_id, cmd->cmd_seq,
1673 cmd->cmd_par1, cmd->cmd_par2, cmd->cmd_par3);
1675 case CMD_FLAGS_TYPE_RESP:
1676 /* response descriptor */
1677 printf("[rsp flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n",
1678 rsp->rsp_flags, rsp->rsp_numdesc, rsp->rsp_id, rsp->rsp_seq,
1679 rsp->rsp_par1, rsp->rsp_par2, rsp->rsp_par3);
1681 case CMD_FLAGS_TYPE_DATA:
1682 /* data header (assuming tx for now) */
1683 printf("[data flags 0x%x num %d totlen %d addr 0x%x/0x%x pflags 0x%x]",
1684 txd->tx_flags, txd->tx_numdesc, txd->tx_totlen,
1685 txd->tx_addrlo, txd->tx_addrhi, txd->tx_pflags);
1687 case CMD_FLAGS_TYPE_FRAG:
1688 /* fragment descriptor */
1689 printf("[frag flags 0x%x rsvd1 0x%x len %d addr 0x%x/0x%x rsvd2 0x%x]",
1690 frgd->frag_flags, frgd->frag_rsvd1, frgd->frag_len,
1691 frgd->frag_addrlo, frgd->frag_addrhi, frgd->frag_rsvd2);
1694 printf("[unknown(%x) flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n",
1695 cmd->cmd_flags & CMD_FLAGS_TYPE_M,
1696 cmd->cmd_flags, cmd->cmd_numdesc, cmd->cmd_id, cmd->cmd_seq,
1697 cmd->cmd_par1, cmd->cmd_par2, cmd->cmd_par3);
1705 struct txp_softc *sc;
1707 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
1709 struct ifmultiaddr *ifma;
1711 if (ifp->if_flags & IFF_PROMISC) {
1712 filter = TXP_RXFILT_PROMISC;
1716 filter = TXP_RXFILT_DIRECT;
1718 if (ifp->if_flags & IFF_BROADCAST)
1719 filter |= TXP_RXFILT_BROADCAST;
1721 if (ifp->if_flags & IFF_ALLMULTI) {
1722 filter |= TXP_RXFILT_ALLMULTI;
1724 uint32_t hashbit, hash[2];
1727 hash[0] = hash[1] = 0;
1729 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
1730 ifma = ifma->ifma_link.le_next) {
1731 if (ifma->ifma_addr->sa_family != AF_LINK)
1735 hashbit = (uint16_t)(ether_crc32_be(
1736 LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1737 ETHER_ADDR_LEN) & (64 - 1));
1738 hash[hashbit / 32] |= (1 << hashbit % 32);
1742 filter |= TXP_RXFILT_HASHMULTI;
1743 txp_command(sc, TXP_CMD_MCAST_HASH_MASK_WRITE,
1744 2, hash[0], hash[1], NULL, NULL, NULL, 0);
1749 txp_command(sc, TXP_CMD_RX_FILTER_WRITE, filter, 0, 0,
1750 NULL, NULL, NULL, 1);
1754 txp_capabilities(sc)
1755 struct txp_softc *sc;
1757 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
1758 struct txp_rsp_desc *rsp = NULL;
1759 struct txp_ext_desc *ext;
1761 if (txp_command2(sc, TXP_CMD_OFFLOAD_READ, 0, 0, 0, NULL, 0, &rsp, 1))
1764 if (rsp->rsp_numdesc != 1)
1766 ext = (struct txp_ext_desc *)(rsp + 1);
1768 sc->sc_tx_capability = ext->ext_1 & OFFLOAD_MASK;
1769 sc->sc_rx_capability = ext->ext_2 & OFFLOAD_MASK;
1770 ifp->if_capabilities = 0;
1772 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_VLAN) {
1773 sc->sc_tx_capability |= OFFLOAD_VLAN;
1774 sc->sc_rx_capability |= OFFLOAD_VLAN;
1779 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_IPSEC) {
1780 sc->sc_tx_capability |= OFFLOAD_IPSEC;
1781 sc->sc_rx_capability |= OFFLOAD_IPSEC;
1782 ifp->if_capabilities |= IFCAP_IPSEC;
1786 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_IPCKSUM) {
1787 sc->sc_tx_capability |= OFFLOAD_IPCKSUM;
1788 sc->sc_rx_capability |= OFFLOAD_IPCKSUM;
1789 ifp->if_capabilities |= IFCAP_HWCSUM;
1790 ifp->if_hwassist |= CSUM_IP;
1793 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_TCPCKSUM) {
1795 sc->sc_tx_capability |= OFFLOAD_TCPCKSUM;
1797 sc->sc_rx_capability |= OFFLOAD_TCPCKSUM;
1798 ifp->if_capabilities |= IFCAP_HWCSUM;
1801 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_UDPCKSUM) {
1803 sc->sc_tx_capability |= OFFLOAD_UDPCKSUM;
1805 sc->sc_rx_capability |= OFFLOAD_UDPCKSUM;
1806 ifp->if_capabilities |= IFCAP_HWCSUM;
1808 ifp->if_capenable = ifp->if_capabilities;
1810 if (txp_command(sc, TXP_CMD_OFFLOAD_WRITE, 0,
1811 sc->sc_tx_capability, sc->sc_rx_capability, NULL, NULL, NULL, 1))
1816 free(rsp, M_DEVBUF);