sys/dev/netif/bge/if_bge.c

   1 /*
   2  * Copyright (c) 2001 Wind River Systems
   3  * Copyright (c) 1997, 1998, 1999, 2001
   4  *      Bill Paul <wpaul@windriver.com>.  All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. All advertising materials mentioning features or use of this software
  15  *    must display the following acknowledgement:
  16  *      This product includes software developed by Bill Paul.
  17  * 4. Neither the name of the author nor the names of any co-contributors
  18  *    may be used to endorse or promote products derived from this software
  19  *    without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
  22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  25  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  31  * THE POSSIBILITY OF SUCH DAMAGE.
  32  *
  33  * $FreeBSD: src/sys/dev/bge/if_bge.c,v 1.3.2.39 2005/07/03 03:41:18 silby Exp $
  34  */
  35
  36 /*
  37  * Broadcom BCM570x family gigabit ethernet driver for FreeBSD.
  38  *
  39  * Written by Bill Paul <wpaul@windriver.com>
  40  * Senior Engineer, Wind River Systems
  41  */
  42
  43 /*
  44  * The Broadcom BCM5700 is based on technology originally developed by
  45  * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet
  46  * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has
  47  * two on-board MIPS R4000 CPUs and can have as much as 16MB of external
  48  * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo
  49  * frames, highly configurable RX filtering, and 16 RX and TX queues
  50  * (which, along with RX filter rules, can be used for QOS applications).
  51  * Other features, such as TCP segmentation, may be available as part
  52  * of value-added firmware updates. Unlike the Tigon I and Tigon II,
  53  * firmware images can be stored in hardware and need not be compiled
  54  * into the driver.
  55  *
  56  * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will
  57  * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus.
  58  *
  59  * The BCM5701 is a single-chip solution incorporating both the BCM5700
  60  * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701
  61  * does not support external SSRAM.
  62  *
  63  * Broadcom also produces a variation of the BCM5700 under the "Altima"
  64  * brand name, which is functionally similar but lacks PCI-X support.
  65  *
  66  * Without external SSRAM, you can only have at most 4 TX rings,
  67  * and the use of the mini RX ring is disabled. This seems to imply
  68  * that these features are simply not available on the BCM5701. As a
  69  * result, this driver does not implement any support for the mini RX
  70  * ring.
  71  */
  72
  73 #include "opt_ifpoll.h"
  74
  75 #include <sys/param.h>
  76 #include <sys/bus.h>
  77 #include <sys/endian.h>
  78 #include <sys/kernel.h>
  79 #include <sys/ktr.h>
  80 #include <sys/interrupt.h>
  81 #include <sys/mbuf.h>
  82 #include <sys/malloc.h>
  83 #include <sys/queue.h>
  84 #include <sys/rman.h>
  85 #include <sys/serialize.h>
  86 #include <sys/socket.h>
  87 #include <sys/sockio.h>
  88 #include <sys/sysctl.h>
  89
  90 #include <netinet/ip.h>
  91 #include <netinet/tcp.h>
  92
  93 #include <net/bpf.h>
  94 #include <net/ethernet.h>
  95 #include <net/if.h>
  96 #include <net/if_arp.h>
  97 #include <net/if_dl.h>
  98 #include <net/if_media.h>
  99 #include <net/if_poll.h>
 100 #include <net/if_types.h>
 101 #include <net/ifq_var.h>
 102 #include <net/vlan/if_vlan_var.h>
 103 #include <net/vlan/if_vlan_ether.h>
 104
 105 #include <dev/netif/mii_layer/mii.h>
 106 #include <dev/netif/mii_layer/miivar.h>
 107 #include <dev/netif/mii_layer/brgphyreg.h>
 108
 109 #include <bus/pci/pcidevs.h>
 110 #include <bus/pci/pcireg.h>
 111 #include <bus/pci/pcivar.h>
 112
 113 #include <dev/netif/bge/if_bgereg.h>
 114 #include <dev/netif/bge/if_bgevar.h>
 115
 116 /* "device miibus" required.  See GENERIC if you get errors here. */
 117 #include "miibus_if.h"
 118
 119 #define BGE_CSUM_FEATURES       (CSUM_IP | CSUM_TCP)
 120
 121 static const struct bge_type {
 122         uint16_t                bge_vid;
 123         uint16_t                bge_did;
 124         char                    *bge_name;
 125 } bge_devs[] = {
 126         { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C996,
 127                 "3COM 3C996 Gigabit Ethernet" },
 128
 129         { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5700,
 130                 "Alteon BCM5700 Gigabit Ethernet" },
 131         { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5701,
 132                 "Alteon BCM5701 Gigabit Ethernet" },
 133
 134         { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1000,
 135                 "Altima AC1000 Gigabit Ethernet" },
 136         { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1001,
 137                 "Altima AC1002 Gigabit Ethernet" },
 138         { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC9100,
 139                 "Altima AC9100 Gigabit Ethernet" },
 140
 141         { PCI_VENDOR_APPLE, PCI_PRODUCT_APPLE_BCM5701,
 142                 "Apple BCM5701 Gigabit Ethernet" },
 143
 144         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5700,
 145                 "Broadcom BCM5700 Gigabit Ethernet" },
 146         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5701,
 147                 "Broadcom BCM5701 Gigabit Ethernet" },
 148         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702,
 149                 "Broadcom BCM5702 Gigabit Ethernet" },
 150         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702X,
 151                 "Broadcom BCM5702X Gigabit Ethernet" },
 152         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702_ALT,
 153                 "Broadcom BCM5702 Gigabit Ethernet" },
 154         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703,
 155                 "Broadcom BCM5703 Gigabit Ethernet" },
 156         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703X,
 157                 "Broadcom BCM5703X Gigabit Ethernet" },
 158         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703A3,
 159                 "Broadcom BCM5703 Gigabit Ethernet" },
 160         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704C,
 161                 "Broadcom BCM5704C Dual Gigabit Ethernet" },
 162         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704S,
 163                 "Broadcom BCM5704S Dual Gigabit Ethernet" },
 164         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704S_ALT,
 165                 "Broadcom BCM5704S Dual Gigabit Ethernet" },
 166         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705,
 167                 "Broadcom BCM5705 Gigabit Ethernet" },
 168         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705F,
 169                 "Broadcom BCM5705F Gigabit Ethernet" },
 170         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705K,
 171                 "Broadcom BCM5705K Gigabit Ethernet" },
 172         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M,
 173                 "Broadcom BCM5705M Gigabit Ethernet" },
 174         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M_ALT,
 175                 "Broadcom BCM5705M Gigabit Ethernet" },
 176         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5714,
 177                 "Broadcom BCM5714C Gigabit Ethernet" },
 178         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5714S,
 179                 "Broadcom BCM5714S Gigabit Ethernet" },
 180         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5715,
 181                 "Broadcom BCM5715 Gigabit Ethernet" },
 182         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5715S,
 183                 "Broadcom BCM5715S Gigabit Ethernet" },
 184         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5720,
 185                 "Broadcom BCM5720 Gigabit Ethernet" },
 186         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5721,
 187                 "Broadcom BCM5721 Gigabit Ethernet" },
 188         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5722,
 189                 "Broadcom BCM5722 Gigabit Ethernet" },
 190         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5723,
 191                 "Broadcom BCM5723 Gigabit Ethernet" },
 192         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750,
 193                 "Broadcom BCM5750 Gigabit Ethernet" },
 194         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750M,
 195                 "Broadcom BCM5750M Gigabit Ethernet" },
 196         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751,
 197                 "Broadcom BCM5751 Gigabit Ethernet" },
 198         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751F,
 199                 "Broadcom BCM5751F Gigabit Ethernet" },
 200         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751M,
 201                 "Broadcom BCM5751M Gigabit Ethernet" },
 202         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5752,
 203                 "Broadcom BCM5752 Gigabit Ethernet" },
 204         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5752M,
 205                 "Broadcom BCM5752M Gigabit Ethernet" },
 206         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753,
 207                 "Broadcom BCM5753 Gigabit Ethernet" },
 208         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753F,
 209                 "Broadcom BCM5753F Gigabit Ethernet" },
 210         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753M,
 211                 "Broadcom BCM5753M Gigabit Ethernet" },
 212         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5754,
 213                 "Broadcom BCM5754 Gigabit Ethernet" },
 214         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5754M,
 215                 "Broadcom BCM5754M Gigabit Ethernet" },
 216         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5755,
 217                 "Broadcom BCM5755 Gigabit Ethernet" },
 218         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5755M,
 219                 "Broadcom BCM5755M Gigabit Ethernet" },
 220         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5756,
 221                 "Broadcom BCM5756 Gigabit Ethernet" },
 222         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761,
 223                 "Broadcom BCM5761 Gigabit Ethernet" },
 224         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761E,
 225                 "Broadcom BCM5761E Gigabit Ethernet" },
 226         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761S,
 227                 "Broadcom BCM5761S Gigabit Ethernet" },
 228         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761SE,
 229                 "Broadcom BCM5761SE Gigabit Ethernet" },
 230         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5764,
 231                 "Broadcom BCM5764 Gigabit Ethernet" },
 232         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5780,
 233                 "Broadcom BCM5780 Gigabit Ethernet" },
 234         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5780S,
 235                 "Broadcom BCM5780S Gigabit Ethernet" },
 236         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5781,
 237                 "Broadcom BCM5781 Gigabit Ethernet" },
 238         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5782,
 239                 "Broadcom BCM5782 Gigabit Ethernet" },
 240         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5784,
 241                 "Broadcom BCM5784 Gigabit Ethernet" },
 242         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5785F,
 243                 "Broadcom BCM5785F Gigabit Ethernet" },
 244         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5785G,
 245                 "Broadcom BCM5785G Gigabit Ethernet" },
 246         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5786,
 247                 "Broadcom BCM5786 Gigabit Ethernet" },
 248         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787,
 249                 "Broadcom BCM5787 Gigabit Ethernet" },
 250         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787F,
 251                 "Broadcom BCM5787F Gigabit Ethernet" },
 252         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787M,
 253                 "Broadcom BCM5787M Gigabit Ethernet" },
 254         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5788,
 255                 "Broadcom BCM5788 Gigabit Ethernet" },
 256         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5789,
 257                 "Broadcom BCM5789 Gigabit Ethernet" },
 258         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901,
 259                 "Broadcom BCM5901 Fast Ethernet" },
 260         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901A2,
 261                 "Broadcom BCM5901A2 Fast Ethernet" },
 262         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5903M,
 263                 "Broadcom BCM5903M Fast Ethernet" },
 264         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5906,
 265                 "Broadcom BCM5906 Fast Ethernet"},
 266         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5906M,
 267                 "Broadcom BCM5906M Fast Ethernet"},
 268         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57760,
 269                 "Broadcom BCM57760 Gigabit Ethernet"},
 270         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57780,
 271                 "Broadcom BCM57780 Gigabit Ethernet"},
 272         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57788,
 273                 "Broadcom BCM57788 Gigabit Ethernet"},
 274         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57790,
 275                 "Broadcom BCM57790 Gigabit Ethernet"},
 276         { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1,
 277                 "SysKonnect Gigabit Ethernet" },
 278
 279         { 0, 0, NULL }
 280 };
 281
 282 #define BGE_IS_JUMBO_CAPABLE(sc)        ((sc)->bge_flags & BGE_FLAG_JUMBO)
 283 #define BGE_IS_5700_FAMILY(sc)          ((sc)->bge_flags & BGE_FLAG_5700_FAMILY)
 284 #define BGE_IS_5705_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_5705_PLUS)
 285 #define BGE_IS_5714_FAMILY(sc)          ((sc)->bge_flags & BGE_FLAG_5714_FAMILY)
 286 #define BGE_IS_575X_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_575X_PLUS)
 287 #define BGE_IS_5755_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_5755_PLUS)
 288 #define BGE_IS_5788(sc)                 ((sc)->bge_flags & BGE_FLAG_5788)
 289
 290 #define BGE_IS_CRIPPLED(sc)             \
 291         (BGE_IS_5788((sc)) || (sc)->bge_asicrev == BGE_ASICREV_BCM5700)
 292
 293 typedef int     (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]);
 294
 295 static int      bge_probe(device_t);
 296 static int      bge_attach(device_t);
 297 static int      bge_detach(device_t);
 298 static void     bge_txeof(struct bge_softc *, uint16_t);
 299 static void     bge_rxeof(struct bge_softc *, uint16_t, int);
 300
 301 static void     bge_tick(void *);
 302 static void     bge_stats_update(struct bge_softc *);
 303 static void     bge_stats_update_regs(struct bge_softc *);
 304 static struct mbuf *
 305                 bge_defrag_shortdma(struct mbuf *);
 306 static int      bge_encap(struct bge_softc *, struct mbuf **,
 307                     uint32_t *, int *);
 308 static void     bge_xmit(struct bge_softc *, uint32_t);
 309 static int      bge_setup_tso(struct bge_softc *, struct mbuf **,
 310                     uint16_t *, uint16_t *);
 311
 312 #ifdef IFPOLL_ENABLE
 313 static void     bge_npoll(struct ifnet *, struct ifpoll_info *);
 314 static void     bge_npoll_compat(struct ifnet *, void *, int );
 315 #endif
 316 static void     bge_intr_crippled(void *);
 317 static void     bge_intr_legacy(void *);
 318 static void     bge_msi(void *);
 319 static void     bge_msi_oneshot(void *);
 320 static void     bge_intr(struct bge_softc *);
 321 static void     bge_enable_intr(struct bge_softc *);
 322 static void     bge_disable_intr(struct bge_softc *);
 323 static void     bge_start(struct ifnet *, struct ifaltq_subque *);
 324 static int      bge_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
 325 static void     bge_init(void *);
 326 static void     bge_stop(struct bge_softc *);
 327 static void     bge_watchdog(struct ifnet *);
 328 static void     bge_shutdown(device_t);
 329 static int      bge_suspend(device_t);
 330 static int      bge_resume(device_t);
 331 static int      bge_ifmedia_upd(struct ifnet *);
 332 static void     bge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
 333
 334 static uint8_t  bge_nvram_getbyte(struct bge_softc *, int, uint8_t *);
 335 static int      bge_read_nvram(struct bge_softc *, caddr_t, int, int);
 336
 337 static uint8_t  bge_eeprom_getbyte(struct bge_softc *, uint32_t, uint8_t *);
 338 static int      bge_read_eeprom(struct bge_softc *, caddr_t, uint32_t, size_t);
 339
 340 static void     bge_setmulti(struct bge_softc *);
 341 static void     bge_setpromisc(struct bge_softc *);
 342 static void     bge_enable_msi(struct bge_softc *sc);
 343
 344 static int      bge_alloc_jumbo_mem(struct bge_softc *);
 345 static void     bge_free_jumbo_mem(struct bge_softc *);
 346 static struct bge_jslot
 347                 *bge_jalloc(struct bge_softc *);
 348 static void     bge_jfree(void *);
 349 static void     bge_jref(void *);
 350 static int      bge_newbuf_std(struct bge_softc *, int, int);
 351 static int      bge_newbuf_jumbo(struct bge_softc *, int, int);
 352 static void     bge_setup_rxdesc_std(struct bge_softc *, int);
 353 static void     bge_setup_rxdesc_jumbo(struct bge_softc *, int);
 354 static int      bge_init_rx_ring_std(struct bge_softc *);
 355 static void     bge_free_rx_ring_std(struct bge_softc *);
 356 static int      bge_init_rx_ring_jumbo(struct bge_softc *);
 357 static void     bge_free_rx_ring_jumbo(struct bge_softc *);
 358 static void     bge_free_tx_ring(struct bge_softc *);
 359 static int      bge_init_tx_ring(struct bge_softc *);
 360
 361 static int      bge_chipinit(struct bge_softc *);
 362 static int      bge_blockinit(struct bge_softc *);
 363 static void     bge_stop_block(struct bge_softc *, bus_size_t, uint32_t);
 364
 365 static uint32_t bge_readmem_ind(struct bge_softc *, uint32_t);
 366 static void     bge_writemem_ind(struct bge_softc *, uint32_t, uint32_t);
 367 #ifdef notdef
 368 static uint32_t bge_readreg_ind(struct bge_softc *, uint32_t);
 369 #endif
 370 static void     bge_writereg_ind(struct bge_softc *, uint32_t, uint32_t);
 371 static void     bge_writemem_direct(struct bge_softc *, uint32_t, uint32_t);
 372 static void     bge_writembx(struct bge_softc *, int, int);
 373
 374 static int      bge_miibus_readreg(device_t, int, int);
 375 static int      bge_miibus_writereg(device_t, int, int, int);
 376 static void     bge_miibus_statchg(device_t);
 377 static void     bge_bcm5700_link_upd(struct bge_softc *, uint32_t);
 378 static void     bge_tbi_link_upd(struct bge_softc *, uint32_t);
 379 static void     bge_copper_link_upd(struct bge_softc *, uint32_t);
 380 static void     bge_autopoll_link_upd(struct bge_softc *, uint32_t);
 381 static void     bge_link_poll(struct bge_softc *);
 382
 383 static void     bge_reset(struct bge_softc *);
 384
 385 static int      bge_dma_alloc(struct bge_softc *);
 386 static void     bge_dma_free(struct bge_softc *);
 387 static int      bge_dma_block_alloc(struct bge_softc *, bus_size_t,
 388                                     bus_dma_tag_t *, bus_dmamap_t *,
 389                                     void **, bus_addr_t *);
 390 static void     bge_dma_block_free(bus_dma_tag_t, bus_dmamap_t, void *);
 391
 392 static int      bge_get_eaddr_mem(struct bge_softc *, uint8_t[]);
 393 static int      bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]);
 394 static int      bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]);
 395 static int      bge_get_eaddr(struct bge_softc *, uint8_t[]);
 396
 397 static void     bge_coal_change(struct bge_softc *);
 398 static int      bge_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS);
 399 static int      bge_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS);
 400 static int      bge_sysctl_rx_coal_bds(SYSCTL_HANDLER_ARGS);
 401 static int      bge_sysctl_tx_coal_bds(SYSCTL_HANDLER_ARGS);
 402 static int      bge_sysctl_rx_coal_ticks_int(SYSCTL_HANDLER_ARGS);
 403 static int      bge_sysctl_tx_coal_ticks_int(SYSCTL_HANDLER_ARGS);
 404 static int      bge_sysctl_rx_coal_bds_int(SYSCTL_HANDLER_ARGS);
 405 static int      bge_sysctl_tx_coal_bds_int(SYSCTL_HANDLER_ARGS);
 406 static int      bge_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *,
 407                     int, int, uint32_t);
 408
 409 /*
 410  * Set following tunable to 1 for some IBM blade servers with the DNLK
 411  * switch module. Auto negotiation is broken for those configurations.
 412  */
 413 static int      bge_fake_autoneg = 0;
 414 TUNABLE_INT("hw.bge.fake_autoneg", &bge_fake_autoneg);
 415
 416 static int      bge_msi_enable = 1;
 417 TUNABLE_INT("hw.bge.msi.enable", &bge_msi_enable);
 418
 419 #if !defined(KTR_IF_BGE)
 420 #define KTR_IF_BGE      KTR_ALL
 421 #endif
 422 KTR_INFO_MASTER(if_bge);
 423 KTR_INFO(KTR_IF_BGE, if_bge, intr, 0, "intr");
 424 KTR_INFO(KTR_IF_BGE, if_bge, rx_pkt, 1, "rx_pkt");
 425 KTR_INFO(KTR_IF_BGE, if_bge, tx_pkt, 2, "tx_pkt");
 426 #define logif(name)     KTR_LOG(if_bge_ ## name)
 427
 428 static device_method_t bge_methods[] = {
 429         /* Device interface */
 430         DEVMETHOD(device_probe,         bge_probe),
 431         DEVMETHOD(device_attach,        bge_attach),
 432         DEVMETHOD(device_detach,        bge_detach),
 433         DEVMETHOD(device_shutdown,      bge_shutdown),
 434         DEVMETHOD(device_suspend,       bge_suspend),
 435         DEVMETHOD(device_resume,        bge_resume),
 436
 437         /* bus interface */
 438         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 439         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 440
 441         /* MII interface */
 442         DEVMETHOD(miibus_readreg,       bge_miibus_readreg),
 443         DEVMETHOD(miibus_writereg,      bge_miibus_writereg),
 444         DEVMETHOD(miibus_statchg,       bge_miibus_statchg),
 445
 446         { 0, 0 }
 447 };
 448
 449 static DEFINE_CLASS_0(bge, bge_driver, bge_methods, sizeof(struct bge_softc));
 450 static devclass_t bge_devclass;
 451
 452 DECLARE_DUMMY_MODULE(if_bge);
 453 DRIVER_MODULE(if_bge, pci, bge_driver, bge_devclass, NULL, NULL);
 454 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, NULL, NULL);
 455
 456 static uint32_t
 457 bge_readmem_ind(struct bge_softc *sc, uint32_t off)
 458 {
 459         device_t dev = sc->bge_dev;
 460         uint32_t val;
 461
 462         if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
 463             off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4)
 464                 return 0;
 465
 466         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
 467         val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4);
 468         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
 469         return (val);
 470 }
 471
 472 static void
 473 bge_writemem_ind(struct bge_softc *sc, uint32_t off, uint32_t val)
 474 {
 475         device_t dev = sc->bge_dev;
 476
 477         if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
 478             off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4)
 479                 return;
 480
 481         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
 482         pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
 483         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
 484 }
 485
 486 #ifdef notdef
 487 static uint32_t
 488 bge_readreg_ind(struct bge_softc *sc, uin32_t off)
 489 {
 490         device_t dev = sc->bge_dev;
 491
 492         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
 493         return(pci_read_config(dev, BGE_PCI_REG_DATA, 4));
 494 }
 495 #endif
 496
 497 static void
 498 bge_writereg_ind(struct bge_softc *sc, uint32_t off, uint32_t val)
 499 {
 500         device_t dev = sc->bge_dev;
 501
 502         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
 503         pci_write_config(dev, BGE_PCI_REG_DATA, val, 4);
 504 }
 505
 506 static void
 507 bge_writemem_direct(struct bge_softc *sc, uint32_t off, uint32_t val)
 508 {
 509         CSR_WRITE_4(sc, off, val);
 510 }
 511
 512 static void
 513 bge_writembx(struct bge_softc *sc, int off, int val)
 514 {
 515         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
 516                 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI;
 517
 518         CSR_WRITE_4(sc, off, val);
 519         if (sc->bge_mbox_reorder)
 520                 CSR_READ_4(sc, off);
 521 }
 522
 523 static uint8_t
 524 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
 525 {
 526         uint32_t access, byte = 0;
 527         int i;
 528
 529         /* Lock. */
 530         CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1);
 531         for (i = 0; i < 8000; i++) {
 532                 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1)
 533                         break;
 534                 DELAY(20);
 535         }
 536         if (i == 8000)
 537                 return (1);
 538
 539         /* Enable access. */
 540         access = CSR_READ_4(sc, BGE_NVRAM_ACCESS);
 541         CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE);
 542
 543         CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc);
 544         CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD);
 545         for (i = 0; i < BGE_TIMEOUT * 10; i++) {
 546                 DELAY(10);
 547                 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) {
 548                         DELAY(10);
 549                         break;
 550                 }
 551         }
 552
 553         if (i == BGE_TIMEOUT * 10) {
 554                 if_printf(&sc->arpcom.ac_if, "nvram read timed out\n");
 555                 return (1);
 556         }
 557
 558         /* Get result. */
 559         byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA);
 560
 561         *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF;
 562
 563         /* Disable access. */
 564         CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access);
 565
 566         /* Unlock. */
 567         CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1);
 568         CSR_READ_4(sc, BGE_NVRAM_SWARB);
 569
 570         return (0);
 571 }
 572
 573 /*
 574  * Read a sequence of bytes from NVRAM.
 575  */
 576 static int
 577 bge_read_nvram(struct bge_softc *sc, caddr_t dest, int off, int cnt)
 578 {
 579         int err = 0, i;
 580         uint8_t byte = 0;
 581
 582         if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
 583                 return (1);
 584
 585         for (i = 0; i < cnt; i++) {
 586                 err = bge_nvram_getbyte(sc, off + i, &byte);
 587                 if (err)
 588                         break;
 589                 *(dest + i) = byte;
 590         }
 591
 592         return (err ? 1 : 0);
 593 }
 594
 595 /*
 596  * Read a byte of data stored in the EEPROM at address 'addr.' The
 597  * BCM570x supports both the traditional bitbang interface and an
 598  * auto access interface for reading the EEPROM. We use the auto
 599  * access method.
 600  */
 601 static uint8_t
 602 bge_eeprom_getbyte(struct bge_softc *sc, uint32_t addr, uint8_t *dest)
 603 {
 604         int i;
 605         uint32_t byte = 0;
 606
 607         /*
 608          * Enable use of auto EEPROM access so we can avoid
 609          * having to use the bitbang method.
 610          */
 611         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
 612
 613         /* Reset the EEPROM, load the clock period. */
 614         CSR_WRITE_4(sc, BGE_EE_ADDR,
 615             BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
 616         DELAY(20);
 617
 618         /* Issue the read EEPROM command. */
 619         CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
 620
 621         /* Wait for completion */
 622         for(i = 0; i < BGE_TIMEOUT * 10; i++) {
 623                 DELAY(10);
 624                 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
 625                         break;
 626         }
 627
 628         if (i == BGE_TIMEOUT) {
 629                 if_printf(&sc->arpcom.ac_if, "eeprom read timed out\n");
 630                 return(1);
 631         }
 632
 633         /* Get result. */
 634         byte = CSR_READ_4(sc, BGE_EE_DATA);
 635
 636         *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
 637
 638         return(0);
 639 }
 640
 641 /*
 642  * Read a sequence of bytes from the EEPROM.
 643  */
 644 static int
 645 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, uint32_t off, size_t len)
 646 {
 647         size_t i;
 648         int err;
 649         uint8_t byte;
 650
 651         for (byte = 0, err = 0, i = 0; i < len; i++) {
 652                 err = bge_eeprom_getbyte(sc, off + i, &byte);
 653                 if (err)
 654                         break;
 655                 *(dest + i) = byte;
 656         }
 657
 658         return(err ? 1 : 0);
 659 }
 660
 661 static int
 662 bge_miibus_readreg(device_t dev, int phy, int reg)
 663 {
 664         struct bge_softc *sc = device_get_softc(dev);
 665         uint32_t val;
 666         int i;
 667
 668         KASSERT(phy == sc->bge_phyno,
 669             ("invalid phyno %d, should be %d", phy, sc->bge_phyno));
 670
 671         /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
 672         if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
 673                 CSR_WRITE_4(sc, BGE_MI_MODE,
 674                     sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL);
 675                 DELAY(80);
 676         }
 677
 678         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY |
 679             BGE_MIPHY(phy) | BGE_MIREG(reg));
 680
 681         /* Poll for the PHY register access to complete. */
 682         for (i = 0; i < BGE_TIMEOUT; i++) {
 683                 DELAY(10);
 684                 val = CSR_READ_4(sc, BGE_MI_COMM);
 685                 if ((val & BGE_MICOMM_BUSY) == 0) {
 686                         DELAY(5);
 687                         val = CSR_READ_4(sc, BGE_MI_COMM);
 688                         break;
 689                 }
 690         }
 691         if (i == BGE_TIMEOUT) {
 692                 if_printf(&sc->arpcom.ac_if, "PHY read timed out "
 693                     "(phy %d, reg %d, val 0x%08x)\n", phy, reg, val);
 694                 val = 0;
 695         }
 696
 697         /* Restore the autopoll bit if necessary. */
 698         if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
 699                 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
 700                 DELAY(80);
 701         }
 702
 703         if (val & BGE_MICOMM_READFAIL)
 704                 return 0;
 705
 706         return (val & 0xFFFF);
 707 }
 708
 709 static int
 710 bge_miibus_writereg(device_t dev, int phy, int reg, int val)
 711 {
 712         struct bge_softc *sc = device_get_softc(dev);
 713         int i;
 714
 715         KASSERT(phy == sc->bge_phyno,
 716             ("invalid phyno %d, should be %d", phy, sc->bge_phyno));
 717
 718         if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
 719             (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL))
 720                return 0;
 721
 722         /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
 723         if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
 724                 CSR_WRITE_4(sc, BGE_MI_MODE,
 725                     sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL);
 726                 DELAY(80);
 727         }
 728
 729         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY |
 730             BGE_MIPHY(phy) | BGE_MIREG(reg) | val);
 731
 732         for (i = 0; i < BGE_TIMEOUT; i++) {
 733                 DELAY(10);
 734                 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) {
 735                         DELAY(5);
 736                         CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */
 737                         break;
 738                 }
 739         }
 740         if (i == BGE_TIMEOUT) {
 741                 if_printf(&sc->arpcom.ac_if, "PHY write timed out "
 742                     "(phy %d, reg %d, val %d)\n", phy, reg, val);
 743         }
 744
 745         /* Restore the autopoll bit if necessary. */
 746         if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
 747                 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
 748                 DELAY(80);
 749         }
 750
 751         return 0;
 752 }
 753
 754 static void
 755 bge_miibus_statchg(device_t dev)
 756 {
 757         struct bge_softc *sc;
 758         struct mii_data *mii;
 759
 760         sc = device_get_softc(dev);
 761         mii = device_get_softc(sc->bge_miibus);
 762
 763         if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
 764             (IFM_ACTIVE | IFM_AVALID)) {
 765                 switch (IFM_SUBTYPE(mii->mii_media_active)) {
 766                 case IFM_10_T:
 767                 case IFM_100_TX:
 768                         sc->bge_link = 1;
 769                         break;
 770                 case IFM_1000_T:
 771                 case IFM_1000_SX:
 772                 case IFM_2500_SX:
 773                         if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
 774                                 sc->bge_link = 1;
 775                         else
 776                                 sc->bge_link = 0;
 777                         break;
 778                 default:
 779                         sc->bge_link = 0;
 780                         break;
 781                 }
 782         } else {
 783                 sc->bge_link = 0;
 784         }
 785         if (sc->bge_link == 0)
 786                 return;
 787
 788         BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE);
 789         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
 790             IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) {
 791                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII);
 792         } else {
 793                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII);
 794         }
 795
 796         if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
 797                 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
 798         } else {
 799                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
 800         }
 801 }
 802
 803 /*
 804  * Memory management for jumbo frames.
 805  */
 806 static int
 807 bge_alloc_jumbo_mem(struct bge_softc *sc)
 808 {
 809         struct ifnet *ifp = &sc->arpcom.ac_if;
 810         struct bge_jslot *entry;
 811         uint8_t *ptr;
 812         bus_addr_t paddr;
 813         int i, error;
 814
 815         /*
 816          * Create tag for jumbo mbufs.
 817          * This is really a bit of a kludge. We allocate a special
 818          * jumbo buffer pool which (thanks to the way our DMA
 819          * memory allocation works) will consist of contiguous
 820          * pages. This means that even though a jumbo buffer might
 821          * be larger than a page size, we don't really need to
 822          * map it into more than one DMA segment. However, the
 823          * default mbuf tag will result in multi-segment mappings,
 824          * so we have to create a special jumbo mbuf tag that
 825          * lets us get away with mapping the jumbo buffers as
 826          * a single segment. I think eventually the driver should
 827          * be changed so that it uses ordinary mbufs and cluster
 828          * buffers, i.e. jumbo frames can span multiple DMA
 829          * descriptors. But that's a project for another day.
 830          */
 831
 832         /*
 833          * Create DMA stuffs for jumbo RX ring.
 834          */
 835         error = bge_dma_block_alloc(sc, BGE_JUMBO_RX_RING_SZ,
 836                                     &sc->bge_cdata.bge_rx_jumbo_ring_tag,
 837                                     &sc->bge_cdata.bge_rx_jumbo_ring_map,
 838                                     (void *)&sc->bge_ldata.bge_rx_jumbo_ring,
 839                                     &sc->bge_ldata.bge_rx_jumbo_ring_paddr);
 840         if (error) {
 841                 if_printf(ifp, "could not create jumbo RX ring\n");
 842                 return error;
 843         }
 844
 845         /*
 846          * Create DMA stuffs for jumbo buffer block.
 847          */
 848         error = bge_dma_block_alloc(sc, BGE_JMEM,
 849                                     &sc->bge_cdata.bge_jumbo_tag,
 850                                     &sc->bge_cdata.bge_jumbo_map,
 851                                     (void **)&sc->bge_ldata.bge_jumbo_buf,
 852                                     &paddr);
 853         if (error) {
 854                 if_printf(ifp, "could not create jumbo buffer\n");
 855                 return error;
 856         }
 857
 858         SLIST_INIT(&sc->bge_jfree_listhead);
 859
 860         /*
 861          * Now divide it up into 9K pieces and save the addresses
 862          * in an array. Note that we play an evil trick here by using
 863          * the first few bytes in the buffer to hold the the address
 864          * of the softc structure for this interface. This is because
 865          * bge_jfree() needs it, but it is called by the mbuf management
 866          * code which will not pass it to us explicitly.
 867          */
 868         for (i = 0, ptr = sc->bge_ldata.bge_jumbo_buf; i < BGE_JSLOTS; i++) {
 869                 entry = &sc->bge_cdata.bge_jslots[i];
 870                 entry->bge_sc = sc;
 871                 entry->bge_buf = ptr;
 872                 entry->bge_paddr = paddr;
 873                 entry->bge_inuse = 0;
 874                 entry->bge_slot = i;
 875                 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jslot_link);
 876
 877                 ptr += BGE_JLEN;
 878                 paddr += BGE_JLEN;
 879         }
 880         return 0;
 881 }
 882
 883 static void
 884 bge_free_jumbo_mem(struct bge_softc *sc)
 885 {
 886         /* Destroy jumbo RX ring. */
 887         bge_dma_block_free(sc->bge_cdata.bge_rx_jumbo_ring_tag,
 888                            sc->bge_cdata.bge_rx_jumbo_ring_map,
 889                            sc->bge_ldata.bge_rx_jumbo_ring);
 890
 891         /* Destroy jumbo buffer block. */
 892         bge_dma_block_free(sc->bge_cdata.bge_jumbo_tag,
 893                            sc->bge_cdata.bge_jumbo_map,
 894                            sc->bge_ldata.bge_jumbo_buf);
 895 }
 896
 897 /*
 898  * Allocate a jumbo buffer.
 899  */
 900 static struct bge_jslot *
 901 bge_jalloc(struct bge_softc *sc)
 902 {
 903         struct bge_jslot *entry;
 904
 905         lwkt_serialize_enter(&sc->bge_jslot_serializer);
 906         entry = SLIST_FIRST(&sc->bge_jfree_listhead);
 907         if (entry) {
 908                 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jslot_link);
 909                 entry->bge_inuse = 1;
 910         } else {
 911                 if_printf(&sc->arpcom.ac_if, "no free jumbo buffers\n");
 912         }
 913         lwkt_serialize_exit(&sc->bge_jslot_serializer);
 914         return(entry);
 915 }
 916
 917 /*
 918  * Adjust usage count on a jumbo buffer.
 919  */
 920 static void
 921 bge_jref(void *arg)
 922 {
 923         struct bge_jslot *entry = (struct bge_jslot *)arg;
 924         struct bge_softc *sc = entry->bge_sc;
 925
 926         if (sc == NULL)
 927                 panic("bge_jref: can't find softc pointer!");
 928
 929         if (&sc->bge_cdata.bge_jslots[entry->bge_slot] != entry) {
 930                 panic("bge_jref: asked to reference buffer "
 931                     "that we don't manage!");
 932         } else if (entry->bge_inuse == 0) {
 933                 panic("bge_jref: buffer already free!");
 934         } else {
 935                 atomic_add_int(&entry->bge_inuse, 1);
 936         }
 937 }
 938
 939 /*
 940  * Release a jumbo buffer.
 941  */
 942 static void
 943 bge_jfree(void *arg)
 944 {
 945         struct bge_jslot *entry = (struct bge_jslot *)arg;
 946         struct bge_softc *sc = entry->bge_sc;
 947
 948         if (sc == NULL)
 949                 panic("bge_jfree: can't find softc pointer!");
 950
 951         if (&sc->bge_cdata.bge_jslots[entry->bge_slot] != entry) {
 952                 panic("bge_jfree: asked to free buffer that we don't manage!");
 953         } else if (entry->bge_inuse == 0) {
 954                 panic("bge_jfree: buffer already free!");
 955         } else {
 956                 /*
 957                  * Possible MP race to 0, use the serializer.  The atomic insn
 958                  * is still needed for races against bge_jref().
 959                  */
 960                 lwkt_serialize_enter(&sc->bge_jslot_serializer);
 961                 atomic_subtract_int(&entry->bge_inuse, 1);
 962                 if (entry->bge_inuse == 0) {
 963                         SLIST_INSERT_HEAD(&sc->bge_jfree_listhead,
 964                                           entry, jslot_link);
 965                 }
 966                 lwkt_serialize_exit(&sc->bge_jslot_serializer);
 967         }
 968 }
 969
 970
 971 /*
 972  * Intialize a standard receive ring descriptor.
 973  */
 974 static int
 975 bge_newbuf_std(struct bge_softc *sc, int i, int init)
 976 {
 977         struct mbuf *m_new = NULL;
 978         bus_dma_segment_t seg;
 979         bus_dmamap_t map;
 980         int error, nsegs;
 981
 982         m_new = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
 983         if (m_new == NULL)
 984                 return ENOBUFS;
 985         m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
 986
 987         if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
 988                 m_adj(m_new, ETHER_ALIGN);
 989
 990         error = bus_dmamap_load_mbuf_segment(sc->bge_cdata.bge_rx_mtag,
 991                         sc->bge_cdata.bge_rx_tmpmap, m_new,
 992                         &seg, 1, &nsegs, BUS_DMA_NOWAIT);
 993         if (error) {
 994                 m_freem(m_new);
 995                 return error;
 996         }
 997
 998         if (!init) {
 999                 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
1000                                 sc->bge_cdata.bge_rx_std_dmamap[i],
1001                                 BUS_DMASYNC_POSTREAD);
1002                 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
1003                         sc->bge_cdata.bge_rx_std_dmamap[i]);
1004         }
1005
1006         map = sc->bge_cdata.bge_rx_tmpmap;
1007         sc->bge_cdata.bge_rx_tmpmap = sc->bge_cdata.bge_rx_std_dmamap[i];
1008         sc->bge_cdata.bge_rx_std_dmamap[i] = map;
1009
1010         sc->bge_cdata.bge_rx_std_chain[i].bge_mbuf = m_new;
1011         sc->bge_cdata.bge_rx_std_chain[i].bge_paddr = seg.ds_addr;
1012
1013         bge_setup_rxdesc_std(sc, i);
1014         return 0;
1015 }
1016
1017 static void
1018 bge_setup_rxdesc_std(struct bge_softc *sc, int i)
1019 {
1020         struct bge_rxchain *rc;
1021         struct bge_rx_bd *r;
1022
1023         rc = &sc->bge_cdata.bge_rx_std_chain[i];
1024         r = &sc->bge_ldata.bge_rx_std_ring[i];
1025
1026         r->bge_addr.bge_addr_lo = BGE_ADDR_LO(rc->bge_paddr);
1027         r->bge_addr.bge_addr_hi = BGE_ADDR_HI(rc->bge_paddr);
1028         r->bge_len = rc->bge_mbuf->m_len;
1029         r->bge_idx = i;
1030         r->bge_flags = BGE_RXBDFLAG_END;
1031 }
1032
1033 /*
1034  * Initialize a jumbo receive ring descriptor. This allocates
1035  * a jumbo buffer from the pool managed internally by the driver.
1036  */
1037 static int
1038 bge_newbuf_jumbo(struct bge_softc *sc, int i, int init)
1039 {
1040         struct mbuf *m_new = NULL;
1041         struct bge_jslot *buf;
1042         bus_addr_t paddr;
1043
1044         /* Allocate the mbuf. */
1045         MGETHDR(m_new, init ? MB_WAIT : MB_DONTWAIT, MT_DATA);
1046         if (m_new == NULL)
1047                 return ENOBUFS;
1048
1049         /* Allocate the jumbo buffer */
1050         buf = bge_jalloc(sc);
1051         if (buf == NULL) {
1052                 m_freem(m_new);
1053                 return ENOBUFS;
1054         }
1055
1056         /* Attach the buffer to the mbuf. */
1057         m_new->m_ext.ext_arg = buf;
1058         m_new->m_ext.ext_buf = buf->bge_buf;
1059         m_new->m_ext.ext_free = bge_jfree;
1060         m_new->m_ext.ext_ref = bge_jref;
1061         m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN;
1062
1063         m_new->m_flags |= M_EXT;
1064
1065         m_new->m_data = m_new->m_ext.ext_buf;
1066         m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size;
1067
1068         paddr = buf->bge_paddr;
1069         if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) {
1070                 m_adj(m_new, ETHER_ALIGN);
1071                 paddr += ETHER_ALIGN;
1072         }
1073
1074         /* Save necessary information */
1075         sc->bge_cdata.bge_rx_jumbo_chain[i].bge_mbuf = m_new;
1076         sc->bge_cdata.bge_rx_jumbo_chain[i].bge_paddr = paddr;
1077
1078         /* Set up the descriptor. */
1079         bge_setup_rxdesc_jumbo(sc, i);
1080         return 0;
1081 }
1082
1083 static void
1084 bge_setup_rxdesc_jumbo(struct bge_softc *sc, int i)
1085 {
1086         struct bge_rx_bd *r;
1087         struct bge_rxchain *rc;
1088
1089         r = &sc->bge_ldata.bge_rx_jumbo_ring[i];
1090         rc = &sc->bge_cdata.bge_rx_jumbo_chain[i];
1091
1092         r->bge_addr.bge_addr_lo = BGE_ADDR_LO(rc->bge_paddr);
1093         r->bge_addr.bge_addr_hi = BGE_ADDR_HI(rc->bge_paddr);
1094         r->bge_len = rc->bge_mbuf->m_len;
1095         r->bge_idx = i;
1096         r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING;
1097 }
1098
1099 static int
1100 bge_init_rx_ring_std(struct bge_softc *sc)
1101 {
1102         int i, error;
1103
1104         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1105                 error = bge_newbuf_std(sc, i, 1);
1106                 if (error)
1107                         return error;
1108         }
1109
1110         sc->bge_std = BGE_STD_RX_RING_CNT - 1;
1111         bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
1112
1113         return(0);
1114 }
1115
1116 static void
1117 bge_free_rx_ring_std(struct bge_softc *sc)
1118 {
1119         int i;
1120
1121         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1122                 struct bge_rxchain *rc = &sc->bge_cdata.bge_rx_std_chain[i];
1123
1124                 if (rc->bge_mbuf != NULL) {
1125                         bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
1126                                           sc->bge_cdata.bge_rx_std_dmamap[i]);
1127                         m_freem(rc->bge_mbuf);
1128                         rc->bge_mbuf = NULL;
1129                 }
1130                 bzero(&sc->bge_ldata.bge_rx_std_ring[i],
1131                     sizeof(struct bge_rx_bd));
1132         }
1133 }
1134
1135 static int
1136 bge_init_rx_ring_jumbo(struct bge_softc *sc)
1137 {
1138         struct bge_rcb *rcb;
1139         int i, error;
1140
1141         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1142                 error = bge_newbuf_jumbo(sc, i, 1);
1143                 if (error)
1144                         return error;
1145         }
1146
1147         sc->bge_jumbo = BGE_JUMBO_RX_RING_CNT - 1;
1148
1149         rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1150         rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 0);
1151         CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1152
1153         bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
1154
1155         return(0);
1156 }
1157
1158 static void
1159 bge_free_rx_ring_jumbo(struct bge_softc *sc)
1160 {
1161         int i;
1162
1163         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1164                 struct bge_rxchain *rc = &sc->bge_cdata.bge_rx_jumbo_chain[i];
1165
1166                 if (rc->bge_mbuf != NULL) {
1167                         m_freem(rc->bge_mbuf);
1168                         rc->bge_mbuf = NULL;
1169                 }
1170                 bzero(&sc->bge_ldata.bge_rx_jumbo_ring[i],
1171                     sizeof(struct bge_rx_bd));
1172         }
1173 }
1174
1175 static void
1176 bge_free_tx_ring(struct bge_softc *sc)
1177 {
1178         int i;
1179
1180         for (i = 0; i < BGE_TX_RING_CNT; i++) {
1181                 if (sc->bge_cdata.bge_tx_chain[i] != NULL) {
1182                         bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
1183                                           sc->bge_cdata.bge_tx_dmamap[i]);
1184                         m_freem(sc->bge_cdata.bge_tx_chain[i]);
1185                         sc->bge_cdata.bge_tx_chain[i] = NULL;
1186                 }
1187                 bzero(&sc->bge_ldata.bge_tx_ring[i],
1188                     sizeof(struct bge_tx_bd));
1189         }
1190 }
1191
1192 static int
1193 bge_init_tx_ring(struct bge_softc *sc)
1194 {
1195         sc->bge_txcnt = 0;
1196         sc->bge_tx_saved_considx = 0;
1197         sc->bge_tx_prodidx = 0;
1198
1199         /* Initialize transmit producer index for host-memory send ring. */
1200         bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1201
1202         /* 5700 b2 errata */
1203         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1204                 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1205
1206         bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1207         /* 5700 b2 errata */
1208         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1209                 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1210
1211         return(0);
1212 }
1213
1214 static void
1215 bge_setmulti(struct bge_softc *sc)
1216 {
1217         struct ifnet *ifp;
1218         struct ifmultiaddr *ifma;
1219         uint32_t hashes[4] = { 0, 0, 0, 0 };
1220         int h, i;
1221
1222         ifp = &sc->arpcom.ac_if;
1223
1224         if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
1225                 for (i = 0; i < 4; i++)
1226                         CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
1227                 return;
1228         }
1229
1230         /* First, zot all the existing filters. */
1231         for (i = 0; i < 4; i++)
1232                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
1233
1234         /* Now program new ones. */
1235         TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1236                 if (ifma->ifma_addr->sa_family != AF_LINK)
1237                         continue;
1238                 h = ether_crc32_le(
1239                     LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1240                     ETHER_ADDR_LEN) & 0x7f;
1241                 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
1242         }
1243
1244         for (i = 0; i < 4; i++)
1245                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
1246 }
1247
1248 /*
1249  * Do endian, PCI and DMA initialization. Also check the on-board ROM
1250  * self-test results.
1251  */
1252 static int
1253 bge_chipinit(struct bge_softc *sc)
1254 {
1255         int i;
1256         uint32_t dma_rw_ctl;
1257         uint16_t val;
1258
1259         /* Set endian type before we access any non-PCI registers. */
1260         pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL,
1261             BGE_INIT | sc->bge_pci_miscctl, 4);
1262
1263         /* Clear the MAC control register */
1264         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
1265
1266         /*
1267          * Clear the MAC statistics block in the NIC's
1268          * internal memory.
1269          */
1270         for (i = BGE_STATS_BLOCK;
1271             i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
1272                 BGE_MEMWIN_WRITE(sc, i, 0);
1273
1274         for (i = BGE_STATUS_BLOCK;
1275             i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
1276                 BGE_MEMWIN_WRITE(sc, i, 0);
1277
1278         if (sc->bge_chiprev == BGE_CHIPREV_5704_BX) {
1279                 /*
1280                  * Fix data corruption caused by non-qword write with WB.
1281                  * Fix master abort in PCI mode.
1282                  * Fix PCI latency timer.
1283                  */
1284                 val = pci_read_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, 2);
1285                 val |= (1 << 10) | (1 << 12) | (1 << 13);
1286                 pci_write_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, val, 2);
1287         }
1288
1289         /* Set up the PCI DMA control register. */
1290         dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD;
1291         if (sc->bge_flags & BGE_FLAG_PCIE) {
1292                 /* PCI-E bus */
1293                 /* DMA read watermark not used on PCI-E */
1294                 dma_rw_ctl |= (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1295         } else if (sc->bge_flags & BGE_FLAG_PCIX) {
1296                 /* PCI-X bus */
1297                 if (sc->bge_asicrev == BGE_ASICREV_BCM5780) {
1298                         dma_rw_ctl |= (0x4 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1299                             (0x2 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1300                         dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL;
1301                 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5714) {
1302                         dma_rw_ctl |= (0x4 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1303                             (0x2 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1304                         dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL;
1305                 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1306                     sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1307                         uint32_t rd_wat = 0x7;
1308                         uint32_t clkctl;
1309
1310                         clkctl = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f;
1311                         if ((sc->bge_flags & BGE_FLAG_MAXADDR_40BIT) &&
1312                             sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1313                                 dma_rw_ctl |=
1314                                     BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL;
1315                         } else if (clkctl == 0x6 || clkctl == 0x7) {
1316                                 dma_rw_ctl |=
1317                                     BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL;
1318                         }
1319                         if (sc->bge_asicrev == BGE_ASICREV_BCM5703)
1320                                 rd_wat = 0x4;
1321
1322                         dma_rw_ctl |= (rd_wat << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1323                             (3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1324                         dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE;
1325                 } else {
1326                         dma_rw_ctl |= (0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1327                             (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1328                         dma_rw_ctl |= 0xf;
1329                 }
1330         } else {
1331                 /* Conventional PCI bus */
1332                 dma_rw_ctl |= (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1333                     (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1334                 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1335                     sc->bge_asicrev != BGE_ASICREV_BCM5750)
1336                         dma_rw_ctl |= 0xf;
1337         }
1338
1339         if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1340             sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1341                 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
1342         } else if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
1343             sc->bge_asicrev == BGE_ASICREV_BCM5701) {
1344                 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM |
1345                     BGE_PCIDMARWCTL_ASRT_ALL_BE;
1346         }
1347         pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1348
1349         /*
1350          * Set up general mode register.
1351          */
1352         CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS|
1353             BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS|
1354             BGE_MODECTL_TX_NO_PHDR_CSUM);
1355
1356         /*
1357          * BCM5701 B5 have a bug causing data corruption when using
1358          * 64-bit DMA reads, which can be terminated early and then
1359          * completed later as 32-bit accesses, in combination with
1360          * certain bridges.
1361          */
1362         if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
1363             sc->bge_chipid == BGE_CHIPID_BCM5701_B5)
1364                 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_FORCE_PCI32);
1365
1366         /*
1367          * Disable memory write invalidate.  Apparently it is not supported
1368          * properly by these devices.  Also ensure that INTx isn't disabled,
1369          * as these chips need it even when using MSI.
1370          */
1371         PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD,
1372             (PCIM_CMD_MWRICEN | PCIM_CMD_INTxDIS), 4);
1373
1374         /* Set the timer prescaler (always 66Mhz) */
1375         CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/);
1376
1377         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1378                 DELAY(40);      /* XXX */
1379
1380                 /* Put PHY into ready state */
1381                 BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ);
1382                 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */
1383                 DELAY(40);
1384         }
1385
1386         return(0);
1387 }
1388
1389 static int
1390 bge_blockinit(struct bge_softc *sc)
1391 {
1392         struct bge_rcb *rcb;
1393         bus_size_t vrcb;
1394         bge_hostaddr taddr;
1395         uint32_t val;
1396         int i, limit;
1397
1398         /*
1399          * Initialize the memory window pointer register so that
1400          * we can access the first 32K of internal NIC RAM. This will
1401          * allow us to set up the TX send ring RCBs and the RX return
1402          * ring RCBs, plus other things which live in NIC memory.
1403          */
1404         CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1405
1406         /* Note: the BCM5704 has a smaller mbuf space than other chips. */
1407
1408         if (!BGE_IS_5705_PLUS(sc)) {
1409                 /* Configure mbuf memory pool */
1410                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1);
1411                 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1412                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
1413                 else
1414                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
1415
1416                 /* Configure DMA resource pool */
1417                 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,
1418                     BGE_DMA_DESCRIPTORS);
1419                 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
1420         }
1421
1422         /* Configure mbuf pool watermarks */
1423         if (!BGE_IS_5705_PLUS(sc)) {
1424                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50);
1425                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20);
1426                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1427         } else if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1428                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1429                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04);
1430                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10);
1431         } else {
1432                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1433                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
1434                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1435         }
1436
1437         /* Configure DMA resource watermarks */
1438         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
1439         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
1440
1441         /* Enable buffer manager */
1442         CSR_WRITE_4(sc, BGE_BMAN_MODE,
1443             BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN);
1444
1445         /* Poll for buffer manager start indication */
1446         for (i = 0; i < BGE_TIMEOUT; i++) {
1447                 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
1448                         break;
1449                 DELAY(10);
1450         }
1451
1452         if (i == BGE_TIMEOUT) {
1453                 if_printf(&sc->arpcom.ac_if,
1454                           "buffer manager failed to start\n");
1455                 return(ENXIO);
1456         }
1457
1458         /* Enable flow-through queues */
1459         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
1460         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
1461
1462         /* Wait until queue initialization is complete */
1463         for (i = 0; i < BGE_TIMEOUT; i++) {
1464                 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
1465                         break;
1466                 DELAY(10);
1467         }
1468
1469         if (i == BGE_TIMEOUT) {
1470                 if_printf(&sc->arpcom.ac_if,
1471                           "flow-through queue init failed\n");
1472                 return(ENXIO);
1473         }
1474
1475         /*
1476          * Summary of rings supported by the controller:
1477          *
1478          * Standard Receive Producer Ring
1479          * - This ring is used to feed receive buffers for "standard"
1480          *   sized frames (typically 1536 bytes) to the controller.
1481          *
1482          * Jumbo Receive Producer Ring
1483          * - This ring is used to feed receive buffers for jumbo sized
1484          *   frames (i.e. anything bigger than the "standard" frames)
1485          *   to the controller.
1486          *
1487          * Mini Receive Producer Ring
1488          * - This ring is used to feed receive buffers for "mini"
1489          *   sized frames to the controller.
1490          * - This feature required external memory for the controller
1491          *   but was never used in a production system.  Should always
1492          *   be disabled.
1493          *
1494          * Receive Return Ring
1495          * - After the controller has placed an incoming frame into a
1496          *   receive buffer that buffer is moved into a receive return
1497          *   ring.  The driver is then responsible to passing the
1498          *   buffer up to the stack.  Many versions of the controller
1499          *   support multiple RR rings.
1500          *
1501          * Send Ring
1502          * - This ring is used for outgoing frames.  Many versions of
1503          *   the controller support multiple send rings.
1504          */
1505
1506         /* Initialize the standard receive producer ring control block. */
1507         rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb;
1508         rcb->bge_hostaddr.bge_addr_lo =
1509             BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr);
1510         rcb->bge_hostaddr.bge_addr_hi =
1511             BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr);
1512         if (BGE_IS_5705_PLUS(sc)) {
1513                 /*
1514                  * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32)
1515                  * Bits 15-2 : Reserved (should be 0)
1516                  * Bit 1     : 1 = Ring Disabled, 0 = Ring Enabled
1517                  * Bit 0     : Reserved
1518                  */
1519                 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
1520         } else {
1521                 /*
1522                  * Ring size is always XXX entries
1523                  * Bits 31-16: Maximum RX frame size
1524                  * Bits 15-2 : Reserved (should be 0)
1525                  * Bit 1     : 1 = Ring Disabled, 0 = Ring Enabled
1526                  * Bit 0     : Reserved
1527                  */
1528                 rcb->bge_maxlen_flags =
1529                     BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0);
1530         }
1531         rcb->bge_nicaddr = BGE_STD_RX_RINGS;
1532         /* Write the standard receive producer ring control block. */
1533         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
1534         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
1535         CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1536         CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
1537         /* Reset the standard receive producer ring producer index. */
1538         bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0);
1539
1540         /*
1541          * Initialize the jumbo RX producer ring control
1542          * block.  We set the 'ring disabled' bit in the
1543          * flags field until we're actually ready to start
1544          * using this ring (i.e. once we set the MTU
1545          * high enough to require it).
1546          */
1547         if (BGE_IS_JUMBO_CAPABLE(sc)) {
1548                 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1549                 /* Get the jumbo receive producer ring RCB parameters. */
1550                 rcb->bge_hostaddr.bge_addr_lo =
1551                     BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1552                 rcb->bge_hostaddr.bge_addr_hi =
1553                     BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1554                 rcb->bge_maxlen_flags =
1555                     BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN,
1556                     BGE_RCB_FLAG_RING_DISABLED);
1557                 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
1558                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
1559                     rcb->bge_hostaddr.bge_addr_hi);
1560                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
1561                     rcb->bge_hostaddr.bge_addr_lo);
1562                 /* Program the jumbo receive producer ring RCB parameters. */
1563                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
1564                     rcb->bge_maxlen_flags);
1565                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
1566                 /* Reset the jumbo receive producer ring producer index. */
1567                 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
1568         }
1569
1570         /* Disable the mini receive producer ring RCB. */
1571         if (BGE_IS_5700_FAMILY(sc)) {
1572                 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb;
1573                 rcb->bge_maxlen_flags =
1574                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);
1575                 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS,
1576                     rcb->bge_maxlen_flags);
1577                 /* Reset the mini receive producer ring producer index. */
1578                 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0);
1579         }
1580
1581         /* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */
1582         if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
1583             (sc->bge_chipid == BGE_CHIPID_BCM5906_A0 ||
1584              sc->bge_chipid == BGE_CHIPID_BCM5906_A1 ||
1585              sc->bge_chipid == BGE_CHIPID_BCM5906_A2)) {
1586                 CSR_WRITE_4(sc, BGE_ISO_PKT_TX,
1587                     (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2);
1588         }
1589
1590         /*
1591          * The BD ring replenish thresholds control how often the
1592          * hardware fetches new BD's from the producer rings in host
1593          * memory.  Setting the value too low on a busy system can
1594          * starve the hardware and recue the throughpout.
1595          *
1596          * Set the BD ring replentish thresholds. The recommended
1597          * values are 1/8th the number of descriptors allocated to
1598          * each ring.
1599          */
1600         if (BGE_IS_5705_PLUS(sc))
1601                 val = 8;
1602         else
1603                 val = BGE_STD_RX_RING_CNT / 8;
1604         CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val);
1605         if (BGE_IS_JUMBO_CAPABLE(sc)) {
1606                 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH,
1607                     BGE_JUMBO_RX_RING_CNT/8);
1608         }
1609
1610         /*
1611          * Disable all send rings by setting the 'ring disabled' bit
1612          * in the flags field of all the TX send ring control blocks,
1613          * located in NIC memory.
1614          */
1615         if (!BGE_IS_5705_PLUS(sc)) {
1616                 /* 5700 to 5704 had 16 send rings. */
1617                 limit = BGE_TX_RINGS_EXTSSRAM_MAX;
1618         } else {
1619                 limit = 1;
1620         }
1621         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1622         for (i = 0; i < limit; i++) {
1623                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1624                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED));
1625                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1626                 vrcb += sizeof(struct bge_rcb);
1627         }
1628
1629         /* Configure send ring RCB 0 (we use only the first ring) */
1630         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1631         BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr);
1632         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1633         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1634         RCB_WRITE_4(sc, vrcb, bge_nicaddr,
1635             BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT));
1636         RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1637             BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
1638
1639         /*
1640          * Disable all receive return rings by setting the
1641          * 'ring diabled' bit in the flags field of all the receive
1642          * return ring control blocks, located in NIC memory.
1643          */
1644         if (!BGE_IS_5705_PLUS(sc))
1645                 limit = BGE_RX_RINGS_MAX;
1646         else if (sc->bge_asicrev == BGE_ASICREV_BCM5755)
1647                 limit = 4;
1648         else
1649                 limit = 1;
1650         /* Disable all receive return rings. */
1651         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1652         for (i = 0; i < limit; i++) {
1653                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0);
1654                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0);
1655                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1656                     BGE_RCB_FLAG_RING_DISABLED);
1657                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1658                 bge_writembx(sc, BGE_MBX_RX_CONS0_LO +
1659                     (i * (sizeof(uint64_t))), 0);
1660                 vrcb += sizeof(struct bge_rcb);
1661         }
1662
1663         /*
1664          * Set up receive return ring 0.  Note that the NIC address
1665          * for RX return rings is 0x0.  The return rings live entirely
1666          * within the host, so the nicaddr field in the RCB isn't used.
1667          */
1668         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1669         BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr);
1670         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1671         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1672         RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1673         RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1674             BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0));
1675
1676         /* Set random backoff seed for TX */
1677         CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
1678             sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] +
1679             sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] +
1680             sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5] +
1681             BGE_TX_BACKOFF_SEED_MASK);
1682
1683         /* Set inter-packet gap */
1684         CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620);
1685
1686         /*
1687          * Specify which ring to use for packets that don't match
1688          * any RX rules.
1689          */
1690         CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
1691
1692         /*
1693          * Configure number of RX lists. One interrupt distribution
1694          * list, sixteen active lists, one bad frames class.
1695          */
1696         CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
1697
1698         /* Inialize RX list placement stats mask. */
1699         CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
1700         CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
1701
1702         /* Disable host coalescing until we get it set up */
1703         CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
1704
1705         /* Poll to make sure it's shut down. */
1706         for (i = 0; i < BGE_TIMEOUT; i++) {
1707                 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
1708                         break;
1709                 DELAY(10);
1710         }
1711
1712         if (i == BGE_TIMEOUT) {
1713                 if_printf(&sc->arpcom.ac_if,
1714                           "host coalescing engine failed to idle\n");
1715                 return(ENXIO);
1716         }
1717
1718         /* Set up host coalescing defaults */
1719         CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks);
1720         CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
1721         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_coal_bds);
1722         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_coal_bds);
1723         if (!BGE_IS_5705_PLUS(sc)) {
1724                 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT,
1725                     sc->bge_rx_coal_ticks_int);
1726                 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT,
1727                     sc->bge_tx_coal_ticks_int);
1728         }
1729         /*
1730          * NOTE:
1731          * The datasheet (57XX-PG105-R) says BCM5705+ do not
1732          * have following two registers; obviously it is wrong.
1733          */
1734         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, sc->bge_rx_coal_bds_int);
1735         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, sc->bge_tx_coal_bds_int);
1736
1737         /* Set up address of statistics block */
1738         if (!BGE_IS_5705_PLUS(sc)) {
1739                 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI,
1740                     BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr));
1741                 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO,
1742                     BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr));
1743
1744                 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);
1745                 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK);
1746                 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);
1747         }
1748
1749         /* Set up address of status block */
1750         bzero(sc->bge_ldata.bge_status_block, BGE_STATUS_BLK_SZ);
1751         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI,
1752             BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr));
1753         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
1754             BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr));
1755
1756         /*
1757          * Set up status block partail update size.
1758          *
1759          * Because only single TX ring, RX produce ring and Rx return ring
1760          * are used, ask device to update only minimum part of status block
1761          * except for BCM5700 AX/BX, whose status block partial update size
1762          * can't be configured.
1763          */
1764         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
1765             sc->bge_chipid != BGE_CHIPID_BCM5700_C0) {
1766                 /* XXX Actually reserved on BCM5700 AX/BX */
1767                 val = BGE_STATBLKSZ_FULL;
1768         } else {
1769                 val = BGE_STATBLKSZ_32BYTE;
1770         }
1771 #if 0
1772         /*
1773          * Does not seem to have visible effect in both
1774          * bulk data (1472B UDP datagram) and tiny data
1775          * (18B UDP datagram) TX tests.
1776          */
1777         if (!BGE_IS_CRIPPLED(sc))
1778                 val |= BGE_HCCMODE_CLRTICK_TX;
1779 #endif
1780
1781         /* Turn on host coalescing state machine */
1782         CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE);
1783
1784         /* Turn on RX BD completion state machine and enable attentions */
1785         CSR_WRITE_4(sc, BGE_RBDC_MODE,
1786             BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN);
1787
1788         /* Turn on RX list placement state machine */
1789         CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
1790
1791         /* Turn on RX list selector state machine. */
1792         if (!BGE_IS_5705_PLUS(sc))
1793                 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
1794
1795         val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB |
1796             BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR |
1797             BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB |
1798             BGE_MACMODE_FRMHDR_DMA_ENB;
1799
1800         if (sc->bge_flags & BGE_FLAG_TBI)
1801                 val |= BGE_PORTMODE_TBI;
1802         else if (sc->bge_flags & BGE_FLAG_MII_SERDES)
1803                 val |= BGE_PORTMODE_GMII;
1804         else
1805                 val |= BGE_PORTMODE_MII;
1806
1807         /* Turn on DMA, clear stats */
1808         CSR_WRITE_4(sc, BGE_MAC_MODE, val);
1809
1810         /* Set misc. local control, enable interrupts on attentions */
1811         CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
1812
1813 #ifdef notdef
1814         /* Assert GPIO pins for PHY reset */
1815         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0|
1816             BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2);
1817         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0|
1818             BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2);
1819 #endif
1820
1821         /* Turn on DMA completion state machine */
1822         if (!BGE_IS_5705_PLUS(sc))
1823                 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
1824
1825         /* Turn on write DMA state machine */
1826         val = BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS;
1827         if (BGE_IS_5755_PLUS(sc)) {
1828                 /* Enable host coalescing bug fix. */
1829                 val |= BGE_WDMAMODE_STATUS_TAG_FIX;
1830         }
1831         if (sc->bge_asicrev == BGE_ASICREV_BCM5785) {
1832                 /* Request larger DMA burst size to get better performance. */
1833                 val |= BGE_WDMAMODE_BURST_ALL_DATA;
1834         }
1835         CSR_WRITE_4(sc, BGE_WDMA_MODE, val);
1836         DELAY(40);
1837
1838         if (sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
1839             sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
1840             sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
1841             sc->bge_asicrev == BGE_ASICREV_BCM57780) {
1842                 /*
1843                  * Enable fix for read DMA FIFO overruns.
1844                  * The fix is to limit the number of RX BDs
1845                  * the hardware would fetch at a fime.
1846                  */
1847                 val = CSR_READ_4(sc, BGE_RDMA_RSRVCTRL);
1848                 CSR_WRITE_4(sc, BGE_RDMA_RSRVCTRL,
1849                     val| BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
1850         }
1851
1852         /* Turn on read DMA state machine */
1853         val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS;
1854         if (sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
1855             sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
1856             sc->bge_asicrev == BGE_ASICREV_BCM57780)
1857                 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN |
1858                   BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN |
1859                   BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN;
1860         if (sc->bge_flags & BGE_FLAG_PCIE)
1861                 val |= BGE_RDMAMODE_FIFO_LONG_BURST;
1862         if (sc->bge_flags & BGE_FLAG_TSO)
1863                 val |= BGE_RDMAMODE_TSO4_ENABLE;
1864         CSR_WRITE_4(sc, BGE_RDMA_MODE, val);
1865         DELAY(40);
1866
1867         /* Turn on RX data completion state machine */
1868         CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
1869
1870         /* Turn on RX BD initiator state machine */
1871         CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
1872
1873         /* Turn on RX data and RX BD initiator state machine */
1874         CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
1875
1876         /* Turn on Mbuf cluster free state machine */
1877         if (!BGE_IS_5705_PLUS(sc))
1878                 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
1879
1880         /* Turn on send BD completion state machine */
1881         CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
1882
1883         /* Turn on send data completion state machine */
1884         val = BGE_SDCMODE_ENABLE;
1885         if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
1886                 val |= BGE_SDCMODE_CDELAY;
1887         CSR_WRITE_4(sc, BGE_SDC_MODE, val);
1888
1889         /* Turn on send data initiator state machine */
1890         if (sc->bge_flags & BGE_FLAG_TSO)
1891                 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE |
1892                     BGE_SDIMODE_HW_LSO_PRE_DMA);
1893         else
1894                 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
1895
1896         /* Turn on send BD initiator state machine */
1897         CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
1898
1899         /* Turn on send BD selector state machine */
1900         CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
1901
1902         CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
1903         CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
1904             BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER);
1905
1906         /* ack/clear link change events */
1907         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1908             BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1909             BGE_MACSTAT_LINK_CHANGED);
1910         CSR_WRITE_4(sc, BGE_MI_STS, 0);
1911
1912         /*
1913          * Enable attention when the link has changed state for
1914          * devices that use auto polling.
1915          */
1916         if (sc->bge_flags & BGE_FLAG_TBI) {
1917                 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
1918         } else {
1919                 if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
1920                         CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
1921                         DELAY(80);
1922                 }
1923                 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
1924                     sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
1925                         CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
1926                             BGE_EVTENB_MI_INTERRUPT);
1927                 }
1928         }
1929
1930         /*
1931          * Clear any pending link state attention.
1932          * Otherwise some link state change events may be lost until attention
1933          * is cleared by bge_intr() -> bge_softc.bge_link_upd() sequence.
1934          * It's not necessary on newer BCM chips - perhaps enabling link
1935          * state change attentions implies clearing pending attention.
1936          */
1937         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1938             BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1939             BGE_MACSTAT_LINK_CHANGED);
1940
1941         /* Enable link state change attentions. */
1942         BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
1943
1944         return(0);
1945 }
1946
1947 /*
1948  * Probe for a Broadcom chip. Check the PCI vendor and device IDs
1949  * against our list and return its name if we find a match. Note
1950  * that since the Broadcom controller contains VPD support, we
1951  * can get the device name string from the controller itself instead
1952  * of the compiled-in string. This is a little slow, but it guarantees
1953  * we'll always announce the right product name.
1954  */
1955 static int
1956 bge_probe(device_t dev)
1957 {
1958         const struct bge_type *t;
1959         uint16_t product, vendor;
1960
1961         product = pci_get_device(dev);
1962         vendor = pci_get_vendor(dev);
1963
1964         for (t = bge_devs; t->bge_name != NULL; t++) {
1965                 if (vendor == t->bge_vid && product == t->bge_did)
1966                         break;
1967         }
1968         if (t->bge_name == NULL)
1969                 return(ENXIO);
1970
1971         device_set_desc(dev, t->bge_name);
1972         return(0);
1973 }
1974
1975 static int
1976 bge_attach(device_t dev)
1977 {
1978         struct ifnet *ifp;
1979         struct bge_softc *sc;
1980         uint32_t hwcfg = 0, misccfg;
1981         int error = 0, rid, capmask;
1982         uint8_t ether_addr[ETHER_ADDR_LEN];
1983         uint16_t product, vendor;
1984         driver_intr_t *intr_func;
1985         uintptr_t mii_priv = 0;
1986         u_int intr_flags;
1987         int msi_enable;
1988
1989         sc = device_get_softc(dev);
1990         sc->bge_dev = dev;
1991         callout_init_mp(&sc->bge_stat_timer);
1992         lwkt_serialize_init(&sc->bge_jslot_serializer);
1993
1994         product = pci_get_device(dev);
1995         vendor = pci_get_vendor(dev);
1996
1997 #ifndef BURN_BRIDGES
1998         if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1999                 uint32_t irq, mem;
2000
2001                 irq = pci_read_config(dev, PCIR_INTLINE, 4);
2002                 mem = pci_read_config(dev, BGE_PCI_BAR0, 4);
2003
2004                 device_printf(dev, "chip is in D%d power mode "
2005                     "-- setting to D0\n", pci_get_powerstate(dev));
2006
2007                 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
2008
2009                 pci_write_config(dev, PCIR_INTLINE, irq, 4);
2010                 pci_write_config(dev, BGE_PCI_BAR0, mem, 4);
2011         }
2012 #endif  /* !BURN_BRIDGE */
2013
2014         /*
2015          * Map control/status registers.
2016          */
2017         pci_enable_busmaster(dev);
2018
2019         rid = BGE_PCI_BAR0;
2020         sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
2021             RF_ACTIVE);
2022
2023         if (sc->bge_res == NULL) {
2024                 device_printf(dev, "couldn't map memory\n");
2025                 return ENXIO;
2026         }
2027
2028         sc->bge_btag = rman_get_bustag(sc->bge_res);
2029         sc->bge_bhandle = rman_get_bushandle(sc->bge_res);
2030
2031         /* Save various chip information */
2032         sc->bge_chipid =
2033             pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >>
2034             BGE_PCIMISCCTL_ASICREV_SHIFT;
2035         if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_USE_PRODID_REG) {
2036                 /* All chips, which use BGE_PCI_PRODID_ASICREV, have CPMU */
2037                 sc->bge_flags |= BGE_FLAG_CPMU;
2038                 sc->bge_chipid = pci_read_config(dev, BGE_PCI_PRODID_ASICREV, 4);
2039         }
2040         sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid);
2041         sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid);
2042
2043         /* Save chipset family. */
2044         switch (sc->bge_asicrev) {
2045         case BGE_ASICREV_BCM5755:
2046         case BGE_ASICREV_BCM5761:
2047         case BGE_ASICREV_BCM5784:
2048         case BGE_ASICREV_BCM5785:
2049         case BGE_ASICREV_BCM5787:
2050         case BGE_ASICREV_BCM57780:
2051             sc->bge_flags |= BGE_FLAG_5755_PLUS | BGE_FLAG_575X_PLUS |
2052                 BGE_FLAG_5705_PLUS;
2053             break;
2054
2055         case BGE_ASICREV_BCM5700:
2056         case BGE_ASICREV_BCM5701:
2057         case BGE_ASICREV_BCM5703:
2058         case BGE_ASICREV_BCM5704:
2059                 sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO;
2060                 break;
2061
2062         case BGE_ASICREV_BCM5714_A0:
2063         case BGE_ASICREV_BCM5780:
2064         case BGE_ASICREV_BCM5714:
2065                 sc->bge_flags |= BGE_FLAG_5714_FAMILY;
2066                 /* Fall through */
2067
2068         case BGE_ASICREV_BCM5750:
2069         case BGE_ASICREV_BCM5752:
2070         case BGE_ASICREV_BCM5906:
2071                 sc->bge_flags |= BGE_FLAG_575X_PLUS;
2072                 /* Fall through */
2073
2074         case BGE_ASICREV_BCM5705:
2075                 sc->bge_flags |= BGE_FLAG_5705_PLUS;
2076                 break;
2077         }
2078
2079         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
2080                 sc->bge_flags |= BGE_FLAG_NO_EEPROM;
2081
2082         misccfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID_MASK;
2083         if (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
2084             (misccfg == BGE_MISCCFG_BOARD_ID_5788 ||
2085              misccfg == BGE_MISCCFG_BOARD_ID_5788M))
2086                 sc->bge_flags |= BGE_FLAG_5788;
2087
2088         /* BCM5755 or higher and BCM5906 have short DMA bug. */
2089         if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906)
2090                 sc->bge_flags |= BGE_FLAG_SHORTDMA;
2091
2092         /*
2093          * Check if this is a PCI-X or PCI Express device.
2094          */
2095         if (BGE_IS_5705_PLUS(sc)) {
2096                 if (pci_is_pcie(dev)) {
2097                         sc->bge_flags |= BGE_FLAG_PCIE;
2098                         sc->bge_pciecap = pci_get_pciecap_ptr(sc->bge_dev);
2099                         pcie_set_max_readrq(dev, PCIEM_DEVCTL_MAX_READRQ_4096);
2100                 }
2101         } else {
2102                 /*
2103                  * Check if the device is in PCI-X Mode.
2104                  * (This bit is not valid on PCI Express controllers.)
2105                  */
2106                 if ((pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4) &
2107                     BGE_PCISTATE_PCI_BUSMODE) == 0) {
2108                         sc->bge_flags |= BGE_FLAG_PCIX;
2109                         sc->bge_pcixcap = pci_get_pcixcap_ptr(sc->bge_dev);
2110                         sc->bge_mbox_reorder = device_getenv_int(sc->bge_dev,
2111                             "mbox_reorder", 0);
2112                 }
2113         }
2114         device_printf(dev, "CHIP ID 0x%08x; "
2115                       "ASIC REV 0x%02x; CHIP REV 0x%02x; %s\n",
2116                       sc->bge_chipid, sc->bge_asicrev, sc->bge_chiprev,
2117                       (sc->bge_flags & BGE_FLAG_PCIX) ? "PCI-X"
2118                       : ((sc->bge_flags & BGE_FLAG_PCIE) ?
2119                         "PCI-E" : "PCI"));
2120
2121         /*
2122          * The 40bit DMA bug applies to the 5714/5715 controllers and is
2123          * not actually a MAC controller bug but an issue with the embedded
2124          * PCIe to PCI-X bridge in the device. Use 40bit DMA workaround.
2125          */
2126         if ((sc->bge_flags & BGE_FLAG_PCIX) &&
2127             (BGE_IS_5714_FAMILY(sc) || device_getenv_int(dev, "dma40b", 0)))
2128                 sc->bge_flags |= BGE_FLAG_MAXADDR_40BIT;
2129
2130         /*
2131          * When using the BCM5701 in PCI-X mode, data corruption has
2132          * been observed in the first few bytes of some received packets.
2133          * Aligning the packet buffer in memory eliminates the corruption.
2134          * Unfortunately, this misaligns the packet payloads.  On platforms
2135          * which do not support unaligned accesses, we will realign the
2136          * payloads by copying the received packets.
2137          */
2138         if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
2139             (sc->bge_flags & BGE_FLAG_PCIX))
2140                 sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG;
2141
2142         if (!BGE_IS_CRIPPLED(sc)) {
2143                 if (device_getenv_int(dev, "status_tag", 1)) {
2144                         sc->bge_flags |= BGE_FLAG_STATUS_TAG;
2145                         sc->bge_pci_miscctl = BGE_PCIMISCCTL_TAGGED_STATUS;
2146                         if (bootverbose)
2147                                 device_printf(dev, "enable status tag\n");
2148                 }
2149         }
2150
2151         if (BGE_IS_5755_PLUS(sc)) {
2152                 /*
2153                  * BCM5754 and BCM5787 shares the same ASIC id so
2154                  * explicit device id check is required.
2155                  * Due to unknown reason TSO does not work on BCM5755M.
2156                  */
2157                 if (product != PCI_PRODUCT_BROADCOM_BCM5754 &&
2158                     product != PCI_PRODUCT_BROADCOM_BCM5754M &&
2159                     product != PCI_PRODUCT_BROADCOM_BCM5755M)
2160                         sc->bge_flags |= BGE_FLAG_TSO;
2161         }
2162
2163         /*
2164          * Set various PHY quirk flags.
2165          */
2166
2167         if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
2168              sc->bge_asicrev == BGE_ASICREV_BCM5701) &&
2169             pci_get_subvendor(dev) == PCI_VENDOR_DELL)
2170                 mii_priv |= BRGPHY_FLAG_NO_3LED;
2171
2172         capmask = MII_CAPMASK_DEFAULT;
2173         if ((sc->bge_asicrev == BGE_ASICREV_BCM5703 &&
2174              (misccfg == 0x4000 || misccfg == 0x8000)) ||
2175             (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
2176              vendor == PCI_VENDOR_BROADCOM &&
2177              (product == PCI_PRODUCT_BROADCOM_BCM5901 ||
2178               product == PCI_PRODUCT_BROADCOM_BCM5901A2 ||
2179               product == PCI_PRODUCT_BROADCOM_BCM5705F)) ||
2180             (vendor == PCI_VENDOR_BROADCOM &&
2181              (product == PCI_PRODUCT_BROADCOM_BCM5751F ||
2182               product == PCI_PRODUCT_BROADCOM_BCM5753F ||
2183               product == PCI_PRODUCT_BROADCOM_BCM5787F)) ||
2184             product == PCI_PRODUCT_BROADCOM_BCM57790 ||
2185             sc->bge_asicrev == BGE_ASICREV_BCM5906) {
2186                 /* 10/100 only */
2187                 capmask &= ~BMSR_EXTSTAT;
2188         }
2189
2190         mii_priv |= BRGPHY_FLAG_WIRESPEED;
2191         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
2192             (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
2193              (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 &&
2194               sc->bge_chipid != BGE_CHIPID_BCM5705_A1)) ||
2195             sc->bge_asicrev == BGE_ASICREV_BCM5906)
2196                 mii_priv &= ~BRGPHY_FLAG_WIRESPEED;
2197
2198         if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 ||
2199             sc->bge_chipid == BGE_CHIPID_BCM5701_B0)
2200                 mii_priv |= BRGPHY_FLAG_CRC_BUG;
2201
2202         if (sc->bge_chiprev == BGE_CHIPREV_5703_AX ||
2203             sc->bge_chiprev == BGE_CHIPREV_5704_AX)
2204                 mii_priv |= BRGPHY_FLAG_ADC_BUG;
2205
2206         if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0)
2207                 mii_priv |= BRGPHY_FLAG_5704_A0;
2208
2209         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
2210                 mii_priv |= BRGPHY_FLAG_5906;
2211
2212         if (BGE_IS_5705_PLUS(sc) &&
2213             sc->bge_asicrev != BGE_ASICREV_BCM5906 &&
2214             /* sc->bge_asicrev != BGE_ASICREV_BCM5717 && */
2215             sc->bge_asicrev != BGE_ASICREV_BCM5785 &&
2216             /* sc->bge_asicrev != BGE_ASICREV_BCM57765 && */
2217             sc->bge_asicrev != BGE_ASICREV_BCM57780) {
2218                 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
2219                     sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
2220                     sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
2221                     sc->bge_asicrev == BGE_ASICREV_BCM5787) {
2222                         if (product != PCI_PRODUCT_BROADCOM_BCM5722 &&
2223                             product != PCI_PRODUCT_BROADCOM_BCM5756)
2224                                 mii_priv |= BRGPHY_FLAG_JITTER_BUG;
2225                         if (product == PCI_PRODUCT_BROADCOM_BCM5755M)
2226                                 mii_priv |= BRGPHY_FLAG_ADJUST_TRIM;
2227                 } else {
2228                         mii_priv |= BRGPHY_FLAG_BER_BUG;
2229                 }
2230         }
2231
2232         /*
2233          * Allocate interrupt
2234          */
2235         msi_enable = bge_msi_enable;
2236         if ((sc->bge_flags & BGE_FLAG_STATUS_TAG) == 0) {
2237                 /* If "tagged status" is disabled, don't enable MSI */
2238                 msi_enable = 0;
2239         } else if (msi_enable) {
2240                 msi_enable = 0; /* Disable by default */
2241                 if (BGE_IS_575X_PLUS(sc)) {
2242                         msi_enable = 1;
2243                         /* XXX we filter all 5714 chips */
2244                         if (sc->bge_asicrev == BGE_ASICREV_BCM5714 ||
2245                             (sc->bge_asicrev == BGE_ASICREV_BCM5750 &&
2246                              (sc->bge_chiprev == BGE_CHIPREV_5750_AX ||
2247                               sc->bge_chiprev == BGE_CHIPREV_5750_BX)))
2248                                 msi_enable = 0;
2249                         else if (BGE_IS_5755_PLUS(sc) ||
2250                             sc->bge_asicrev == BGE_ASICREV_BCM5906)
2251                                 sc->bge_flags |= BGE_FLAG_ONESHOT_MSI;
2252                 }
2253         }
2254         if (msi_enable) {
2255                 if (pci_find_extcap(dev, PCIY_MSI, &sc->bge_msicap)) {
2256                         device_printf(dev, "no MSI capability\n");
2257                         msi_enable = 0;
2258                 }
2259         }
2260
2261         sc->bge_irq_type = pci_alloc_1intr(dev, msi_enable, &sc->bge_irq_rid,
2262             &intr_flags);
2263
2264         sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->bge_irq_rid,
2265             intr_flags);
2266         if (sc->bge_irq == NULL) {
2267                 device_printf(dev, "couldn't map interrupt\n");
2268                 error = ENXIO;
2269                 goto fail;
2270         }
2271
2272         if (sc->bge_irq_type == PCI_INTR_TYPE_MSI)
2273                 bge_enable_msi(sc);
2274         else
2275                 sc->bge_flags &= ~BGE_FLAG_ONESHOT_MSI;
2276
2277         /* Initialize if_name earlier, so if_printf could be used */
2278         ifp = &sc->arpcom.ac_if;
2279         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
2280
2281         /* Try to reset the chip. */
2282         bge_reset(sc);
2283
2284         if (bge_chipinit(sc)) {
2285                 device_printf(dev, "chip initialization failed\n");
2286                 error = ENXIO;
2287                 goto fail;
2288         }
2289
2290         /*
2291          * Get station address
2292          */
2293         error = bge_get_eaddr(sc, ether_addr);
2294         if (error) {
2295                 device_printf(dev, "failed to read station address\n");
2296                 goto fail;
2297         }
2298
2299         /* 5705/5750 limits RX return ring to 512 entries. */
2300         if (BGE_IS_5705_PLUS(sc))
2301                 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
2302         else
2303                 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
2304
2305         error = bge_dma_alloc(sc);
2306         if (error)
2307                 goto fail;
2308
2309         /* Set default tuneable values. */
2310         sc->bge_stat_ticks = BGE_TICKS_PER_SEC;
2311         sc->bge_rx_coal_ticks = BGE_RX_COAL_TICKS_DEF;
2312         sc->bge_tx_coal_ticks = BGE_TX_COAL_TICKS_DEF;
2313         sc->bge_rx_coal_bds = BGE_RX_COAL_BDS_DEF;
2314         sc->bge_tx_coal_bds = BGE_TX_COAL_BDS_DEF;
2315         if (sc->bge_flags & BGE_FLAG_STATUS_TAG) {
2316                 sc->bge_rx_coal_ticks_int = BGE_RX_COAL_TICKS_DEF;
2317                 sc->bge_tx_coal_ticks_int = BGE_TX_COAL_TICKS_DEF;
2318                 sc->bge_rx_coal_bds_int = BGE_RX_COAL_BDS_DEF;
2319                 sc->bge_tx_coal_bds_int = BGE_TX_COAL_BDS_DEF;
2320         } else {
2321                 sc->bge_rx_coal_ticks_int = BGE_RX_COAL_TICKS_MIN;
2322                 sc->bge_tx_coal_ticks_int = BGE_TX_COAL_TICKS_MIN;
2323                 sc->bge_rx_coal_bds_int = BGE_RX_COAL_BDS_MIN;
2324                 sc->bge_tx_coal_bds_int = BGE_TX_COAL_BDS_MIN;
2325         }
2326         sc->bge_tx_wreg = BGE_TX_WREG_NSEGS;
2327
2328         /* Set up TX spare and reserved descriptor count */
2329         if (sc->bge_flags & BGE_FLAG_TSO) {
2330                 sc->bge_txspare = BGE_NSEG_SPARE_TSO;
2331                 sc->bge_txrsvd = BGE_NSEG_RSVD_TSO;
2332         } else {
2333                 sc->bge_txspare = BGE_NSEG_SPARE;
2334                 sc->bge_txrsvd = BGE_NSEG_RSVD;
2335         }
2336
2337         /* Set up ifnet structure */
2338         ifp->if_softc = sc;
2339         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2340         ifp->if_ioctl = bge_ioctl;
2341         ifp->if_start = bge_start;
2342 #ifdef IFPOLL_ENABLE
2343         ifp->if_npoll = bge_npoll;
2344 #endif
2345         ifp->if_watchdog = bge_watchdog;
2346         ifp->if_init = bge_init;
2347         ifp->if_mtu = ETHERMTU;
2348         ifp->if_capabilities = IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU;
2349         ifq_set_maxlen(&ifp->if_snd, BGE_TX_RING_CNT - 1);
2350         ifq_set_ready(&ifp->if_snd);
2351
2352         /*
2353          * 5700 B0 chips do not support checksumming correctly due
2354          * to hardware bugs.
2355          */
2356         if (sc->bge_chipid != BGE_CHIPID_BCM5700_B0) {
2357                 ifp->if_capabilities |= IFCAP_HWCSUM;
2358                 ifp->if_hwassist |= BGE_CSUM_FEATURES;
2359         }
2360         if (sc->bge_flags & BGE_FLAG_TSO) {
2361                 ifp->if_capabilities |= IFCAP_TSO;
2362                 ifp->if_hwassist |= CSUM_TSO;
2363         }
2364         ifp->if_capenable = ifp->if_capabilities;
2365
2366         /*
2367          * Figure out what sort of media we have by checking the
2368          * hardware config word in the first 32k of NIC internal memory,
2369          * or fall back to examining the EEPROM if necessary.
2370          * Note: on some BCM5700 cards, this value appears to be unset.
2371          * If that's the case, we have to rely on identifying the NIC
2372          * by its PCI subsystem ID, as we do below for the SysKonnect
2373          * SK-9D41.
2374          */
2375         if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER) {
2376                 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG);
2377         } else {
2378                 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET,
2379                                     sizeof(hwcfg))) {
2380                         device_printf(dev, "failed to read EEPROM\n");
2381                         error = ENXIO;
2382                         goto fail;
2383                 }
2384                 hwcfg = ntohl(hwcfg);
2385         }
2386
2387         /* The SysKonnect SK-9D41 is a 1000baseSX card. */
2388         if (pci_get_subvendor(dev) == PCI_PRODUCT_SCHNEIDERKOCH_SK_9D41 ||
2389             (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) {
2390                 if (BGE_IS_5714_FAMILY(sc))
2391                         sc->bge_flags |= BGE_FLAG_MII_SERDES;
2392                 else
2393                         sc->bge_flags |= BGE_FLAG_TBI;
2394         }
2395
2396         /* Setup MI MODE */
2397         if (sc->bge_flags & BGE_FLAG_CPMU)
2398                 sc->bge_mi_mode = BGE_MIMODE_500KHZ_CONST;
2399         else
2400                 sc->bge_mi_mode = BGE_MIMODE_BASE;
2401         if (BGE_IS_5700_FAMILY(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5705) {
2402                 /* Enable auto polling for BCM570[0-5]. */
2403                 sc->bge_mi_mode |= BGE_MIMODE_AUTOPOLL;
2404         }
2405
2406         /* Setup link status update stuffs */
2407         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
2408             sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
2409                 sc->bge_link_upd = bge_bcm5700_link_upd;
2410                 sc->bge_link_chg = BGE_MACSTAT_MI_INTERRUPT;
2411         } else if (sc->bge_flags & BGE_FLAG_TBI) {
2412                 sc->bge_link_upd = bge_tbi_link_upd;
2413                 sc->bge_link_chg = BGE_MACSTAT_LINK_CHANGED;
2414         } else if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
2415                 sc->bge_link_upd = bge_autopoll_link_upd;
2416                 sc->bge_link_chg = BGE_MACSTAT_LINK_CHANGED;
2417         } else {
2418                 sc->bge_link_upd = bge_copper_link_upd;
2419                 sc->bge_link_chg = BGE_MACSTAT_LINK_CHANGED;
2420         }
2421
2422         /*
2423          * Broadcom's own driver always assumes the internal
2424          * PHY is at GMII address 1.  On some chips, the PHY responds
2425          * to accesses at all addresses, which could cause us to
2426          * bogusly attach the PHY 32 times at probe type.  Always
2427          * restricting the lookup to address 1 is simpler than
2428          * trying to figure out which chips revisions should be
2429          * special-cased.
2430          */
2431         sc->bge_phyno = 1;
2432
2433         if (sc->bge_flags & BGE_FLAG_TBI) {
2434                 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK,
2435                     bge_ifmedia_upd, bge_ifmedia_sts);
2436                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
2437                 ifmedia_add(&sc->bge_ifmedia,
2438                     IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
2439                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
2440                 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO);
2441                 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media;
2442         } else {
2443                 struct mii_probe_args mii_args;
2444
2445                 mii_probe_args_init(&mii_args, bge_ifmedia_upd, bge_ifmedia_sts);
2446                 mii_args.mii_probemask = 1 << sc->bge_phyno;
2447                 mii_args.mii_capmask = capmask;
2448                 mii_args.mii_privtag = MII_PRIVTAG_BRGPHY;
2449                 mii_args.mii_priv = mii_priv;
2450
2451                 error = mii_probe(dev, &sc->bge_miibus, &mii_args);
2452                 if (error) {
2453                         device_printf(dev, "MII without any PHY!\n");
2454                         goto fail;
2455                 }
2456         }
2457
2458         /*
2459          * Create sysctl nodes.
2460          */
2461         sysctl_ctx_init(&sc->bge_sysctl_ctx);
2462         sc->bge_sysctl_tree = SYSCTL_ADD_NODE(&sc->bge_sysctl_ctx,
2463                                               SYSCTL_STATIC_CHILDREN(_hw),
2464                                               OID_AUTO,
2465                                               device_get_nameunit(dev),
2466                                               CTLFLAG_RD, 0, "");
2467         if (sc->bge_sysctl_tree == NULL) {
2468                 device_printf(dev, "can't add sysctl node\n");
2469                 error = ENXIO;
2470                 goto fail;
2471         }
2472
2473         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2474                         SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2475                         OID_AUTO, "rx_coal_ticks",
2476                         CTLTYPE_INT | CTLFLAG_RW,
2477                         sc, 0, bge_sysctl_rx_coal_ticks, "I",
2478                         "Receive coalescing ticks (usec).");
2479         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2480                         SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2481                         OID_AUTO, "tx_coal_ticks",
2482                         CTLTYPE_INT | CTLFLAG_RW,
2483                         sc, 0, bge_sysctl_tx_coal_ticks, "I",
2484                         "Transmit coalescing ticks (usec).");
2485         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2486                         SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2487                         OID_AUTO, "rx_coal_bds",
2488                         CTLTYPE_INT | CTLFLAG_RW,
2489                         sc, 0, bge_sysctl_rx_coal_bds, "I",
2490                         "Receive max coalesced BD count.");
2491         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2492                         SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2493                         OID_AUTO, "tx_coal_bds",
2494                         CTLTYPE_INT | CTLFLAG_RW,
2495                         sc, 0, bge_sysctl_tx_coal_bds, "I",
2496                         "Transmit max coalesced BD count.");
2497
2498         SYSCTL_ADD_INT(&sc->bge_sysctl_ctx,
2499                        SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2500                        OID_AUTO, "tx_wreg", CTLFLAG_RW,
2501                        &sc->bge_tx_wreg, 0,
2502                        "# of segments before writing to hardware register");
2503
2504         if (sc->bge_flags & BGE_FLAG_PCIE) {
2505                 /*
2506                  * A common design characteristic for many Broadcom
2507                  * client controllers is that they only support a
2508                  * single outstanding DMA read operation on the PCIe
2509                  * bus. This means that it will take twice as long to
2510                  * fetch a TX frame that is split into header and
2511                  * payload buffers as it does to fetch a single,
2512                  * contiguous TX frame (2 reads vs. 1 read). For these
2513                  * controllers, coalescing buffers to reduce the number
2514                  * of memory reads is effective way to get maximum
2515                  * performance(about 940Mbps).  Without collapsing TX
2516                  * buffers the maximum TCP bulk transfer performance
2517                  * is about 850Mbps. However forcing coalescing mbufs
2518                  * consumes a lot of CPU cycles, so leave it off by
2519                  * default.
2520                  */
2521                 SYSCTL_ADD_INT(&sc->bge_sysctl_ctx,
2522                                SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2523                                OID_AUTO, "force_defrag", CTLFLAG_RW,
2524                                &sc->bge_force_defrag, 0,
2525                                "Force defragment on TX path");
2526         }
2527         if (sc->bge_flags & BGE_FLAG_STATUS_TAG) {
2528                 if (!BGE_IS_5705_PLUS(sc)) {
2529                         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2530                             SYSCTL_CHILDREN(sc->bge_sysctl_tree), OID_AUTO,
2531                             "rx_coal_ticks_int", CTLTYPE_INT | CTLFLAG_RW,
2532                             sc, 0, bge_sysctl_rx_coal_ticks_int, "I",
2533                             "Receive coalescing ticks "
2534                             "during interrupt (usec).");
2535                         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2536                             SYSCTL_CHILDREN(sc->bge_sysctl_tree), OID_AUTO,
2537                             "tx_coal_ticks_int", CTLTYPE_INT | CTLFLAG_RW,
2538                             sc, 0, bge_sysctl_tx_coal_ticks_int, "I",
2539                             "Transmit coalescing ticks "
2540                             "during interrupt (usec).");
2541                 }
2542                 SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2543                     SYSCTL_CHILDREN(sc->bge_sysctl_tree), OID_AUTO,
2544                     "rx_coal_bds_int", CTLTYPE_INT | CTLFLAG_RW,
2545                     sc, 0, bge_sysctl_rx_coal_bds_int, "I",
2546                     "Receive max coalesced BD count during interrupt.");
2547                 SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2548                     SYSCTL_CHILDREN(sc->bge_sysctl_tree), OID_AUTO,
2549                     "tx_coal_bds_int", CTLTYPE_INT | CTLFLAG_RW,
2550                     sc, 0, bge_sysctl_tx_coal_bds_int, "I",
2551                     "Transmit max coalesced BD count during interrupt.");
2552         }
2553
2554         /*
2555          * Call MI attach routine.
2556          */
2557         ether_ifattach(ifp, ether_addr, NULL);
2558
2559 #ifdef IFPOLL_ENABLE
2560         /* Polling setup */
2561         ifpoll_compat_setup(&sc->bge_npoll,
2562             &sc->bge_sysctl_ctx, sc->bge_sysctl_tree, device_get_unit(dev),
2563             ifp->if_serializer);
2564 #endif
2565
2566         if (sc->bge_irq_type == PCI_INTR_TYPE_MSI) {
2567                 if (sc->bge_flags & BGE_FLAG_ONESHOT_MSI) {
2568                         intr_func = bge_msi_oneshot;
2569                         if (bootverbose)
2570                                 device_printf(dev, "oneshot MSI\n");
2571                 } else {
2572                         intr_func = bge_msi;
2573                 }
2574         } else if (sc->bge_flags & BGE_FLAG_STATUS_TAG) {
2575                 intr_func = bge_intr_legacy;
2576         } else {
2577                 intr_func = bge_intr_crippled;
2578         }
2579         error = bus_setup_intr(dev, sc->bge_irq, INTR_MPSAFE, intr_func, sc,
2580             &sc->bge_intrhand, ifp->if_serializer);
2581         if (error) {
2582                 ether_ifdetach(ifp);
2583                 device_printf(dev, "couldn't set up irq\n");
2584                 goto fail;
2585         }
2586
2587         ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(sc->bge_irq));
2588
2589         return(0);
2590 fail:
2591         bge_detach(dev);
2592         return(error);
2593 }
2594
2595 static int
2596 bge_detach(device_t dev)
2597 {
2598         struct bge_softc *sc = device_get_softc(dev);
2599
2600         if (device_is_attached(dev)) {
2601                 struct ifnet *ifp = &sc->arpcom.ac_if;
2602
2603                 lwkt_serialize_enter(ifp->if_serializer);
2604                 bge_stop(sc);
2605                 bge_reset(sc);
2606                 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand);
2607                 lwkt_serialize_exit(ifp->if_serializer);
2608
2609                 ether_ifdetach(ifp);
2610         }
2611
2612         if (sc->bge_flags & BGE_FLAG_TBI)
2613                 ifmedia_removeall(&sc->bge_ifmedia);
2614         if (sc->bge_miibus)
2615                 device_delete_child(dev, sc->bge_miibus);
2616         bus_generic_detach(dev);
2617
2618         if (sc->bge_irq != NULL) {
2619                 bus_release_resource(dev, SYS_RES_IRQ, sc->bge_irq_rid,
2620                     sc->bge_irq);
2621         }
2622         if (sc->bge_irq_type == PCI_INTR_TYPE_MSI)
2623                 pci_release_msi(dev);
2624
2625         if (sc->bge_res != NULL) {
2626                 bus_release_resource(dev, SYS_RES_MEMORY,
2627                     BGE_PCI_BAR0, sc->bge_res);
2628         }
2629
2630         if (sc->bge_sysctl_tree != NULL)
2631                 sysctl_ctx_free(&sc->bge_sysctl_ctx);
2632
2633         bge_dma_free(sc);
2634
2635         return 0;
2636 }
2637
2638 static void
2639 bge_reset(struct bge_softc *sc)
2640 {
2641         device_t dev;
2642         uint32_t cachesize, command, pcistate, reset;
2643         void (*write_op)(struct bge_softc *, uint32_t, uint32_t);
2644         int i, val = 0;
2645
2646         dev = sc->bge_dev;
2647
2648         if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) &&
2649             sc->bge_asicrev != BGE_ASICREV_BCM5906) {
2650                 if (sc->bge_flags & BGE_FLAG_PCIE)
2651                         write_op = bge_writemem_direct;
2652                 else
2653                         write_op = bge_writemem_ind;
2654         } else {
2655                 write_op = bge_writereg_ind;
2656         }
2657
2658         /* Save some important PCI state. */
2659         cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
2660         command = pci_read_config(dev, BGE_PCI_CMD, 4);
2661         pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
2662
2663         pci_write_config(dev, BGE_PCI_MISC_CTL,
2664             BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2665             BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW|
2666             sc->bge_pci_miscctl, 4);
2667
2668         /* Disable fastboot on controllers that support it. */
2669         if (sc->bge_asicrev == BGE_ASICREV_BCM5752 ||
2670             BGE_IS_5755_PLUS(sc)) {
2671                 if (bootverbose)
2672                         if_printf(&sc->arpcom.ac_if, "Disabling fastboot\n");
2673                 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0);
2674         }
2675
2676         /*
2677          * Write the magic number to SRAM at offset 0xB50.
2678          * When firmware finishes its initialization it will
2679          * write ~BGE_MAGIC_NUMBER to the same location.
2680          */
2681         bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
2682
2683         reset = BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1);
2684
2685         /* XXX: Broadcom Linux driver. */
2686         if (sc->bge_flags & BGE_FLAG_PCIE) {
2687                 /* Force PCI-E 1.0a mode */
2688                 if (sc->bge_asicrev != BGE_ASICREV_BCM5785 &&
2689                     CSR_READ_4(sc, BGE_PCIE_PHY_TSTCTL) ==
2690                     (BGE_PCIE_PHY_TSTCTL_PSCRAM |
2691                      BGE_PCIE_PHY_TSTCTL_PCIE10)) {
2692                         CSR_WRITE_4(sc, BGE_PCIE_PHY_TSTCTL,
2693                             BGE_PCIE_PHY_TSTCTL_PSCRAM);
2694                 }
2695                 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
2696                         /* Prevent PCIE link training during global reset */
2697                         CSR_WRITE_4(sc, BGE_MISC_CFG, (1<<29));
2698                         reset |= (1<<29);
2699                 }
2700         }
2701
2702         /*
2703          * Set GPHY Power Down Override to leave GPHY
2704          * powered up in D0 uninitialized.
2705          */
2706         if (BGE_IS_5705_PLUS(sc) && (sc->bge_flags & BGE_FLAG_CPMU) == 0)
2707                 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE;
2708
2709         /* Issue global reset */
2710         write_op(sc, BGE_MISC_CFG, reset);
2711
2712         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
2713                 uint32_t status, ctrl;
2714
2715                 status = CSR_READ_4(sc, BGE_VCPU_STATUS);
2716                 CSR_WRITE_4(sc, BGE_VCPU_STATUS,
2717                     status | BGE_VCPU_STATUS_DRV_RESET);
2718                 ctrl = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL);
2719                 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL,
2720                     ctrl & ~BGE_VCPU_EXT_CTRL_HALT_CPU);
2721         }
2722
2723         DELAY(1000);
2724
2725         /* XXX: Broadcom Linux driver. */
2726         if (sc->bge_flags & BGE_FLAG_PCIE) {
2727                 uint16_t devctl;
2728
2729                 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) {
2730                         uint32_t v;
2731
2732                         DELAY(500000); /* wait for link training to complete */
2733                         v = pci_read_config(dev, 0xc4, 4);
2734                         pci_write_config(dev, 0xc4, v | (1<<15), 4);
2735                 }
2736
2737                 devctl = pci_read_config(dev,
2738                     sc->bge_pciecap + PCIER_DEVCTRL, 2);
2739
2740                 /* Disable no snoop and disable relaxed ordering. */
2741                 devctl &= ~(PCIEM_DEVCTL_RELAX_ORDER | PCIEM_DEVCTL_NOSNOOP);
2742
2743                 /* Old PCI-E chips only support 128 bytes Max PayLoad Size. */
2744                 if ((sc->bge_flags & BGE_FLAG_CPMU) == 0) {
2745                         devctl &= ~PCIEM_DEVCTL_MAX_PAYLOAD_MASK;
2746                         devctl |= PCIEM_DEVCTL_MAX_PAYLOAD_128;
2747                 }
2748
2749                 pci_write_config(dev, sc->bge_pciecap + PCIER_DEVCTRL,
2750                     devctl, 2);
2751
2752                 /* Clear error status. */
2753                 pci_write_config(dev, sc->bge_pciecap + PCIER_DEVSTS,
2754                     PCIEM_DEVSTS_CORR_ERR |
2755                     PCIEM_DEVSTS_NFATAL_ERR |
2756                     PCIEM_DEVSTS_FATAL_ERR |
2757                     PCIEM_DEVSTS_UNSUPP_REQ, 2);
2758         }
2759
2760         /* Reset some of the PCI state that got zapped by reset */
2761         pci_write_config(dev, BGE_PCI_MISC_CTL,
2762             BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2763             BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW|
2764             sc->bge_pci_miscctl, 4);
2765         pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
2766         pci_write_config(dev, BGE_PCI_CMD, command, 4);
2767         write_op(sc, BGE_MISC_CFG, (65 << 1));
2768
2769         /*
2770          * Disable PCI-X relaxed ordering to ensure status block update
2771          * comes first then packet buffer DMA. Otherwise driver may
2772          * read stale status block.
2773          */
2774         if (sc->bge_flags & BGE_FLAG_PCIX) {
2775                 uint16_t devctl;
2776
2777                 devctl = pci_read_config(dev,
2778                     sc->bge_pcixcap + PCIXR_COMMAND, 2);
2779                 devctl &= ~PCIXM_COMMAND_ERO;
2780                 if (sc->bge_asicrev == BGE_ASICREV_BCM5703) {
2781                         devctl &= ~PCIXM_COMMAND_MAX_READ;
2782                         devctl |= PCIXM_COMMAND_MAX_READ_2048;
2783                 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
2784                         devctl &= ~(PCIXM_COMMAND_MAX_SPLITS |
2785                             PCIXM_COMMAND_MAX_READ);
2786                         devctl |= PCIXM_COMMAND_MAX_READ_2048;
2787                 }
2788                 pci_write_config(dev, sc->bge_pcixcap + PCIXR_COMMAND,
2789                     devctl, 2);
2790         }
2791
2792         /*
2793          * Enable memory arbiter and re-enable MSI if necessary.
2794          */
2795         if (BGE_IS_5714_FAMILY(sc)) {
2796                 uint32_t val;
2797
2798                 if (sc->bge_irq_type == PCI_INTR_TYPE_MSI) {
2799                         /*
2800                          * Resetting BCM5714 family will clear MSI
2801                          * enable bit; restore it after resetting.
2802                          */
2803                         PCI_SETBIT(sc->bge_dev, sc->bge_msicap + PCIR_MSI_CTRL,
2804                             PCIM_MSICTRL_MSI_ENABLE, 2);
2805                         BGE_SETBIT(sc, BGE_MSI_MODE, BGE_MSIMODE_ENABLE);
2806                 }
2807                 val = CSR_READ_4(sc, BGE_MARB_MODE);
2808                 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val);
2809         } else {
2810                 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
2811         }
2812
2813         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
2814                 for (i = 0; i < BGE_TIMEOUT; i++) {
2815                         val = CSR_READ_4(sc, BGE_VCPU_STATUS);
2816                         if (val & BGE_VCPU_STATUS_INIT_DONE)
2817                                 break;
2818                         DELAY(100);
2819                 }
2820                 if (i == BGE_TIMEOUT) {
2821                         if_printf(&sc->arpcom.ac_if, "reset timed out\n");
2822                         return;
2823                 }
2824         } else {
2825                 /*
2826                  * Poll until we see the 1's complement of the magic number.
2827                  * This indicates that the firmware initialization
2828                  * is complete.
2829                  */
2830                 for (i = 0; i < BGE_FIRMWARE_TIMEOUT; i++) {
2831                         val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM);
2832                         if (val == ~BGE_MAGIC_NUMBER)
2833                                 break;
2834                         DELAY(10);
2835                 }
2836                 if (i == BGE_FIRMWARE_TIMEOUT) {
2837                         if_printf(&sc->arpcom.ac_if, "firmware handshake "
2838                                   "timed out, found 0x%08x\n", val);
2839                 }
2840         }
2841
2842         /*
2843          * XXX Wait for the value of the PCISTATE register to
2844          * return to its original pre-reset state. This is a
2845          * fairly good indicator of reset completion. If we don't
2846          * wait for the reset to fully complete, trying to read
2847          * from the device's non-PCI registers may yield garbage
2848          * results.
2849          */
2850         for (i = 0; i < BGE_TIMEOUT; i++) {
2851                 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate)
2852                         break;
2853                 DELAY(10);
2854         }
2855
2856         /* Fix up byte swapping */
2857         CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS |
2858             BGE_MODECTL_BYTESWAP_DATA);
2859
2860         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
2861
2862         /*
2863          * The 5704 in TBI mode apparently needs some special
2864          * adjustment to insure the SERDES drive level is set
2865          * to 1.2V.
2866          */
2867         if (sc->bge_asicrev == BGE_ASICREV_BCM5704 &&
2868             (sc->bge_flags & BGE_FLAG_TBI)) {
2869                 uint32_t serdescfg;
2870
2871                 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG);
2872                 serdescfg = (serdescfg & ~0xFFF) | 0x880;
2873                 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg);
2874         }
2875
2876         /* XXX: Broadcom Linux driver. */
2877         if ((sc->bge_flags & BGE_FLAG_PCIE) &&
2878             sc->bge_chipid != BGE_CHIPID_BCM5750_A0 &&
2879             sc->bge_asicrev != BGE_ASICREV_BCM5785) {
2880                 uint32_t v;
2881
2882                 /* Enable Data FIFO protection. */
2883                 v = CSR_READ_4(sc, BGE_PCIE_TLDLPL_PORT);
2884                 CSR_WRITE_4(sc, BGE_PCIE_TLDLPL_PORT, v | (1 << 25));
2885         }
2886
2887         DELAY(10000);
2888 }
2889
2890 /*
2891  * Frame reception handling. This is called if there's a frame
2892  * on the receive return list.
2893  *
2894  * Note: we have to be able to handle two possibilities here:
2895  * 1) the frame is from the jumbo recieve ring
2896  * 2) the frame is from the standard receive ring
2897  */
2898
2899 static void
2900 bge_rxeof(struct bge_softc *sc, uint16_t rx_prod, int count)
2901 {
2902         struct ifnet *ifp;
2903         int stdcnt = 0, jumbocnt = 0;
2904
2905         ifp = &sc->arpcom.ac_if;
2906
2907         while (sc->bge_rx_saved_considx != rx_prod && count != 0) {
2908                 struct bge_rx_bd        *cur_rx;
2909                 uint32_t                rxidx;
2910                 struct mbuf             *m = NULL;
2911                 uint16_t                vlan_tag = 0;
2912                 int                     have_tag = 0;
2913
2914                 --count;
2915
2916                 cur_rx =
2917             &sc->bge_ldata.bge_rx_return_ring[sc->bge_rx_saved_considx];
2918
2919                 rxidx = cur_rx->bge_idx;
2920                 BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt);
2921                 logif(rx_pkt);
2922
2923                 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
2924                         have_tag = 1;
2925                         vlan_tag = cur_rx->bge_vlan_tag;
2926                 }
2927
2928                 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
2929                         BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
2930                         jumbocnt++;
2931
2932                         if (rxidx != sc->bge_jumbo) {
2933                                 IFNET_STAT_INC(ifp, ierrors, 1);
2934                                 if_printf(ifp, "sw jumbo index(%d) "
2935                                     "and hw jumbo index(%d) mismatch, drop!\n",
2936                                     sc->bge_jumbo, rxidx);
2937                                 bge_setup_rxdesc_jumbo(sc, rxidx);
2938                                 continue;
2939                         }
2940
2941                         m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx].bge_mbuf;
2942                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2943                                 IFNET_STAT_INC(ifp, ierrors, 1);
2944                                 bge_setup_rxdesc_jumbo(sc, sc->bge_jumbo);
2945                                 continue;
2946                         }
2947                         if (bge_newbuf_jumbo(sc, sc->bge_jumbo, 0)) {
2948                                 IFNET_STAT_INC(ifp, ierrors, 1);
2949                                 bge_setup_rxdesc_jumbo(sc, sc->bge_jumbo);
2950                                 continue;
2951                         }
2952                 } else {
2953                         BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
2954                         stdcnt++;
2955
2956                         if (rxidx != sc->bge_std) {
2957                                 IFNET_STAT_INC(ifp, ierrors, 1);
2958                                 if_printf(ifp, "sw std index(%d) "
2959                                     "and hw std index(%d) mismatch, drop!\n",
2960                                     sc->bge_std, rxidx);
2961                                 bge_setup_rxdesc_std(sc, rxidx);
2962                                 continue;
2963                         }
2964
2965                         m = sc->bge_cdata.bge_rx_std_chain[rxidx].bge_mbuf;
2966                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2967                                 IFNET_STAT_INC(ifp, ierrors, 1);
2968                                 bge_setup_rxdesc_std(sc, sc->bge_std);
2969                                 continue;
2970                         }
2971                         if (bge_newbuf_std(sc, sc->bge_std, 0)) {
2972                                 IFNET_STAT_INC(ifp, ierrors, 1);
2973                                 bge_setup_rxdesc_std(sc, sc->bge_std);
2974                                 continue;
2975                         }
2976                 }
2977
2978                 IFNET_STAT_INC(ifp, ipackets, 1);
2979 #if !defined(__i386__) && !defined(__x86_64__)
2980                 /*
2981                  * The x86 allows unaligned accesses, but for other
2982                  * platforms we must make sure the payload is aligned.
2983                  */
2984                 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) {
2985                         bcopy(m->m_data, m->m_data + ETHER_ALIGN,
2986                             cur_rx->bge_len);
2987                         m->m_data += ETHER_ALIGN;
2988                 }
2989 #endif
2990                 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
2991                 m->m_pkthdr.rcvif = ifp;
2992
2993                 if (ifp->if_capenable & IFCAP_RXCSUM) {
2994                         if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
2995                                 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2996                                 if ((cur_rx->bge_ip_csum ^ 0xffff) == 0)
2997                                         m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2998                         }
2999                         if ((cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) &&
3000                             m->m_pkthdr.len >= BGE_MIN_FRAMELEN) {
3001                                 m->m_pkthdr.csum_data =
3002                                         cur_rx->bge_tcp_udp_csum;
3003                                 m->m_pkthdr.csum_flags |=
3004                                         CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
3005                         }
3006                 }
3007
3008                 /*
3009                  * If we received a packet with a vlan tag, pass it
3010                  * to vlan_input() instead of ether_input().
3011                  */
3012                 if (have_tag) {
3013                         m->m_flags |= M_VLANTAG;
3014                         m->m_pkthdr.ether_vlantag = vlan_tag;
3015                 }
3016                 ifp->if_input(ifp, m);
3017         }
3018
3019         bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);
3020         if (stdcnt)
3021                 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
3022         if (jumbocnt)
3023                 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
3024 }
3025
3026 static void
3027 bge_txeof(struct bge_softc *sc, uint16_t tx_cons)
3028 {
3029         struct ifnet *ifp;
3030
3031         ifp = &sc->arpcom.ac_if;
3032
3033         /*
3034          * Go through our tx ring and free mbufs for those
3035          * frames that have been sent.
3036          */
3037         while (sc->bge_tx_saved_considx != tx_cons) {
3038                 uint32_t idx = 0;
3039
3040                 idx = sc->bge_tx_saved_considx;
3041                 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) {
3042                         IFNET_STAT_INC(ifp, opackets, 1);
3043                         bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
3044                             sc->bge_cdata.bge_tx_dmamap[idx]);
3045                         m_freem(sc->bge_cdata.bge_tx_chain[idx]);
3046                         sc->bge_cdata.bge_tx_chain[idx] = NULL;
3047                 }
3048                 sc->bge_txcnt--;
3049                 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT);
3050                 logif(tx_pkt);
3051         }
3052
3053         if ((BGE_TX_RING_CNT - sc->bge_txcnt) >=
3054             (sc->bge_txrsvd + sc->bge_txspare))
3055                 ifq_clr_oactive(&ifp->if_snd);
3056
3057         if (sc->bge_txcnt == 0)
3058                 ifp->if_timer = 0;
3059
3060         if (!ifq_is_empty(&ifp->if_snd))
3061                 if_devstart(ifp);
3062 }
3063
3064 #ifdef IFPOLL_ENABLE
3065
3066 static void
3067 bge_npoll_compat(struct ifnet *ifp, void *arg __unused, int cycles)
3068 {
3069         struct bge_softc *sc = ifp->if_softc;
3070         struct bge_status_block *sblk = sc->bge_ldata.bge_status_block;
3071         uint16_t rx_prod, tx_cons;
3072
3073         ASSERT_SERIALIZED(ifp->if_serializer);
3074
3075         if (sc->bge_npoll.ifpc_stcount-- == 0) {
3076                 sc->bge_npoll.ifpc_stcount = sc->bge_npoll.ifpc_stfrac;
3077                 /*
3078                  * Process link state changes.
3079                  */
3080                 bge_link_poll(sc);
3081         }
3082
3083         if (sc->bge_flags & BGE_FLAG_STATUS_TAG) {
3084                 sc->bge_status_tag = sblk->bge_status_tag;
3085                 /*
3086                  * Use a load fence to ensure that status_tag
3087                  * is saved  before rx_prod and tx_cons.
3088                  */
3089                 cpu_lfence();
3090         }
3091
3092         rx_prod = sblk->bge_idx[0].bge_rx_prod_idx;
3093         if (sc->bge_rx_saved_considx != rx_prod)
3094                 bge_rxeof(sc, rx_prod, cycles);
3095
3096         tx_cons = sblk->bge_idx[0].bge_tx_cons_idx;
3097         if (sc->bge_tx_saved_considx != tx_cons)
3098                 bge_txeof(sc, tx_cons);
3099
3100         if (sc->bge_flags & BGE_FLAG_STATUS_TAG)
3101                 bge_writembx(sc, BGE_MBX_IRQ0_LO, sc->bge_status_tag << 24);
3102
3103         if (sc->bge_coal_chg)
3104                 bge_coal_change(sc);
3105 }
3106
3107 static void
3108 bge_npoll(struct ifnet *ifp, struct ifpoll_info *info)
3109 {
3110         struct bge_softc *sc = ifp->if_softc;
3111
3112         ASSERT_SERIALIZED(ifp->if_serializer);
3113
3114         if (info != NULL) {
3115                 int cpuid = sc->bge_npoll.ifpc_cpuid;
3116
3117                 info->ifpi_rx[cpuid].poll_func = bge_npoll_compat;
3118                 info->ifpi_rx[cpuid].arg = NULL;
3119                 info->ifpi_rx[cpuid].serializer = ifp->if_serializer;
3120
3121                 if (ifp->if_flags & IFF_RUNNING)
3122                         bge_disable_intr(sc);
3123                 ifq_set_cpuid(&ifp->if_snd, cpuid);
3124         } else {
3125                 if (ifp->if_flags & IFF_RUNNING)
3126                         bge_enable_intr(sc);
3127                 ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(sc->bge_irq));
3128         }
3129 }
3130
3131 #endif  /* IFPOLL_ENABLE */
3132
3133 static void
3134 bge_intr_crippled(void *xsc)
3135 {
3136         struct bge_softc *sc = xsc;
3137         struct ifnet *ifp = &sc->arpcom.ac_if;
3138
3139         logif(intr);
3140
3141         /*
3142          * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO.  Don't
3143          * disable interrupts by writing nonzero like we used to, since with
3144          * our current organization this just gives complications and
3145          * pessimizations for re-enabling interrupts.  We used to have races
3146          * instead of the necessary complications.  Disabling interrupts
3147          * would just reduce the chance of a status update while we are
3148          * running (by switching to the interrupt-mode coalescence
3149          * parameters), but this chance is already very low so it is more
3150          * efficient to get another interrupt than prevent it.
3151          *
3152          * We do the ack first to ensure another interrupt if there is a
3153          * status update after the ack.  We don't check for the status
3154          * changing later because it is more efficient to get another
3155          * interrupt than prevent it, not quite as above (not checking is
3156          * a smaller optimization than not toggling the interrupt enable,
3157          * since checking doesn't involve PCI accesses and toggling require
3158          * the status check).  So toggling would probably be a pessimization
3159          * even with MSI.  It would only be needed for using a task queue.
3160          */
3161         bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
3162
3163         /*
3164          * Process link state changes.
3165          */
3166         bge_link_poll(sc);
3167
3168         if (ifp->if_flags & IFF_RUNNING) {
3169                 struct bge_status_block *sblk = sc->bge_ldata.bge_status_block;
3170                 uint16_t rx_prod, tx_cons;
3171
3172                 rx_prod = sblk->bge_idx[0].bge_rx_prod_idx;
3173                 if (sc->bge_rx_saved_considx != rx_prod)
3174                         bge_rxeof(sc, rx_prod, -1);
3175
3176                 tx_cons = sblk->bge_idx[0].bge_tx_cons_idx;
3177                 if (sc->bge_tx_saved_considx != tx_cons)
3178                         bge_txeof(sc, tx_cons);
3179         }
3180
3181         if (sc->bge_coal_chg)
3182                 bge_coal_change(sc);
3183 }
3184
3185 static void
3186 bge_intr_legacy(void *xsc)
3187 {
3188         struct bge_softc *sc = xsc;
3189         struct bge_status_block *sblk = sc->bge_ldata.bge_status_block;
3190
3191         if (sc->bge_status_tag == sblk->bge_status_tag) {
3192                 uint32_t val;
3193
3194                 val = pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4);
3195                 if (val & BGE_PCISTAT_INTR_NOTACT)
3196                         return;
3197         }
3198
3199         /*
3200          * NOTE:
3201          * Interrupt will have to be disabled if tagged status
3202          * is used, else interrupt will always be asserted on
3203          * certain chips (at least on BCM5750 AX/BX).
3204          */
3205         bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
3206
3207         bge_intr(sc);
3208 }
3209
3210 static void
3211 bge_msi(void *xsc)
3212 {
3213         struct bge_softc *sc = xsc;
3214
3215         /* Disable interrupt first */
3216         bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
3217         bge_intr(sc);
3218 }
3219
3220 static void
3221 bge_msi_oneshot(void *xsc)
3222 {
3223         bge_intr(xsc);
3224 }
3225
3226 static void
3227 bge_intr(struct bge_softc *sc)
3228 {
3229         struct ifnet *ifp = &sc->arpcom.ac_if;
3230         struct bge_status_block *sblk = sc->bge_ldata.bge_status_block;
3231         uint16_t rx_prod, tx_cons;
3232         uint32_t status;
3233
3234         sc->bge_status_tag = sblk->bge_status_tag;
3235         /*
3236          * Use a load fence to ensure that status_tag is saved
3237          * before rx_prod, tx_cons and status.
3238          */
3239         cpu_lfence();
3240
3241         rx_prod = sblk->bge_idx[0].bge_rx_prod_idx;
3242         tx_cons = sblk->bge_idx[0].bge_tx_cons_idx;
3243         status = sblk->bge_status;
3244
3245         if ((status & BGE_STATFLAG_LINKSTATE_CHANGED) || sc->bge_link_evt)
3246                 bge_link_poll(sc);
3247
3248         if (ifp->if_flags & IFF_RUNNING) {
3249                 if (sc->bge_rx_saved_considx != rx_prod)
3250                         bge_rxeof(sc, rx_prod, -1);
3251
3252                 if (sc->bge_tx_saved_considx != tx_cons)
3253                         bge_txeof(sc, tx_cons);
3254         }
3255
3256         bge_writembx(sc, BGE_MBX_IRQ0_LO, sc->bge_status_tag << 24);
3257
3258         if (sc->bge_coal_chg)
3259                 bge_coal_change(sc);
3260 }
3261
3262 static void
3263 bge_tick(void *xsc)
3264 {
3265         struct bge_softc *sc = xsc;
3266         struct ifnet *ifp = &sc->arpcom.ac_if;
3267
3268         lwkt_serialize_enter(ifp->if_serializer);
3269
3270         if (BGE_IS_5705_PLUS(sc))
3271                 bge_stats_update_regs(sc);
3272         else
3273                 bge_stats_update(sc);
3274
3275         if (sc->bge_flags & BGE_FLAG_TBI) {
3276                 /*
3277                  * Since in TBI mode auto-polling can't be used we should poll
3278                  * link status manually. Here we register pending link event
3279                  * and trigger interrupt.
3280                  */
3281                 sc->bge_link_evt++;
3282                 if (BGE_IS_CRIPPLED(sc))
3283                         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
3284                 else
3285                         BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
3286         } else if (!sc->bge_link) {
3287                 mii_tick(device_get_softc(sc->bge_miibus));
3288         }
3289
3290         callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc);
3291
3292         lwkt_serialize_exit(ifp->if_serializer);
3293 }
3294
3295 static void
3296 bge_stats_update_regs(struct bge_softc *sc)
3297 {
3298         struct ifnet *ifp = &sc->arpcom.ac_if;
3299         struct bge_mac_stats_regs stats;
3300         uint32_t *s;
3301         int i;
3302
3303         s = (uint32_t *)&stats;
3304         for (i = 0; i < sizeof(struct bge_mac_stats_regs); i += 4) {
3305                 *s = CSR_READ_4(sc, BGE_RX_STATS + i);
3306                 s++;
3307         }
3308
3309         IFNET_STAT_SET(ifp, collisions,
3310            (stats.dot3StatsSingleCollisionFrames +
3311            stats.dot3StatsMultipleCollisionFrames +
3312            stats.dot3StatsExcessiveCollisions +
3313            stats.dot3StatsLateCollisions));
3314 }
3315
3316 static void
3317 bge_stats_update(struct bge_softc *sc)
3318 {
3319         struct ifnet *ifp = &sc->arpcom.ac_if;
3320         bus_size_t stats;
3321
3322         stats = BGE_MEMWIN_START + BGE_STATS_BLOCK;
3323
3324 #define READ_STAT(sc, stats, stat)      \
3325         CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat))
3326
3327         IFNET_STAT_SET(ifp, collisions,
3328            (READ_STAT(sc, stats,
3329                 txstats.dot3StatsSingleCollisionFrames.bge_addr_lo) +
3330             READ_STAT(sc, stats,
3331                 txstats.dot3StatsMultipleCollisionFrames.bge_addr_lo) +
3332             READ_STAT(sc, stats,
3333                 txstats.dot3StatsExcessiveCollisions.bge_addr_lo) +
3334             READ_STAT(sc, stats,
3335                 txstats.dot3StatsLateCollisions.bge_addr_lo)));
3336
3337 #undef READ_STAT
3338
3339 #ifdef notdef
3340         IFNET_STAT_SET(ifp, collisions,
3341            (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames +
3342            sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames +
3343            sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions +
3344            sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions));
3345 #endif
3346 }
3347
3348 /*
3349  * Encapsulate an mbuf chain in the tx ring  by coupling the mbuf data
3350  * pointers to descriptors.
3351  */
3352 static int
3353 bge_encap(struct bge_softc *sc, struct mbuf **m_head0, uint32_t *txidx,
3354     int *segs_used)
3355 {
3356         struct bge_tx_bd *d = NULL, *last_d;
3357         uint16_t csum_flags = 0, mss = 0;
3358         bus_dma_segment_t segs[BGE_NSEG_NEW];
3359         bus_dmamap_t map;
3360         int error, maxsegs, nsegs, idx, i;
3361         struct mbuf *m_head = *m_head0, *m_new;
3362
3363         if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3364                 error = bge_setup_tso(sc, m_head0, &mss, &csum_flags);
3365                 if (error)
3366                         return ENOBUFS;
3367                 m_head = *m_head0;
3368         } else if (m_head->m_pkthdr.csum_flags & BGE_CSUM_FEATURES) {
3369                 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
3370                         csum_flags |= BGE_TXBDFLAG_IP_CSUM;
3371                 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
3372                         csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
3373                 if (m_head->m_flags & M_LASTFRAG)
3374                         csum_flags |= BGE_TXBDFLAG_IP_FRAG_END;
3375                 else if (m_head->m_flags & M_FRAG)
3376                         csum_flags |= BGE_TXBDFLAG_IP_FRAG;
3377         }
3378
3379         idx = *txidx;
3380         map = sc->bge_cdata.bge_tx_dmamap[idx];
3381
3382         maxsegs = (BGE_TX_RING_CNT - sc->bge_txcnt) - sc->bge_txrsvd;
3383         KASSERT(maxsegs >= sc->bge_txspare,
3384                 ("not enough segments %d", maxsegs));
3385
3386         if (maxsegs > BGE_NSEG_NEW)
3387                 maxsegs = BGE_NSEG_NEW;
3388
3389         /*
3390          * Pad outbound frame to BGE_MIN_FRAMELEN for an unusual reason.
3391          * The bge hardware will pad out Tx runts to BGE_MIN_FRAMELEN,
3392          * but when such padded frames employ the bge IP/TCP checksum
3393          * offload, the hardware checksum assist gives incorrect results
3394          * (possibly from incorporating its own padding into the UDP/TCP
3395          * checksum; who knows).  If we pad such runts with zeros, the
3396          * onboard checksum comes out correct.
3397          */
3398         if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) &&
3399             m_head->m_pkthdr.len < BGE_MIN_FRAMELEN) {
3400                 error = m_devpad(m_head, BGE_MIN_FRAMELEN);
3401                 if (error)
3402                         goto back;
3403         }
3404
3405         if ((sc->bge_flags & BGE_FLAG_SHORTDMA) && m_head->m_next != NULL) {
3406                 m_new = bge_defrag_shortdma(m_head);
3407                 if (m_new == NULL) {
3408                         error = ENOBUFS;
3409                         goto back;
3410                 }
3411                 *m_head0 = m_head = m_new;
3412         }
3413         if ((m_head->m_pkthdr.csum_flags & CSUM_TSO) == 0 &&
3414             sc->bge_force_defrag && (sc->bge_flags & BGE_FLAG_PCIE) &&
3415             m_head->m_next != NULL) {
3416                 /*
3417                  * Forcefully defragment mbuf chain to overcome hardware
3418                  * limitation which only support a single outstanding
3419                  * DMA read operation.  If it fails, keep moving on using
3420                  * the original mbuf chain.
3421                  */
3422                 m_new = m_defrag(m_head, MB_DONTWAIT);
3423                 if (m_new != NULL)
3424                         *m_head0 = m_head = m_new;
3425         }
3426
3427         error = bus_dmamap_load_mbuf_defrag(sc->bge_cdata.bge_tx_mtag, map,
3428                         m_head0, segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
3429         if (error)
3430                 goto back;
3431         *segs_used += nsegs;
3432
3433         m_head = *m_head0;
3434         bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map, BUS_DMASYNC_PREWRITE);
3435
3436         for (i = 0; ; i++) {
3437                 d = &sc->bge_ldata.bge_tx_ring[idx];
3438
3439                 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr);
3440                 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr);
3441                 d->bge_len = segs[i].ds_len;
3442                 d->bge_flags = csum_flags;
3443                 d->bge_mss = mss;
3444
3445                 if (i == nsegs - 1)
3446                         break;
3447                 BGE_INC(idx, BGE_TX_RING_CNT);
3448         }
3449         last_d = d;
3450
3451         /* Set vlan tag to the first segment of the packet. */
3452         d = &sc->bge_ldata.bge_tx_ring[*txidx];
3453         if (m_head->m_flags & M_VLANTAG) {
3454                 d->bge_flags |= BGE_TXBDFLAG_VLAN_TAG;
3455                 d->bge_vlan_tag = m_head->m_pkthdr.ether_vlantag;
3456         } else {
3457                 d->bge_vlan_tag = 0;
3458         }
3459
3460         /* Mark the last segment as end of packet... */
3461         last_d->bge_flags |= BGE_TXBDFLAG_END;
3462
3463         /*
3464          * Insure that the map for this transmission is placed at
3465          * the array index of the last descriptor in this chain.
3466          */
3467         sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx];
3468         sc->bge_cdata.bge_tx_dmamap[idx] = map;
3469         sc->bge_cdata.bge_tx_chain[idx] = m_head;
3470         sc->bge_txcnt += nsegs;
3471
3472         BGE_INC(idx, BGE_TX_RING_CNT);
3473         *txidx = idx;
3474 back:
3475         if (error) {
3476                 m_freem(*m_head0);
3477                 *m_head0 = NULL;
3478         }
3479         return error;
3480 }
3481
3482 static void
3483 bge_xmit(struct bge_softc *sc, uint32_t prodidx)
3484 {
3485         /* Transmit */
3486         bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
3487         /* 5700 b2 errata */
3488         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
3489                 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
3490 }
3491
3492 /*
3493  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
3494  * to the mbuf data regions directly in the transmit descriptors.
3495  */
3496 static void
3497 bge_start(struct ifnet *ifp, struct ifaltq_subque *ifsq)
3498 {
3499         struct bge_softc *sc = ifp->if_softc;
3500         struct mbuf *m_head = NULL;
3501         uint32_t prodidx;
3502         int nsegs = 0;
3503
3504         ASSERT_ALTQ_SQ_DEFAULT(ifp, ifsq);
3505
3506         if ((ifp->if_flags & IFF_RUNNING) == 0 || ifq_is_oactive(&ifp->if_snd))
3507                 return;
3508
3509         prodidx = sc->bge_tx_prodidx;
3510
3511         while (sc->bge_cdata.bge_tx_chain[prodidx] == NULL) {
3512                 m_head = ifq_dequeue(&ifp->if_snd, NULL);
3513                 if (m_head == NULL)
3514                         break;
3515
3516                 /*
3517                  * XXX
3518                  * The code inside the if() block is never reached since we
3519                  * must mark CSUM_IP_FRAGS in our if_hwassist to start getting
3520                  * requests to checksum TCP/UDP in a fragmented packet.
3521                  *
3522                  * XXX
3523                  * safety overkill.  If this is a fragmented packet chain
3524                  * with delayed TCP/UDP checksums, then only encapsulate
3525                  * it if we have enough descriptors to handle the entire
3526                  * chain at once.
3527                  * (paranoia -- may not actually be needed)
3528                  */
3529                 if ((m_head->m_flags & M_FIRSTFRAG) &&
3530                     (m_head->m_pkthdr.csum_flags & CSUM_DELAY_DATA)) {
3531                         if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
3532                             m_head->m_pkthdr.csum_data + sc->bge_txrsvd) {
3533                                 ifq_set_oactive(&ifp->if_snd);
3534                                 ifq_prepend(&ifp->if_snd, m_head);
3535                                 break;
3536                         }
3537                 }
3538
3539                 /*
3540                  * Sanity check: avoid coming within bge_txrsvd
3541                  * descriptors of the end of the ring.  Also make
3542                  * sure there are bge_txspare descriptors for
3543                  * jumbo buffers' defragmentation.
3544                  */
3545                 if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
3546                     (sc->bge_txrsvd + sc->bge_txspare)) {
3547                         ifq_set_oactive(&ifp->if_snd);
3548                         ifq_prepend(&ifp->if_snd, m_head);
3549                         break;
3550                 }
3551
3552                 /*
3553                  * Pack the data into the transmit ring. If we
3554                  * don't have room, set the OACTIVE flag and wait
3555                  * for the NIC to drain the ring.
3556                  */
3557                 if (bge_encap(sc, &m_head, &prodidx, &nsegs)) {
3558                         ifq_set_oactive(&ifp->if_snd);
3559                         IFNET_STAT_INC(ifp, oerrors, 1);
3560                         break;
3561                 }
3562
3563                 if (nsegs >= sc->bge_tx_wreg) {
3564                         bge_xmit(sc, prodidx);
3565                         nsegs = 0;
3566                 }
3567
3568                 ETHER_BPF_MTAP(ifp, m_head);
3569
3570                 /*
3571                  * Set a timeout in case the chip goes out to lunch.
3572                  */
3573                 ifp->if_timer = 5;
3574         }
3575
3576         if (nsegs > 0)
3577                 bge_xmit(sc, prodidx);
3578         sc->bge_tx_prodidx = prodidx;
3579 }
3580
3581 static void
3582 bge_init(void *xsc)
3583 {
3584         struct bge_softc *sc = xsc;
3585         struct ifnet *ifp = &sc->arpcom.ac_if;
3586         uint16_t *m;
3587         uint32_t mode;
3588
3589         ASSERT_SERIALIZED(ifp->if_serializer);
3590
3591         /* Cancel pending I/O and flush buffers. */
3592         bge_stop(sc);
3593         bge_reset(sc);
3594         bge_chipinit(sc);
3595
3596         /*
3597          * Init the various state machines, ring
3598          * control blocks and firmware.
3599          */
3600         if (bge_blockinit(sc)) {
3601                 if_printf(ifp, "initialization failure\n");
3602                 bge_stop(sc);
3603                 return;
3604         }
3605
3606         /* Specify MTU. */
3607         CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
3608             ETHER_HDR_LEN + ETHER_CRC_LEN + EVL_ENCAPLEN);
3609
3610         /* Load our MAC address. */
3611         m = (uint16_t *)&sc->arpcom.ac_enaddr[0];
3612         CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
3613         CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
3614
3615         /* Enable or disable promiscuous mode as needed. */
3616         bge_setpromisc(sc);
3617
3618         /* Program multicast filter. */
3619         bge_setmulti(sc);
3620
3621         /* Init RX ring. */
3622         if (bge_init_rx_ring_std(sc)) {
3623                 if_printf(ifp, "RX ring initialization failed\n");
3624                 bge_stop(sc);
3625                 return;
3626         }
3627
3628         /*
3629          * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's
3630          * memory to insure that the chip has in fact read the first
3631          * entry of the ring.
3632          */
3633         if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) {
3634                 uint32_t                v, i;
3635                 for (i = 0; i < 10; i++) {
3636                         DELAY(20);
3637                         v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8);
3638                         if (v == (MCLBYTES - ETHER_ALIGN))
3639                                 break;
3640                 }
3641                 if (i == 10)
3642                         if_printf(ifp, "5705 A0 chip failed to load RX ring\n");
3643         }
3644
3645         /* Init jumbo RX ring. */
3646         if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) {
3647                 if (bge_init_rx_ring_jumbo(sc)) {
3648                         if_printf(ifp, "Jumbo RX ring initialization failed\n");
3649                         bge_stop(sc);
3650                         return;
3651                 }
3652         }
3653
3654         /* Init our RX return ring index */
3655         sc->bge_rx_saved_considx = 0;
3656
3657         /* Init TX ring. */
3658         bge_init_tx_ring(sc);
3659
3660         /* Enable TX MAC state machine lockup fix. */
3661         mode = CSR_READ_4(sc, BGE_TX_MODE);
3662         if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906)
3663                 mode |= BGE_TXMODE_MBUF_LOCKUP_FIX;
3664         /* Turn on transmitter */
3665         CSR_WRITE_4(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE);
3666
3667         /* Turn on receiver */
3668         BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
3669
3670         /*
3671          * Set the number of good frames to receive after RX MBUF
3672          * Low Watermark has been reached.  After the RX MAC receives
3673          * this number of frames, it will drop subsequent incoming
3674          * frames until the MBUF High Watermark is reached.
3675          */
3676         CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2);
3677
3678         if (sc->bge_irq_type == PCI_INTR_TYPE_MSI) {
3679                 if (bootverbose) {
3680                         if_printf(ifp, "MSI_MODE: %#x\n",
3681                             CSR_READ_4(sc, BGE_MSI_MODE));
3682                 }
3683
3684                 /*
3685                  * XXX
3686                  * Linux driver turns it on for all chips supporting MSI?!
3687                  */
3688                 if (sc->bge_flags & BGE_FLAG_ONESHOT_MSI) {
3689                         /*
3690                          * XXX
3691                          * According to 5722-PG101-R,
3692                          * BGE_PCIE_TRANSACT_ONESHOT_MSI applies only to
3693                          * BCM5906.
3694                          */
3695                         BGE_SETBIT(sc, BGE_PCIE_TRANSACT,
3696                             BGE_PCIE_TRANSACT_ONESHOT_MSI);
3697                 }
3698         }
3699
3700         /* Tell firmware we're alive. */
3701         BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3702
3703         /* Enable host interrupts if polling(4) is not enabled. */
3704         PCI_SETBIT(sc->bge_dev, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA, 4);
3705 #ifdef IFPOLL_ENABLE
3706         if (ifp->if_flags & IFF_NPOLLING)
3707                 bge_disable_intr(sc);
3708         else
3709 #endif
3710         bge_enable_intr(sc);
3711
3712         bge_ifmedia_upd(ifp);
3713
3714         ifp->if_flags |= IFF_RUNNING;
3715         ifq_clr_oactive(&ifp->if_snd);
3716
3717         callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc);
3718 }
3719
3720 /*
3721  * Set media options.
3722  */
3723 static int
3724 bge_ifmedia_upd(struct ifnet *ifp)
3725 {
3726         struct bge_softc *sc = ifp->if_softc;
3727
3728         /* If this is a 1000baseX NIC, enable the TBI port. */
3729         if (sc->bge_flags & BGE_FLAG_TBI) {
3730                 struct ifmedia *ifm = &sc->bge_ifmedia;
3731
3732                 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
3733                         return(EINVAL);
3734
3735                 switch(IFM_SUBTYPE(ifm->ifm_media)) {
3736                 case IFM_AUTO:
3737                         /*
3738                          * The BCM5704 ASIC appears to have a special
3739                          * mechanism for programming the autoneg
3740                          * advertisement registers in TBI mode.
3741                          */
3742                         if (!bge_fake_autoneg &&
3743                             sc->bge_asicrev == BGE_ASICREV_BCM5704) {
3744                                 uint32_t sgdig;
3745
3746                                 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0);
3747                                 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG);
3748                                 sgdig |= BGE_SGDIGCFG_AUTO |
3749                                          BGE_SGDIGCFG_PAUSE_CAP |
3750                                          BGE_SGDIGCFG_ASYM_PAUSE;
3751                                 CSR_WRITE_4(sc, BGE_SGDIG_CFG,
3752                                             sgdig | BGE_SGDIGCFG_SEND);
3753                                 DELAY(5);
3754                                 CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig);
3755                         }
3756                         break;
3757                 case IFM_1000_SX:
3758                         if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
3759                                 BGE_CLRBIT(sc, BGE_MAC_MODE,
3760                                     BGE_MACMODE_HALF_DUPLEX);
3761                         } else {
3762                                 BGE_SETBIT(sc, BGE_MAC_MODE,
3763                                     BGE_MACMODE_HALF_DUPLEX);
3764                         }
3765                         break;
3766                 default:
3767                         return(EINVAL);
3768                 }
3769         } else {
3770                 struct mii_data *mii = device_get_softc(sc->bge_miibus);
3771
3772                 sc->bge_link_evt++;
3773                 sc->bge_link = 0;
3774                 if (mii->mii_instance) {
3775                         struct mii_softc *miisc;
3776
3777                         LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
3778                                 mii_phy_reset(miisc);
3779                 }
3780                 mii_mediachg(mii);
3781
3782                 /*
3783                  * Force an interrupt so that we will call bge_link_upd
3784                  * if needed and clear any pending link state attention.
3785                  * Without this we are not getting any further interrupts
3786                  * for link state changes and thus will not UP the link and
3787                  * not be able to send in bge_start.  The only way to get
3788                  * things working was to receive a packet and get an RX
3789                  * intr.
3790                  *
3791                  * bge_tick should help for fiber cards and we might not
3792                  * need to do this here if BGE_FLAG_TBI is set but as
3793                  * we poll for fiber anyway it should not harm.
3794                  */
3795                 if (BGE_IS_CRIPPLED(sc))
3796                         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
3797                 else
3798                         BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
3799         }
3800         return(0);
3801 }
3802
3803 /*
3804  * Report current media status.
3805  */
3806 static void
3807 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3808 {
3809         struct bge_softc *sc = ifp->if_softc;
3810
3811         if (sc->bge_flags & BGE_FLAG_TBI) {
3812                 ifmr->ifm_status = IFM_AVALID;
3813                 ifmr->ifm_active = IFM_ETHER;
3814                 if (CSR_READ_4(sc, BGE_MAC_STS) &
3815                     BGE_MACSTAT_TBI_PCS_SYNCHED) {
3816                         ifmr->ifm_status |= IFM_ACTIVE;
3817                 } else {
3818                         ifmr->ifm_active |= IFM_NONE;
3819                         return;
3820                 }
3821
3822                 ifmr->ifm_active |= IFM_1000_SX;
3823                 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
3824                         ifmr->ifm_active |= IFM_HDX;
3825                 else
3826                         ifmr->ifm_active |= IFM_FDX;
3827         } else {
3828                 struct mii_data *mii = device_get_softc(sc->bge_miibus);
3829
3830                 mii_pollstat(mii);
3831                 ifmr->ifm_active = mii->mii_media_active;
3832                 ifmr->ifm_status = mii->mii_media_status;
3833         }
3834 }
3835
3836 static int
3837 bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
3838 {
3839         struct bge_softc *sc = ifp->if_softc;
3840         struct ifreq *ifr = (struct ifreq *)data;
3841         int mask, error = 0;
3842
3843         ASSERT_SERIALIZED(ifp->if_serializer);
3844
3845         switch (command) {
3846         case SIOCSIFMTU:
3847                 if ((!BGE_IS_JUMBO_CAPABLE(sc) && ifr->ifr_mtu > ETHERMTU) ||
3848                     (BGE_IS_JUMBO_CAPABLE(sc) &&
3849                      ifr->ifr_mtu > BGE_JUMBO_MTU)) {
3850                         error = EINVAL;
3851                 } else if (ifp->if_mtu != ifr->ifr_mtu) {
3852                         ifp->if_mtu = ifr->ifr_mtu;
3853                         if (ifp->if_flags & IFF_RUNNING)
3854                                 bge_init(sc);
3855                 }
3856                 break;
3857         case SIOCSIFFLAGS:
3858                 if (ifp->if_flags & IFF_UP) {
3859                         if (ifp->if_flags & IFF_RUNNING) {
3860                                 mask = ifp->if_flags ^ sc->bge_if_flags;
3861
3862                                 /*
3863                                  * If only the state of the PROMISC flag
3864                                  * changed, then just use the 'set promisc
3865                                  * mode' command instead of reinitializing
3866                                  * the entire NIC. Doing a full re-init
3867                                  * means reloading the firmware and waiting
3868                                  * for it to start up, which may take a
3869                                  * second or two.  Similarly for ALLMULTI.
3870                                  */
3871                                 if (mask & IFF_PROMISC)
3872                                         bge_setpromisc(sc);
3873                                 if (mask & IFF_ALLMULTI)
3874                                         bge_setmulti(sc);
3875                         } else {
3876                                 bge_init(sc);
3877                         }
3878                 } else if (ifp->if_flags & IFF_RUNNING) {
3879                         bge_stop(sc);
3880                 }
3881                 sc->bge_if_flags = ifp->if_flags;
3882                 break;
3883         case SIOCADDMULTI:
3884         case SIOCDELMULTI:
3885                 if (ifp->if_flags & IFF_RUNNING)
3886                         bge_setmulti(sc);
3887                 break;
3888         case SIOCSIFMEDIA:
3889         case SIOCGIFMEDIA:
3890                 if (sc->bge_flags & BGE_FLAG_TBI) {
3891                         error = ifmedia_ioctl(ifp, ifr,
3892                             &sc->bge_ifmedia, command);
3893                 } else {
3894                         struct mii_data *mii;
3895
3896                         mii = device_get_softc(sc->bge_miibus);
3897                         error = ifmedia_ioctl(ifp, ifr,
3898                                               &mii->mii_media, command);
3899                 }
3900                 break;
3901         case SIOCSIFCAP:
3902                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3903                 if (mask & IFCAP_HWCSUM) {
3904                         ifp->if_capenable ^= (mask & IFCAP_HWCSUM);
3905                         if (ifp->if_capenable & IFCAP_TXCSUM)
3906                                 ifp->if_hwassist |= BGE_CSUM_FEATURES;
3907                         else
3908                                 ifp->if_hwassist &= ~BGE_CSUM_FEATURES;
3909                 }
3910                 if (mask & IFCAP_TSO) {
3911                         ifp->if_capenable ^= IFCAP_TSO;
3912                         if (ifp->if_capenable & IFCAP_TSO)
3913                                 ifp->if_hwassist |= CSUM_TSO;
3914                         else
3915                                 ifp->if_hwassist &= ~CSUM_TSO;
3916                 }
3917                 break;
3918         default:
3919                 error = ether_ioctl(ifp, command, data);
3920                 break;
3921         }
3922         return error;
3923 }
3924
3925 static void
3926 bge_watchdog(struct ifnet *ifp)
3927 {
3928         struct bge_softc *sc = ifp->if_softc;
3929
3930         if_printf(ifp, "watchdog timeout -- resetting\n");
3931
3932         bge_init(sc);
3933
3934         IFNET_STAT_INC(ifp, oerrors, 1);
3935
3936         if (!ifq_is_empty(&ifp->if_snd))
3937                 if_devstart(ifp);
3938 }
3939
3940 /*
3941  * Stop the adapter and free any mbufs allocated to the
3942  * RX and TX lists.
3943  */
3944 static void
3945 bge_stop(struct bge_softc *sc)
3946 {
3947         struct ifnet *ifp = &sc->arpcom.ac_if;
3948
3949         ASSERT_SERIALIZED(ifp->if_serializer);
3950
3951         callout_stop(&sc->bge_stat_timer);
3952
3953         /*
3954          * Disable all of the receiver blocks
3955          */
3956         bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
3957         bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
3958         bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
3959         if (BGE_IS_5700_FAMILY(sc))
3960                 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
3961         bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
3962         bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
3963         bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
3964
3965         /*
3966          * Disable all of the transmit blocks
3967          */
3968         bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
3969         bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
3970         bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
3971         bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
3972         bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
3973         if (BGE_IS_5700_FAMILY(sc))
3974                 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
3975         bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
3976
3977         /*
3978          * Shut down all of the memory managers and related
3979          * state machines.
3980          */
3981         bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
3982         bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
3983         if (BGE_IS_5700_FAMILY(sc))
3984                 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
3985         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
3986         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
3987         if (!BGE_IS_5705_PLUS(sc)) {
3988                 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);
3989                 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
3990         }
3991
3992         /* Disable host interrupts. */
3993         bge_disable_intr(sc);
3994
3995         /*
3996          * Tell firmware we're shutting down.
3997          */
3998         BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3999
4000         /* Free the RX lists. */
4001         bge_free_rx_ring_std(sc);
4002
4003         /* Free jumbo RX list. */
4004         if (BGE_IS_JUMBO_CAPABLE(sc))
4005                 bge_free_rx_ring_jumbo(sc);
4006
4007         /* Free TX buffers. */
4008         bge_free_tx_ring(sc);
4009
4010         sc->bge_status_tag = 0;
4011         sc->bge_link = 0;
4012         sc->bge_coal_chg = 0;
4013
4014         sc->bge_tx_saved_considx = BGE_TXCONS_UNSET;
4015
4016         ifp->if_flags &= ~IFF_RUNNING;
4017         ifq_clr_oactive(&ifp->if_snd);
4018         ifp->if_timer = 0;
4019 }
4020
4021 /*
4022  * Stop all chip I/O so that the kernel's probe routines don't
4023  * get confused by errant DMAs when rebooting.
4024  */
4025 static void
4026 bge_shutdown(device_t dev)
4027 {
4028         struct bge_softc *sc = device_get_softc(dev);
4029         struct ifnet *ifp = &sc->arpcom.ac_if;
4030
4031         lwkt_serialize_enter(ifp->if_serializer);
4032         bge_stop(sc);
4033         bge_reset(sc);
4034         lwkt_serialize_exit(ifp->if_serializer);
4035 }
4036
4037 static int
4038 bge_suspend(device_t dev)
4039 {
4040         struct bge_softc *sc = device_get_softc(dev);
4041         struct ifnet *ifp = &sc->arpcom.ac_if;
4042
4043         lwkt_serialize_enter(ifp->if_serializer);
4044         bge_stop(sc);
4045         lwkt_serialize_exit(ifp->if_serializer);
4046
4047         return 0;
4048 }
4049
4050 static int
4051 bge_resume(device_t dev)
4052 {
4053         struct bge_softc *sc = device_get_softc(dev);
4054         struct ifnet *ifp = &sc->arpcom.ac_if;
4055
4056         lwkt_serialize_enter(ifp->if_serializer);
4057
4058         if (ifp->if_flags & IFF_UP) {
4059                 bge_init(sc);
4060
4061                 if (!ifq_is_empty(&ifp->if_snd))
4062                         if_devstart(ifp);
4063         }
4064
4065         lwkt_serialize_exit(ifp->if_serializer);
4066
4067         return 0;
4068 }
4069
4070 static void
4071 bge_setpromisc(struct bge_softc *sc)
4072 {
4073         struct ifnet *ifp = &sc->arpcom.ac_if;
4074
4075         if (ifp->if_flags & IFF_PROMISC)
4076                 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
4077         else
4078                 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
4079 }
4080
4081 static void
4082 bge_dma_free(struct bge_softc *sc)
4083 {
4084         int i;
4085
4086         /* Destroy RX mbuf DMA stuffs. */
4087         if (sc->bge_cdata.bge_rx_mtag != NULL) {
4088                 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
4089                         bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
4090                             sc->bge_cdata.bge_rx_std_dmamap[i]);
4091                 }
4092                 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
4093                                    sc->bge_cdata.bge_rx_tmpmap);
4094                 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag);
4095         }
4096
4097         /* Destroy TX mbuf DMA stuffs. */
4098         if (sc->bge_cdata.bge_tx_mtag != NULL) {
4099                 for (i = 0; i < BGE_TX_RING_CNT; i++) {
4100                         bus_dmamap_destroy(sc->bge_cdata.bge_tx_mtag,
4101                             sc->bge_cdata.bge_tx_dmamap[i]);
4102                 }
4103                 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_mtag);
4104         }
4105
4106         /* Destroy standard RX ring */
4107         bge_dma_block_free(sc->bge_cdata.bge_rx_std_ring_tag,
4108                            sc->bge_cdata.bge_rx_std_ring_map,
4109                            sc->bge_ldata.bge_rx_std_ring);
4110
4111         if (BGE_IS_JUMBO_CAPABLE(sc))
4112                 bge_free_jumbo_mem(sc);
4113
4114         /* Destroy RX return ring */
4115         bge_dma_block_free(sc->bge_cdata.bge_rx_return_ring_tag,
4116                            sc->bge_cdata.bge_rx_return_ring_map,
4117                            sc->bge_ldata.bge_rx_return_ring);
4118
4119         /* Destroy TX ring */
4120         bge_dma_block_free(sc->bge_cdata.bge_tx_ring_tag,
4121                            sc->bge_cdata.bge_tx_ring_map,
4122                            sc->bge_ldata.bge_tx_ring);
4123
4124         /* Destroy status block */
4125         bge_dma_block_free(sc->bge_cdata.bge_status_tag,
4126                            sc->bge_cdata.bge_status_map,
4127                            sc->bge_ldata.bge_status_block);
4128
4129         /* Destroy statistics block */
4130         bge_dma_block_free(sc->bge_cdata.bge_stats_tag,
4131                            sc->bge_cdata.bge_stats_map,
4132                            sc->bge_ldata.bge_stats);
4133
4134         /* Destroy the parent tag */
4135         if (sc->bge_cdata.bge_parent_tag != NULL)
4136                 bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag);
4137 }
4138
4139 static int
4140 bge_dma_alloc(struct bge_softc *sc)
4141 {
4142         struct ifnet *ifp = &sc->arpcom.ac_if;
4143         int i, error;
4144         bus_addr_t lowaddr;
4145         bus_size_t txmaxsz;
4146
4147         lowaddr = BUS_SPACE_MAXADDR;
4148         if (sc->bge_flags & BGE_FLAG_MAXADDR_40BIT)
4149                 lowaddr = BGE_DMA_MAXADDR_40BIT;
4150
4151         /*
4152          * Allocate the parent bus DMA tag appropriate for PCI.
4153          *
4154          * All of the NetExtreme/NetLink controllers have 4GB boundary
4155          * DMA bug.
4156          * Whenever an address crosses a multiple of the 4GB boundary
4157          * (including 4GB, 8Gb, 12Gb, etc.) and makes the transition
4158          * from 0xX_FFFF_FFFF to 0x(X+1)_0000_0000 an internal DMA
4159          * state machine will lockup and cause the device to hang.
4160          */
4161         error = bus_dma_tag_create(NULL, 1, BGE_DMA_BOUNDARY_4G,
4162                                    lowaddr, BUS_SPACE_MAXADDR,
4163                                    NULL, NULL,
4164                                    BUS_SPACE_MAXSIZE_32BIT, 0,
4165                                    BUS_SPACE_MAXSIZE_32BIT,
4166                                    0, &sc->bge_cdata.bge_parent_tag);
4167         if (error) {
4168                 if_printf(ifp, "could not allocate parent dma tag\n");
4169                 return error;
4170         }
4171
4172         /*
4173          * Create DMA tag and maps for RX mbufs.
4174          */
4175         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1, 0,
4176                                    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
4177                                    NULL, NULL, MCLBYTES, 1, MCLBYTES,
4178                                    BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK,
4179                                    &sc->bge_cdata.bge_rx_mtag);
4180         if (error) {
4181                 if_printf(ifp, "could not allocate RX mbuf dma tag\n");
4182                 return error;
4183         }
4184
4185         error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag,
4186                                   BUS_DMA_WAITOK, &sc->bge_cdata.bge_rx_tmpmap);
4187         if (error) {
4188                 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag);
4189                 sc->bge_cdata.bge_rx_mtag = NULL;
4190                 return error;
4191         }
4192
4193         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
4194                 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag,
4195                                           BUS_DMA_WAITOK,
4196                                           &sc->bge_cdata.bge_rx_std_dmamap[i]);
4197                 if (error) {
4198                         int j;
4199
4200                         for (j = 0; j < i; ++j) {
4201                                 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
4202                                         sc->bge_cdata.bge_rx_std_dmamap[j]);
4203                         }
4204                         bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag);
4205                         sc->bge_cdata.bge_rx_mtag = NULL;
4206
4207                         if_printf(ifp, "could not create DMA map for RX\n");
4208                         return error;
4209                 }
4210         }
4211
4212         /*
4213          * Create DMA tag and maps for TX mbufs.
4214          */
4215         if (sc->bge_flags & BGE_FLAG_TSO)
4216                 txmaxsz = IP_MAXPACKET + sizeof(struct ether_vlan_header);
4217         else
4218                 txmaxsz = BGE_JUMBO_FRAMELEN;
4219         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1, 0,
4220                                    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
4221                                    NULL, NULL,
4222                                    txmaxsz, BGE_NSEG_NEW, PAGE_SIZE,
4223                                    BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK |
4224                                    BUS_DMA_ONEBPAGE,
4225                                    &sc->bge_cdata.bge_tx_mtag);
4226         if (error) {
4227                 if_printf(ifp, "could not allocate TX mbuf dma tag\n");
4228                 return error;
4229         }
4230
4231         for (i = 0; i < BGE_TX_RING_CNT; i++) {
4232                 error = bus_dmamap_create(sc->bge_cdata.bge_tx_mtag,
4233                                           BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
4234                                           &sc->bge_cdata.bge_tx_dmamap[i]);
4235                 if (error) {
4236                         int j;
4237
4238                         for (j = 0; j < i; ++j) {
4239                                 bus_dmamap_destroy(sc->bge_cdata.bge_tx_mtag,
4240                                         sc->bge_cdata.bge_tx_dmamap[j]);
4241                         }
4242                         bus_dma_tag_destroy(sc->bge_cdata.bge_tx_mtag);
4243                         sc->bge_cdata.bge_tx_mtag = NULL;
4244
4245                         if_printf(ifp, "could not create DMA map for TX\n");
4246                         return error;
4247                 }
4248         }
4249
4250         /*
4251          * Create DMA stuffs for standard RX ring.
4252          */
4253         error = bge_dma_block_alloc(sc, BGE_STD_RX_RING_SZ,
4254                                     &sc->bge_cdata.bge_rx_std_ring_tag,
4255                                     &sc->bge_cdata.bge_rx_std_ring_map,
4256                                     (void *)&sc->bge_ldata.bge_rx_std_ring,
4257                                     &sc->bge_ldata.bge_rx_std_ring_paddr);
4258         if (error) {
4259                 if_printf(ifp, "could not create std RX ring\n");
4260                 return error;
4261         }
4262
4263         /*
4264          * Create jumbo buffer pool.
4265          */
4266         if (BGE_IS_JUMBO_CAPABLE(sc)) {
4267                 error = bge_alloc_jumbo_mem(sc);
4268                 if (error) {
4269                         if_printf(ifp, "could not create jumbo buffer pool\n");
4270                         return error;
4271                 }
4272         }
4273
4274         /*
4275          * Create DMA stuffs for RX return ring.
4276          */
4277         error = bge_dma_block_alloc(sc,
4278             BGE_RX_RTN_RING_SZ(sc->bge_return_ring_cnt),
4279             &sc->bge_cdata.bge_rx_return_ring_tag,
4280             &sc->bge_cdata.bge_rx_return_ring_map,
4281             (void *)&sc->bge_ldata.bge_rx_return_ring,
4282             &sc->bge_ldata.bge_rx_return_ring_paddr);
4283         if (error) {
4284                 if_printf(ifp, "could not create RX ret ring\n");
4285                 return error;
4286         }
4287
4288         /*
4289          * Create DMA stuffs for TX ring.
4290          */
4291         error = bge_dma_block_alloc(sc, BGE_TX_RING_SZ,
4292                                     &sc->bge_cdata.bge_tx_ring_tag,
4293                                     &sc->bge_cdata.bge_tx_ring_map,
4294                                     (void *)&sc->bge_ldata.bge_tx_ring,
4295                                     &sc->bge_ldata.bge_tx_ring_paddr);
4296         if (error) {
4297                 if_printf(ifp, "could not create TX ring\n");
4298                 return error;
4299         }
4300
4301         /*
4302          * Create DMA stuffs for status block.
4303          */
4304         error = bge_dma_block_alloc(sc, BGE_STATUS_BLK_SZ,
4305                                     &sc->bge_cdata.bge_status_tag,
4306                                     &sc->bge_cdata.bge_status_map,
4307                                     (void *)&sc->bge_ldata.bge_status_block,
4308                                     &sc->bge_ldata.bge_status_block_paddr);
4309         if (error) {
4310                 if_printf(ifp, "could not create status block\n");
4311                 return error;
4312         }
4313
4314         /*
4315          * Create DMA stuffs for statistics block.
4316          */
4317         error = bge_dma_block_alloc(sc, BGE_STATS_SZ,
4318                                     &sc->bge_cdata.bge_stats_tag,
4319                                     &sc->bge_cdata.bge_stats_map,
4320                                     (void *)&sc->bge_ldata.bge_stats,
4321                                     &sc->bge_ldata.bge_stats_paddr);
4322         if (error) {
4323                 if_printf(ifp, "could not create stats block\n");
4324                 return error;
4325         }
4326         return 0;
4327 }
4328
4329 static int
4330 bge_dma_block_alloc(struct bge_softc *sc, bus_size_t size, bus_dma_tag_t *tag,
4331                     bus_dmamap_t *map, void **addr, bus_addr_t *paddr)
4332 {
4333         bus_dmamem_t dmem;
4334         int error;
4335
4336         error = bus_dmamem_coherent(sc->bge_cdata.bge_parent_tag, PAGE_SIZE, 0,
4337                                     BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
4338                                     size, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
4339         if (error)
4340                 return error;
4341
4342         *tag = dmem.dmem_tag;
4343         *map = dmem.dmem_map;
4344         *addr = dmem.dmem_addr;
4345         *paddr = dmem.dmem_busaddr;
4346
4347         return 0;
4348 }
4349
4350 static void
4351 bge_dma_block_free(bus_dma_tag_t tag, bus_dmamap_t map, void *addr)
4352 {
4353         if (tag != NULL) {
4354                 bus_dmamap_unload(tag, map);
4355                 bus_dmamem_free(tag, addr, map);
4356                 bus_dma_tag_destroy(tag);
4357         }
4358 }
4359
4360 /*
4361  * Grrr. The link status word in the status block does
4362  * not work correctly on the BCM5700 rev AX and BX chips,
4363  * according to all available information. Hence, we have
4364  * to enable MII interrupts in order to properly obtain
4365  * async link changes. Unfortunately, this also means that
4366  * we have to read the MAC status register to detect link
4367  * changes, thereby adding an additional register access to
4368  * the interrupt handler.
4369  *
4370  * XXX: perhaps link state detection procedure used for
4371  * BGE_CHIPID_BCM5700_B2 can be used for others BCM5700 revisions.
4372  */
4373 static void
4374 bge_bcm5700_link_upd(struct bge_softc *sc, uint32_t status __unused)
4375 {
4376         struct ifnet *ifp = &sc->arpcom.ac_if;
4377         struct mii_data *mii = device_get_softc(sc->bge_miibus);
4378
4379         mii_pollstat(mii);
4380
4381         if (!sc->bge_link &&
4382             (mii->mii_media_status & IFM_ACTIVE) &&
4383             IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
4384                 sc->bge_link++;
4385                 if (bootverbose)
4386                         if_printf(ifp, "link UP\n");
4387         } else if (sc->bge_link &&
4388             (!(mii->mii_media_status & IFM_ACTIVE) ||
4389             IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
4390                 sc->bge_link = 0;
4391                 if (bootverbose)
4392                         if_printf(ifp, "link DOWN\n");
4393         }
4394
4395         /* Clear the interrupt. */
4396         CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_MI_INTERRUPT);
4397         bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR);
4398         bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR, BRGPHY_INTRS);
4399 }
4400
4401 static void
4402 bge_tbi_link_upd(struct bge_softc *sc, uint32_t status)
4403 {
4404         struct ifnet *ifp = &sc->arpcom.ac_if;
4405
4406 #define PCS_ENCODE_ERR  (BGE_MACSTAT_PORT_DECODE_ERROR|BGE_MACSTAT_MI_COMPLETE)
4407
4408         /*
4409          * Sometimes PCS encoding errors are detected in
4410          * TBI mode (on fiber NICs), and for some reason
4411          * the chip will signal them as link changes.
4412          * If we get a link change event, but the 'PCS
4413          * encoding error' bit in the MAC status register
4414          * is set, don't bother doing a link check.
4415          * This avoids spurious "gigabit link up" messages
4416          * that sometimes appear on fiber NICs during
4417          * periods of heavy traffic.
4418          */
4419         if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) {
4420                 if (!sc->bge_link) {
4421                         sc->bge_link++;
4422                         if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
4423                                 BGE_CLRBIT(sc, BGE_MAC_MODE,
4424                                     BGE_MACMODE_TBI_SEND_CFGS);
4425                         }
4426                         CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
4427
4428                         if (bootverbose)
4429                                 if_printf(ifp, "link UP\n");
4430
4431                         ifp->if_link_state = LINK_STATE_UP;
4432                         if_link_state_change(ifp);
4433                 }
4434         } else if ((status & PCS_ENCODE_ERR) != PCS_ENCODE_ERR) {
4435                 if (sc->bge_link) {
4436                         sc->bge_link = 0;
4437
4438                         if (bootverbose)
4439                                 if_printf(ifp, "link DOWN\n");
4440
4441                         ifp->if_link_state = LINK_STATE_DOWN;
4442                         if_link_state_change(ifp);
4443                 }
4444         }
4445
4446 #undef PCS_ENCODE_ERR
4447
4448         /* Clear the attention. */
4449         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
4450             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
4451             BGE_MACSTAT_LINK_CHANGED);
4452 }
4453
4454 static void
4455 bge_copper_link_upd(struct bge_softc *sc, uint32_t status __unused)
4456 {
4457         struct ifnet *ifp = &sc->arpcom.ac_if;
4458         struct mii_data *mii = device_get_softc(sc->bge_miibus);
4459
4460         mii_pollstat(mii);
4461         bge_miibus_statchg(sc->bge_dev);
4462
4463         if (bootverbose) {
4464                 if (sc->bge_link)
4465                         if_printf(ifp, "link UP\n");
4466                 else
4467                         if_printf(ifp, "link DOWN\n");
4468         }
4469
4470         /* Clear the attention. */
4471         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
4472             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
4473             BGE_MACSTAT_LINK_CHANGED);
4474 }
4475
4476 static void
4477 bge_autopoll_link_upd(struct bge_softc *sc, uint32_t status __unused)
4478 {
4479         struct ifnet *ifp = &sc->arpcom.ac_if;
4480         struct mii_data *mii = device_get_softc(sc->bge_miibus);
4481
4482         mii_pollstat(mii);
4483
4484         if (!sc->bge_link &&
4485             (mii->mii_media_status & IFM_ACTIVE) &&
4486             IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
4487                 sc->bge_link++;
4488                 if (bootverbose)
4489                         if_printf(ifp, "link UP\n");
4490         } else if (sc->bge_link &&
4491             (!(mii->mii_media_status & IFM_ACTIVE) ||
4492             IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
4493                 sc->bge_link = 0;
4494                 if (bootverbose)
4495                         if_printf(ifp, "link DOWN\n");
4496         }
4497
4498         /* Clear the attention. */
4499         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
4500             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
4501             BGE_MACSTAT_LINK_CHANGED);
4502 }
4503
4504 static int
4505 bge_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS)
4506 {
4507         struct bge_softc *sc = arg1;
4508
4509         return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
4510             &sc->bge_rx_coal_ticks,
4511             BGE_RX_COAL_TICKS_MIN, BGE_RX_COAL_TICKS_MAX,
4512             BGE_RX_COAL_TICKS_CHG);
4513 }
4514
4515 static int
4516 bge_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS)
4517 {
4518         struct bge_softc *sc = arg1;
4519
4520         return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
4521             &sc->bge_tx_coal_ticks,
4522             BGE_TX_COAL_TICKS_MIN, BGE_TX_COAL_TICKS_MAX,
4523             BGE_TX_COAL_TICKS_CHG);
4524 }
4525
4526 static int
4527 bge_sysctl_rx_coal_bds(SYSCTL_HANDLER_ARGS)
4528 {
4529         struct bge_softc *sc = arg1;
4530
4531         return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
4532             &sc->bge_rx_coal_bds,
4533             BGE_RX_COAL_BDS_MIN, BGE_RX_COAL_BDS_MAX,
4534             BGE_RX_COAL_BDS_CHG);
4535 }
4536
4537 static int
4538 bge_sysctl_tx_coal_bds(SYSCTL_HANDLER_ARGS)
4539 {
4540         struct bge_softc *sc = arg1;
4541
4542         return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
4543             &sc->bge_tx_coal_bds,
4544             BGE_TX_COAL_BDS_MIN, BGE_TX_COAL_BDS_MAX,
4545             BGE_TX_COAL_BDS_CHG);
4546 }
4547
4548 static int
4549 bge_sysctl_rx_coal_ticks_int(SYSCTL_HANDLER_ARGS)
4550 {
4551         struct bge_softc *sc = arg1;
4552
4553         return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
4554             &sc->bge_rx_coal_ticks_int,
4555             BGE_RX_COAL_TICKS_MIN, BGE_RX_COAL_TICKS_MAX,
4556             BGE_RX_COAL_TICKS_INT_CHG);
4557 }
4558
4559 static int
4560 bge_sysctl_tx_coal_ticks_int(SYSCTL_HANDLER_ARGS)
4561 {
4562         struct bge_softc *sc = arg1;
4563
4564         return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
4565             &sc->bge_tx_coal_ticks_int,
4566             BGE_TX_COAL_TICKS_MIN, BGE_TX_COAL_TICKS_MAX,
4567             BGE_TX_COAL_TICKS_INT_CHG);
4568 }
4569
4570 static int
4571 bge_sysctl_rx_coal_bds_int(SYSCTL_HANDLER_ARGS)
4572 {
4573         struct bge_softc *sc = arg1;
4574
4575         return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
4576             &sc->bge_rx_coal_bds_int,
4577             BGE_RX_COAL_BDS_MIN, BGE_RX_COAL_BDS_MAX,
4578             BGE_RX_COAL_BDS_INT_CHG);
4579 }
4580
4581 static int
4582 bge_sysctl_tx_coal_bds_int(SYSCTL_HANDLER_ARGS)
4583 {
4584         struct bge_softc *sc = arg1;
4585
4586         return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
4587             &sc->bge_tx_coal_bds_int,
4588             BGE_TX_COAL_BDS_MIN, BGE_TX_COAL_BDS_MAX,
4589             BGE_TX_COAL_BDS_INT_CHG);
4590 }
4591
4592 static int
4593 bge_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *coal,
4594     int coal_min, int coal_max, uint32_t coal_chg_mask)
4595 {
4596         struct bge_softc *sc = arg1;
4597         struct ifnet *ifp = &sc->arpcom.ac_if;
4598         int error = 0, v;
4599
4600         lwkt_serialize_enter(ifp->if_serializer);
4601
4602         v = *coal;
4603         error = sysctl_handle_int(oidp, &v, 0, req);
4604         if (!error && req->newptr != NULL) {
4605                 if (v < coal_min || v > coal_max) {
4606                         error = EINVAL;
4607                 } else {
4608                         *coal = v;
4609                         sc->bge_coal_chg |= coal_chg_mask;
4610                 }
4611         }
4612
4613         lwkt_serialize_exit(ifp->if_serializer);
4614         return error;
4615 }
4616
4617 static void
4618 bge_coal_change(struct bge_softc *sc)
4619 {
4620         struct ifnet *ifp = &sc->arpcom.ac_if;
4621
4622         ASSERT_SERIALIZED(ifp->if_serializer);
4623
4624         if (sc->bge_coal_chg & BGE_RX_COAL_TICKS_CHG) {
4625                 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS,
4626                             sc->bge_rx_coal_ticks);
4627                 DELAY(10);
4628                 CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS);
4629
4630                 if (bootverbose) {
4631                         if_printf(ifp, "rx_coal_ticks -> %u\n",
4632                                   sc->bge_rx_coal_ticks);
4633                 }
4634         }
4635
4636         if (sc->bge_coal_chg & BGE_TX_COAL_TICKS_CHG) {
4637                 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS,
4638                             sc->bge_tx_coal_ticks);
4639                 DELAY(10);
4640                 CSR_READ_4(sc, BGE_HCC_TX_COAL_TICKS);
4641
4642                 if (bootverbose) {
4643                         if_printf(ifp, "tx_coal_ticks -> %u\n",
4644                                   sc->bge_tx_coal_ticks);
4645                 }
4646         }
4647
4648         if (sc->bge_coal_chg & BGE_RX_COAL_BDS_CHG) {
4649                 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS,
4650                             sc->bge_rx_coal_bds);
4651                 DELAY(10);
4652                 CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS);
4653
4654                 if (bootverbose) {
4655                         if_printf(ifp, "rx_coal_bds -> %u\n",
4656                                   sc->bge_rx_coal_bds);
4657                 }
4658         }
4659
4660         if (sc->bge_coal_chg & BGE_TX_COAL_BDS_CHG) {
4661                 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS,
4662                             sc->bge_tx_coal_bds);
4663                 DELAY(10);
4664                 CSR_READ_4(sc, BGE_HCC_TX_MAX_COAL_BDS);
4665
4666                 if (bootverbose) {
4667                         if_printf(ifp, "tx_max_coal_bds -> %u\n",
4668                                   sc->bge_tx_coal_bds);
4669                 }
4670         }
4671
4672         if (sc->bge_coal_chg & BGE_RX_COAL_TICKS_INT_CHG) {
4673                 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT,
4674                     sc->bge_rx_coal_ticks_int);
4675                 DELAY(10);
4676                 CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS_INT);
4677
4678                 if (bootverbose) {
4679                         if_printf(ifp, "rx_coal_ticks_int -> %u\n",
4680                             sc->bge_rx_coal_ticks_int);
4681                 }
4682         }
4683
4684         if (sc->bge_coal_chg & BGE_TX_COAL_TICKS_INT_CHG) {
4685                 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT,
4686                     sc->bge_tx_coal_ticks_int);
4687                 DELAY(10);
4688                 CSR_READ_4(sc, BGE_HCC_TX_COAL_TICKS_INT);
4689
4690                 if (bootverbose) {
4691                         if_printf(ifp, "tx_coal_ticks_int -> %u\n",
4692                             sc->bge_tx_coal_ticks_int);
4693                 }
4694         }
4695
4696         if (sc->bge_coal_chg & BGE_RX_COAL_BDS_INT_CHG) {
4697                 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT,
4698                     sc->bge_rx_coal_bds_int);
4699                 DELAY(10);
4700                 CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT);
4701
4702                 if (bootverbose) {
4703                         if_printf(ifp, "rx_coal_bds_int -> %u\n",
4704                             sc->bge_rx_coal_bds_int);
4705                 }
4706         }
4707
4708         if (sc->bge_coal_chg & BGE_TX_COAL_BDS_INT_CHG) {
4709                 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT,
4710                     sc->bge_tx_coal_bds_int);
4711                 DELAY(10);
4712                 CSR_READ_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT);
4713
4714                 if (bootverbose) {
4715                         if_printf(ifp, "tx_coal_bds_int -> %u\n",
4716                             sc->bge_tx_coal_bds_int);
4717                 }
4718         }
4719
4720         sc->bge_coal_chg = 0;
4721 }
4722
4723 static void
4724 bge_enable_intr(struct bge_softc *sc)
4725 {
4726         struct ifnet *ifp = &sc->arpcom.ac_if;
4727
4728         lwkt_serialize_handler_enable(ifp->if_serializer);
4729
4730         /*
4731          * Enable interrupt.
4732          */
4733         bge_writembx(sc, BGE_MBX_IRQ0_LO, sc->bge_status_tag << 24);
4734         if (sc->bge_flags & BGE_FLAG_ONESHOT_MSI) {
4735                 /* XXX Linux driver */
4736                 bge_writembx(sc, BGE_MBX_IRQ0_LO, sc->bge_status_tag << 24);
4737         }
4738
4739         /*
4740          * Unmask the interrupt when we stop polling.
4741          */
4742         PCI_CLRBIT(sc->bge_dev, BGE_PCI_MISC_CTL,
4743             BGE_PCIMISCCTL_MASK_PCI_INTR, 4);
4744
4745         /*
4746          * Trigger another interrupt, since above writing
4747          * to interrupt mailbox0 may acknowledge pending
4748          * interrupt.
4749          */
4750         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
4751 }
4752
4753 static void
4754 bge_disable_intr(struct bge_softc *sc)
4755 {
4756         struct ifnet *ifp = &sc->arpcom.ac_if;
4757
4758         /*
4759          * Mask the interrupt when we start polling.
4760          */
4761         PCI_SETBIT(sc->bge_dev, BGE_PCI_MISC_CTL,
4762             BGE_PCIMISCCTL_MASK_PCI_INTR, 4);
4763
4764         /*
4765          * Acknowledge possible asserted interrupt.
4766          */
4767         bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
4768
4769         sc->bge_npoll.ifpc_stcount = 0;
4770
4771         lwkt_serialize_handler_disable(ifp->if_serializer);
4772 }
4773
4774 static int
4775 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[])
4776 {
4777         uint32_t mac_addr;
4778         int ret = 1;
4779
4780         mac_addr = bge_readmem_ind(sc, 0x0c14);
4781         if ((mac_addr >> 16) == 0x484b) {
4782                 ether_addr[0] = (uint8_t)(mac_addr >> 8);
4783                 ether_addr[1] = (uint8_t)mac_addr;
4784                 mac_addr = bge_readmem_ind(sc, 0x0c18);
4785                 ether_addr[2] = (uint8_t)(mac_addr >> 24);
4786                 ether_addr[3] = (uint8_t)(mac_addr >> 16);
4787                 ether_addr[4] = (uint8_t)(mac_addr >> 8);
4788                 ether_addr[5] = (uint8_t)mac_addr;
4789                 ret = 0;
4790         }
4791         return ret;
4792 }
4793
4794 static int
4795 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[])
4796 {
4797         int mac_offset = BGE_EE_MAC_OFFSET;
4798
4799         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
4800                 mac_offset = BGE_EE_MAC_OFFSET_5906;
4801
4802         return bge_read_nvram(sc, ether_addr, mac_offset + 2, ETHER_ADDR_LEN);
4803 }
4804
4805 static int
4806 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[])
4807 {
4808         if (sc->bge_flags & BGE_FLAG_NO_EEPROM)
4809                 return 1;
4810
4811         return bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2,
4812                                ETHER_ADDR_LEN);
4813 }
4814
4815 static int
4816 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[])
4817 {
4818         static const bge_eaddr_fcn_t bge_eaddr_funcs[] = {
4819                 /* NOTE: Order is critical */
4820                 bge_get_eaddr_mem,
4821                 bge_get_eaddr_nvram,
4822                 bge_get_eaddr_eeprom,
4823                 NULL
4824         };
4825         const bge_eaddr_fcn_t *func;
4826
4827         for (func = bge_eaddr_funcs; *func != NULL; ++func) {
4828                 if ((*func)(sc, eaddr) == 0)
4829                         break;
4830         }
4831         return (*func == NULL ? ENXIO : 0);
4832 }
4833
4834 /*
4835  * NOTE: 'm' is not freed upon failure
4836  */
4837 struct mbuf *
4838 bge_defrag_shortdma(struct mbuf *m)
4839 {
4840         struct mbuf *n;
4841         int found;
4842
4843         /*
4844          * If device receive two back-to-back send BDs with less than
4845          * or equal to 8 total bytes then the device may hang.  The two
4846          * back-to-back send BDs must in the same frame for this failure
4847          * to occur.  Scan mbuf chains and see whether two back-to-back
4848          * send BDs are there.  If this is the case, allocate new mbuf
4849          * and copy the frame to workaround the silicon bug.
4850          */
4851         for (n = m, found = 0; n != NULL; n = n->m_next) {
4852                 if (n->m_len < 8) {
4853                         found++;
4854                         if (found > 1)
4855                                 break;
4856                         continue;
4857                 }
4858                 found = 0;
4859         }
4860
4861         if (found > 1)
4862                 n = m_defrag(m, MB_DONTWAIT);
4863         else
4864                 n = m;
4865         return n;
4866 }
4867
4868 static void
4869 bge_stop_block(struct bge_softc *sc, bus_size_t reg, uint32_t bit)
4870 {
4871         int i;
4872
4873         BGE_CLRBIT(sc, reg, bit);
4874         for (i = 0; i < BGE_TIMEOUT; i++) {
4875                 if ((CSR_READ_4(sc, reg) & bit) == 0)
4876                         return;
4877                 DELAY(100);
4878         }
4879 }
4880
4881 static void
4882 bge_link_poll(struct bge_softc *sc)
4883 {
4884         uint32_t status;
4885
4886         status = CSR_READ_4(sc, BGE_MAC_STS);
4887         if ((status & sc->bge_link_chg) || sc->bge_link_evt) {
4888                 sc->bge_link_evt = 0;
4889                 sc->bge_link_upd(sc, status);
4890         }
4891 }
4892
4893 static void
4894 bge_enable_msi(struct bge_softc *sc)
4895 {
4896         uint32_t msi_mode;
4897
4898         msi_mode = CSR_READ_4(sc, BGE_MSI_MODE);
4899         msi_mode |= BGE_MSIMODE_ENABLE;
4900         if (sc->bge_flags & BGE_FLAG_ONESHOT_MSI) {
4901                 /*
4902                  * According to all of the datasheets that are publicly
4903                  * available, bit 5 of the MSI_MODE is defined to be
4904                  * "MSI FIFO Underrun Attn" for BCM5755+ and BCM5906, on
4905                  * which "oneshot MSI" is enabled.  However, it is always
4906                  * safe to clear it here.
4907                  */
4908                 msi_mode &= ~BGE_MSIMODE_ONESHOT_DISABLE;
4909         }
4910         CSR_WRITE_4(sc, BGE_MSI_MODE, msi_mode);
4911 }
4912
4913 static int
4914 bge_setup_tso(struct bge_softc *sc, struct mbuf **mp,
4915     uint16_t *mss0, uint16_t *flags0)
4916 {
4917         struct mbuf *m;
4918         struct ip *ip;
4919         struct tcphdr *th;
4920         int thoff, iphlen, hoff, hlen;
4921         uint16_t flags, mss;
4922
4923         m = *mp;
4924         KASSERT(M_WRITABLE(m), ("TSO mbuf not writable"));
4925
4926         hoff = m->m_pkthdr.csum_lhlen;
4927         iphlen = m->m_pkthdr.csum_iphlen;
4928         thoff = m->m_pkthdr.csum_thlen;
4929
4930         KASSERT(hoff > 0, ("invalid ether header len"));
4931         KASSERT(iphlen > 0, ("invalid ip header len"));
4932         KASSERT(thoff > 0, ("invalid tcp header len"));
4933
4934         if (__predict_false(m->m_len < hoff + iphlen + thoff)) {
4935                 m = m_pullup(m, hoff + iphlen + thoff);
4936                 if (m == NULL) {
4937                         *mp = NULL;
4938                         return ENOBUFS;
4939                 }
4940                 *mp = m;
4941         }
4942         ip = mtodoff(m, struct ip *, hoff);
4943         th = mtodoff(m, struct tcphdr *, hoff + iphlen);
4944
4945         mss = m->m_pkthdr.tso_segsz;
4946         flags = BGE_TXBDFLAG_CPU_PRE_DMA | BGE_TXBDFLAG_CPU_POST_DMA;
4947
4948         ip->ip_len = htons(mss + iphlen + thoff);
4949         th->th_sum = 0;
4950
4951         hlen = (iphlen + thoff) >> 2;
4952         mss |= (hlen << 11);
4953
4954         *mss0 = mss;
4955         *flags0 = flags;
4956
4957         return 0;
4958 }