sys/dev/netif/ig_hal/e1000_nvm.c

   1 /******************************************************************************
   2
   3   Copyright (c) 2001-2011, Intel Corporation
   4   All rights reserved.
   5
   6   Redistribution and use in source and binary forms, with or without
   7   modification, are permitted provided that the following conditions are met:
   8
   9    1. Redistributions of source code must retain the above copyright notice,
  10       this list of conditions and the following disclaimer.
  11
  12    2. Redistributions in binary form must reproduce the above copyright
  13       notice, this list of conditions and the following disclaimer in the
  14       documentation and/or other materials provided with the distribution.
  15
  16    3. Neither the name of the Intel Corporation nor the names of its
  17       contributors may be used to endorse or promote products derived from
  18       this software without specific prior written permission.
  19
  20   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30   POSSIBILITY OF SUCH DAMAGE.
  31
  32 ******************************************************************************/
  33 /*$FreeBSD$*/
  34
  35 #include "e1000_api.h"
  36
  37 static void e1000_reload_nvm_generic(struct e1000_hw *hw);
  38
  39 /**
  40  *  e1000_init_nvm_ops_generic - Initialize NVM function pointers
  41  *  @hw: pointer to the HW structure
  42  *
  43  *  Setups up the function pointers to no-op functions
  44  **/
  45 void e1000_init_nvm_ops_generic(struct e1000_hw *hw)
  46 {
  47         struct e1000_nvm_info *nvm = &hw->nvm;
  48         DEBUGFUNC("e1000_init_nvm_ops_generic");
  49
  50         /* Initialize function pointers */
  51         nvm->ops.init_params = e1000_null_ops_generic;
  52         nvm->ops.acquire = e1000_null_ops_generic;
  53         nvm->ops.read = e1000_null_read_nvm;
  54         nvm->ops.release = e1000_null_nvm_generic;
  55         nvm->ops.reload = e1000_reload_nvm_generic;
  56         nvm->ops.update = e1000_null_ops_generic;
  57         nvm->ops.valid_led_default = e1000_null_led_default;
  58         nvm->ops.validate = e1000_null_ops_generic;
  59         nvm->ops.write = e1000_null_write_nvm;
  60 }
  61
  62 /**
  63  *  e1000_null_nvm_read - No-op function, return 0
  64  *  @hw: pointer to the HW structure
  65  **/
  66 s32 e1000_null_read_nvm(struct e1000_hw *hw, u16 a, u16 b, u16 *c)
  67 {
  68         DEBUGFUNC("e1000_null_read_nvm");
  69         return E1000_SUCCESS;
  70 }
  71
  72 /**
  73  *  e1000_null_nvm_generic - No-op function, return void
  74  *  @hw: pointer to the HW structure
  75  **/
  76 void e1000_null_nvm_generic(struct e1000_hw *hw)
  77 {
  78         DEBUGFUNC("e1000_null_nvm_generic");
  79         return;
  80 }
  81
  82 /**
  83  *  e1000_null_led_default - No-op function, return 0
  84  *  @hw: pointer to the HW structure
  85  **/
  86 s32 e1000_null_led_default(struct e1000_hw *hw, u16 *data)
  87 {
  88         DEBUGFUNC("e1000_null_led_default");
  89         return E1000_SUCCESS;
  90 }
  91
  92 /**
  93  *  e1000_null_write_nvm - No-op function, return 0
  94  *  @hw: pointer to the HW structure
  95  **/
  96 s32 e1000_null_write_nvm(struct e1000_hw *hw, u16 a, u16 b, u16 *c)
  97 {
  98         DEBUGFUNC("e1000_null_write_nvm");
  99         return E1000_SUCCESS;
 100 }
 101
 102 /**
 103  *  e1000_raise_eec_clk - Raise EEPROM clock
 104  *  @hw: pointer to the HW structure
 105  *  @eecd: pointer to the EEPROM
 106  *
 107  *  Enable/Raise the EEPROM clock bit.
 108  **/
 109 static void e1000_raise_eec_clk(struct e1000_hw *hw, u32 *eecd)
 110 {
 111         *eecd = *eecd | E1000_EECD_SK;
 112         E1000_WRITE_REG(hw, E1000_EECD, *eecd);
 113         E1000_WRITE_FLUSH(hw);
 114         usec_delay(hw->nvm.delay_usec);
 115 }
 116
 117 /**
 118  *  e1000_lower_eec_clk - Lower EEPROM clock
 119  *  @hw: pointer to the HW structure
 120  *  @eecd: pointer to the EEPROM
 121  *
 122  *  Clear/Lower the EEPROM clock bit.
 123  **/
 124 static void e1000_lower_eec_clk(struct e1000_hw *hw, u32 *eecd)
 125 {
 126         *eecd = *eecd & ~E1000_EECD_SK;
 127         E1000_WRITE_REG(hw, E1000_EECD, *eecd);
 128         E1000_WRITE_FLUSH(hw);
 129         usec_delay(hw->nvm.delay_usec);
 130 }
 131
 132 /**
 133  *  e1000_shift_out_eec_bits - Shift data bits our to the EEPROM
 134  *  @hw: pointer to the HW structure
 135  *  @data: data to send to the EEPROM
 136  *  @count: number of bits to shift out
 137  *
 138  *  We need to shift 'count' bits out to the EEPROM.  So, the value in the
 139  *  "data" parameter will be shifted out to the EEPROM one bit at a time.
 140  *  In order to do this, "data" must be broken down into bits.
 141  **/
 142 static void e1000_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count)
 143 {
 144         struct e1000_nvm_info *nvm = &hw->nvm;
 145         u32 eecd = E1000_READ_REG(hw, E1000_EECD);
 146         u32 mask;
 147
 148         DEBUGFUNC("e1000_shift_out_eec_bits");
 149
 150         mask = 0x01 << (count - 1);
 151         if (nvm->type == e1000_nvm_eeprom_microwire)
 152                 eecd &= ~E1000_EECD_DO;
 153         else
 154         if (nvm->type == e1000_nvm_eeprom_spi)
 155                 eecd |= E1000_EECD_DO;
 156
 157         do {
 158                 eecd &= ~E1000_EECD_DI;
 159
 160                 if (data & mask)
 161                         eecd |= E1000_EECD_DI;
 162
 163                 E1000_WRITE_REG(hw, E1000_EECD, eecd);
 164                 E1000_WRITE_FLUSH(hw);
 165
 166                 usec_delay(nvm->delay_usec);
 167
 168                 e1000_raise_eec_clk(hw, &eecd);
 169                 e1000_lower_eec_clk(hw, &eecd);
 170
 171                 mask >>= 1;
 172         } while (mask);
 173
 174         eecd &= ~E1000_EECD_DI;
 175         E1000_WRITE_REG(hw, E1000_EECD, eecd);
 176 }
 177
 178 /**
 179  *  e1000_shift_in_eec_bits - Shift data bits in from the EEPROM
 180  *  @hw: pointer to the HW structure
 181  *  @count: number of bits to shift in
 182  *
 183  *  In order to read a register from the EEPROM, we need to shift 'count' bits
 184  *  in from the EEPROM.  Bits are "shifted in" by raising the clock input to
 185  *  the EEPROM (setting the SK bit), and then reading the value of the data out
 186  *  "DO" bit.  During this "shifting in" process the data in "DI" bit should
 187  *  always be clear.
 188  **/
 189 static u16 e1000_shift_in_eec_bits(struct e1000_hw *hw, u16 count)
 190 {
 191         u32 eecd;
 192         u32 i;
 193         u16 data;
 194
 195         DEBUGFUNC("e1000_shift_in_eec_bits");
 196
 197         eecd = E1000_READ_REG(hw, E1000_EECD);
 198
 199         eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
 200         data = 0;
 201
 202         for (i = 0; i < count; i++) {
 203                 data <<= 1;
 204                 e1000_raise_eec_clk(hw, &eecd);
 205
 206                 eecd = E1000_READ_REG(hw, E1000_EECD);
 207
 208                 eecd &= ~E1000_EECD_DI;
 209                 if (eecd & E1000_EECD_DO)
 210                         data |= 1;
 211
 212                 e1000_lower_eec_clk(hw, &eecd);
 213         }
 214
 215         return data;
 216 }
 217
 218 /**
 219  *  e1000_poll_eerd_eewr_done - Poll for EEPROM read/write completion
 220  *  @hw: pointer to the HW structure
 221  *  @ee_reg: EEPROM flag for polling
 222  *
 223  *  Polls the EEPROM status bit for either read or write completion based
 224  *  upon the value of 'ee_reg'.
 225  **/
 226 s32 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg)
 227 {
 228         u32 attempts = 100000;
 229         u32 i, reg = 0;
 230
 231         DEBUGFUNC("e1000_poll_eerd_eewr_done");
 232
 233         for (i = 0; i < attempts; i++) {
 234                 if (ee_reg == E1000_NVM_POLL_READ)
 235                         reg = E1000_READ_REG(hw, E1000_EERD);
 236                 else
 237                         reg = E1000_READ_REG(hw, E1000_EEWR);
 238
 239                 if (reg & E1000_NVM_RW_REG_DONE)
 240                         return E1000_SUCCESS;
 241
 242                 usec_delay(5);
 243         }
 244
 245         return -E1000_ERR_NVM;
 246 }
 247
 248 /**
 249  *  e1000_acquire_nvm_generic - Generic request for access to EEPROM
 250  *  @hw: pointer to the HW structure
 251  *
 252  *  Set the EEPROM access request bit and wait for EEPROM access grant bit.
 253  *  Return successful if access grant bit set, else clear the request for
 254  *  EEPROM access and return -E1000_ERR_NVM (-1).
 255  **/
 256 s32 e1000_acquire_nvm_generic(struct e1000_hw *hw)
 257 {
 258         u32 eecd = E1000_READ_REG(hw, E1000_EECD);
 259         s32 timeout = E1000_NVM_GRANT_ATTEMPTS;
 260
 261         DEBUGFUNC("e1000_acquire_nvm_generic");
 262
 263         E1000_WRITE_REG(hw, E1000_EECD, eecd | E1000_EECD_REQ);
 264         eecd = E1000_READ_REG(hw, E1000_EECD);
 265
 266         while (timeout) {
 267                 if (eecd & E1000_EECD_GNT)
 268                         break;
 269                 usec_delay(5);
 270                 eecd = E1000_READ_REG(hw, E1000_EECD);
 271                 timeout--;
 272         }
 273
 274         if (!timeout) {
 275                 eecd &= ~E1000_EECD_REQ;
 276                 E1000_WRITE_REG(hw, E1000_EECD, eecd);
 277                 DEBUGOUT("Could not acquire NVM grant\n");
 278                 return -E1000_ERR_NVM;
 279         }
 280
 281         return E1000_SUCCESS;
 282 }
 283
 284 /**
 285  *  e1000_standby_nvm - Return EEPROM to standby state
 286  *  @hw: pointer to the HW structure
 287  *
 288  *  Return the EEPROM to a standby state.
 289  **/
 290 static void e1000_standby_nvm(struct e1000_hw *hw)
 291 {
 292         struct e1000_nvm_info *nvm = &hw->nvm;
 293         u32 eecd = E1000_READ_REG(hw, E1000_EECD);
 294
 295         DEBUGFUNC("e1000_standby_nvm");
 296
 297         if (nvm->type == e1000_nvm_eeprom_microwire) {
 298                 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
 299                 E1000_WRITE_REG(hw, E1000_EECD, eecd);
 300                 E1000_WRITE_FLUSH(hw);
 301                 usec_delay(nvm->delay_usec);
 302
 303                 e1000_raise_eec_clk(hw, &eecd);
 304
 305                 /* Select EEPROM */
 306                 eecd |= E1000_EECD_CS;
 307                 E1000_WRITE_REG(hw, E1000_EECD, eecd);
 308                 E1000_WRITE_FLUSH(hw);
 309                 usec_delay(nvm->delay_usec);
 310
 311                 e1000_lower_eec_clk(hw, &eecd);
 312         } else if (nvm->type == e1000_nvm_eeprom_spi) {
 313                 /* Toggle CS to flush commands */
 314                 eecd |= E1000_EECD_CS;
 315                 E1000_WRITE_REG(hw, E1000_EECD, eecd);
 316                 E1000_WRITE_FLUSH(hw);
 317                 usec_delay(nvm->delay_usec);
 318                 eecd &= ~E1000_EECD_CS;
 319                 E1000_WRITE_REG(hw, E1000_EECD, eecd);
 320                 E1000_WRITE_FLUSH(hw);
 321                 usec_delay(nvm->delay_usec);
 322         }
 323 }
 324
 325 /**
 326  *  e1000_stop_nvm - Terminate EEPROM command
 327  *  @hw: pointer to the HW structure
 328  *
 329  *  Terminates the current command by inverting the EEPROM's chip select pin.
 330  **/
 331 #ifdef NO_82542_SUPPORT
 332 static void e1000_stop_nvm(struct e1000_hw *hw)
 333 #else
 334 void e1000_stop_nvm(struct e1000_hw *hw)
 335 #endif
 336 {
 337         u32 eecd;
 338
 339         DEBUGFUNC("e1000_stop_nvm");
 340
 341         eecd = E1000_READ_REG(hw, E1000_EECD);
 342         if (hw->nvm.type == e1000_nvm_eeprom_spi) {
 343                 /* Pull CS high */
 344                 eecd |= E1000_EECD_CS;
 345                 e1000_lower_eec_clk(hw, &eecd);
 346         } else if (hw->nvm.type == e1000_nvm_eeprom_microwire) {
 347                 /* CS on Microwire is active-high */
 348                 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
 349                 E1000_WRITE_REG(hw, E1000_EECD, eecd);
 350                 e1000_raise_eec_clk(hw, &eecd);
 351                 e1000_lower_eec_clk(hw, &eecd);
 352         }
 353 }
 354
 355 /**
 356  *  e1000_release_nvm_generic - Release exclusive access to EEPROM
 357  *  @hw: pointer to the HW structure
 358  *
 359  *  Stop any current commands to the EEPROM and clear the EEPROM request bit.
 360  **/
 361 void e1000_release_nvm_generic(struct e1000_hw *hw)
 362 {
 363         u32 eecd;
 364
 365         DEBUGFUNC("e1000_release_nvm_generic");
 366
 367         e1000_stop_nvm(hw);
 368
 369         eecd = E1000_READ_REG(hw, E1000_EECD);
 370         eecd &= ~E1000_EECD_REQ;
 371         E1000_WRITE_REG(hw, E1000_EECD, eecd);
 372 }
 373
 374 /**
 375  *  e1000_ready_nvm_eeprom - Prepares EEPROM for read/write
 376  *  @hw: pointer to the HW structure
 377  *
 378  *  Setups the EEPROM for reading and writing.
 379  **/
 380 static s32 e1000_ready_nvm_eeprom(struct e1000_hw *hw)
 381 {
 382         struct e1000_nvm_info *nvm = &hw->nvm;
 383         u32 eecd = E1000_READ_REG(hw, E1000_EECD);
 384         u8 spi_stat_reg;
 385
 386         DEBUGFUNC("e1000_ready_nvm_eeprom");
 387
 388         if (nvm->type == e1000_nvm_eeprom_microwire) {
 389                 /* Clear SK and DI */
 390                 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
 391                 E1000_WRITE_REG(hw, E1000_EECD, eecd);
 392                 /* Set CS */
 393                 eecd |= E1000_EECD_CS;
 394                 E1000_WRITE_REG(hw, E1000_EECD, eecd);
 395         } else if (nvm->type == e1000_nvm_eeprom_spi) {
 396                 u16 timeout = NVM_MAX_RETRY_SPI;
 397
 398                 /* Clear SK and CS */
 399                 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
 400                 E1000_WRITE_REG(hw, E1000_EECD, eecd);
 401                 E1000_WRITE_FLUSH(hw);
 402                 usec_delay(1);
 403
 404                 /*
 405                  * Read "Status Register" repeatedly until the LSB is cleared.
 406                  * The EEPROM will signal that the command has been completed
 407                  * by clearing bit 0 of the internal status register.  If it's
 408                  * not cleared within 'timeout', then error out.
 409                  */
 410                 while (timeout) {
 411                         e1000_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI,
 412                                                  hw->nvm.opcode_bits);
 413                         spi_stat_reg = (u8)e1000_shift_in_eec_bits(hw, 8);
 414                         if (!(spi_stat_reg & NVM_STATUS_RDY_SPI))
 415                                 break;
 416
 417                         usec_delay(5);
 418                         e1000_standby_nvm(hw);
 419                         timeout--;
 420                 }
 421
 422                 if (!timeout) {
 423                         DEBUGOUT("SPI NVM Status error\n");
 424                         return -E1000_ERR_NVM;
 425                 }
 426         }
 427
 428         return E1000_SUCCESS;
 429 }
 430
 431 /**
 432  *  e1000_read_nvm_spi - Read EEPROM's using SPI
 433  *  @hw: pointer to the HW structure
 434  *  @offset: offset of word in the EEPROM to read
 435  *  @words: number of words to read
 436  *  @data: word read from the EEPROM
 437  *
 438  *  Reads a 16 bit word from the EEPROM.
 439  **/
 440 s32 e1000_read_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
 441 {
 442         struct e1000_nvm_info *nvm = &hw->nvm;
 443         u32 i = 0;
 444         s32 ret_val;
 445         u16 word_in;
 446         u8 read_opcode = NVM_READ_OPCODE_SPI;
 447
 448         DEBUGFUNC("e1000_read_nvm_spi");
 449
 450         /*
 451          * A check for invalid values:  offset too large, too many words,
 452          * and not enough words.
 453          */
 454         if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
 455             (words == 0)) {
 456                 DEBUGOUT("nvm parameter(s) out of bounds\n");
 457                 return -E1000_ERR_NVM;
 458         }
 459
 460         ret_val = nvm->ops.acquire(hw);
 461         if (ret_val)
 462                 return ret_val;
 463
 464         ret_val = e1000_ready_nvm_eeprom(hw);
 465         if (ret_val)
 466                 goto release;
 467
 468         e1000_standby_nvm(hw);
 469
 470         if ((nvm->address_bits == 8) && (offset >= 128))
 471                 read_opcode |= NVM_A8_OPCODE_SPI;
 472
 473         /* Send the READ command (opcode + addr) */
 474         e1000_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits);
 475         e1000_shift_out_eec_bits(hw, (u16)(offset*2), nvm->address_bits);
 476
 477         /*
 478          * Read the data.  SPI NVMs increment the address with each byte
 479          * read and will roll over if reading beyond the end.  This allows
 480          * us to read the whole NVM from any offset
 481          */
 482         for (i = 0; i < words; i++) {
 483                 word_in = e1000_shift_in_eec_bits(hw, 16);
 484                 data[i] = (word_in >> 8) | (word_in << 8);
 485         }
 486
 487 release:
 488         nvm->ops.release(hw);
 489
 490         return ret_val;
 491 }
 492
 493 /**
 494  *  e1000_read_nvm_microwire - Reads EEPROM's using microwire
 495  *  @hw: pointer to the HW structure
 496  *  @offset: offset of word in the EEPROM to read
 497  *  @words: number of words to read
 498  *  @data: word read from the EEPROM
 499  *
 500  *  Reads a 16 bit word from the EEPROM.
 501  **/
 502 s32 e1000_read_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words,
 503                              u16 *data)
 504 {
 505         struct e1000_nvm_info *nvm = &hw->nvm;
 506         u32 i = 0;
 507         s32 ret_val;
 508         u8 read_opcode = NVM_READ_OPCODE_MICROWIRE;
 509
 510         DEBUGFUNC("e1000_read_nvm_microwire");
 511
 512         /*
 513          * A check for invalid values:  offset too large, too many words,
 514          * and not enough words.
 515          */
 516         if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
 517             (words == 0)) {
 518                 DEBUGOUT("nvm parameter(s) out of bounds\n");
 519                 return -E1000_ERR_NVM;
 520         }
 521
 522         ret_val = nvm->ops.acquire(hw);
 523         if (ret_val)
 524                 return ret_val;
 525
 526         ret_val = e1000_ready_nvm_eeprom(hw);
 527         if (ret_val)
 528                 goto release;
 529
 530         for (i = 0; i < words; i++) {
 531                 /* Send the READ command (opcode + addr) */
 532                 e1000_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits);
 533                 e1000_shift_out_eec_bits(hw, (u16)(offset + i),
 534                                         nvm->address_bits);
 535
 536                 /*
 537                  * Read the data.  For microwire, each word requires the
 538                  * overhead of setup and tear-down.
 539                  */
 540                 data[i] = e1000_shift_in_eec_bits(hw, 16);
 541                 e1000_standby_nvm(hw);
 542         }
 543
 544 release:
 545         nvm->ops.release(hw);
 546
 547         return ret_val;
 548 }
 549
 550 /**
 551  *  e1000_read_nvm_eerd - Reads EEPROM using EERD register
 552  *  @hw: pointer to the HW structure
 553  *  @offset: offset of word in the EEPROM to read
 554  *  @words: number of words to read
 555  *  @data: word read from the EEPROM
 556  *
 557  *  Reads a 16 bit word from the EEPROM using the EERD register.
 558  **/
 559 s32 e1000_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
 560 {
 561         struct e1000_nvm_info *nvm = &hw->nvm;
 562         u32 i, eerd = 0;
 563         s32 ret_val = E1000_SUCCESS;
 564
 565         DEBUGFUNC("e1000_read_nvm_eerd");
 566
 567         /*
 568          * A check for invalid values:  offset too large, too many words,
 569          * too many words for the offset, and not enough words.
 570          */
 571         if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
 572             (words == 0)) {
 573                 DEBUGOUT("nvm parameter(s) out of bounds\n");
 574                 return -E1000_ERR_NVM;
 575         }
 576
 577         for (i = 0; i < words; i++) {
 578                 eerd = ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) +
 579                        E1000_NVM_RW_REG_START;
 580
 581                 E1000_WRITE_REG(hw, E1000_EERD, eerd);
 582                 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ);
 583                 if (ret_val)
 584                         break;
 585
 586                 data[i] = (E1000_READ_REG(hw, E1000_EERD) >>
 587                            E1000_NVM_RW_REG_DATA);
 588         }
 589
 590         return ret_val;
 591 }
 592
 593 /**
 594  *  e1000_write_nvm_spi - Write to EEPROM using SPI
 595  *  @hw: pointer to the HW structure
 596  *  @offset: offset within the EEPROM to be written to
 597  *  @words: number of words to write
 598  *  @data: 16 bit word(s) to be written to the EEPROM
 599  *
 600  *  Writes data to EEPROM at offset using SPI interface.
 601  *
 602  *  If e1000_update_nvm_checksum is not called after this function , the
 603  *  EEPROM will most likely contain an invalid checksum.
 604  **/
 605 s32 e1000_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
 606 {
 607         struct e1000_nvm_info *nvm = &hw->nvm;
 608         s32 ret_val;
 609         u16 widx = 0;
 610
 611         DEBUGFUNC("e1000_write_nvm_spi");
 612
 613         /*
 614          * A check for invalid values:  offset too large, too many words,
 615          * and not enough words.
 616          */
 617         if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
 618             (words == 0)) {
 619                 DEBUGOUT("nvm parameter(s) out of bounds\n");
 620                 return -E1000_ERR_NVM;
 621         }
 622
 623         ret_val = nvm->ops.acquire(hw);
 624         if (ret_val)
 625                 return ret_val;
 626
 627         while (widx < words) {
 628                 u8 write_opcode = NVM_WRITE_OPCODE_SPI;
 629
 630                 ret_val = e1000_ready_nvm_eeprom(hw);
 631                 if (ret_val)
 632                         goto release;
 633
 634                 e1000_standby_nvm(hw);
 635
 636                 /* Send the WRITE ENABLE command (8 bit opcode) */
 637                 e1000_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI,
 638                                          nvm->opcode_bits);
 639
 640                 e1000_standby_nvm(hw);
 641
 642                 /*
 643                  * Some SPI eeproms use the 8th address bit embedded in the
 644                  * opcode
 645                  */
 646                 if ((nvm->address_bits == 8) && (offset >= 128))
 647                         write_opcode |= NVM_A8_OPCODE_SPI;
 648
 649                 /* Send the Write command (8-bit opcode + addr) */
 650                 e1000_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits);
 651                 e1000_shift_out_eec_bits(hw, (u16)((offset + widx) * 2),
 652                                          nvm->address_bits);
 653
 654                 /* Loop to allow for up to whole page write of eeprom */
 655                 while (widx < words) {
 656                         u16 word_out = data[widx];
 657                         word_out = (word_out >> 8) | (word_out << 8);
 658                         e1000_shift_out_eec_bits(hw, word_out, 16);
 659                         widx++;
 660
 661                         if ((((offset + widx) * 2) % nvm->page_size) == 0) {
 662                                 e1000_standby_nvm(hw);
 663                                 break;
 664                         }
 665                 }
 666         }
 667
 668         msec_delay(10);
 669 release:
 670         nvm->ops.release(hw);
 671
 672         return ret_val;
 673 }
 674
 675 /**
 676  *  e1000_write_nvm_microwire - Writes EEPROM using microwire
 677  *  @hw: pointer to the HW structure
 678  *  @offset: offset within the EEPROM to be written to
 679  *  @words: number of words to write
 680  *  @data: 16 bit word(s) to be written to the EEPROM
 681  *
 682  *  Writes data to EEPROM at offset using microwire interface.
 683  *
 684  *  If e1000_update_nvm_checksum is not called after this function , the
 685  *  EEPROM will most likely contain an invalid checksum.
 686  **/
 687 s32 e1000_write_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words,
 688                               u16 *data)
 689 {
 690         struct e1000_nvm_info *nvm = &hw->nvm;
 691         s32  ret_val;
 692         u32 eecd;
 693         u16 words_written = 0;
 694         u16 widx = 0;
 695
 696         DEBUGFUNC("e1000_write_nvm_microwire");
 697
 698         /*
 699          * A check for invalid values:  offset too large, too many words,
 700          * and not enough words.
 701          */
 702         if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
 703             (words == 0)) {
 704                 DEBUGOUT("nvm parameter(s) out of bounds\n");
 705                 return -E1000_ERR_NVM;
 706         }
 707
 708         ret_val = nvm->ops.acquire(hw);
 709         if (ret_val)
 710                 return ret_val;
 711
 712         ret_val = e1000_ready_nvm_eeprom(hw);
 713         if (ret_val)
 714                 goto release;
 715
 716         e1000_shift_out_eec_bits(hw, NVM_EWEN_OPCODE_MICROWIRE,
 717                                  (u16)(nvm->opcode_bits + 2));
 718
 719         e1000_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2));
 720
 721         e1000_standby_nvm(hw);
 722
 723         while (words_written < words) {
 724                 e1000_shift_out_eec_bits(hw, NVM_WRITE_OPCODE_MICROWIRE,
 725                                          nvm->opcode_bits);
 726
 727                 e1000_shift_out_eec_bits(hw, (u16)(offset + words_written),
 728                                          nvm->address_bits);
 729
 730                 e1000_shift_out_eec_bits(hw, data[words_written], 16);
 731
 732                 e1000_standby_nvm(hw);
 733
 734                 for (widx = 0; widx < 200; widx++) {
 735                         eecd = E1000_READ_REG(hw, E1000_EECD);
 736                         if (eecd & E1000_EECD_DO)
 737                                 break;
 738                         usec_delay(50);
 739                 }
 740
 741                 if (widx == 200) {
 742                         DEBUGOUT("NVM Write did not complete\n");
 743                         ret_val = -E1000_ERR_NVM;
 744                         goto release;
 745                 }
 746
 747                 e1000_standby_nvm(hw);
 748
 749                 words_written++;
 750         }
 751
 752         e1000_shift_out_eec_bits(hw, NVM_EWDS_OPCODE_MICROWIRE,
 753                                  (u16)(nvm->opcode_bits + 2));
 754
 755         e1000_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2));
 756
 757 release:
 758         nvm->ops.release(hw);
 759
 760         return ret_val;
 761 }
 762
 763 /**
 764  *  e1000_read_pba_string_generic - Read device part number
 765  *  @hw: pointer to the HW structure
 766  *  @pba_num: pointer to device part number
 767  *  @pba_num_size: size of part number buffer
 768  *
 769  *  Reads the product board assembly (PBA) number from the EEPROM and stores
 770  *  the value in pba_num.
 771  **/
 772 s32 e1000_read_pba_string_generic(struct e1000_hw *hw, u8 *pba_num,
 773                                   u32 pba_num_size)
 774 {
 775         s32 ret_val;
 776         u16 nvm_data;
 777         u16 pba_ptr;
 778         u16 offset;
 779         u16 length;
 780
 781         DEBUGFUNC("e1000_read_pba_string_generic");
 782
 783         if (pba_num == NULL) {
 784                 DEBUGOUT("PBA string buffer was null\n");
 785                 return -E1000_ERR_INVALID_ARGUMENT;
 786         }
 787
 788         ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
 789         if (ret_val) {
 790                 DEBUGOUT("NVM Read Error\n");
 791                 return ret_val;
 792         }
 793
 794         ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &pba_ptr);
 795         if (ret_val) {
 796                 DEBUGOUT("NVM Read Error\n");
 797                 return ret_val;
 798         }
 799
 800         /*
 801          * if nvm_data is not ptr guard the PBA must be in legacy format which
 802          * means pba_ptr is actually our second data word for the PBA number
 803          * and we can decode it into an ascii string
 804          */
 805         if (nvm_data != NVM_PBA_PTR_GUARD) {
 806                 DEBUGOUT("NVM PBA number is not stored as string\n");
 807
 808                 /* make sure callers buffer is big enough to store the PBA */
 809                 if (pba_num_size < E1000_PBANUM_LENGTH) {
 810                         DEBUGOUT("PBA string buffer too small\n");
 811                         return E1000_ERR_NO_SPACE;
 812                 }
 813
 814                 /* extract hex string from data and pba_ptr */
 815                 pba_num[0] = (nvm_data >> 12) & 0xF;
 816                 pba_num[1] = (nvm_data >> 8) & 0xF;
 817                 pba_num[2] = (nvm_data >> 4) & 0xF;
 818                 pba_num[3] = nvm_data & 0xF;
 819                 pba_num[4] = (pba_ptr >> 12) & 0xF;
 820                 pba_num[5] = (pba_ptr >> 8) & 0xF;
 821                 pba_num[6] = '-';
 822                 pba_num[7] = 0;
 823                 pba_num[8] = (pba_ptr >> 4) & 0xF;
 824                 pba_num[9] = pba_ptr & 0xF;
 825
 826                 /* put a null character on the end of our string */
 827                 pba_num[10] = '\0';
 828
 829                 /* switch all the data but the '-' to hex char */
 830                 for (offset = 0; offset < 10; offset++) {
 831                         if (pba_num[offset] < 0xA)
 832                                 pba_num[offset] += '0';
 833                         else if (pba_num[offset] < 0x10)
 834                                 pba_num[offset] += 'A' - 0xA;
 835                 }
 836
 837                 return E1000_SUCCESS;
 838         }
 839
 840         ret_val = hw->nvm.ops.read(hw, pba_ptr, 1, &length);
 841         if (ret_val) {
 842                 DEBUGOUT("NVM Read Error\n");
 843                 return ret_val;
 844         }
 845
 846         if (length == 0xFFFF || length == 0) {
 847                 DEBUGOUT("NVM PBA number section invalid length\n");
 848                 return -E1000_ERR_NVM_PBA_SECTION;
 849         }
 850         /* check if pba_num buffer is big enough */
 851         if (pba_num_size < (((u32)length * 2) - 1)) {
 852                 DEBUGOUT("PBA string buffer too small\n");
 853                 return -E1000_ERR_NO_SPACE;
 854         }
 855
 856         /* trim pba length from start of string */
 857         pba_ptr++;
 858         length--;
 859
 860         for (offset = 0; offset < length; offset++) {
 861                 ret_val = hw->nvm.ops.read(hw, pba_ptr + offset, 1, &nvm_data);
 862                 if (ret_val) {
 863                         DEBUGOUT("NVM Read Error\n");
 864                         return ret_val;
 865                 }
 866                 pba_num[offset * 2] = (u8)(nvm_data >> 8);
 867                 pba_num[(offset * 2) + 1] = (u8)(nvm_data & 0xFF);
 868         }
 869         pba_num[offset * 2] = '\0';
 870
 871         return E1000_SUCCESS;
 872 }
 873
 874 /**
 875  *  e1000_read_pba_length_generic - Read device part number length
 876  *  @hw: pointer to the HW structure
 877  *  @pba_num_size: size of part number buffer
 878  *
 879  *  Reads the product board assembly (PBA) number length from the EEPROM and
 880  *  stores the value in pba_num_size.
 881  **/
 882 s32 e1000_read_pba_length_generic(struct e1000_hw *hw, u32 *pba_num_size)
 883 {
 884         s32 ret_val;
 885         u16 nvm_data;
 886         u16 pba_ptr;
 887         u16 length;
 888
 889         DEBUGFUNC("e1000_read_pba_length_generic");
 890
 891         if (pba_num_size == NULL) {
 892                 DEBUGOUT("PBA buffer size was null\n");
 893                 return -E1000_ERR_INVALID_ARGUMENT;
 894         }
 895
 896         ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
 897         if (ret_val) {
 898                 DEBUGOUT("NVM Read Error\n");
 899                 return ret_val;
 900         }
 901
 902         ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &pba_ptr);
 903         if (ret_val) {
 904                 DEBUGOUT("NVM Read Error\n");
 905                 return ret_val;
 906         }
 907
 908          /* if data is not ptr guard the PBA must be in legacy format */
 909         if (nvm_data != NVM_PBA_PTR_GUARD) {
 910                 *pba_num_size = E1000_PBANUM_LENGTH;
 911                 return E1000_SUCCESS;
 912         }
 913
 914         ret_val = hw->nvm.ops.read(hw, pba_ptr, 1, &length);
 915         if (ret_val) {
 916                 DEBUGOUT("NVM Read Error\n");
 917                 return ret_val;
 918         }
 919
 920         if (length == 0xFFFF || length == 0) {
 921                 DEBUGOUT("NVM PBA number section invalid length\n");
 922                 return -E1000_ERR_NVM_PBA_SECTION;
 923         }
 924
 925         /*
 926          * Convert from length in u16 values to u8 chars, add 1 for NULL,
 927          * and subtract 2 because length field is included in length.
 928          */
 929         *pba_num_size = ((u32)length * 2) - 1;
 930
 931         return E1000_SUCCESS;
 932 }
 933
 934 /**
 935  *  e1000_read_pba_num_generic - Read device part number
 936  *  @hw: pointer to the HW structure
 937  *  @pba_num: pointer to device part number
 938  *
 939  *  Reads the product board assembly (PBA) number from the EEPROM and stores
 940  *  the value in pba_num.
 941  **/
 942 s32 e1000_read_pba_num_generic(struct e1000_hw *hw, u32 *pba_num)
 943 {
 944         s32 ret_val;
 945         u16 nvm_data;
 946
 947         DEBUGFUNC("e1000_read_pba_num_generic");
 948
 949         ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
 950         if (ret_val) {
 951                 DEBUGOUT("NVM Read Error\n");
 952                 return ret_val;
 953         } else if (nvm_data == NVM_PBA_PTR_GUARD) {
 954                 DEBUGOUT("NVM Not Supported\n");
 955                 return -E1000_NOT_IMPLEMENTED;
 956         }
 957         *pba_num = (u32)(nvm_data << 16);
 958
 959         ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &nvm_data);
 960         if (ret_val) {
 961                 DEBUGOUT("NVM Read Error\n");
 962                 return ret_val;
 963         }
 964         *pba_num |= nvm_data;
 965
 966         return E1000_SUCCESS;
 967 }
 968
 969 /**
 970  *  e1000_read_pba_raw
 971  *  @hw: pointer to the HW structure
 972  *  @eeprom_buf: optional pointer to EEPROM image
 973  *  @eeprom_buf_size: size of EEPROM image in words
 974  *  @max_pba_block_size: PBA block size limit
 975  *  @pba: pointer to output PBA structure
 976  *
 977  *  Reads PBA from EEPROM image when eeprom_buf is not NULL.
 978  *  Reads PBA from physical EEPROM device when eeprom_buf is NULL.
 979  *
 980  **/
 981 s32 e1000_read_pba_raw(struct e1000_hw *hw, u16 *eeprom_buf,
 982                        u32 eeprom_buf_size, u16 max_pba_block_size,
 983                        struct e1000_pba *pba)
 984 {
 985         s32 ret_val;
 986         u16 pba_block_size;
 987
 988         if (pba == NULL)
 989                 return -E1000_ERR_PARAM;
 990
 991         if (eeprom_buf == NULL) {
 992                 ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_0, 2,
 993                                          &pba->word[0]);
 994                 if (ret_val)
 995                         return ret_val;
 996         } else {
 997                 if (eeprom_buf_size > NVM_PBA_OFFSET_1) {
 998                         pba->word[0] = eeprom_buf[NVM_PBA_OFFSET_0];
 999                         pba->word[1] = eeprom_buf[NVM_PBA_OFFSET_1];
1000                 } else {
1001                         return -E1000_ERR_PARAM;
1002                 }
1003         }
1004
1005         if (pba->word[0] == NVM_PBA_PTR_GUARD) {
1006                 if (pba->pba_block == NULL)
1007                         return -E1000_ERR_PARAM;
1008
1009                 ret_val = e1000_get_pba_block_size(hw, eeprom_buf,
1010                                                    eeprom_buf_size,
1011                                                    &pba_block_size);
1012                 if (ret_val)
1013                         return ret_val;
1014
1015                 if (pba_block_size > max_pba_block_size)
1016                         return -E1000_ERR_PARAM;
1017
1018                 if (eeprom_buf == NULL) {
1019                         ret_val = e1000_read_nvm(hw, pba->word[1],
1020                                                  pba_block_size,
1021                                                  pba->pba_block);
1022                         if (ret_val)
1023                                 return ret_val;
1024                 } else {
1025                         if (eeprom_buf_size > (u32)(pba->word[1] +
1026                                               pba->pba_block[0])) {
1027                                 memcpy(pba->pba_block,
1028                                        &eeprom_buf[pba->word[1]],
1029                                        pba_block_size * sizeof(u16));
1030                         } else {
1031                                 return -E1000_ERR_PARAM;
1032                         }
1033                 }
1034         }
1035
1036         return E1000_SUCCESS;
1037 }
1038
1039 /**
1040  *  e1000_write_pba_raw
1041  *  @hw: pointer to the HW structure
1042  *  @eeprom_buf: optional pointer to EEPROM image
1043  *  @eeprom_buf_size: size of EEPROM image in words
1044  *  @pba: pointer to PBA structure
1045  *
1046  *  Writes PBA to EEPROM image when eeprom_buf is not NULL.
1047  *  Writes PBA to physical EEPROM device when eeprom_buf is NULL.
1048  *
1049  **/
1050 s32 e1000_write_pba_raw(struct e1000_hw *hw, u16 *eeprom_buf,
1051                         u32 eeprom_buf_size, struct e1000_pba *pba)
1052 {
1053         s32 ret_val;
1054
1055         if (pba == NULL)
1056                 return -E1000_ERR_PARAM;
1057
1058         if (eeprom_buf == NULL) {
1059                 ret_val = e1000_write_nvm(hw, NVM_PBA_OFFSET_0, 2,
1060                                           &pba->word[0]);
1061                 if (ret_val)
1062                         return ret_val;
1063         } else {
1064                 if (eeprom_buf_size > NVM_PBA_OFFSET_1) {
1065                         eeprom_buf[NVM_PBA_OFFSET_0] = pba->word[0];
1066                         eeprom_buf[NVM_PBA_OFFSET_1] = pba->word[1];
1067                 } else {
1068                         return -E1000_ERR_PARAM;
1069                 }
1070         }
1071
1072         if (pba->word[0] == NVM_PBA_PTR_GUARD) {
1073                 if (pba->pba_block == NULL)
1074                         return -E1000_ERR_PARAM;
1075
1076                 if (eeprom_buf == NULL) {
1077                         ret_val = e1000_write_nvm(hw, pba->word[1],
1078                                                   pba->pba_block[0],
1079                                                   pba->pba_block);
1080                         if (ret_val)
1081                                 return ret_val;
1082                 } else {
1083                         if (eeprom_buf_size > (u32)(pba->word[1] +
1084                                               pba->pba_block[0])) {
1085                                 memcpy(&eeprom_buf[pba->word[1]],
1086                                        pba->pba_block,
1087                                        pba->pba_block[0] * sizeof(u16));
1088                         } else {
1089                                 return -E1000_ERR_PARAM;
1090                         }
1091                 }
1092         }
1093
1094         return E1000_SUCCESS;
1095 }
1096
1097 /**
1098  *  e1000_get_pba_block_size
1099  *  @hw: pointer to the HW structure
1100  *  @eeprom_buf: optional pointer to EEPROM image
1101  *  @eeprom_buf_size: size of EEPROM image in words
1102  *  @pba_data_size: pointer to output variable
1103  *
1104  *  Returns the size of the PBA block in words. Function operates on EEPROM
1105  *  image if the eeprom_buf pointer is not NULL otherwise it accesses physical
1106  *  EEPROM device.
1107  *
1108  **/
1109 s32 e1000_get_pba_block_size(struct e1000_hw *hw, u16 *eeprom_buf,
1110                              u32 eeprom_buf_size, u16 *pba_block_size)
1111 {
1112         s32 ret_val;
1113         u16 pba_word[2];
1114         u16 length;
1115
1116         DEBUGFUNC("e1000_get_pba_block_size");
1117
1118         if (eeprom_buf == NULL) {
1119                 ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_0, 2, &pba_word[0]);
1120                 if (ret_val)
1121                         return ret_val;
1122         } else {
1123                 if (eeprom_buf_size > NVM_PBA_OFFSET_1) {
1124                         pba_word[0] = eeprom_buf[NVM_PBA_OFFSET_0];
1125                         pba_word[1] = eeprom_buf[NVM_PBA_OFFSET_1];
1126                 } else {
1127                         return -E1000_ERR_PARAM;
1128                 }
1129         }
1130
1131         if (pba_word[0] == NVM_PBA_PTR_GUARD) {
1132                 if (eeprom_buf == NULL) {
1133                         ret_val = e1000_read_nvm(hw, pba_word[1] + 0, 1,
1134                                                  &length);
1135                         if (ret_val)
1136                                 return ret_val;
1137                 } else {
1138                         if (eeprom_buf_size > pba_word[1])
1139                                 length = eeprom_buf[pba_word[1] + 0];
1140                         else
1141                                 return -E1000_ERR_PARAM;
1142                 }
1143
1144                 if (length == 0xFFFF || length == 0)
1145                         return -E1000_ERR_NVM_PBA_SECTION;
1146         } else {
1147                 /* PBA number in legacy format, there is no PBA Block. */
1148                 length = 0;
1149         }
1150
1151         if (pba_block_size != NULL)
1152                 *pba_block_size = length;
1153
1154         return E1000_SUCCESS;
1155 }
1156
1157 /**
1158  *  e1000_read_mac_addr_generic - Read device MAC address
1159  *  @hw: pointer to the HW structure
1160  *
1161  *  Reads the device MAC address from the EEPROM and stores the value.
1162  *  Since devices with two ports use the same EEPROM, we increment the
1163  *  last bit in the MAC address for the second port.
1164  **/
1165 s32 e1000_read_mac_addr_generic(struct e1000_hw *hw)
1166 {
1167         u32 rar_high;
1168         u32 rar_low;
1169         u16 i;
1170
1171         rar_high = E1000_READ_REG(hw, E1000_RAH(0));
1172         rar_low = E1000_READ_REG(hw, E1000_RAL(0));
1173
1174         for (i = 0; i < E1000_RAL_MAC_ADDR_LEN; i++)
1175                 hw->mac.perm_addr[i] = (u8)(rar_low >> (i*8));
1176
1177         for (i = 0; i < E1000_RAH_MAC_ADDR_LEN; i++)
1178                 hw->mac.perm_addr[i+4] = (u8)(rar_high >> (i*8));
1179
1180         for (i = 0; i < ETH_ADDR_LEN; i++)
1181                 hw->mac.addr[i] = hw->mac.perm_addr[i];
1182
1183         return E1000_SUCCESS;
1184 }
1185
1186 /**
1187  *  e1000_validate_nvm_checksum_generic - Validate EEPROM checksum
1188  *  @hw: pointer to the HW structure
1189  *
1190  *  Calculates the EEPROM checksum by reading/adding each word of the EEPROM
1191  *  and then verifies that the sum of the EEPROM is equal to 0xBABA.
1192  **/
1193 s32 e1000_validate_nvm_checksum_generic(struct e1000_hw *hw)
1194 {
1195         s32 ret_val;
1196         u16 checksum = 0;
1197         u16 i, nvm_data;
1198
1199         DEBUGFUNC("e1000_validate_nvm_checksum_generic");
1200
1201         for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
1202                 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
1203                 if (ret_val) {
1204                         DEBUGOUT("NVM Read Error\n");
1205                         return ret_val;
1206                 }
1207                 checksum += nvm_data;
1208         }
1209
1210         if (checksum != (u16) NVM_SUM) {
1211                 DEBUGOUT("NVM Checksum Invalid\n");
1212                 return -E1000_ERR_NVM;
1213         }
1214
1215         return E1000_SUCCESS;
1216 }
1217
1218 /**
1219  *  e1000_update_nvm_checksum_generic - Update EEPROM checksum
1220  *  @hw: pointer to the HW structure
1221  *
1222  *  Updates the EEPROM checksum by reading/adding each word of the EEPROM
1223  *  up to the checksum.  Then calculates the EEPROM checksum and writes the
1224  *  value to the EEPROM.
1225  **/
1226 s32 e1000_update_nvm_checksum_generic(struct e1000_hw *hw)
1227 {
1228         s32 ret_val;
1229         u16 checksum = 0;
1230         u16 i, nvm_data;
1231
1232         DEBUGFUNC("e1000_update_nvm_checksum");
1233
1234         for (i = 0; i < NVM_CHECKSUM_REG; i++) {
1235                 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
1236                 if (ret_val) {
1237                         DEBUGOUT("NVM Read Error while updating checksum.\n");
1238                         return ret_val;
1239                 }
1240                 checksum += nvm_data;
1241         }
1242         checksum = (u16) NVM_SUM - checksum;
1243         ret_val = hw->nvm.ops.write(hw, NVM_CHECKSUM_REG, 1, &checksum);
1244         if (ret_val)
1245                 DEBUGOUT("NVM Write Error while updating checksum.\n");
1246
1247         return ret_val;
1248 }
1249
1250 /**
1251  *  e1000_reload_nvm_generic - Reloads EEPROM
1252  *  @hw: pointer to the HW structure
1253  *
1254  *  Reloads the EEPROM by setting the "Reinitialize from EEPROM" bit in the
1255  *  extended control register.
1256  **/
1257 static void e1000_reload_nvm_generic(struct e1000_hw *hw)
1258 {
1259         u32 ctrl_ext;
1260
1261         DEBUGFUNC("e1000_reload_nvm_generic");
1262
1263         usec_delay(10);
1264         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1265         ctrl_ext |= E1000_CTRL_EXT_EE_RST;
1266         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1267         E1000_WRITE_FLUSH(hw);
1268 }
1269
1270 /**
1271  *  e1000_get_fw_version - Get firmware version information
1272  *  @hw: pointer to the HW structure
1273  *  @fw_vers: pointer to output version structure
1274  *
1275  *  unsupported/not present features return 0 in version structure
1276  **/
1277 void e1000_get_fw_version(struct e1000_hw *hw, struct e1000_fw_version *fw_vers)
1278 {
1279         u16 eeprom_verh, eeprom_verl, fw_version;
1280         u16 comb_verh, comb_verl, comb_offset;
1281
1282         memset(fw_vers, 0, sizeof(struct e1000_fw_version));
1283
1284         /* this code only applies to certain mac types */
1285         switch (hw->mac.type) {
1286         case e1000_i211:
1287                 e1000_read_invm_version(hw, fw_vers);
1288                 return;
1289         case e1000_82575:
1290         case e1000_82576:
1291         case e1000_82580:
1292         case e1000_i350:
1293         case e1000_i210:
1294                 break;
1295         default:
1296                 return;
1297         }
1298
1299         /* basic eeprom version numbers */
1300         hw->nvm.ops.read(hw, NVM_VERSION, 1, &fw_version);
1301         fw_vers->eep_major = (fw_version & NVM_MAJOR_MASK) >> NVM_MAJOR_SHIFT;
1302         fw_vers->eep_minor = (fw_version & NVM_MINOR_MASK);
1303
1304         /* etrack id */
1305         hw->nvm.ops.read(hw, NVM_ETRACK_WORD, 1, &eeprom_verl);
1306         hw->nvm.ops.read(hw, (NVM_ETRACK_WORD + 1), 1, &eeprom_verh);
1307         fw_vers->etrack_id = (eeprom_verh << NVM_ETRACK_SHIFT) | eeprom_verl;
1308
1309         switch (hw->mac.type) {
1310         case e1000_i210:
1311         case e1000_i350:
1312                 /* find combo image version */
1313                 hw->nvm.ops.read(hw, NVM_COMB_VER_PTR, 1, &comb_offset);
1314                 if ((comb_offset != 0x0) &&
1315                     (comb_offset != NVM_VER_INVALID)) {
1316
1317                         hw->nvm.ops.read(hw, (NVM_COMB_VER_OFF + comb_offset
1318                                          + 1), 1, &comb_verh);
1319                         hw->nvm.ops.read(hw, (NVM_COMB_VER_OFF + comb_offset),
1320                                          1, &comb_verl);
1321
1322                         /* get Option Rom version if it exists and is valid */
1323                         if ((comb_verh && comb_verl) &&
1324                             ((comb_verh != NVM_VER_INVALID) &&
1325                              (comb_verl != NVM_VER_INVALID))) {
1326
1327                                 fw_vers->or_valid = TRUE;
1328                                 fw_vers->or_major =
1329                                         comb_verl >> NVM_COMB_VER_SHFT;
1330                                 fw_vers->or_build =
1331                                         (comb_verl << NVM_COMB_VER_SHFT)
1332                                         | (comb_verh >> NVM_COMB_VER_SHFT);
1333                                 fw_vers->or_patch =
1334                                         comb_verh & NVM_COMB_VER_MASK;
1335                         }
1336                 }
1337                 break;
1338
1339         default:
1340                 break;
1341         }
1342         return;
1343 }
1344
1345