sys/dev/drm/i915/intel_guc_fwif.h

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23 #ifndef _INTEL_GUC_FWIF_H
  24 #define _INTEL_GUC_FWIF_H
  25
  26 /*
  27  * This file is partially autogenerated, although currently with some manual
  28  * fixups afterwards. In future, it should be entirely autogenerated, in order
  29  * to ensure that the definitions herein remain in sync with those used by the
  30  * GuC's own firmware.
  31  *
  32  * EDITING THIS FILE IS THEREFORE NOT RECOMMENDED - YOUR CHANGES MAY BE LOST.
  33  */
  34
  35 #define GFXCORE_FAMILY_GEN8             11
  36 #define GFXCORE_FAMILY_GEN9             12
  37 #define GFXCORE_FAMILY_FORCE_ULONG      0x7fffffff
  38
  39 #define GUC_CTX_PRIORITY_CRITICAL       0
  40 #define GUC_CTX_PRIORITY_HIGH           1
  41 #define GUC_CTX_PRIORITY_NORMAL         2
  42 #define GUC_CTX_PRIORITY_LOW            3
  43
  44 #define GUC_MAX_GPU_CONTEXTS            1024
  45 #define GUC_INVALID_CTX_ID              (GUC_MAX_GPU_CONTEXTS + 1)
  46
  47 /* Work queue item header definitions */
  48 #define WQ_STATUS_ACTIVE                1
  49 #define WQ_STATUS_SUSPENDED             2
  50 #define WQ_STATUS_CMD_ERROR             3
  51 #define WQ_STATUS_ENGINE_ID_NOT_USED    4
  52 #define WQ_STATUS_SUSPENDED_FROM_RESET  5
  53 #define WQ_TYPE_SHIFT                   0
  54 #define   WQ_TYPE_BATCH_BUF             (0x1 << WQ_TYPE_SHIFT)
  55 #define   WQ_TYPE_PSEUDO                (0x2 << WQ_TYPE_SHIFT)
  56 #define   WQ_TYPE_INORDER               (0x3 << WQ_TYPE_SHIFT)
  57 #define WQ_TARGET_SHIFT                 10
  58 #define WQ_LEN_SHIFT                    16
  59 #define WQ_NO_WCFLUSH_WAIT              (1 << 27)
  60 #define WQ_PRESENT_WORKLOAD             (1 << 28)
  61 #define WQ_WORKLOAD_SHIFT               29
  62 #define   WQ_WORKLOAD_GENERAL           (0 << WQ_WORKLOAD_SHIFT)
  63 #define   WQ_WORKLOAD_GPGPU             (1 << WQ_WORKLOAD_SHIFT)
  64 #define   WQ_WORKLOAD_TOUCH             (2 << WQ_WORKLOAD_SHIFT)
  65
  66 #define WQ_RING_TAIL_SHIFT              20
  67 #define WQ_RING_TAIL_MASK               (0x7FF << WQ_RING_TAIL_SHIFT)
  68
  69 #define GUC_DOORBELL_ENABLED            1
  70 #define GUC_DOORBELL_DISABLED           0
  71
  72 #define GUC_CTX_DESC_ATTR_ACTIVE        (1 << 0)
  73 #define GUC_CTX_DESC_ATTR_PENDING_DB    (1 << 1)
  74 #define GUC_CTX_DESC_ATTR_KERNEL        (1 << 2)
  75 #define GUC_CTX_DESC_ATTR_PREEMPT       (1 << 3)
  76 #define GUC_CTX_DESC_ATTR_RESET         (1 << 4)
  77 #define GUC_CTX_DESC_ATTR_WQLOCKED      (1 << 5)
  78 #define GUC_CTX_DESC_ATTR_PCH           (1 << 6)
  79
  80 /* The guc control data is 10 DWORDs */
  81 #define GUC_CTL_CTXINFO                 0
  82 #define   GUC_CTL_CTXNUM_IN16_SHIFT     0
  83 #define   GUC_CTL_BASE_ADDR_SHIFT       12
  84 #define GUC_CTL_ARAT_HIGH               1
  85 #define GUC_CTL_ARAT_LOW                2
  86 #define GUC_CTL_DEVICE_INFO             3
  87 #define   GUC_CTL_GTTYPE_SHIFT          0
  88 #define   GUC_CTL_COREFAMILY_SHIFT      7
  89 #define GUC_CTL_LOG_PARAMS              4
  90 #define   GUC_LOG_VALID                 (1 << 0)
  91 #define   GUC_LOG_NOTIFY_ON_HALF_FULL   (1 << 1)
  92 #define   GUC_LOG_ALLOC_IN_MEGABYTE     (1 << 3)
  93 #define   GUC_LOG_CRASH_PAGES           1
  94 #define   GUC_LOG_CRASH_SHIFT           4
  95 #define   GUC_LOG_DPC_PAGES             3
  96 #define   GUC_LOG_DPC_SHIFT             6
  97 #define   GUC_LOG_ISR_PAGES             3
  98 #define   GUC_LOG_ISR_SHIFT             9
  99 #define   GUC_LOG_BUF_ADDR_SHIFT        12
 100 #define GUC_CTL_PAGE_FAULT_CONTROL      5
 101 #define GUC_CTL_WA                      6
 102 #define   GUC_CTL_WA_UK_BY_DRIVER       (1 << 3)
 103 #define GUC_CTL_FEATURE                 7
 104 #define   GUC_CTL_VCS2_ENABLED          (1 << 0)
 105 #define   GUC_CTL_KERNEL_SUBMISSIONS    (1 << 1)
 106 #define   GUC_CTL_FEATURE2              (1 << 2)
 107 #define   GUC_CTL_POWER_GATING          (1 << 3)
 108 #define   GUC_CTL_DISABLE_SCHEDULER     (1 << 4)
 109 #define   GUC_CTL_PREEMPTION_LOG        (1 << 5)
 110 #define   GUC_CTL_ENABLE_SLPC           (1 << 7)
 111 #define GUC_CTL_DEBUG                   8
 112 #define   GUC_LOG_VERBOSITY_SHIFT       0
 113 #define   GUC_LOG_VERBOSITY_LOW         (0 << GUC_LOG_VERBOSITY_SHIFT)
 114 #define   GUC_LOG_VERBOSITY_MED         (1 << GUC_LOG_VERBOSITY_SHIFT)
 115 #define   GUC_LOG_VERBOSITY_HIGH        (2 << GUC_LOG_VERBOSITY_SHIFT)
 116 #define   GUC_LOG_VERBOSITY_ULTRA       (3 << GUC_LOG_VERBOSITY_SHIFT)
 117 /* Verbosity range-check limits, without the shift */
 118 #define   GUC_LOG_VERBOSITY_MIN         0
 119 #define   GUC_LOG_VERBOSITY_MAX         3
 120
 121 #define GUC_CTL_MAX_DWORDS              (GUC_CTL_DEBUG + 1)
 122
 123 struct guc_doorbell_info {
 124         u32 db_status;
 125         u32 cookie;
 126         u32 reserved[14];
 127 } __packed;
 128
 129 union guc_doorbell_qw {
 130         struct {
 131                 u32 db_status;
 132                 u32 cookie;
 133         };
 134         u64 value_qw;
 135 } __packed;
 136
 137 #define GUC_MAX_DOORBELLS               256
 138 #define GUC_INVALID_DOORBELL_ID         (GUC_MAX_DOORBELLS)
 139
 140 #define GUC_DB_SIZE                     (PAGE_SIZE)
 141 #define GUC_WQ_SIZE                     (PAGE_SIZE * 2)
 142
 143 /* Work item for submitting workloads into work queue of GuC. */
 144 struct guc_wq_item {
 145         u32 header;
 146         u32 context_desc;
 147         u32 ring_tail;
 148         u32 fence_id;
 149 } __packed;
 150
 151 struct guc_process_desc {
 152         u32 context_id;
 153         u64 db_base_addr;
 154         u32 head;
 155         u32 tail;
 156         u32 error_offset;
 157         u64 wq_base_addr;
 158         u32 wq_size_bytes;
 159         u32 wq_status;
 160         u32 engine_presence;
 161         u32 priority;
 162         u32 reserved[30];
 163 } __packed;
 164
 165 /* engine id and context id is packed into guc_execlist_context.context_id*/
 166 #define GUC_ELC_CTXID_OFFSET            0
 167 #define GUC_ELC_ENGINE_OFFSET           29
 168
 169 /* The execlist context including software and HW information */
 170 struct guc_execlist_context {
 171         u32 context_desc;
 172         u32 context_id;
 173         u32 ring_status;
 174         u32 ring_lcra;
 175         u32 ring_begin;
 176         u32 ring_end;
 177         u32 ring_next_free_location;
 178         u32 ring_current_tail_pointer_value;
 179         u8 engine_state_submit_value;
 180         u8 engine_state_wait_value;
 181         u16 pagefault_count;
 182         u16 engine_submit_queue_count;
 183 } __packed;
 184
 185 /*Context descriptor for communicating between uKernel and Driver*/
 186 struct guc_context_desc {
 187         u32 sched_common_area;
 188         u32 context_id;
 189         u32 pas_id;
 190         u8 engines_used;
 191         u64 db_trigger_cpu;
 192         u32 db_trigger_uk;
 193         u64 db_trigger_phy;
 194         u16 db_id;
 195
 196         struct guc_execlist_context lrc[I915_NUM_RINGS];
 197
 198         u8 attribute;
 199
 200         u32 priority;
 201
 202         u32 wq_sampled_tail_offset;
 203         u32 wq_total_submit_enqueues;
 204
 205         u32 process_desc;
 206         u32 wq_addr;
 207         u32 wq_size;
 208
 209         u32 engine_presence;
 210
 211         u32 reserved0[1];
 212         u64 reserved1[1];
 213
 214         u64 desc_private;
 215 } __packed;
 216
 217 /* This Action will be programmed in C180 - SOFT_SCRATCH_O_REG */
 218 enum host2guc_action {
 219         HOST2GUC_ACTION_DEFAULT = 0x0,
 220         HOST2GUC_ACTION_SAMPLE_FORCEWAKE = 0x6,
 221         HOST2GUC_ACTION_ALLOCATE_DOORBELL = 0x10,
 222         HOST2GUC_ACTION_DEALLOCATE_DOORBELL = 0x20,
 223         HOST2GUC_ACTION_SLPC_REQUEST = 0x3003,
 224         HOST2GUC_ACTION_LIMIT
 225 };
 226
 227 /*
 228  * The GuC sends its response to a command by overwriting the
 229  * command in SS0. The response is distinguishable from a command
 230  * by the fact that all the MASK bits are set. The remaining bits
 231  * give more detail.
 232  */
 233 #define GUC2HOST_RESPONSE_MASK          ((u32)0xF0000000)
 234 #define GUC2HOST_IS_RESPONSE(x)         ((u32)(x) >= GUC2HOST_RESPONSE_MASK)
 235 #define GUC2HOST_STATUS(x)              (GUC2HOST_RESPONSE_MASK | (x))
 236
 237 /* GUC will return status back to SOFT_SCRATCH_O_REG */
 238 enum guc2host_status {
 239         GUC2HOST_STATUS_SUCCESS = GUC2HOST_STATUS(0x0),
 240         GUC2HOST_STATUS_ALLOCATE_DOORBELL_FAIL = GUC2HOST_STATUS(0x10),
 241         GUC2HOST_STATUS_DEALLOCATE_DOORBELL_FAIL = GUC2HOST_STATUS(0x20),
 242         GUC2HOST_STATUS_GENERIC_FAIL = GUC2HOST_STATUS(0x0000F000)
 243 };
 244
 245 #endif