sys/dev/drm/radeon/dce6_afmt.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/hdmi.h>
  24 #include <drm/drmP.h>
  25 #include "radeon.h"
  26 #include "radeon_asic.h"
  27 #include "sid.h"
  28
  29 static u32 dce6_endpoint_rreg(struct radeon_device *rdev,
  30                               u32 block_offset, u32 reg)
  31 {
  32         u32 r;
  33
  34         spin_lock(&rdev->end_idx_lock);
  35         WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
  36         r = RREG32(AZ_F0_CODEC_ENDPOINT_DATA + block_offset);
  37         spin_unlock(&rdev->end_idx_lock);
  38
  39         return r;
  40 }
  41
  42 static void dce6_endpoint_wreg(struct radeon_device *rdev,
  43                                u32 block_offset, u32 reg, u32 v)
  44 {
  45         spin_lock(&rdev->end_idx_lock);
  46         if (ASIC_IS_DCE8(rdev))
  47                 WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
  48         else
  49                 WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset,
  50                        AZ_ENDPOINT_REG_WRITE_EN | AZ_ENDPOINT_REG_INDEX(reg));
  51         WREG32(AZ_F0_CODEC_ENDPOINT_DATA + block_offset, v);
  52         spin_unlock(&rdev->end_idx_lock);
  53 }
  54
  55 #define RREG32_ENDPOINT(block, reg) dce6_endpoint_rreg(rdev, (block), (reg))
  56 #define WREG32_ENDPOINT(block, reg, v) dce6_endpoint_wreg(rdev, (block), (reg), (v))
  57
  58
  59 static void dce6_afmt_get_connected_pins(struct radeon_device *rdev)
  60 {
  61         int i;
  62         u32 offset, tmp;
  63
  64         for (i = 0; i < rdev->audio.num_pins; i++) {
  65                 offset = rdev->audio.pin[i].offset;
  66                 tmp = RREG32_ENDPOINT(offset,
  67                                       AZ_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
  68                 if (((tmp & PORT_CONNECTIVITY_MASK) >> PORT_CONNECTIVITY_SHIFT) == 1)
  69                         rdev->audio.pin[i].connected = false;
  70                 else
  71                         rdev->audio.pin[i].connected = true;
  72         }
  73 }
  74
  75 struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev)
  76 {
  77         int i;
  78
  79         dce6_afmt_get_connected_pins(rdev);
  80
  81         for (i = 0; i < rdev->audio.num_pins; i++) {
  82                 if (rdev->audio.pin[i].connected)
  83                         return &rdev->audio.pin[i];
  84         }
  85         DRM_ERROR("No connected audio pins found!\n");
  86         return NULL;
  87 }
  88
  89 void dce6_afmt_select_pin(struct drm_encoder *encoder)
  90 {
  91         struct radeon_device *rdev = encoder->dev->dev_private;
  92         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  93         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
  94         u32 offset;
  95
  96         if (!dig || !dig->afmt || !dig->afmt->pin)
  97                 return;
  98
  99         offset = dig->afmt->offset;
 100
 101         WREG32(AFMT_AUDIO_SRC_CONTROL + offset,
 102                AFMT_AUDIO_SRC_SELECT(dig->afmt->pin->id));
 103 }
 104
 105 void dce6_afmt_write_latency_fields(struct drm_encoder *encoder,
 106                                     struct drm_display_mode *mode)
 107 {
 108         struct radeon_device *rdev = encoder->dev->dev_private;
 109         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 110         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 111         struct drm_connector *connector;
 112         struct radeon_connector *radeon_connector = NULL;
 113         u32 tmp = 0, offset;
 114
 115         if (!dig || !dig->afmt || !dig->afmt->pin)
 116                 return;
 117
 118         offset = dig->afmt->pin->offset;
 119
 120         list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
 121                 if (connector->encoder == encoder) {
 122                         radeon_connector = to_radeon_connector(connector);
 123                         break;
 124                 }
 125         }
 126
 127         if (!radeon_connector) {
 128                 DRM_ERROR("Couldn't find encoder's connector\n");
 129                 return;
 130         }
 131
 132         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
 133                 if (connector->latency_present[1])
 134                         tmp = VIDEO_LIPSYNC(connector->video_latency[1]) |
 135                                 AUDIO_LIPSYNC(connector->audio_latency[1]);
 136                 else
 137                         tmp = VIDEO_LIPSYNC(0) | AUDIO_LIPSYNC(0);
 138         } else {
 139                 if (connector->latency_present[0])
 140                         tmp = VIDEO_LIPSYNC(connector->video_latency[0]) |
 141                                 AUDIO_LIPSYNC(connector->audio_latency[0]);
 142                 else
 143                         tmp = VIDEO_LIPSYNC(0) | AUDIO_LIPSYNC(0);
 144         }
 145         WREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
 146 }
 147
 148 void dce6_afmt_write_speaker_allocation(struct drm_encoder *encoder)
 149 {
 150         struct radeon_device *rdev = encoder->dev->dev_private;
 151         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 152         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 153         struct drm_connector *connector;
 154         struct radeon_connector *radeon_connector = NULL;
 155         u32 offset, tmp;
 156         u8 *sadb = NULL;
 157         int sad_count;
 158
 159         if (!dig || !dig->afmt || !dig->afmt->pin)
 160                 return;
 161
 162         offset = dig->afmt->pin->offset;
 163
 164         list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
 165                 if (connector->encoder == encoder) {
 166                         radeon_connector = to_radeon_connector(connector);
 167                         break;
 168                 }
 169         }
 170
 171         if (!radeon_connector) {
 172                 DRM_ERROR("Couldn't find encoder's connector\n");
 173                 return;
 174         }
 175
 176         sad_count = drm_edid_to_speaker_allocation(radeon_connector_edid(connector), &sadb);
 177         if (sad_count < 0) {
 178                 DRM_DEBUG("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
 179                 sad_count = 0;
 180         }
 181
 182         /* program the speaker allocation */
 183         tmp = RREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
 184         tmp &= ~(DP_CONNECTION | SPEAKER_ALLOCATION_MASK);
 185         /* set HDMI mode */
 186         tmp |= HDMI_CONNECTION;
 187         if (sad_count)
 188                 tmp |= SPEAKER_ALLOCATION(sadb[0]);
 189         else
 190                 tmp |= SPEAKER_ALLOCATION(5); /* stereo */
 191         WREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
 192
 193         kfree(sadb);
 194 }
 195
 196 void dce6_afmt_write_sad_regs(struct drm_encoder *encoder)
 197 {
 198         struct radeon_device *rdev = encoder->dev->dev_private;
 199         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 200         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 201         u32 offset;
 202         struct drm_connector *connector;
 203         struct radeon_connector *radeon_connector = NULL;
 204         struct cea_sad *sads;
 205         int i, sad_count;
 206
 207         static const u16 eld_reg_to_type[][2] = {
 208                 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
 209                 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
 210                 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
 211                 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
 212                 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
 213                 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
 214                 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
 215                 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
 216                 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
 217                 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
 218                 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
 219                 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
 220         };
 221
 222         if (!dig || !dig->afmt || !dig->afmt->pin)
 223                 return;
 224
 225         offset = dig->afmt->pin->offset;
 226
 227         list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
 228                 if (connector->encoder == encoder) {
 229                         radeon_connector = to_radeon_connector(connector);
 230                         break;
 231                 }
 232         }
 233
 234         if (!radeon_connector) {
 235                 DRM_ERROR("Couldn't find encoder's connector\n");
 236                 return;
 237         }
 238
 239         sad_count = drm_edid_to_sad(radeon_connector_edid(connector), &sads);
 240         if (sad_count <= 0) {
 241                 DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
 242                 return;
 243         }
 244         BUG_ON(!sads);
 245
 246         for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
 247                 u32 value = 0;
 248                 u8 stereo_freqs = 0;
 249                 int max_channels = -1;
 250                 int j;
 251
 252                 for (j = 0; j < sad_count; j++) {
 253                         struct cea_sad *sad = &sads[j];
 254
 255                         if (sad->format == eld_reg_to_type[i][1]) {
 256                                 if (sad->channels > max_channels) {
 257                                         value = MAX_CHANNELS(sad->channels) |
 258                                                 DESCRIPTOR_BYTE_2(sad->byte2) |
 259                                                 SUPPORTED_FREQUENCIES(sad->freq);
 260                                         max_channels = sad->channels;
 261                                 }
 262
 263                                 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
 264                                         stereo_freqs |= sad->freq;
 265                                 else
 266                                         break;
 267                         }
 268                 }
 269
 270                 value |= SUPPORTED_FREQUENCIES_STEREO(stereo_freqs);
 271
 272                 WREG32_ENDPOINT(offset, eld_reg_to_type[i][0], value);
 273         }
 274
 275         kfree(sads);
 276 }
 277
 278 static int dce6_audio_chipset_supported(struct radeon_device *rdev)
 279 {
 280         return !ASIC_IS_NODCE(rdev);
 281 }
 282
 283 void dce6_audio_enable(struct radeon_device *rdev,
 284                        struct r600_audio_pin *pin,
 285                        u8 enable_mask)
 286 {
 287         if (!pin)
 288                 return;
 289
 290         WREG32_ENDPOINT(pin->offset, AZ_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
 291                         enable_mask ? AUDIO_ENABLED : 0);
 292 }
 293
 294 static const u32 pin_offsets[7] =
 295 {
 296         (0x5e00 - 0x5e00),
 297         (0x5e18 - 0x5e00),
 298         (0x5e30 - 0x5e00),
 299         (0x5e48 - 0x5e00),
 300         (0x5e60 - 0x5e00),
 301         (0x5e78 - 0x5e00),
 302         (0x5e90 - 0x5e00),
 303 };
 304
 305 int dce6_audio_init(struct radeon_device *rdev)
 306 {
 307         int i;
 308
 309         if (!radeon_audio || !dce6_audio_chipset_supported(rdev))
 310                 return 0;
 311
 312         rdev->audio.enabled = true;
 313
 314         if (ASIC_IS_DCE81(rdev)) /* KV: 4 streams, 7 endpoints */
 315                 rdev->audio.num_pins = 7;
 316         else if (ASIC_IS_DCE83(rdev)) /* KB: 2 streams, 3 endpoints */
 317                 rdev->audio.num_pins = 3;
 318         else if (ASIC_IS_DCE8(rdev)) /* BN/HW: 6 streams, 7 endpoints */
 319                 rdev->audio.num_pins = 7;
 320         else if (ASIC_IS_DCE61(rdev)) /* TN: 4 streams, 6 endpoints */
 321                 rdev->audio.num_pins = 6;
 322         else if (ASIC_IS_DCE64(rdev)) /* OL: 2 streams, 2 endpoints */
 323                 rdev->audio.num_pins = 2;
 324         else /* SI: 6 streams, 6 endpoints */
 325                 rdev->audio.num_pins = 6;
 326
 327         for (i = 0; i < rdev->audio.num_pins; i++) {
 328                 rdev->audio.pin[i].channels = -1;
 329                 rdev->audio.pin[i].rate = -1;
 330                 rdev->audio.pin[i].bits_per_sample = -1;
 331                 rdev->audio.pin[i].status_bits = 0;
 332                 rdev->audio.pin[i].category_code = 0;
 333                 rdev->audio.pin[i].connected = false;
 334                 rdev->audio.pin[i].offset = pin_offsets[i];
 335                 rdev->audio.pin[i].id = i;
 336                 /* disable audio.  it will be set up later */
 337                 dce6_audio_enable(rdev, &rdev->audio.pin[i], false);
 338         }
 339
 340         return 0;
 341 }
 342
 343 void dce6_audio_fini(struct radeon_device *rdev)
 344 {
 345         int i;
 346
 347         if (!rdev->audio.enabled)
 348                 return;
 349
 350         for (i = 0; i < rdev->audio.num_pins; i++)
 351                 dce6_audio_enable(rdev, &rdev->audio.pin[i], false);
 352
 353         rdev->audio.enabled = false;
 354 }