2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
25 * Michel Thierry <michel.thierry@intel.com>
26 * Thomas Daniel <thomas.daniel@intel.com>
27 * Oscar Mateo <oscar.mateo@intel.com>
32 * DOC: Logical Rings, Logical Ring Contexts and Execlists
35 * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts".
36 * These expanded contexts enable a number of new abilities, especially
37 * "Execlists" (also implemented in this file).
39 * One of the main differences with the legacy HW contexts is that logical
40 * ring contexts incorporate many more things to the context's state, like
41 * PDPs or ringbuffer control registers:
43 * The reason why PDPs are included in the context is straightforward: as
44 * PPGTTs (per-process GTTs) are actually per-context, having the PDPs
45 * contained there mean you don't need to do a ppgtt->switch_mm yourself,
46 * instead, the GPU will do it for you on the context switch.
48 * But, what about the ringbuffer control registers (head, tail, etc..)?
49 * shouldn't we just need a set of those per engine command streamer? This is
50 * where the name "Logical Rings" starts to make sense: by virtualizing the
51 * rings, the engine cs shifts to a new "ring buffer" with every context
52 * switch. When you want to submit a workload to the GPU you: A) choose your
53 * context, B) find its appropriate virtualized ring, C) write commands to it
54 * and then, finally, D) tell the GPU to switch to that context.
56 * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch
57 * to a contexts is via a context execution list, ergo "Execlists".
60 * Regarding the creation of contexts, we have:
62 * - One global default context.
63 * - One local default context for each opened fd.
64 * - One local extra context for each context create ioctl call.
66 * Now that ringbuffers belong per-context (and not per-engine, like before)
67 * and that contexts are uniquely tied to a given engine (and not reusable,
68 * like before) we need:
70 * - One ringbuffer per-engine inside each context.
71 * - One backing object per-engine inside each context.
73 * The global default context starts its life with these new objects fully
74 * allocated and populated. The local default context for each opened fd is
75 * more complex, because we don't know at creation time which engine is going
76 * to use them. To handle this, we have implemented a deferred creation of LR
79 * The local context starts its life as a hollow or blank holder, that only
80 * gets populated for a given engine once we receive an execbuffer. If later
81 * on we receive another execbuffer ioctl for the same context but a different
82 * engine, we allocate/populate a new ringbuffer and context backing object and
85 * Finally, regarding local contexts created using the ioctl call: as they are
86 * only allowed with the render ring, we can allocate & populate them right
87 * away (no need to defer anything, at least for now).
89 * Execlists implementation:
90 * Execlists are the new method by which, on gen8+ hardware, workloads are
91 * submitted for execution (as opposed to the legacy, ringbuffer-based, method).
92 * This method works as follows:
94 * When a request is committed, its commands (the BB start and any leading or
95 * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer
96 * for the appropriate context. The tail pointer in the hardware context is not
97 * updated at this time, but instead, kept by the driver in the ringbuffer
98 * structure. A structure representing this request is added to a request queue
99 * for the appropriate engine: this structure contains a copy of the context's
100 * tail after the request was written to the ring buffer and a pointer to the
103 * If the engine's request queue was empty before the request was added, the
104 * queue is processed immediately. Otherwise the queue will be processed during
105 * a context switch interrupt. In any case, elements on the queue will get sent
106 * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a
107 * globally unique 20-bits submission ID.
109 * When execution of a request completes, the GPU updates the context status
110 * buffer with a context complete event and generates a context switch interrupt.
111 * During the interrupt handling, the driver examines the events in the buffer:
112 * for each context complete event, if the announced ID matches that on the head
113 * of the request queue, then that request is retired and removed from the queue.
115 * After processing, if any requests were retired and the queue is not empty
116 * then a new execution list can be submitted. The two requests at the front of
117 * the queue are next to be submitted but since a context may not occur twice in
118 * an execution list, if subsequent requests have the same ID as the first then
119 * the two requests must be combined. This is done simply by discarding requests
120 * at the head of the queue until either only one requests is left (in which case
121 * we use a NULL second context) or the first two requests have unique IDs.
123 * By always executing the first two requests in the queue the driver ensures
124 * that the GPU is kept as busy as possible. In the case where a single context
125 * completes but a second context is still executing, the request for this second
126 * context will be at the head of the queue when we remove the first one. This
127 * request will then be resubmitted along with a new request for a different context,
128 * which will cause the hardware to continue executing the second request and queue
129 * the new request (the GPU detects the condition of a context getting preempted
130 * with the same context and optimizes the context switch flow by not doing
131 * preemption, but just sampling the new tail pointer).
135 #include <drm/drmP.h>
136 #include <drm/i915_drm.h>
137 #include "i915_drv.h"
138 #include "intel_drv.h"
140 #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE)
141 #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE)
142 #define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE)
144 #define RING_EXECLIST_QFULL (1 << 0x2)
145 #define RING_EXECLIST1_VALID (1 << 0x3)
146 #define RING_EXECLIST0_VALID (1 << 0x4)
147 #define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE)
148 #define RING_EXECLIST1_ACTIVE (1 << 0x11)
149 #define RING_EXECLIST0_ACTIVE (1 << 0x12)
151 #define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0)
152 #define GEN8_CTX_STATUS_PREEMPTED (1 << 1)
153 #define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2)
154 #define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3)
155 #define GEN8_CTX_STATUS_COMPLETE (1 << 4)
156 #define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15)
158 #define CTX_LRI_HEADER_0 0x01
159 #define CTX_CONTEXT_CONTROL 0x02
160 #define CTX_RING_HEAD 0x04
161 #define CTX_RING_TAIL 0x06
162 #define CTX_RING_BUFFER_START 0x08
163 #define CTX_RING_BUFFER_CONTROL 0x0a
164 #define CTX_BB_HEAD_U 0x0c
165 #define CTX_BB_HEAD_L 0x0e
166 #define CTX_BB_STATE 0x10
167 #define CTX_SECOND_BB_HEAD_U 0x12
168 #define CTX_SECOND_BB_HEAD_L 0x14
169 #define CTX_SECOND_BB_STATE 0x16
170 #define CTX_BB_PER_CTX_PTR 0x18
171 #define CTX_RCS_INDIRECT_CTX 0x1a
172 #define CTX_RCS_INDIRECT_CTX_OFFSET 0x1c
173 #define CTX_LRI_HEADER_1 0x21
174 #define CTX_CTX_TIMESTAMP 0x22
175 #define CTX_PDP3_UDW 0x24
176 #define CTX_PDP3_LDW 0x26
177 #define CTX_PDP2_UDW 0x28
178 #define CTX_PDP2_LDW 0x2a
179 #define CTX_PDP1_UDW 0x2c
180 #define CTX_PDP1_LDW 0x2e
181 #define CTX_PDP0_UDW 0x30
182 #define CTX_PDP0_LDW 0x32
183 #define CTX_LRI_HEADER_2 0x41
184 #define CTX_R_PWR_CLK_STATE 0x42
185 #define CTX_GPGPU_CSR_BASE_ADDRESS 0x44
187 #define GEN8_CTX_VALID (1<<0)
188 #define GEN8_CTX_FORCE_PD_RESTORE (1<<1)
189 #define GEN8_CTX_FORCE_RESTORE (1<<2)
190 #define GEN8_CTX_L3LLC_COHERENT (1<<5)
191 #define GEN8_CTX_PRIVILEGE (1<<8)
193 ADVANCED_CONTEXT = 0,
198 #define GEN8_CTX_MODE_SHIFT 3
201 FAULT_AND_HALT, /* Debug only */
203 FAULT_AND_CONTINUE /* Unsupported */
205 #define GEN8_CTX_ID_SHIFT 32
207 static int intel_lr_context_pin(struct intel_engine_cs *ring,
208 struct intel_context *ctx);
211 * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists
213 * @enable_execlists: value of i915.enable_execlists module parameter.
215 * Only certain platforms support Execlists (the prerequisites being
216 * support for Logical Ring Contexts and Aliasing PPGTT or better).
218 * Return: 1 if Execlists is supported and has to be enabled.
220 int intel_sanitize_enable_execlists(struct drm_device *dev, int enable_execlists)
222 WARN_ON(i915.enable_ppgtt == -1);
224 if (INTEL_INFO(dev)->gen >= 9)
227 if (enable_execlists == 0)
230 if (HAS_LOGICAL_RING_CONTEXTS(dev) && USES_PPGTT(dev) &&
231 i915.use_mmio_flip >= 0)
238 * intel_execlists_ctx_id() - get the Execlists Context ID
239 * @ctx_obj: Logical Ring Context backing object.
241 * Do not confuse with ctx->id! Unfortunately we have a name overload
242 * here: the old context ID we pass to userspace as a handler so that
243 * they can refer to a context, and the new context ID we pass to the
244 * ELSP so that the GPU can inform us of the context status via
247 * Return: 20-bits globally unique context ID.
249 u32 intel_execlists_ctx_id(struct drm_i915_gem_object *ctx_obj)
251 u32 lrca = i915_gem_obj_ggtt_offset(ctx_obj);
253 /* LRCA is required to be 4K aligned so the more significant 20 bits
254 * are globally unique */
258 static uint64_t execlists_ctx_descriptor(struct drm_i915_gem_object *ctx_obj)
261 uint64_t lrca = i915_gem_obj_ggtt_offset(ctx_obj);
263 WARN_ON(lrca & 0xFFFFFFFF00000FFFULL);
265 desc = GEN8_CTX_VALID;
266 desc |= LEGACY_CONTEXT << GEN8_CTX_MODE_SHIFT;
267 desc |= GEN8_CTX_L3LLC_COHERENT;
268 desc |= GEN8_CTX_PRIVILEGE;
270 desc |= (u64)intel_execlists_ctx_id(ctx_obj) << GEN8_CTX_ID_SHIFT;
272 /* TODO: WaDisableLiteRestore when we start using semaphore
273 * signalling between Command Streamers */
274 /* desc |= GEN8_CTX_FORCE_RESTORE; */
279 static void execlists_elsp_write(struct intel_engine_cs *ring,
280 struct drm_i915_gem_object *ctx_obj0,
281 struct drm_i915_gem_object *ctx_obj1)
283 struct drm_device *dev = ring->dev;
284 struct drm_i915_private *dev_priv = dev->dev_private;
288 /* XXX: You must always write both descriptors in the order below. */
290 temp = execlists_ctx_descriptor(ctx_obj1);
293 desc[1] = (u32)(temp >> 32);
296 temp = execlists_ctx_descriptor(ctx_obj0);
297 desc[3] = (u32)(temp >> 32);
300 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
301 I915_WRITE(RING_ELSP(ring), desc[1]);
302 I915_WRITE(RING_ELSP(ring), desc[0]);
303 I915_WRITE(RING_ELSP(ring), desc[3]);
305 /* The context is automatically loaded after the following */
306 I915_WRITE(RING_ELSP(ring), desc[2]);
308 /* ELSP is a wo register, so use another nearby reg for posting instead */
309 POSTING_READ(RING_EXECLIST_STATUS(ring));
310 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
313 static int execlists_update_context(struct drm_i915_gem_object *ctx_obj,
314 struct drm_i915_gem_object *ring_obj,
317 struct vm_page *page;
320 page = i915_gem_object_get_page(ctx_obj, 1);
321 reg_state = kmap_atomic(page);
323 reg_state[CTX_RING_TAIL+1] = tail;
324 reg_state[CTX_RING_BUFFER_START+1] = i915_gem_obj_ggtt_offset(ring_obj);
326 kunmap_atomic(reg_state);
331 static void execlists_submit_contexts(struct intel_engine_cs *ring,
332 struct intel_context *to0, u32 tail0,
333 struct intel_context *to1, u32 tail1)
335 struct drm_i915_gem_object *ctx_obj0 = to0->engine[ring->id].state;
336 struct intel_ringbuffer *ringbuf0 = to0->engine[ring->id].ringbuf;
337 struct drm_i915_gem_object *ctx_obj1 = NULL;
338 struct intel_ringbuffer *ringbuf1 = NULL;
341 WARN_ON(!i915_gem_obj_is_pinned(ctx_obj0));
342 WARN_ON(!i915_gem_obj_is_pinned(ringbuf0->obj));
344 execlists_update_context(ctx_obj0, ringbuf0->obj, tail0);
347 ringbuf1 = to1->engine[ring->id].ringbuf;
348 ctx_obj1 = to1->engine[ring->id].state;
350 WARN_ON(!i915_gem_obj_is_pinned(ctx_obj1));
351 WARN_ON(!i915_gem_obj_is_pinned(ringbuf1->obj));
353 execlists_update_context(ctx_obj1, ringbuf1->obj, tail1);
356 execlists_elsp_write(ring, ctx_obj0, ctx_obj1);
359 static void execlists_context_unqueue(struct intel_engine_cs *ring)
361 struct drm_i915_gem_request *req0 = NULL, *req1 = NULL;
362 struct drm_i915_gem_request *cursor = NULL, *tmp = NULL;
364 assert_spin_locked(&ring->execlist_lock);
366 if (list_empty(&ring->execlist_queue))
369 /* Try to read in pairs */
370 list_for_each_entry_safe(cursor, tmp, &ring->execlist_queue,
374 } else if (req0->ctx == cursor->ctx) {
375 /* Same ctx: ignore first request, as second request
376 * will update tail past first request's workload */
377 cursor->elsp_submitted = req0->elsp_submitted;
378 list_del(&req0->execlist_link);
379 list_add_tail(&req0->execlist_link,
380 &ring->execlist_retired_req_list);
388 WARN_ON(req1 && req1->elsp_submitted);
390 execlists_submit_contexts(ring, req0->ctx, req0->tail,
391 req1 ? req1->ctx : NULL,
392 req1 ? req1->tail : 0);
394 req0->elsp_submitted++;
396 req1->elsp_submitted++;
399 static bool execlists_check_remove_request(struct intel_engine_cs *ring,
402 struct drm_i915_gem_request *head_req;
404 assert_spin_locked(&ring->execlist_lock);
406 head_req = list_first_entry_or_null(&ring->execlist_queue,
407 struct drm_i915_gem_request,
410 if (head_req != NULL) {
411 struct drm_i915_gem_object *ctx_obj =
412 head_req->ctx->engine[ring->id].state;
413 if (intel_execlists_ctx_id(ctx_obj) == request_id) {
414 WARN(head_req->elsp_submitted == 0,
415 "Never submitted head request\n");
417 if (--head_req->elsp_submitted <= 0) {
418 list_del(&head_req->execlist_link);
419 list_add_tail(&head_req->execlist_link,
420 &ring->execlist_retired_req_list);
430 * intel_lrc_irq_handler() - handle Context Switch interrupts
431 * @ring: Engine Command Streamer to handle.
433 * Check the unread Context Status Buffers and manage the submission of new
434 * contexts to the ELSP accordingly.
436 void intel_lrc_irq_handler(struct intel_engine_cs *ring)
438 struct drm_i915_private *dev_priv = ring->dev->dev_private;
444 u32 submit_contexts = 0;
446 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring));
448 read_pointer = ring->next_context_status_buffer;
449 write_pointer = status_pointer & 0x07;
450 if (read_pointer > write_pointer)
453 lockmgr(&ring->execlist_lock, LK_EXCLUSIVE);
455 while (read_pointer < write_pointer) {
457 status = I915_READ(RING_CONTEXT_STATUS_BUF(ring) +
458 (read_pointer % 6) * 8);
459 status_id = I915_READ(RING_CONTEXT_STATUS_BUF(ring) +
460 (read_pointer % 6) * 8 + 4);
462 if (status & GEN8_CTX_STATUS_PREEMPTED) {
463 if (status & GEN8_CTX_STATUS_LITE_RESTORE) {
464 if (execlists_check_remove_request(ring, status_id))
465 WARN(1, "Lite Restored request removed from queue\n");
467 WARN(1, "Preemption without Lite Restore\n");
470 if ((status & GEN8_CTX_STATUS_ACTIVE_IDLE) ||
471 (status & GEN8_CTX_STATUS_ELEMENT_SWITCH)) {
472 if (execlists_check_remove_request(ring, status_id))
477 if (submit_contexts != 0)
478 execlists_context_unqueue(ring);
480 lockmgr(&ring->execlist_lock, LK_RELEASE);
482 WARN(submit_contexts > 2, "More than two context complete events?\n");
483 ring->next_context_status_buffer = write_pointer % 6;
485 I915_WRITE(RING_CONTEXT_STATUS_PTR(ring),
486 ((u32)ring->next_context_status_buffer & 0x07) << 8);
489 static int execlists_context_queue(struct intel_engine_cs *ring,
490 struct intel_context *to,
492 struct drm_i915_gem_request *request)
494 struct drm_i915_gem_request *cursor;
495 struct drm_i915_private *dev_priv = ring->dev->dev_private;
496 int num_elements = 0;
498 if (to != ring->default_context)
499 intel_lr_context_pin(ring, to);
503 * If there isn't a request associated with this submission,
504 * create one as a temporary holder.
506 request = kzalloc(sizeof(*request), GFP_KERNEL);
509 request->ring = ring;
511 kref_init(&request->ref);
512 request->uniq = dev_priv->request_uniq++;
513 i915_gem_context_reference(request->ctx);
515 i915_gem_request_reference(request);
516 WARN_ON(to != request->ctx);
518 request->tail = tail;
520 intel_runtime_pm_get(dev_priv);
522 lockmgr(&ring->execlist_lock, LK_EXCLUSIVE);
524 list_for_each_entry(cursor, &ring->execlist_queue, execlist_link)
525 if (++num_elements > 2)
528 if (num_elements > 2) {
529 struct drm_i915_gem_request *tail_req;
531 tail_req = list_last_entry(&ring->execlist_queue,
532 struct drm_i915_gem_request,
535 if (to == tail_req->ctx) {
536 WARN(tail_req->elsp_submitted != 0,
537 "More than 2 already-submitted reqs queued\n");
538 list_del(&tail_req->execlist_link);
539 list_add_tail(&tail_req->execlist_link,
540 &ring->execlist_retired_req_list);
544 list_add_tail(&request->execlist_link, &ring->execlist_queue);
545 if (num_elements == 0)
546 execlists_context_unqueue(ring);
548 lockmgr(&ring->execlist_lock, LK_RELEASE);
553 static int logical_ring_invalidate_all_caches(struct intel_ringbuffer *ringbuf,
554 struct intel_context *ctx)
556 struct intel_engine_cs *ring = ringbuf->ring;
557 uint32_t flush_domains;
561 if (ring->gpu_caches_dirty)
562 flush_domains = I915_GEM_GPU_DOMAINS;
564 ret = ring->emit_flush(ringbuf, ctx,
565 I915_GEM_GPU_DOMAINS, flush_domains);
569 ring->gpu_caches_dirty = false;
573 static int execlists_move_to_gpu(struct intel_ringbuffer *ringbuf,
574 struct intel_context *ctx,
575 struct list_head *vmas)
577 struct intel_engine_cs *ring = ringbuf->ring;
578 struct i915_vma *vma;
579 uint32_t flush_domains = 0;
580 bool flush_chipset = false;
583 list_for_each_entry(vma, vmas, exec_list) {
584 struct drm_i915_gem_object *obj = vma->obj;
586 ret = i915_gem_object_sync(obj, ring);
590 if (obj->base.write_domain & I915_GEM_DOMAIN_CPU)
591 flush_chipset |= i915_gem_clflush_object(obj, false);
593 flush_domains |= obj->base.write_domain;
596 if (flush_domains & I915_GEM_DOMAIN_GTT)
599 /* Unconditionally invalidate gpu caches and ensure that we do flush
600 * any residual writes from the previous batch.
602 return logical_ring_invalidate_all_caches(ringbuf, ctx);
606 * execlists_submission() - submit a batchbuffer for execution, Execlists style
609 * @ring: Engine Command Streamer to submit to.
610 * @ctx: Context to employ for this submission.
611 * @args: execbuffer call arguments.
612 * @vmas: list of vmas.
613 * @batch_obj: the batchbuffer to submit.
614 * @exec_start: batchbuffer start virtual address pointer.
615 * @flags: translated execbuffer call flags.
617 * This is the evil twin version of i915_gem_ringbuffer_submission. It abstracts
618 * away the submission details of the execbuffer ioctl call.
620 * Return: non-zero if the submission fails.
622 int intel_execlists_submission(struct drm_device *dev, struct drm_file *file,
623 struct intel_engine_cs *ring,
624 struct intel_context *ctx,
625 struct drm_i915_gem_execbuffer2 *args,
626 struct list_head *vmas,
627 struct drm_i915_gem_object *batch_obj,
628 u64 exec_start, u32 flags)
630 struct drm_i915_private *dev_priv = dev->dev_private;
631 struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf;
636 instp_mode = args->flags & I915_EXEC_CONSTANTS_MASK;
637 instp_mask = I915_EXEC_CONSTANTS_MASK;
638 switch (instp_mode) {
639 case I915_EXEC_CONSTANTS_REL_GENERAL:
640 case I915_EXEC_CONSTANTS_ABSOLUTE:
641 case I915_EXEC_CONSTANTS_REL_SURFACE:
642 if (instp_mode != 0 && ring != &dev_priv->ring[RCS]) {
643 DRM_DEBUG("non-0 rel constants mode on non-RCS\n");
647 if (instp_mode != dev_priv->relative_constants_mode) {
648 if (instp_mode == I915_EXEC_CONSTANTS_REL_SURFACE) {
649 DRM_DEBUG("rel surface constants mode invalid on gen5+\n");
653 /* The HW changed the meaning on this bit on gen6 */
654 instp_mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE;
658 DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode);
662 if (args->num_cliprects != 0) {
663 DRM_DEBUG("clip rectangles are only valid on pre-gen5\n");
666 if (args->DR4 == 0xffffffff) {
667 DRM_DEBUG("UXA submitting garbage DR4, fixing up\n");
671 if (args->DR1 || args->DR4 || args->cliprects_ptr) {
672 DRM_DEBUG("0 cliprects but dirt in cliprects fields\n");
677 if (args->flags & I915_EXEC_GEN7_SOL_RESET) {
678 DRM_DEBUG("sol reset is gen7 only\n");
682 ret = execlists_move_to_gpu(ringbuf, ctx, vmas);
686 if (ring == &dev_priv->ring[RCS] &&
687 instp_mode != dev_priv->relative_constants_mode) {
688 ret = intel_logical_ring_begin(ringbuf, ctx, 4);
692 intel_logical_ring_emit(ringbuf, MI_NOOP);
693 intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(1));
694 intel_logical_ring_emit(ringbuf, INSTPM);
695 intel_logical_ring_emit(ringbuf, instp_mask << 16 | instp_mode);
696 intel_logical_ring_advance(ringbuf);
698 dev_priv->relative_constants_mode = instp_mode;
701 ret = ring->emit_bb_start(ringbuf, ctx, exec_start, flags);
705 i915_gem_execbuffer_move_to_active(vmas, ring);
706 i915_gem_execbuffer_retire_commands(dev, file, ring, batch_obj);
711 void intel_execlists_retire_requests(struct intel_engine_cs *ring)
713 struct drm_i915_gem_request *req, *tmp;
714 struct drm_i915_private *dev_priv = ring->dev->dev_private;
715 struct list_head retired_list;
717 WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex));
718 if (list_empty(&ring->execlist_retired_req_list))
721 INIT_LIST_HEAD(&retired_list);
722 lockmgr(&ring->execlist_lock, LK_EXCLUSIVE);
723 list_replace_init(&ring->execlist_retired_req_list, &retired_list);
724 lockmgr(&ring->execlist_lock, LK_RELEASE);
726 list_for_each_entry_safe(req, tmp, &retired_list, execlist_link) {
727 struct intel_context *ctx = req->ctx;
728 struct drm_i915_gem_object *ctx_obj =
729 ctx->engine[ring->id].state;
731 if (ctx_obj && (ctx != ring->default_context))
732 intel_lr_context_unpin(ring, ctx);
733 intel_runtime_pm_put(dev_priv);
734 list_del(&req->execlist_link);
735 i915_gem_request_unreference(req);
739 void intel_logical_ring_stop(struct intel_engine_cs *ring)
741 struct drm_i915_private *dev_priv = ring->dev->dev_private;
744 if (!intel_ring_initialized(ring))
747 ret = intel_ring_idle(ring);
748 if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error))
749 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
752 /* TODO: Is this correct with Execlists enabled? */
753 I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING));
754 if (wait_for_atomic((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) {
755 DRM_ERROR("%s :timed out trying to stop ring\n", ring->name);
758 I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING));
761 int logical_ring_flush_all_caches(struct intel_ringbuffer *ringbuf,
762 struct intel_context *ctx)
764 struct intel_engine_cs *ring = ringbuf->ring;
767 if (!ring->gpu_caches_dirty)
770 ret = ring->emit_flush(ringbuf, ctx, 0, I915_GEM_GPU_DOMAINS);
774 ring->gpu_caches_dirty = false;
779 * intel_logical_ring_advance_and_submit() - advance the tail and submit the workload
780 * @ringbuf: Logical Ringbuffer to advance.
782 * The tail is updated in our logical ringbuffer struct, not in the actual context. What
783 * really happens during submission is that the context and current tail will be placed
784 * on a queue waiting for the ELSP to be ready to accept a new context submission. At that
785 * point, the tail *inside* the context is updated and the ELSP written to.
787 void intel_logical_ring_advance_and_submit(struct intel_ringbuffer *ringbuf,
788 struct intel_context *ctx,
789 struct drm_i915_gem_request *request)
791 struct intel_engine_cs *ring = ringbuf->ring;
793 intel_logical_ring_advance(ringbuf);
795 if (intel_ring_stopped(ring))
798 execlists_context_queue(ring, ctx, ringbuf->tail, request);
801 static int intel_lr_context_pin(struct intel_engine_cs *ring,
802 struct intel_context *ctx)
804 struct drm_i915_gem_object *ctx_obj = ctx->engine[ring->id].state;
805 struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf;
808 WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex));
809 if (ctx->engine[ring->id].pin_count++ == 0) {
810 ret = i915_gem_obj_ggtt_pin(ctx_obj,
811 GEN8_LR_CONTEXT_ALIGN, 0);
813 goto reset_pin_count;
815 ret = intel_pin_and_map_ringbuffer_obj(ring->dev, ringbuf);
823 i915_gem_object_ggtt_unpin(ctx_obj);
825 ctx->engine[ring->id].pin_count = 0;
830 void intel_lr_context_unpin(struct intel_engine_cs *ring,
831 struct intel_context *ctx)
833 struct drm_i915_gem_object *ctx_obj = ctx->engine[ring->id].state;
834 struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf;
837 WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex));
838 if (--ctx->engine[ring->id].pin_count == 0) {
839 intel_unpin_ringbuffer_obj(ringbuf);
840 i915_gem_object_ggtt_unpin(ctx_obj);
845 static int logical_ring_alloc_request(struct intel_engine_cs *ring,
846 struct intel_context *ctx)
848 struct drm_i915_gem_request *request;
849 struct drm_i915_private *dev_private = ring->dev->dev_private;
852 if (ring->outstanding_lazy_request)
855 request = kzalloc(sizeof(*request), GFP_KERNEL);
859 if (ctx != ring->default_context) {
860 ret = intel_lr_context_pin(ring, ctx);
867 kref_init(&request->ref);
868 request->ring = ring;
869 request->uniq = dev_private->request_uniq++;
871 ret = i915_gem_get_seqno(ring->dev, &request->seqno);
873 intel_lr_context_unpin(ring, ctx);
878 /* Hold a reference to the context this request belongs to
879 * (we will need it when the time comes to emit/retire the
883 i915_gem_context_reference(request->ctx);
885 ring->outstanding_lazy_request = request;
889 static int logical_ring_wait_request(struct intel_ringbuffer *ringbuf,
892 struct intel_engine_cs *ring = ringbuf->ring;
893 struct drm_i915_gem_request *request;
896 if (intel_ring_space(ringbuf) >= bytes)
899 list_for_each_entry(request, &ring->request_list, list) {
901 * The request queue is per-engine, so can contain requests
902 * from multiple ringbuffers. Here, we must ignore any that
903 * aren't from the ringbuffer we're considering.
905 struct intel_context *ctx = request->ctx;
906 if (ctx->engine[ring->id].ringbuf != ringbuf)
909 /* Would completion of this request free enough space? */
910 if (__intel_ring_space(request->tail, ringbuf->tail,
911 ringbuf->size) >= bytes) {
916 if (&request->list == &ring->request_list)
919 ret = i915_wait_request(request);
923 i915_gem_retire_requests_ring(ring);
925 return intel_ring_space(ringbuf) >= bytes ? 0 : -ENOSPC;
928 static int logical_ring_wait_for_space(struct intel_ringbuffer *ringbuf,
929 struct intel_context *ctx,
932 struct intel_engine_cs *ring = ringbuf->ring;
933 struct drm_device *dev = ring->dev;
934 struct drm_i915_private *dev_priv = dev->dev_private;
938 ret = logical_ring_wait_request(ringbuf, bytes);
942 /* Force the context submission in case we have been skipping it */
943 intel_logical_ring_advance_and_submit(ringbuf, ctx, NULL);
945 /* With GEM the hangcheck timer should kick us out of the loop,
946 * leaving it early runs the risk of corrupting GEM state (due
947 * to running on almost untested codepaths). But on resume
948 * timers don't work yet, so prevent a complete hang in that
949 * case by choosing an insanely large timeout. */
950 end = jiffies + 60 * HZ;
954 if (intel_ring_space(ringbuf) >= bytes)
959 if (dev_priv->mm.interruptible && signal_pending(curthread->td_lwp)) {
964 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
965 dev_priv->mm.interruptible);
969 if (time_after(jiffies, end)) {
978 static int logical_ring_wrap_buffer(struct intel_ringbuffer *ringbuf,
979 struct intel_context *ctx)
981 uint32_t __iomem *virt;
982 int rem = ringbuf->size - ringbuf->tail;
984 if (ringbuf->space < rem) {
985 int ret = logical_ring_wait_for_space(ringbuf, ctx, rem);
991 virt = (unsigned int *)((char *)ringbuf->virtual_start + ringbuf->tail);
994 iowrite32(MI_NOOP, virt++);
997 intel_ring_update_space(ringbuf);
1002 static int logical_ring_prepare(struct intel_ringbuffer *ringbuf,
1003 struct intel_context *ctx, int bytes)
1007 if (unlikely(ringbuf->tail + bytes > ringbuf->effective_size)) {
1008 ret = logical_ring_wrap_buffer(ringbuf, ctx);
1013 if (unlikely(ringbuf->space < bytes)) {
1014 ret = logical_ring_wait_for_space(ringbuf, ctx, bytes);
1023 * intel_logical_ring_begin() - prepare the logical ringbuffer to accept some commands
1025 * @ringbuf: Logical ringbuffer.
1026 * @num_dwords: number of DWORDs that we plan to write to the ringbuffer.
1028 * The ringbuffer might not be ready to accept the commands right away (maybe it needs to
1029 * be wrapped, or wait a bit for the tail to be updated). This function takes care of that
1030 * and also preallocates a request (every workload submission is still mediated through
1031 * requests, same as it did with legacy ringbuffer submission).
1033 * Return: non-zero if the ringbuffer is not ready to be written to.
1035 int intel_logical_ring_begin(struct intel_ringbuffer *ringbuf,
1036 struct intel_context *ctx, int num_dwords)
1038 struct intel_engine_cs *ring = ringbuf->ring;
1039 struct drm_device *dev = ring->dev;
1040 struct drm_i915_private *dev_priv = dev->dev_private;
1043 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
1044 dev_priv->mm.interruptible);
1048 ret = logical_ring_prepare(ringbuf, ctx, num_dwords * sizeof(uint32_t));
1052 /* Preallocate the olr before touching the ring */
1053 ret = logical_ring_alloc_request(ring, ctx);
1057 ringbuf->space -= num_dwords * sizeof(uint32_t);
1061 static int intel_logical_ring_workarounds_emit(struct intel_engine_cs *ring,
1062 struct intel_context *ctx)
1065 struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf;
1066 struct drm_device *dev = ring->dev;
1067 struct drm_i915_private *dev_priv = dev->dev_private;
1068 struct i915_workarounds *w = &dev_priv->workarounds;
1070 if (WARN_ON_ONCE(w->count == 0))
1073 ring->gpu_caches_dirty = true;
1074 ret = logical_ring_flush_all_caches(ringbuf, ctx);
1078 ret = intel_logical_ring_begin(ringbuf, ctx, w->count * 2 + 2);
1082 intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(w->count));
1083 for (i = 0; i < w->count; i++) {
1084 intel_logical_ring_emit(ringbuf, w->reg[i].addr);
1085 intel_logical_ring_emit(ringbuf, w->reg[i].value);
1087 intel_logical_ring_emit(ringbuf, MI_NOOP);
1089 intel_logical_ring_advance(ringbuf);
1091 ring->gpu_caches_dirty = true;
1092 ret = logical_ring_flush_all_caches(ringbuf, ctx);
1099 static int gen8_init_common_ring(struct intel_engine_cs *ring)
1101 struct drm_device *dev = ring->dev;
1102 struct drm_i915_private *dev_priv = dev->dev_private;
1104 I915_WRITE_IMR(ring, ~(ring->irq_enable_mask | ring->irq_keep_mask));
1105 I915_WRITE(RING_HWSTAM(ring->mmio_base), 0xffffffff);
1107 I915_WRITE(RING_MODE_GEN7(ring),
1108 _MASKED_BIT_DISABLE(GFX_REPLAY_MODE) |
1109 _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE));
1110 POSTING_READ(RING_MODE_GEN7(ring));
1111 ring->next_context_status_buffer = 0;
1112 DRM_DEBUG_DRIVER("Execlists enabled for %s\n", ring->name);
1114 memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
1119 static int gen8_init_render_ring(struct intel_engine_cs *ring)
1121 struct drm_device *dev = ring->dev;
1122 struct drm_i915_private *dev_priv = dev->dev_private;
1125 ret = gen8_init_common_ring(ring);
1129 /* We need to disable the AsyncFlip performance optimisations in order
1130 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1131 * programmed to '1' on all products.
1133 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
1135 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1137 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
1139 return init_workarounds_ring(ring);
1142 static int gen8_emit_bb_start(struct intel_ringbuffer *ringbuf,
1143 struct intel_context *ctx,
1144 u64 offset, unsigned flags)
1146 bool ppgtt = !(flags & I915_DISPATCH_SECURE);
1149 ret = intel_logical_ring_begin(ringbuf, ctx, 4);
1153 /* FIXME(BDW): Address space and security selectors. */
1154 intel_logical_ring_emit(ringbuf, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8));
1155 intel_logical_ring_emit(ringbuf, lower_32_bits(offset));
1156 intel_logical_ring_emit(ringbuf, upper_32_bits(offset));
1157 intel_logical_ring_emit(ringbuf, MI_NOOP);
1158 intel_logical_ring_advance(ringbuf);
1163 static bool gen8_logical_ring_get_irq(struct intel_engine_cs *ring)
1165 struct drm_device *dev = ring->dev;
1166 struct drm_i915_private *dev_priv = dev->dev_private;
1168 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1171 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
1172 if (ring->irq_refcount++ == 0) {
1173 I915_WRITE_IMR(ring, ~(ring->irq_enable_mask | ring->irq_keep_mask));
1174 POSTING_READ(RING_IMR(ring->mmio_base));
1176 lockmgr(&dev_priv->irq_lock, LK_RELEASE);
1181 static void gen8_logical_ring_put_irq(struct intel_engine_cs *ring)
1183 struct drm_device *dev = ring->dev;
1184 struct drm_i915_private *dev_priv = dev->dev_private;
1186 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
1187 if (--ring->irq_refcount == 0) {
1188 I915_WRITE_IMR(ring, ~ring->irq_keep_mask);
1189 POSTING_READ(RING_IMR(ring->mmio_base));
1191 lockmgr(&dev_priv->irq_lock, LK_RELEASE);
1194 static int gen8_emit_flush(struct intel_ringbuffer *ringbuf,
1195 struct intel_context *ctx,
1196 u32 invalidate_domains,
1199 struct intel_engine_cs *ring = ringbuf->ring;
1200 struct drm_device *dev = ring->dev;
1201 struct drm_i915_private *dev_priv = dev->dev_private;
1205 ret = intel_logical_ring_begin(ringbuf, ctx, 4);
1209 cmd = MI_FLUSH_DW + 1;
1211 /* We always require a command barrier so that subsequent
1212 * commands, such as breadcrumb interrupts, are strictly ordered
1213 * wrt the contents of the write cache being flushed to memory
1214 * (and thus being coherent from the CPU).
1216 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
1218 if (invalidate_domains & I915_GEM_GPU_DOMAINS) {
1219 cmd |= MI_INVALIDATE_TLB;
1220 if (ring == &dev_priv->ring[VCS])
1221 cmd |= MI_INVALIDATE_BSD;
1224 intel_logical_ring_emit(ringbuf, cmd);
1225 intel_logical_ring_emit(ringbuf,
1226 I915_GEM_HWS_SCRATCH_ADDR |
1227 MI_FLUSH_DW_USE_GTT);
1228 intel_logical_ring_emit(ringbuf, 0); /* upper addr */
1229 intel_logical_ring_emit(ringbuf, 0); /* value */
1230 intel_logical_ring_advance(ringbuf);
1235 static int gen8_emit_flush_render(struct intel_ringbuffer *ringbuf,
1236 struct intel_context *ctx,
1237 u32 invalidate_domains,
1240 struct intel_engine_cs *ring = ringbuf->ring;
1241 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
1245 flags |= PIPE_CONTROL_CS_STALL;
1247 if (flush_domains) {
1248 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
1249 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
1252 if (invalidate_domains) {
1253 flags |= PIPE_CONTROL_TLB_INVALIDATE;
1254 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
1255 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
1256 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
1257 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
1258 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
1259 flags |= PIPE_CONTROL_QW_WRITE;
1260 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
1263 ret = intel_logical_ring_begin(ringbuf, ctx, 6);
1267 intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
1268 intel_logical_ring_emit(ringbuf, flags);
1269 intel_logical_ring_emit(ringbuf, scratch_addr);
1270 intel_logical_ring_emit(ringbuf, 0);
1271 intel_logical_ring_emit(ringbuf, 0);
1272 intel_logical_ring_emit(ringbuf, 0);
1273 intel_logical_ring_advance(ringbuf);
1278 static u32 gen8_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1280 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1283 static void gen8_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1285 intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
1288 static int gen8_emit_request(struct intel_ringbuffer *ringbuf,
1289 struct drm_i915_gem_request *request)
1291 struct intel_engine_cs *ring = ringbuf->ring;
1295 ret = intel_logical_ring_begin(ringbuf, request->ctx, 6);
1299 cmd = MI_STORE_DWORD_IMM_GEN4;
1300 cmd |= MI_GLOBAL_GTT;
1302 intel_logical_ring_emit(ringbuf, cmd);
1303 intel_logical_ring_emit(ringbuf,
1304 (ring->status_page.gfx_addr +
1305 (I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT)));
1306 intel_logical_ring_emit(ringbuf, 0);
1307 intel_logical_ring_emit(ringbuf,
1308 i915_gem_request_get_seqno(ring->outstanding_lazy_request));
1309 intel_logical_ring_emit(ringbuf, MI_USER_INTERRUPT);
1310 intel_logical_ring_emit(ringbuf, MI_NOOP);
1311 intel_logical_ring_advance_and_submit(ringbuf, request->ctx, request);
1316 static int gen8_init_rcs_context(struct intel_engine_cs *ring,
1317 struct intel_context *ctx)
1321 ret = intel_logical_ring_workarounds_emit(ring, ctx);
1325 return intel_lr_context_render_state_init(ring, ctx);
1329 * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer
1331 * @ring: Engine Command Streamer.
1334 void intel_logical_ring_cleanup(struct intel_engine_cs *ring)
1336 struct drm_i915_private *dev_priv;
1338 if (!intel_ring_initialized(ring))
1341 dev_priv = ring->dev->dev_private;
1343 intel_logical_ring_stop(ring);
1344 WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
1345 i915_gem_request_assign(&ring->outstanding_lazy_request, NULL);
1348 ring->cleanup(ring);
1350 i915_cmd_parser_fini_ring(ring);
1352 if (ring->status_page.obj) {
1353 kunmap(ring->status_page.obj->pages[0]);
1354 ring->status_page.obj = NULL;
1358 static int logical_ring_init(struct drm_device *dev, struct intel_engine_cs *ring)
1362 /* Intentionally left blank. */
1363 ring->buffer = NULL;
1366 INIT_LIST_HEAD(&ring->active_list);
1367 INIT_LIST_HEAD(&ring->request_list);
1368 init_waitqueue_head(&ring->irq_queue);
1370 INIT_LIST_HEAD(&ring->execlist_queue);
1371 INIT_LIST_HEAD(&ring->execlist_retired_req_list);
1372 lockinit(&ring->execlist_lock, "i915el", 0, LK_CANRECURSE);
1374 ret = i915_cmd_parser_init_ring(ring);
1378 ret = intel_lr_context_deferred_create(ring->default_context, ring);
1383 static int logical_render_ring_init(struct drm_device *dev)
1385 struct drm_i915_private *dev_priv = dev->dev_private;
1386 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
1389 ring->name = "render ring";
1391 ring->mmio_base = RENDER_RING_BASE;
1392 ring->irq_enable_mask =
1393 GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT;
1394 ring->irq_keep_mask =
1395 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT;
1396 if (HAS_L3_DPF(dev))
1397 ring->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
1399 ring->init_hw = gen8_init_render_ring;
1400 ring->init_context = gen8_init_rcs_context;
1401 ring->cleanup = intel_fini_pipe_control;
1402 ring->get_seqno = gen8_get_seqno;
1403 ring->set_seqno = gen8_set_seqno;
1404 ring->emit_request = gen8_emit_request;
1405 ring->emit_flush = gen8_emit_flush_render;
1406 ring->irq_get = gen8_logical_ring_get_irq;
1407 ring->irq_put = gen8_logical_ring_put_irq;
1408 ring->emit_bb_start = gen8_emit_bb_start;
1411 ret = logical_ring_init(dev, ring);
1415 return intel_init_pipe_control(ring);
1418 static int logical_bsd_ring_init(struct drm_device *dev)
1420 struct drm_i915_private *dev_priv = dev->dev_private;
1421 struct intel_engine_cs *ring = &dev_priv->ring[VCS];
1423 ring->name = "bsd ring";
1425 ring->mmio_base = GEN6_BSD_RING_BASE;
1426 ring->irq_enable_mask =
1427 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
1428 ring->irq_keep_mask =
1429 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
1431 ring->init_hw = gen8_init_common_ring;
1432 ring->get_seqno = gen8_get_seqno;
1433 ring->set_seqno = gen8_set_seqno;
1434 ring->emit_request = gen8_emit_request;
1435 ring->emit_flush = gen8_emit_flush;
1436 ring->irq_get = gen8_logical_ring_get_irq;
1437 ring->irq_put = gen8_logical_ring_put_irq;
1438 ring->emit_bb_start = gen8_emit_bb_start;
1440 return logical_ring_init(dev, ring);
1443 static int logical_bsd2_ring_init(struct drm_device *dev)
1445 struct drm_i915_private *dev_priv = dev->dev_private;
1446 struct intel_engine_cs *ring = &dev_priv->ring[VCS2];
1448 ring->name = "bds2 ring";
1450 ring->mmio_base = GEN8_BSD2_RING_BASE;
1451 ring->irq_enable_mask =
1452 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
1453 ring->irq_keep_mask =
1454 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
1456 ring->init_hw = gen8_init_common_ring;
1457 ring->get_seqno = gen8_get_seqno;
1458 ring->set_seqno = gen8_set_seqno;
1459 ring->emit_request = gen8_emit_request;
1460 ring->emit_flush = gen8_emit_flush;
1461 ring->irq_get = gen8_logical_ring_get_irq;
1462 ring->irq_put = gen8_logical_ring_put_irq;
1463 ring->emit_bb_start = gen8_emit_bb_start;
1465 return logical_ring_init(dev, ring);
1468 static int logical_blt_ring_init(struct drm_device *dev)
1470 struct drm_i915_private *dev_priv = dev->dev_private;
1471 struct intel_engine_cs *ring = &dev_priv->ring[BCS];
1473 ring->name = "blitter ring";
1475 ring->mmio_base = BLT_RING_BASE;
1476 ring->irq_enable_mask =
1477 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
1478 ring->irq_keep_mask =
1479 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
1481 ring->init_hw = gen8_init_common_ring;
1482 ring->get_seqno = gen8_get_seqno;
1483 ring->set_seqno = gen8_set_seqno;
1484 ring->emit_request = gen8_emit_request;
1485 ring->emit_flush = gen8_emit_flush;
1486 ring->irq_get = gen8_logical_ring_get_irq;
1487 ring->irq_put = gen8_logical_ring_put_irq;
1488 ring->emit_bb_start = gen8_emit_bb_start;
1490 return logical_ring_init(dev, ring);
1493 static int logical_vebox_ring_init(struct drm_device *dev)
1495 struct drm_i915_private *dev_priv = dev->dev_private;
1496 struct intel_engine_cs *ring = &dev_priv->ring[VECS];
1498 ring->name = "video enhancement ring";
1500 ring->mmio_base = VEBOX_RING_BASE;
1501 ring->irq_enable_mask =
1502 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
1503 ring->irq_keep_mask =
1504 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
1506 ring->init_hw = gen8_init_common_ring;
1507 ring->get_seqno = gen8_get_seqno;
1508 ring->set_seqno = gen8_set_seqno;
1509 ring->emit_request = gen8_emit_request;
1510 ring->emit_flush = gen8_emit_flush;
1511 ring->irq_get = gen8_logical_ring_get_irq;
1512 ring->irq_put = gen8_logical_ring_put_irq;
1513 ring->emit_bb_start = gen8_emit_bb_start;
1515 return logical_ring_init(dev, ring);
1519 * intel_logical_rings_init() - allocate, populate and init the Engine Command Streamers
1522 * This function inits the engines for an Execlists submission style (the equivalent in the
1523 * legacy ringbuffer submission world would be i915_gem_init_rings). It does it only for
1524 * those engines that are present in the hardware.
1526 * Return: non-zero if the initialization failed.
1528 int intel_logical_rings_init(struct drm_device *dev)
1530 struct drm_i915_private *dev_priv = dev->dev_private;
1533 ret = logical_render_ring_init(dev);
1538 ret = logical_bsd_ring_init(dev);
1540 goto cleanup_render_ring;
1544 ret = logical_blt_ring_init(dev);
1546 goto cleanup_bsd_ring;
1549 if (HAS_VEBOX(dev)) {
1550 ret = logical_vebox_ring_init(dev);
1552 goto cleanup_blt_ring;
1555 if (HAS_BSD2(dev)) {
1556 ret = logical_bsd2_ring_init(dev);
1558 goto cleanup_vebox_ring;
1561 ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000));
1563 goto cleanup_bsd2_ring;
1568 intel_logical_ring_cleanup(&dev_priv->ring[VCS2]);
1570 intel_logical_ring_cleanup(&dev_priv->ring[VECS]);
1572 intel_logical_ring_cleanup(&dev_priv->ring[BCS]);
1574 intel_logical_ring_cleanup(&dev_priv->ring[VCS]);
1575 cleanup_render_ring:
1576 intel_logical_ring_cleanup(&dev_priv->ring[RCS]);
1581 int intel_lr_context_render_state_init(struct intel_engine_cs *ring,
1582 struct intel_context *ctx)
1584 struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf;
1585 struct render_state so;
1586 struct drm_i915_file_private *file_priv = ctx->file_priv;
1587 struct drm_file *file = file_priv ? file_priv->file : NULL;
1590 ret = i915_gem_render_state_prepare(ring, &so);
1594 if (so.rodata == NULL)
1597 ret = ring->emit_bb_start(ringbuf,
1600 I915_DISPATCH_SECURE);
1604 i915_vma_move_to_active(i915_gem_obj_to_ggtt(so.obj), ring);
1606 ret = __i915_add_request(ring, file, so.obj);
1607 /* intel_logical_ring_add_request moves object to inactive if it
1610 i915_gem_render_state_fini(&so);
1615 populate_lr_context(struct intel_context *ctx, struct drm_i915_gem_object *ctx_obj,
1616 struct intel_engine_cs *ring, struct intel_ringbuffer *ringbuf)
1618 struct drm_device *dev = ring->dev;
1619 struct drm_i915_private *dev_priv = dev->dev_private;
1620 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
1621 struct vm_page *page;
1622 uint32_t *reg_state;
1626 ppgtt = dev_priv->mm.aliasing_ppgtt;
1628 ret = i915_gem_object_set_to_cpu_domain(ctx_obj, true);
1630 DRM_DEBUG_DRIVER("Could not set to CPU domain\n");
1634 ret = i915_gem_object_get_pages(ctx_obj);
1636 DRM_DEBUG_DRIVER("Could not get object pages\n");
1640 i915_gem_object_pin_pages(ctx_obj);
1642 /* The second page of the context object contains some fields which must
1643 * be set up prior to the first execution. */
1644 page = i915_gem_object_get_page(ctx_obj, 1);
1645 reg_state = kmap_atomic(page);
1647 /* A context is actually a big batch buffer with several MI_LOAD_REGISTER_IMM
1648 * commands followed by (reg, value) pairs. The values we are setting here are
1649 * only for the first context restore: on a subsequent save, the GPU will
1650 * recreate this batchbuffer with new values (including all the missing
1651 * MI_LOAD_REGISTER_IMM commands that we are not initializing here). */
1652 if (ring->id == RCS)
1653 reg_state[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(14);
1655 reg_state[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(11);
1656 reg_state[CTX_LRI_HEADER_0] |= MI_LRI_FORCE_POSTED;
1657 reg_state[CTX_CONTEXT_CONTROL] = RING_CONTEXT_CONTROL(ring);
1658 reg_state[CTX_CONTEXT_CONTROL+1] =
1659 _MASKED_BIT_ENABLE((1<<3) | MI_RESTORE_INHIBIT);
1660 reg_state[CTX_RING_HEAD] = RING_HEAD(ring->mmio_base);
1661 reg_state[CTX_RING_HEAD+1] = 0;
1662 reg_state[CTX_RING_TAIL] = RING_TAIL(ring->mmio_base);
1663 reg_state[CTX_RING_TAIL+1] = 0;
1664 reg_state[CTX_RING_BUFFER_START] = RING_START(ring->mmio_base);
1665 /* Ring buffer start address is not known until the buffer is pinned.
1666 * It is written to the context image in execlists_update_context()
1668 reg_state[CTX_RING_BUFFER_CONTROL] = RING_CTL(ring->mmio_base);
1669 reg_state[CTX_RING_BUFFER_CONTROL+1] =
1670 ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES) | RING_VALID;
1671 reg_state[CTX_BB_HEAD_U] = ring->mmio_base + 0x168;
1672 reg_state[CTX_BB_HEAD_U+1] = 0;
1673 reg_state[CTX_BB_HEAD_L] = ring->mmio_base + 0x140;
1674 reg_state[CTX_BB_HEAD_L+1] = 0;
1675 reg_state[CTX_BB_STATE] = ring->mmio_base + 0x110;
1676 reg_state[CTX_BB_STATE+1] = (1<<5);
1677 reg_state[CTX_SECOND_BB_HEAD_U] = ring->mmio_base + 0x11c;
1678 reg_state[CTX_SECOND_BB_HEAD_U+1] = 0;
1679 reg_state[CTX_SECOND_BB_HEAD_L] = ring->mmio_base + 0x114;
1680 reg_state[CTX_SECOND_BB_HEAD_L+1] = 0;
1681 reg_state[CTX_SECOND_BB_STATE] = ring->mmio_base + 0x118;
1682 reg_state[CTX_SECOND_BB_STATE+1] = 0;
1683 if (ring->id == RCS) {
1684 /* TODO: according to BSpec, the register state context
1685 * for CHV does not have these. OTOH, these registers do
1686 * exist in CHV. I'm waiting for a clarification */
1687 reg_state[CTX_BB_PER_CTX_PTR] = ring->mmio_base + 0x1c0;
1688 reg_state[CTX_BB_PER_CTX_PTR+1] = 0;
1689 reg_state[CTX_RCS_INDIRECT_CTX] = ring->mmio_base + 0x1c4;
1690 reg_state[CTX_RCS_INDIRECT_CTX+1] = 0;
1691 reg_state[CTX_RCS_INDIRECT_CTX_OFFSET] = ring->mmio_base + 0x1c8;
1692 reg_state[CTX_RCS_INDIRECT_CTX_OFFSET+1] = 0;
1694 reg_state[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9);
1695 reg_state[CTX_LRI_HEADER_1] |= MI_LRI_FORCE_POSTED;
1696 reg_state[CTX_CTX_TIMESTAMP] = ring->mmio_base + 0x3a8;
1697 reg_state[CTX_CTX_TIMESTAMP+1] = 0;
1698 reg_state[CTX_PDP3_UDW] = GEN8_RING_PDP_UDW(ring, 3);
1699 reg_state[CTX_PDP3_LDW] = GEN8_RING_PDP_LDW(ring, 3);
1700 reg_state[CTX_PDP2_UDW] = GEN8_RING_PDP_UDW(ring, 2);
1701 reg_state[CTX_PDP2_LDW] = GEN8_RING_PDP_LDW(ring, 2);
1702 reg_state[CTX_PDP1_UDW] = GEN8_RING_PDP_UDW(ring, 1);
1703 reg_state[CTX_PDP1_LDW] = GEN8_RING_PDP_LDW(ring, 1);
1704 reg_state[CTX_PDP0_UDW] = GEN8_RING_PDP_UDW(ring, 0);
1705 reg_state[CTX_PDP0_LDW] = GEN8_RING_PDP_LDW(ring, 0);
1706 reg_state[CTX_PDP3_UDW+1] = upper_32_bits(ppgtt->pd_dma_addr[3]);
1707 reg_state[CTX_PDP3_LDW+1] = lower_32_bits(ppgtt->pd_dma_addr[3]);
1708 reg_state[CTX_PDP2_UDW+1] = upper_32_bits(ppgtt->pd_dma_addr[2]);
1709 reg_state[CTX_PDP2_LDW+1] = lower_32_bits(ppgtt->pd_dma_addr[2]);
1710 reg_state[CTX_PDP1_UDW+1] = upper_32_bits(ppgtt->pd_dma_addr[1]);
1711 reg_state[CTX_PDP1_LDW+1] = lower_32_bits(ppgtt->pd_dma_addr[1]);
1712 reg_state[CTX_PDP0_UDW+1] = upper_32_bits(ppgtt->pd_dma_addr[0]);
1713 reg_state[CTX_PDP0_LDW+1] = lower_32_bits(ppgtt->pd_dma_addr[0]);
1714 if (ring->id == RCS) {
1715 reg_state[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1);
1716 reg_state[CTX_R_PWR_CLK_STATE] = 0x20c8;
1717 reg_state[CTX_R_PWR_CLK_STATE+1] = 0;
1720 kunmap_atomic(reg_state);
1723 set_page_dirty(page);
1724 i915_gem_object_unpin_pages(ctx_obj);
1730 * intel_lr_context_free() - free the LRC specific bits of a context
1731 * @ctx: the LR context to free.
1733 * The real context freeing is done in i915_gem_context_free: this only
1734 * takes care of the bits that are LRC related: the per-engine backing
1735 * objects and the logical ringbuffer.
1737 void intel_lr_context_free(struct intel_context *ctx)
1741 for (i = 0; i < I915_NUM_RINGS; i++) {
1742 struct drm_i915_gem_object *ctx_obj = ctx->engine[i].state;
1745 struct intel_ringbuffer *ringbuf =
1746 ctx->engine[i].ringbuf;
1747 struct intel_engine_cs *ring = ringbuf->ring;
1749 if (ctx == ring->default_context) {
1750 intel_unpin_ringbuffer_obj(ringbuf);
1751 i915_gem_object_ggtt_unpin(ctx_obj);
1753 WARN_ON(ctx->engine[ring->id].pin_count);
1754 intel_destroy_ringbuffer_obj(ringbuf);
1756 drm_gem_object_unreference(&ctx_obj->base);
1761 static uint32_t get_lr_context_size(struct intel_engine_cs *ring)
1765 WARN_ON(INTEL_INFO(ring->dev)->gen < 8);
1769 if (INTEL_INFO(ring->dev)->gen >= 9)
1770 ret = GEN9_LR_CONTEXT_RENDER_SIZE;
1772 ret = GEN8_LR_CONTEXT_RENDER_SIZE;
1778 ret = GEN8_LR_CONTEXT_OTHER_SIZE;
1785 static void lrc_setup_hardware_status_page(struct intel_engine_cs *ring,
1786 struct drm_i915_gem_object *default_ctx_obj)
1788 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1790 /* The status page is offset 0 from the default context object
1792 ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(default_ctx_obj);
1793 ring->status_page.page_addr =
1794 kmap(default_ctx_obj->pages[0]);
1795 ring->status_page.obj = default_ctx_obj;
1797 I915_WRITE(RING_HWS_PGA(ring->mmio_base),
1798 (u32)ring->status_page.gfx_addr);
1799 POSTING_READ(RING_HWS_PGA(ring->mmio_base));
1803 * intel_lr_context_deferred_create() - create the LRC specific bits of a context
1804 * @ctx: LR context to create.
1805 * @ring: engine to be used with the context.
1807 * This function can be called more than once, with different engines, if we plan
1808 * to use the context with them. The context backing objects and the ringbuffers
1809 * (specially the ringbuffer backing objects) suck a lot of memory up, and that's why
1810 * the creation is a deferred call: it's better to make sure first that we need to use
1811 * a given ring with the context.
1813 * Return: non-zero on error.
1815 int intel_lr_context_deferred_create(struct intel_context *ctx,
1816 struct intel_engine_cs *ring)
1818 const bool is_global_default_ctx = (ctx == ring->default_context);
1819 struct drm_device *dev = ring->dev;
1820 struct drm_i915_gem_object *ctx_obj;
1821 uint32_t context_size;
1822 struct intel_ringbuffer *ringbuf;
1825 WARN_ON(ctx->legacy_hw_ctx.rcs_state != NULL);
1826 WARN_ON(ctx->engine[ring->id].state);
1828 context_size = round_up(get_lr_context_size(ring), 4096);
1830 ctx_obj = i915_gem_alloc_context_obj(dev, context_size);
1831 if (IS_ERR(ctx_obj)) {
1832 ret = PTR_ERR(ctx_obj);
1833 DRM_DEBUG_DRIVER("Alloc LRC backing obj failed: %d\n", ret);
1837 if (is_global_default_ctx) {
1838 ret = i915_gem_obj_ggtt_pin(ctx_obj, GEN8_LR_CONTEXT_ALIGN, 0);
1840 DRM_DEBUG_DRIVER("Pin LRC backing obj failed: %d\n",
1842 drm_gem_object_unreference(&ctx_obj->base);
1847 ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL);
1849 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n",
1852 goto error_unpin_ctx;
1855 ringbuf->ring = ring;
1857 ringbuf->size = 32 * PAGE_SIZE;
1858 ringbuf->effective_size = ringbuf->size;
1861 ringbuf->last_retired_head = -1;
1862 intel_ring_update_space(ringbuf);
1864 if (ringbuf->obj == NULL) {
1865 ret = intel_alloc_ringbuffer_obj(dev, ringbuf);
1868 "Failed to allocate ringbuffer obj %s: %d\n",
1870 goto error_free_rbuf;
1873 if (is_global_default_ctx) {
1874 ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf);
1877 "Failed to pin and map ringbuffer %s: %d\n",
1879 goto error_destroy_rbuf;
1885 ret = populate_lr_context(ctx, ctx_obj, ring, ringbuf);
1887 DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret);
1891 ctx->engine[ring->id].ringbuf = ringbuf;
1892 ctx->engine[ring->id].state = ctx_obj;
1894 if (ctx == ring->default_context)
1895 lrc_setup_hardware_status_page(ring, ctx_obj);
1896 else if (ring->id == RCS && !ctx->rcs_initialized) {
1897 if (ring->init_context) {
1898 ret = ring->init_context(ring, ctx);
1900 DRM_ERROR("ring init context: %d\n", ret);
1901 ctx->engine[ring->id].ringbuf = NULL;
1902 ctx->engine[ring->id].state = NULL;
1907 ctx->rcs_initialized = true;
1913 if (is_global_default_ctx)
1914 intel_unpin_ringbuffer_obj(ringbuf);
1916 intel_destroy_ringbuffer_obj(ringbuf);
1920 if (is_global_default_ctx)
1921 i915_gem_object_ggtt_unpin(ctx_obj);
1922 drm_gem_object_unreference(&ctx_obj->base);