sys/dev/drm/i915/intel_overlay.c

   1 /*
   2  * Copyright © 2009
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Daniel Vetter <daniel@ffwll.ch>
  25  *
  26  * Derived from Xorg ddx, xf86-video-intel, src/i830_video.c
  27  */
  28 #include <drm/drmP.h>
  29 #include <drm/i915_drm.h>
  30 #include "i915_drv.h"
  31 #include "i915_reg.h"
  32 #include "intel_drv.h"
  33
  34 /* Limits for overlay size. According to intel doc, the real limits are:
  35  * Y width: 4095, UV width (planar): 2047, Y height: 2047,
  36  * UV width (planar): * 1023. But the xorg thinks 2048 for height and width. Use
  37  * the mininum of both.  */
  38 #define IMAGE_MAX_WIDTH         2048
  39 #define IMAGE_MAX_HEIGHT        2046 /* 2 * 1023 */
  40 /* on 830 and 845 these large limits result in the card hanging */
  41 #define IMAGE_MAX_WIDTH_LEGACY  1024
  42 #define IMAGE_MAX_HEIGHT_LEGACY 1088
  43
  44 /* overlay register definitions */
  45 /* OCMD register */
  46 #define OCMD_TILED_SURFACE      (0x1<<19)
  47 #define OCMD_MIRROR_MASK        (0x3<<17)
  48 #define OCMD_MIRROR_MODE        (0x3<<17)
  49 #define OCMD_MIRROR_HORIZONTAL  (0x1<<17)
  50 #define OCMD_MIRROR_VERTICAL    (0x2<<17)
  51 #define OCMD_MIRROR_BOTH        (0x3<<17)
  52 #define OCMD_BYTEORDER_MASK     (0x3<<14) /* zero for YUYV or FOURCC YUY2 */
  53 #define OCMD_UV_SWAP            (0x1<<14) /* YVYU */
  54 #define OCMD_Y_SWAP             (0x2<<14) /* UYVY or FOURCC UYVY */
  55 #define OCMD_Y_AND_UV_SWAP      (0x3<<14) /* VYUY */
  56 #define OCMD_SOURCE_FORMAT_MASK (0xf<<10)
  57 #define OCMD_RGB_888            (0x1<<10) /* not in i965 Intel docs */
  58 #define OCMD_RGB_555            (0x2<<10) /* not in i965 Intel docs */
  59 #define OCMD_RGB_565            (0x3<<10) /* not in i965 Intel docs */
  60 #define OCMD_YUV_422_PACKED     (0x8<<10)
  61 #define OCMD_YUV_411_PACKED     (0x9<<10) /* not in i965 Intel docs */
  62 #define OCMD_YUV_420_PLANAR     (0xc<<10)
  63 #define OCMD_YUV_422_PLANAR     (0xd<<10)
  64 #define OCMD_YUV_410_PLANAR     (0xe<<10) /* also 411 */
  65 #define OCMD_TVSYNCFLIP_PARITY  (0x1<<9)
  66 #define OCMD_TVSYNCFLIP_ENABLE  (0x1<<7)
  67 #define OCMD_BUF_TYPE_MASK      (0x1<<5)
  68 #define OCMD_BUF_TYPE_FRAME     (0x0<<5)
  69 #define OCMD_BUF_TYPE_FIELD     (0x1<<5)
  70 #define OCMD_TEST_MODE          (0x1<<4)
  71 #define OCMD_BUFFER_SELECT      (0x3<<2)
  72 #define OCMD_BUFFER0            (0x0<<2)
  73 #define OCMD_BUFFER1            (0x1<<2)
  74 #define OCMD_FIELD_SELECT       (0x1<<2)
  75 #define OCMD_FIELD0             (0x0<<1)
  76 #define OCMD_FIELD1             (0x1<<1)
  77 #define OCMD_ENABLE             (0x1<<0)
  78
  79 /* OCONFIG register */
  80 #define OCONF_PIPE_MASK         (0x1<<18)
  81 #define OCONF_PIPE_A            (0x0<<18)
  82 #define OCONF_PIPE_B            (0x1<<18)
  83 #define OCONF_GAMMA2_ENABLE     (0x1<<16)
  84 #define OCONF_CSC_MODE_BT601    (0x0<<5)
  85 #define OCONF_CSC_MODE_BT709    (0x1<<5)
  86 #define OCONF_CSC_BYPASS        (0x1<<4)
  87 #define OCONF_CC_OUT_8BIT       (0x1<<3)
  88 #define OCONF_TEST_MODE         (0x1<<2)
  89 #define OCONF_THREE_LINE_BUFFER (0x1<<0)
  90 #define OCONF_TWO_LINE_BUFFER   (0x0<<0)
  91
  92 /* DCLRKM (dst-key) register */
  93 #define DST_KEY_ENABLE          (0x1<<31)
  94 #define CLK_RGB24_MASK          0x0
  95 #define CLK_RGB16_MASK          0x070307
  96 #define CLK_RGB15_MASK          0x070707
  97 #define CLK_RGB8I_MASK          0xffffff
  98
  99 #define RGB16_TO_COLORKEY(c) \
 100         (((c & 0xF800) << 8) | ((c & 0x07E0) << 5) | ((c & 0x001F) << 3))
 101 #define RGB15_TO_COLORKEY(c) \
 102         (((c & 0x7c00) << 9) | ((c & 0x03E0) << 6) | ((c & 0x001F) << 3))
 103
 104 /* overlay flip addr flag */
 105 #define OFC_UPDATE              0x1
 106
 107 /* polyphase filter coefficients */
 108 #define N_HORIZ_Y_TAPS          5
 109 #define N_VERT_Y_TAPS           3
 110 #define N_HORIZ_UV_TAPS         3
 111 #define N_VERT_UV_TAPS          3
 112 #define N_PHASES                17
 113 #define MAX_TAPS                5
 114
 115 /* memory bufferd overlay registers */
 116 struct overlay_registers {
 117         u32 OBUF_0Y;
 118         u32 OBUF_1Y;
 119         u32 OBUF_0U;
 120         u32 OBUF_0V;
 121         u32 OBUF_1U;
 122         u32 OBUF_1V;
 123         u32 OSTRIDE;
 124         u32 YRGB_VPH;
 125         u32 UV_VPH;
 126         u32 HORZ_PH;
 127         u32 INIT_PHS;
 128         u32 DWINPOS;
 129         u32 DWINSZ;
 130         u32 SWIDTH;
 131         u32 SWIDTHSW;
 132         u32 SHEIGHT;
 133         u32 YRGBSCALE;
 134         u32 UVSCALE;
 135         u32 OCLRC0;
 136         u32 OCLRC1;
 137         u32 DCLRKV;
 138         u32 DCLRKM;
 139         u32 SCLRKVH;
 140         u32 SCLRKVL;
 141         u32 SCLRKEN;
 142         u32 OCONFIG;
 143         u32 OCMD;
 144         u32 RESERVED1; /* 0x6C */
 145         u32 OSTART_0Y;
 146         u32 OSTART_1Y;
 147         u32 OSTART_0U;
 148         u32 OSTART_0V;
 149         u32 OSTART_1U;
 150         u32 OSTART_1V;
 151         u32 OTILEOFF_0Y;
 152         u32 OTILEOFF_1Y;
 153         u32 OTILEOFF_0U;
 154         u32 OTILEOFF_0V;
 155         u32 OTILEOFF_1U;
 156         u32 OTILEOFF_1V;
 157         u32 FASTHSCALE; /* 0xA0 */
 158         u32 UVSCALEV; /* 0xA4 */
 159         u32 RESERVEDC[(0x200 - 0xA8) / 4]; /* 0xA8 - 0x1FC */
 160         u16 Y_VCOEFS[N_VERT_Y_TAPS * N_PHASES]; /* 0x200 */
 161         u16 RESERVEDD[0x100 / 2 - N_VERT_Y_TAPS * N_PHASES];
 162         u16 Y_HCOEFS[N_HORIZ_Y_TAPS * N_PHASES]; /* 0x300 */
 163         u16 RESERVEDE[0x200 / 2 - N_HORIZ_Y_TAPS * N_PHASES];
 164         u16 UV_VCOEFS[N_VERT_UV_TAPS * N_PHASES]; /* 0x500 */
 165         u16 RESERVEDF[0x100 / 2 - N_VERT_UV_TAPS * N_PHASES];
 166         u16 UV_HCOEFS[N_HORIZ_UV_TAPS * N_PHASES]; /* 0x600 */
 167         u16 RESERVEDG[0x100 / 2 - N_HORIZ_UV_TAPS * N_PHASES];
 168 };
 169
 170 struct intel_overlay {
 171         struct drm_device *dev;
 172         struct intel_crtc *crtc;
 173         struct drm_i915_gem_object *vid_bo;
 174         struct drm_i915_gem_object *old_vid_bo;
 175         bool active;
 176         bool pfit_active;
 177         u32 pfit_vscale_ratio; /* shifted-point number, (1<<12) == 1.0 */
 178         u32 color_key:24;
 179         u32 color_key_enabled:1;
 180         u32 brightness, contrast, saturation;
 181         u32 old_xscale, old_yscale;
 182         /* register access */
 183         u32 flip_addr;
 184         struct drm_i915_gem_object *reg_bo;
 185         /* flip handling */
 186         struct drm_i915_gem_request *last_flip_req;
 187         void (*flip_tail)(struct intel_overlay *);
 188 };
 189
 190 static struct overlay_registers __iomem *
 191 intel_overlay_map_regs(struct intel_overlay *overlay)
 192 {
 193         struct drm_i915_private *dev_priv = overlay->dev->dev_private;
 194         struct overlay_registers __iomem *regs;
 195
 196         if (OVERLAY_NEEDS_PHYSICAL(overlay->dev))
 197                 regs = (struct overlay_registers __iomem *)overlay->reg_bo->phys_handle->vaddr;
 198         else
 199                 regs = io_mapping_map_wc(dev_priv->gtt.mappable,
 200                                          i915_gem_obj_ggtt_offset(overlay->reg_bo));
 201
 202         return regs;
 203 }
 204
 205 static void intel_overlay_unmap_regs(struct intel_overlay *overlay,
 206                                      struct overlay_registers __iomem *regs)
 207 {
 208         if (!OVERLAY_NEEDS_PHYSICAL(overlay->dev))
 209                 pmap_unmapdev((vm_offset_t)regs, PAGE_SIZE);
 210 }
 211
 212 static int intel_overlay_do_wait_request(struct intel_overlay *overlay,
 213                                          void (*tail)(struct intel_overlay *))
 214 {
 215         struct drm_device *dev = overlay->dev;
 216         struct drm_i915_private *dev_priv = dev->dev_private;
 217         struct intel_engine_cs *ring = &dev_priv->ring[RCS];
 218         int ret;
 219
 220         WARN_ON(overlay->last_flip_req);
 221         i915_gem_request_assign(&overlay->last_flip_req,
 222                                              ring->outstanding_lazy_request);
 223         ret = i915_add_request(ring);
 224         if (ret)
 225                 return ret;
 226
 227         overlay->flip_tail = tail;
 228         ret = i915_wait_request(overlay->last_flip_req);
 229         if (ret)
 230                 return ret;
 231
 232         i915_gem_request_assign(&overlay->last_flip_req, NULL);
 233         return 0;
 234 }
 235
 236 /* overlay needs to be disable in OCMD reg */
 237 static int intel_overlay_on(struct intel_overlay *overlay)
 238 {
 239         struct drm_device *dev = overlay->dev;
 240         struct drm_i915_private *dev_priv = dev->dev_private;
 241         struct intel_engine_cs *ring = &dev_priv->ring[RCS];
 242         int ret;
 243
 244         WARN_ON(overlay->active);
 245         WARN_ON(IS_I830(dev) && !(dev_priv->quirks & QUIRK_PIPEA_FORCE));
 246
 247         ret = intel_ring_begin(ring, 4);
 248         if (ret)
 249                 return ret;
 250
 251         overlay->active = true;
 252
 253         intel_ring_emit(ring, MI_OVERLAY_FLIP | MI_OVERLAY_ON);
 254         intel_ring_emit(ring, overlay->flip_addr | OFC_UPDATE);
 255         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
 256         intel_ring_emit(ring, MI_NOOP);
 257         intel_ring_advance(ring);
 258
 259         return intel_overlay_do_wait_request(overlay, NULL);
 260 }
 261
 262 /* overlay needs to be enabled in OCMD reg */
 263 static int intel_overlay_continue(struct intel_overlay *overlay,
 264                                   bool load_polyphase_filter)
 265 {
 266         struct drm_device *dev = overlay->dev;
 267         struct drm_i915_private *dev_priv = dev->dev_private;
 268         struct intel_engine_cs *ring = &dev_priv->ring[RCS];
 269         u32 flip_addr = overlay->flip_addr;
 270         u32 tmp;
 271         int ret;
 272
 273         WARN_ON(!overlay->active);
 274
 275         if (load_polyphase_filter)
 276                 flip_addr |= OFC_UPDATE;
 277
 278         /* check for underruns */
 279         tmp = I915_READ(DOVSTA);
 280         if (tmp & (1 << 17))
 281                 DRM_DEBUG("overlay underrun, DOVSTA: %x\n", tmp);
 282
 283         ret = intel_ring_begin(ring, 2);
 284         if (ret)
 285                 return ret;
 286
 287         intel_ring_emit(ring, MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE);
 288         intel_ring_emit(ring, flip_addr);
 289         intel_ring_advance(ring);
 290
 291         WARN_ON(overlay->last_flip_req);
 292         i915_gem_request_assign(&overlay->last_flip_req,
 293                                              ring->outstanding_lazy_request);
 294         return i915_add_request(ring);
 295 }
 296
 297 static void intel_overlay_release_old_vid_tail(struct intel_overlay *overlay)
 298 {
 299         struct drm_i915_gem_object *obj = overlay->old_vid_bo;
 300
 301         i915_gem_object_ggtt_unpin(obj);
 302         drm_gem_object_unreference(&obj->base);
 303
 304         overlay->old_vid_bo = NULL;
 305 }
 306
 307 static void intel_overlay_off_tail(struct intel_overlay *overlay)
 308 {
 309         struct drm_i915_gem_object *obj = overlay->vid_bo;
 310
 311         /* never have the overlay hw on without showing a frame */
 312         if (WARN_ON(!obj))
 313                 return;
 314
 315         i915_gem_object_ggtt_unpin(obj);
 316         drm_gem_object_unreference(&obj->base);
 317         overlay->vid_bo = NULL;
 318
 319         overlay->crtc->overlay = NULL;
 320         overlay->crtc = NULL;
 321         overlay->active = false;
 322 }
 323
 324 /* overlay needs to be disabled in OCMD reg */
 325 static int intel_overlay_off(struct intel_overlay *overlay)
 326 {
 327         struct drm_device *dev = overlay->dev;
 328         struct drm_i915_private *dev_priv = dev->dev_private;
 329         struct intel_engine_cs *ring = &dev_priv->ring[RCS];
 330         u32 flip_addr = overlay->flip_addr;
 331         int ret;
 332
 333         WARN_ON(!overlay->active);
 334
 335         /* According to intel docs the overlay hw may hang (when switching
 336          * off) without loading the filter coeffs. It is however unclear whether
 337          * this applies to the disabling of the overlay or to the switching off
 338          * of the hw. Do it in both cases */
 339         flip_addr |= OFC_UPDATE;
 340
 341         ret = intel_ring_begin(ring, 6);
 342         if (ret)
 343                 return ret;
 344
 345         /* wait for overlay to go idle */
 346         intel_ring_emit(ring, MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE);
 347         intel_ring_emit(ring, flip_addr);
 348         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
 349         /* turn overlay off */
 350         if (IS_I830(dev)) {
 351                 /* Workaround: Don't disable the overlay fully, since otherwise
 352                  * it dies on the next OVERLAY_ON cmd. */
 353                 intel_ring_emit(ring, MI_NOOP);
 354                 intel_ring_emit(ring, MI_NOOP);
 355                 intel_ring_emit(ring, MI_NOOP);
 356         } else {
 357                 intel_ring_emit(ring, MI_OVERLAY_FLIP | MI_OVERLAY_OFF);
 358                 intel_ring_emit(ring, flip_addr);
 359                 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
 360         }
 361         intel_ring_advance(ring);
 362
 363         return intel_overlay_do_wait_request(overlay, intel_overlay_off_tail);
 364 }
 365
 366 /* recover from an interruption due to a signal
 367  * We have to be careful not to repeat work forever an make forward progess. */
 368 static int intel_overlay_recover_from_interrupt(struct intel_overlay *overlay)
 369 {
 370         int ret;
 371
 372         if (overlay->last_flip_req == NULL)
 373                 return 0;
 374
 375         ret = i915_wait_request(overlay->last_flip_req);
 376         if (ret)
 377                 return ret;
 378
 379         if (overlay->flip_tail)
 380                 overlay->flip_tail(overlay);
 381
 382         i915_gem_request_assign(&overlay->last_flip_req, NULL);
 383         return 0;
 384 }
 385
 386 /* Wait for pending overlay flip and release old frame.
 387  * Needs to be called before the overlay register are changed
 388  * via intel_overlay_(un)map_regs
 389  */
 390 static int intel_overlay_release_old_vid(struct intel_overlay *overlay)
 391 {
 392         struct drm_device *dev = overlay->dev;
 393         struct drm_i915_private *dev_priv = dev->dev_private;
 394         struct intel_engine_cs *ring = &dev_priv->ring[RCS];
 395         int ret;
 396
 397         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
 398
 399         /* Only wait if there is actually an old frame to release to
 400          * guarantee forward progress.
 401          */
 402         if (!overlay->old_vid_bo)
 403                 return 0;
 404
 405         if (I915_READ(ISR) & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT) {
 406                 /* synchronous slowpath */
 407                 ret = intel_ring_begin(ring, 2);
 408                 if (ret)
 409                         return ret;
 410
 411                 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
 412                 intel_ring_emit(ring, MI_NOOP);
 413                 intel_ring_advance(ring);
 414
 415                 ret = intel_overlay_do_wait_request(overlay,
 416                                                     intel_overlay_release_old_vid_tail);
 417                 if (ret)
 418                         return ret;
 419         }
 420
 421         intel_overlay_release_old_vid_tail(overlay);
 422
 423
 424         i915_gem_track_fb(overlay->old_vid_bo, NULL,
 425                           INTEL_FRONTBUFFER_OVERLAY(overlay->crtc->pipe));
 426         return 0;
 427 }
 428
 429 void intel_overlay_reset(struct drm_i915_private *dev_priv)
 430 {
 431         struct intel_overlay *overlay = dev_priv->overlay;
 432
 433         if (!overlay)
 434                 return;
 435
 436         intel_overlay_release_old_vid(overlay);
 437
 438         overlay->last_flip_req = NULL;
 439         overlay->old_xscale = 0;
 440         overlay->old_yscale = 0;
 441         overlay->crtc = NULL;
 442         overlay->active = false;
 443 }
 444
 445 struct put_image_params {
 446         int format;
 447         short dst_x;
 448         short dst_y;
 449         short dst_w;
 450         short dst_h;
 451         short src_w;
 452         short src_scan_h;
 453         short src_scan_w;
 454         short src_h;
 455         short stride_Y;
 456         short stride_UV;
 457         int offset_Y;
 458         int offset_U;
 459         int offset_V;
 460 };
 461
 462 static int packed_depth_bytes(u32 format)
 463 {
 464         switch (format & I915_OVERLAY_DEPTH_MASK) {
 465         case I915_OVERLAY_YUV422:
 466                 return 4;
 467         case I915_OVERLAY_YUV411:
 468                 /* return 6; not implemented */
 469         default:
 470                 return -EINVAL;
 471         }
 472 }
 473
 474 static int packed_width_bytes(u32 format, short width)
 475 {
 476         switch (format & I915_OVERLAY_DEPTH_MASK) {
 477         case I915_OVERLAY_YUV422:
 478                 return width << 1;
 479         default:
 480                 return -EINVAL;
 481         }
 482 }
 483
 484 static int uv_hsubsampling(u32 format)
 485 {
 486         switch (format & I915_OVERLAY_DEPTH_MASK) {
 487         case I915_OVERLAY_YUV422:
 488         case I915_OVERLAY_YUV420:
 489                 return 2;
 490         case I915_OVERLAY_YUV411:
 491         case I915_OVERLAY_YUV410:
 492                 return 4;
 493         default:
 494                 return -EINVAL;
 495         }
 496 }
 497
 498 static int uv_vsubsampling(u32 format)
 499 {
 500         switch (format & I915_OVERLAY_DEPTH_MASK) {
 501         case I915_OVERLAY_YUV420:
 502         case I915_OVERLAY_YUV410:
 503                 return 2;
 504         case I915_OVERLAY_YUV422:
 505         case I915_OVERLAY_YUV411:
 506                 return 1;
 507         default:
 508                 return -EINVAL;
 509         }
 510 }
 511
 512 static u32 calc_swidthsw(struct drm_device *dev, u32 offset, u32 width)
 513 {
 514         u32 mask, shift, ret;
 515         if (IS_GEN2(dev)) {
 516                 mask = 0x1f;
 517                 shift = 5;
 518         } else {
 519                 mask = 0x3f;
 520                 shift = 6;
 521         }
 522         ret = ((offset + width + mask) >> shift) - (offset >> shift);
 523         if (!IS_GEN2(dev))
 524                 ret <<= 1;
 525         ret -= 1;
 526         return ret << 2;
 527 }
 528
 529 static const u16 y_static_hcoeffs[N_HORIZ_Y_TAPS * N_PHASES] = {
 530         0x3000, 0xb4a0, 0x1930, 0x1920, 0xb4a0,
 531         0x3000, 0xb500, 0x19d0, 0x1880, 0xb440,
 532         0x3000, 0xb540, 0x1a88, 0x2f80, 0xb3e0,
 533         0x3000, 0xb580, 0x1b30, 0x2e20, 0xb380,
 534         0x3000, 0xb5c0, 0x1bd8, 0x2cc0, 0xb320,
 535         0x3020, 0xb5e0, 0x1c60, 0x2b80, 0xb2c0,
 536         0x3020, 0xb5e0, 0x1cf8, 0x2a20, 0xb260,
 537         0x3020, 0xb5e0, 0x1d80, 0x28e0, 0xb200,
 538         0x3020, 0xb5c0, 0x1e08, 0x3f40, 0xb1c0,
 539         0x3020, 0xb580, 0x1e78, 0x3ce0, 0xb160,
 540         0x3040, 0xb520, 0x1ed8, 0x3aa0, 0xb120,
 541         0x3040, 0xb4a0, 0x1f30, 0x3880, 0xb0e0,
 542         0x3040, 0xb400, 0x1f78, 0x3680, 0xb0a0,
 543         0x3020, 0xb340, 0x1fb8, 0x34a0, 0xb060,
 544         0x3020, 0xb240, 0x1fe0, 0x32e0, 0xb040,
 545         0x3020, 0xb140, 0x1ff8, 0x3160, 0xb020,
 546         0xb000, 0x3000, 0x0800, 0x3000, 0xb000
 547 };
 548
 549 static const u16 uv_static_hcoeffs[N_HORIZ_UV_TAPS * N_PHASES] = {
 550         0x3000, 0x1800, 0x1800, 0xb000, 0x18d0, 0x2e60,
 551         0xb000, 0x1990, 0x2ce0, 0xb020, 0x1a68, 0x2b40,
 552         0xb040, 0x1b20, 0x29e0, 0xb060, 0x1bd8, 0x2880,
 553         0xb080, 0x1c88, 0x3e60, 0xb0a0, 0x1d28, 0x3c00,
 554         0xb0c0, 0x1db8, 0x39e0, 0xb0e0, 0x1e40, 0x37e0,
 555         0xb100, 0x1eb8, 0x3620, 0xb100, 0x1f18, 0x34a0,
 556         0xb100, 0x1f68, 0x3360, 0xb0e0, 0x1fa8, 0x3240,
 557         0xb0c0, 0x1fe0, 0x3140, 0xb060, 0x1ff0, 0x30a0,
 558         0x3000, 0x0800, 0x3000
 559 };
 560
 561 static void update_polyphase_filter(struct overlay_registers __iomem *regs)
 562 {
 563         memcpy_toio(regs->Y_HCOEFS, y_static_hcoeffs, sizeof(y_static_hcoeffs));
 564         memcpy_toio(regs->UV_HCOEFS, uv_static_hcoeffs,
 565                     sizeof(uv_static_hcoeffs));
 566 }
 567
 568 static bool update_scaling_factors(struct intel_overlay *overlay,
 569                                    struct overlay_registers __iomem *regs,
 570                                    struct put_image_params *params)
 571 {
 572         /* fixed point with a 12 bit shift */
 573         u32 xscale, yscale, xscale_UV, yscale_UV;
 574 #define FP_SHIFT 12
 575 #define FRACT_MASK 0xfff
 576         bool scale_changed = false;
 577         int uv_hscale = uv_hsubsampling(params->format);
 578         int uv_vscale = uv_vsubsampling(params->format);
 579
 580         if (params->dst_w > 1)
 581                 xscale = ((params->src_scan_w - 1) << FP_SHIFT)
 582                         /(params->dst_w);
 583         else
 584                 xscale = 1 << FP_SHIFT;
 585
 586         if (params->dst_h > 1)
 587                 yscale = ((params->src_scan_h - 1) << FP_SHIFT)
 588                         /(params->dst_h);
 589         else
 590                 yscale = 1 << FP_SHIFT;
 591
 592         /*if (params->format & I915_OVERLAY_YUV_PLANAR) {*/
 593         xscale_UV = xscale/uv_hscale;
 594         yscale_UV = yscale/uv_vscale;
 595         /* make the Y scale to UV scale ratio an exact multiply */
 596         xscale = xscale_UV * uv_hscale;
 597         yscale = yscale_UV * uv_vscale;
 598         /*} else {
 599           xscale_UV = 0;
 600           yscale_UV = 0;
 601           }*/
 602
 603         if (xscale != overlay->old_xscale || yscale != overlay->old_yscale)
 604                 scale_changed = true;
 605         overlay->old_xscale = xscale;
 606         overlay->old_yscale = yscale;
 607
 608         iowrite32(((yscale & FRACT_MASK) << 20) |
 609                   ((xscale >> FP_SHIFT)  << 16) |
 610                   ((xscale & FRACT_MASK) << 3),
 611                  &regs->YRGBSCALE);
 612
 613         iowrite32(((yscale_UV & FRACT_MASK) << 20) |
 614                   ((xscale_UV >> FP_SHIFT)  << 16) |
 615                   ((xscale_UV & FRACT_MASK) << 3),
 616                  &regs->UVSCALE);
 617
 618         iowrite32((((yscale    >> FP_SHIFT) << 16) |
 619                    ((yscale_UV >> FP_SHIFT) << 0)),
 620                  &regs->UVSCALEV);
 621
 622         if (scale_changed)
 623                 update_polyphase_filter(regs);
 624
 625         return scale_changed;
 626 }
 627
 628 static void update_colorkey(struct intel_overlay *overlay,
 629                             struct overlay_registers __iomem *regs)
 630 {
 631         u32 key = overlay->color_key;
 632         u32 flags;
 633
 634         flags = 0;
 635         if (overlay->color_key_enabled)
 636                 flags |= DST_KEY_ENABLE;
 637
 638         switch (overlay->crtc->base.primary->fb->bits_per_pixel) {
 639         case 8:
 640                 key = 0;
 641                 flags |= CLK_RGB8I_MASK;
 642                 break;
 643
 644         case 16:
 645                 if (overlay->crtc->base.primary->fb->depth == 15) {
 646                         key = RGB15_TO_COLORKEY(key);
 647                         flags |= CLK_RGB15_MASK;
 648                 } else {
 649                         key = RGB16_TO_COLORKEY(key);
 650                         flags |= CLK_RGB16_MASK;
 651                 }
 652                 break;
 653
 654         case 24:
 655         case 32:
 656                 flags |= CLK_RGB24_MASK;
 657                 break;
 658         }
 659
 660         iowrite32(key, &regs->DCLRKV);
 661         iowrite32(flags, &regs->DCLRKM);
 662 }
 663
 664 static u32 overlay_cmd_reg(struct put_image_params *params)
 665 {
 666         u32 cmd = OCMD_ENABLE | OCMD_BUF_TYPE_FRAME | OCMD_BUFFER0;
 667
 668         if (params->format & I915_OVERLAY_YUV_PLANAR) {
 669                 switch (params->format & I915_OVERLAY_DEPTH_MASK) {
 670                 case I915_OVERLAY_YUV422:
 671                         cmd |= OCMD_YUV_422_PLANAR;
 672                         break;
 673                 case I915_OVERLAY_YUV420:
 674                         cmd |= OCMD_YUV_420_PLANAR;
 675                         break;
 676                 case I915_OVERLAY_YUV411:
 677                 case I915_OVERLAY_YUV410:
 678                         cmd |= OCMD_YUV_410_PLANAR;
 679                         break;
 680                 }
 681         } else { /* YUV packed */
 682                 switch (params->format & I915_OVERLAY_DEPTH_MASK) {
 683                 case I915_OVERLAY_YUV422:
 684                         cmd |= OCMD_YUV_422_PACKED;
 685                         break;
 686                 case I915_OVERLAY_YUV411:
 687                         cmd |= OCMD_YUV_411_PACKED;
 688                         break;
 689                 }
 690
 691                 switch (params->format & I915_OVERLAY_SWAP_MASK) {
 692                 case I915_OVERLAY_NO_SWAP:
 693                         break;
 694                 case I915_OVERLAY_UV_SWAP:
 695                         cmd |= OCMD_UV_SWAP;
 696                         break;
 697                 case I915_OVERLAY_Y_SWAP:
 698                         cmd |= OCMD_Y_SWAP;
 699                         break;
 700                 case I915_OVERLAY_Y_AND_UV_SWAP:
 701                         cmd |= OCMD_Y_AND_UV_SWAP;
 702                         break;
 703                 }
 704         }
 705
 706         return cmd;
 707 }
 708
 709 static int intel_overlay_do_put_image(struct intel_overlay *overlay,
 710                                       struct drm_i915_gem_object *new_bo,
 711                                       struct put_image_params *params)
 712 {
 713         int ret, tmp_width;
 714         struct overlay_registers __iomem *regs;
 715         bool scale_changed = false;
 716         struct drm_device *dev = overlay->dev;
 717         u32 swidth, swidthsw, sheight, ostride;
 718         enum i915_pipe pipe = overlay->crtc->pipe;
 719
 720         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
 721         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
 722
 723         ret = intel_overlay_release_old_vid(overlay);
 724         if (ret != 0)
 725                 return ret;
 726
 727         ret = i915_gem_object_pin_to_display_plane(new_bo, 0, NULL,
 728                                                    &i915_ggtt_view_normal);
 729         if (ret != 0)
 730                 return ret;
 731
 732         ret = i915_gem_object_put_fence(new_bo);
 733         if (ret)
 734                 goto out_unpin;
 735
 736         if (!overlay->active) {
 737                 u32 oconfig;
 738                 regs = intel_overlay_map_regs(overlay);
 739                 if (!regs) {
 740                         ret = -ENOMEM;
 741                         goto out_unpin;
 742                 }
 743                 oconfig = OCONF_CC_OUT_8BIT;
 744                 if (IS_GEN4(overlay->dev))
 745                         oconfig |= OCONF_CSC_MODE_BT709;
 746                 oconfig |= pipe == 0 ?
 747                         OCONF_PIPE_A : OCONF_PIPE_B;
 748                 iowrite32(oconfig, &regs->OCONFIG);
 749                 intel_overlay_unmap_regs(overlay, regs);
 750
 751                 ret = intel_overlay_on(overlay);
 752                 if (ret != 0)
 753                         goto out_unpin;
 754         }
 755
 756         regs = intel_overlay_map_regs(overlay);
 757         if (!regs) {
 758                 ret = -ENOMEM;
 759                 goto out_unpin;
 760         }
 761
 762         iowrite32((params->dst_y << 16) | params->dst_x, &regs->DWINPOS);
 763         iowrite32((params->dst_h << 16) | params->dst_w, &regs->DWINSZ);
 764
 765         if (params->format & I915_OVERLAY_YUV_PACKED)
 766                 tmp_width = packed_width_bytes(params->format, params->src_w);
 767         else
 768                 tmp_width = params->src_w;
 769
 770         swidth = params->src_w;
 771         swidthsw = calc_swidthsw(overlay->dev, params->offset_Y, tmp_width);
 772         sheight = params->src_h;
 773         iowrite32(i915_gem_obj_ggtt_offset(new_bo) + params->offset_Y, &regs->OBUF_0Y);
 774         ostride = params->stride_Y;
 775
 776         if (params->format & I915_OVERLAY_YUV_PLANAR) {
 777                 int uv_hscale = uv_hsubsampling(params->format);
 778                 int uv_vscale = uv_vsubsampling(params->format);
 779                 u32 tmp_U, tmp_V;
 780                 swidth |= (params->src_w/uv_hscale) << 16;
 781                 tmp_U = calc_swidthsw(overlay->dev, params->offset_U,
 782                                       params->src_w/uv_hscale);
 783                 tmp_V = calc_swidthsw(overlay->dev, params->offset_V,
 784                                       params->src_w/uv_hscale);
 785                 swidthsw |= max_t(u32, tmp_U, tmp_V) << 16;
 786                 sheight |= (params->src_h/uv_vscale) << 16;
 787                 iowrite32(i915_gem_obj_ggtt_offset(new_bo) + params->offset_U, &regs->OBUF_0U);
 788                 iowrite32(i915_gem_obj_ggtt_offset(new_bo) + params->offset_V, &regs->OBUF_0V);
 789                 ostride |= params->stride_UV << 16;
 790         }
 791
 792         iowrite32(swidth, &regs->SWIDTH);
 793         iowrite32(swidthsw, &regs->SWIDTHSW);
 794         iowrite32(sheight, &regs->SHEIGHT);
 795         iowrite32(ostride, &regs->OSTRIDE);
 796
 797         scale_changed = update_scaling_factors(overlay, regs, params);
 798
 799         update_colorkey(overlay, regs);
 800
 801         iowrite32(overlay_cmd_reg(params), &regs->OCMD);
 802
 803         intel_overlay_unmap_regs(overlay, regs);
 804
 805         ret = intel_overlay_continue(overlay, scale_changed);
 806         if (ret)
 807                 goto out_unpin;
 808
 809         i915_gem_track_fb(overlay->vid_bo, new_bo,
 810                           INTEL_FRONTBUFFER_OVERLAY(pipe));
 811
 812         overlay->old_vid_bo = overlay->vid_bo;
 813         overlay->vid_bo = new_bo;
 814
 815         intel_frontbuffer_flip(dev,
 816                                INTEL_FRONTBUFFER_OVERLAY(pipe));
 817
 818         return 0;
 819
 820 out_unpin:
 821         i915_gem_object_ggtt_unpin(new_bo);
 822         return ret;
 823 }
 824
 825 int intel_overlay_switch_off(struct intel_overlay *overlay)
 826 {
 827         struct overlay_registers __iomem *regs;
 828         struct drm_device *dev = overlay->dev;
 829         int ret;
 830
 831         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
 832         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
 833
 834         ret = intel_overlay_recover_from_interrupt(overlay);
 835         if (ret != 0)
 836                 return ret;
 837
 838         if (!overlay->active)
 839                 return 0;
 840
 841         ret = intel_overlay_release_old_vid(overlay);
 842         if (ret != 0)
 843                 return ret;
 844
 845         regs = intel_overlay_map_regs(overlay);
 846         iowrite32(0, &regs->OCMD);
 847         intel_overlay_unmap_regs(overlay, regs);
 848
 849         ret = intel_overlay_off(overlay);
 850         if (ret != 0)
 851                 return ret;
 852
 853         intel_overlay_off_tail(overlay);
 854         return 0;
 855 }
 856
 857 static int check_overlay_possible_on_crtc(struct intel_overlay *overlay,
 858                                           struct intel_crtc *crtc)
 859 {
 860         if (!crtc->active)
 861                 return -EINVAL;
 862
 863         /* can't use the overlay with double wide pipe */
 864         if (crtc->config->double_wide)
 865                 return -EINVAL;
 866
 867         return 0;
 868 }
 869
 870 static void update_pfit_vscale_ratio(struct intel_overlay *overlay)
 871 {
 872         struct drm_device *dev = overlay->dev;
 873         struct drm_i915_private *dev_priv = dev->dev_private;
 874         u32 pfit_control = I915_READ(PFIT_CONTROL);
 875         u32 ratio;
 876
 877         /* XXX: This is not the same logic as in the xorg driver, but more in
 878          * line with the intel documentation for the i965
 879          */
 880         if (INTEL_INFO(dev)->gen >= 4) {
 881                 /* on i965 use the PGM reg to read out the autoscaler values */
 882                 ratio = I915_READ(PFIT_PGM_RATIOS) >> PFIT_VERT_SCALE_SHIFT_965;
 883         } else {
 884                 if (pfit_control & VERT_AUTO_SCALE)
 885                         ratio = I915_READ(PFIT_AUTO_RATIOS);
 886                 else
 887                         ratio = I915_READ(PFIT_PGM_RATIOS);
 888                 ratio >>= PFIT_VERT_SCALE_SHIFT;
 889         }
 890
 891         overlay->pfit_vscale_ratio = ratio;
 892 }
 893
 894 static int check_overlay_dst(struct intel_overlay *overlay,
 895                              struct drm_intel_overlay_put_image *rec)
 896 {
 897         struct drm_display_mode *mode = &overlay->crtc->base.mode;
 898
 899         if (rec->dst_x < mode->hdisplay &&
 900             rec->dst_x + rec->dst_width <= mode->hdisplay &&
 901             rec->dst_y < mode->vdisplay &&
 902             rec->dst_y + rec->dst_height <= mode->vdisplay)
 903                 return 0;
 904         else
 905                 return -EINVAL;
 906 }
 907
 908 static int check_overlay_scaling(struct put_image_params *rec)
 909 {
 910         u32 tmp;
 911
 912         /* downscaling limit is 8.0 */
 913         tmp = ((rec->src_scan_h << 16) / rec->dst_h) >> 16;
 914         if (tmp > 7)
 915                 return -EINVAL;
 916         tmp = ((rec->src_scan_w << 16) / rec->dst_w) >> 16;
 917         if (tmp > 7)
 918                 return -EINVAL;
 919
 920         return 0;
 921 }
 922
 923 static int check_overlay_src(struct drm_device *dev,
 924                              struct drm_intel_overlay_put_image *rec,
 925                              struct drm_i915_gem_object *new_bo)
 926 {
 927         int uv_hscale = uv_hsubsampling(rec->flags);
 928         int uv_vscale = uv_vsubsampling(rec->flags);
 929         u32 stride_mask;
 930         int depth;
 931         u32 tmp;
 932
 933         /* check src dimensions */
 934         if (IS_845G(dev) || IS_I830(dev)) {
 935                 if (rec->src_height > IMAGE_MAX_HEIGHT_LEGACY ||
 936                     rec->src_width  > IMAGE_MAX_WIDTH_LEGACY)
 937                         return -EINVAL;
 938         } else {
 939                 if (rec->src_height > IMAGE_MAX_HEIGHT ||
 940                     rec->src_width  > IMAGE_MAX_WIDTH)
 941                         return -EINVAL;
 942         }
 943
 944         /* better safe than sorry, use 4 as the maximal subsampling ratio */
 945         if (rec->src_height < N_VERT_Y_TAPS*4 ||
 946             rec->src_width  < N_HORIZ_Y_TAPS*4)
 947                 return -EINVAL;
 948
 949         /* check alignment constraints */
 950         switch (rec->flags & I915_OVERLAY_TYPE_MASK) {
 951         case I915_OVERLAY_RGB:
 952                 /* not implemented */
 953                 return -EINVAL;
 954
 955         case I915_OVERLAY_YUV_PACKED:
 956                 if (uv_vscale != 1)
 957                         return -EINVAL;
 958
 959                 depth = packed_depth_bytes(rec->flags);
 960                 if (depth < 0)
 961                         return depth;
 962
 963                 /* ignore UV planes */
 964                 rec->stride_UV = 0;
 965                 rec->offset_U = 0;
 966                 rec->offset_V = 0;
 967                 /* check pixel alignment */
 968                 if (rec->offset_Y % depth)
 969                         return -EINVAL;
 970                 break;
 971
 972         case I915_OVERLAY_YUV_PLANAR:
 973                 if (uv_vscale < 0 || uv_hscale < 0)
 974                         return -EINVAL;
 975                 /* no offset restrictions for planar formats */
 976                 break;
 977
 978         default:
 979                 return -EINVAL;
 980         }
 981
 982         if (rec->src_width % uv_hscale)
 983                 return -EINVAL;
 984
 985         /* stride checking */
 986         if (IS_I830(dev) || IS_845G(dev))
 987                 stride_mask = 255;
 988         else
 989                 stride_mask = 63;
 990
 991         if (rec->stride_Y & stride_mask || rec->stride_UV & stride_mask)
 992                 return -EINVAL;
 993         if (IS_GEN4(dev) && rec->stride_Y < 512)
 994                 return -EINVAL;
 995
 996         tmp = (rec->flags & I915_OVERLAY_TYPE_MASK) == I915_OVERLAY_YUV_PLANAR ?
 997                 4096 : 8192;
 998         if (rec->stride_Y > tmp || rec->stride_UV > 2*1024)
 999                 return -EINVAL;
1000
1001         /* check buffer dimensions */
1002         switch (rec->flags & I915_OVERLAY_TYPE_MASK) {
1003         case I915_OVERLAY_RGB:
1004         case I915_OVERLAY_YUV_PACKED:
1005                 /* always 4 Y values per depth pixels */
1006                 if (packed_width_bytes(rec->flags, rec->src_width) > rec->stride_Y)
1007                         return -EINVAL;
1008
1009                 tmp = rec->stride_Y*rec->src_height;
1010                 if (rec->offset_Y + tmp > new_bo->base.size)
1011                         return -EINVAL;
1012                 break;
1013
1014         case I915_OVERLAY_YUV_PLANAR:
1015                 if (rec->src_width > rec->stride_Y)
1016                         return -EINVAL;
1017                 if (rec->src_width/uv_hscale > rec->stride_UV)
1018                         return -EINVAL;
1019
1020                 tmp = rec->stride_Y * rec->src_height;
1021                 if (rec->offset_Y + tmp > new_bo->base.size)
1022                         return -EINVAL;
1023
1024                 tmp = rec->stride_UV * (rec->src_height / uv_vscale);
1025                 if (rec->offset_U + tmp > new_bo->base.size ||
1026                     rec->offset_V + tmp > new_bo->base.size)
1027                         return -EINVAL;
1028                 break;
1029         }
1030
1031         return 0;
1032 }
1033
1034 /**
1035  * Return the pipe currently connected to the panel fitter,
1036  * or -1 if the panel fitter is not present or not in use
1037  */
1038 static int intel_panel_fitter_pipe(struct drm_device *dev)
1039 {
1040         struct drm_i915_private *dev_priv = dev->dev_private;
1041         u32  pfit_control;
1042
1043         /* i830 doesn't have a panel fitter */
1044         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
1045                 return -1;
1046
1047         pfit_control = I915_READ(PFIT_CONTROL);
1048
1049         /* See if the panel fitter is in use */
1050         if ((pfit_control & PFIT_ENABLE) == 0)
1051                 return -1;
1052
1053         /* 965 can place panel fitter on either pipe */
1054         if (IS_GEN4(dev))
1055                 return (pfit_control >> 29) & 0x3;
1056
1057         /* older chips can only use pipe 1 */
1058         return 1;
1059 }
1060
1061 int intel_overlay_put_image(struct drm_device *dev, void *data,
1062                             struct drm_file *file_priv)
1063 {
1064         struct drm_intel_overlay_put_image *put_image_rec = data;
1065         struct drm_i915_private *dev_priv = dev->dev_private;
1066         struct intel_overlay *overlay;
1067         struct drm_crtc *drmmode_crtc;
1068         struct intel_crtc *crtc;
1069         struct drm_i915_gem_object *new_bo;
1070         struct put_image_params *params;
1071         int ret;
1072
1073         overlay = dev_priv->overlay;
1074         if (!overlay) {
1075                 DRM_DEBUG("userspace bug: no overlay\n");
1076                 return -ENODEV;
1077         }
1078
1079         if (!(put_image_rec->flags & I915_OVERLAY_ENABLE)) {
1080                 drm_modeset_lock_all(dev);
1081                 mutex_lock(&dev->struct_mutex);
1082
1083                 ret = intel_overlay_switch_off(overlay);
1084
1085                 mutex_unlock(&dev->struct_mutex);
1086                 drm_modeset_unlock_all(dev);
1087
1088                 return ret;
1089         }
1090
1091         params = kmalloc(sizeof(*params), M_DRM, M_WAITOK);
1092         if (!params)
1093                 return -ENOMEM;
1094
1095         drmmode_crtc = drm_crtc_find(dev, put_image_rec->crtc_id);
1096         if (!drmmode_crtc) {
1097                 ret = -ENOENT;
1098                 goto out_free;
1099         }
1100         crtc = to_intel_crtc(drmmode_crtc);
1101
1102         new_bo = to_intel_bo(drm_gem_object_lookup(dev, file_priv,
1103                                                    put_image_rec->bo_handle));
1104         if (&new_bo->base == NULL) {
1105                 ret = -ENOENT;
1106                 goto out_free;
1107         }
1108
1109         drm_modeset_lock_all(dev);
1110         mutex_lock(&dev->struct_mutex);
1111
1112         if (new_bo->tiling_mode) {
1113                 DRM_DEBUG_KMS("buffer used for overlay image can not be tiled\n");
1114                 ret = -EINVAL;
1115                 goto out_unlock;
1116         }
1117
1118         ret = intel_overlay_recover_from_interrupt(overlay);
1119         if (ret != 0)
1120                 goto out_unlock;
1121
1122         if (overlay->crtc != crtc) {
1123                 struct drm_display_mode *mode = &crtc->base.mode;
1124                 ret = intel_overlay_switch_off(overlay);
1125                 if (ret != 0)
1126                         goto out_unlock;
1127
1128                 ret = check_overlay_possible_on_crtc(overlay, crtc);
1129                 if (ret != 0)
1130                         goto out_unlock;
1131
1132                 overlay->crtc = crtc;
1133                 crtc->overlay = overlay;
1134
1135                 /* line too wide, i.e. one-line-mode */
1136                 if (mode->hdisplay > 1024 &&
1137                     intel_panel_fitter_pipe(dev) == crtc->pipe) {
1138                         overlay->pfit_active = true;
1139                         update_pfit_vscale_ratio(overlay);
1140                 } else
1141                         overlay->pfit_active = false;
1142         }
1143
1144         ret = check_overlay_dst(overlay, put_image_rec);
1145         if (ret != 0)
1146                 goto out_unlock;
1147
1148         if (overlay->pfit_active) {
1149                 params->dst_y = ((((u32)put_image_rec->dst_y) << 12) /
1150                                  overlay->pfit_vscale_ratio);
1151                 /* shifting right rounds downwards, so add 1 */
1152                 params->dst_h = ((((u32)put_image_rec->dst_height) << 12) /
1153                                  overlay->pfit_vscale_ratio) + 1;
1154         } else {
1155                 params->dst_y = put_image_rec->dst_y;
1156                 params->dst_h = put_image_rec->dst_height;
1157         }
1158         params->dst_x = put_image_rec->dst_x;
1159         params->dst_w = put_image_rec->dst_width;
1160
1161         params->src_w = put_image_rec->src_width;
1162         params->src_h = put_image_rec->src_height;
1163         params->src_scan_w = put_image_rec->src_scan_width;
1164         params->src_scan_h = put_image_rec->src_scan_height;
1165         if (params->src_scan_h > params->src_h ||
1166             params->src_scan_w > params->src_w) {
1167                 ret = -EINVAL;
1168                 goto out_unlock;
1169         }
1170
1171         ret = check_overlay_src(dev, put_image_rec, new_bo);
1172         if (ret != 0)
1173                 goto out_unlock;
1174         params->format = put_image_rec->flags & ~I915_OVERLAY_FLAGS_MASK;
1175         params->stride_Y = put_image_rec->stride_Y;
1176         params->stride_UV = put_image_rec->stride_UV;
1177         params->offset_Y = put_image_rec->offset_Y;
1178         params->offset_U = put_image_rec->offset_U;
1179         params->offset_V = put_image_rec->offset_V;
1180
1181         /* Check scaling after src size to prevent a divide-by-zero. */
1182         ret = check_overlay_scaling(params);
1183         if (ret != 0)
1184                 goto out_unlock;
1185
1186         ret = intel_overlay_do_put_image(overlay, new_bo, params);
1187         if (ret != 0)
1188                 goto out_unlock;
1189
1190         mutex_unlock(&dev->struct_mutex);
1191         drm_modeset_unlock_all(dev);
1192
1193         kfree(params);
1194
1195         return 0;
1196
1197 out_unlock:
1198         mutex_unlock(&dev->struct_mutex);
1199         drm_modeset_unlock_all(dev);
1200         drm_gem_object_unreference_unlocked(&new_bo->base);
1201 out_free:
1202         kfree(params);
1203
1204         return ret;
1205 }
1206
1207 static void update_reg_attrs(struct intel_overlay *overlay,
1208                              struct overlay_registers __iomem *regs)
1209 {
1210         iowrite32((overlay->contrast << 18) | (overlay->brightness & 0xff),
1211                   &regs->OCLRC0);
1212         iowrite32(overlay->saturation, &regs->OCLRC1);
1213 }
1214
1215 static bool check_gamma_bounds(u32 gamma1, u32 gamma2)
1216 {
1217         int i;
1218
1219         if (gamma1 & 0xff000000 || gamma2 & 0xff000000)
1220                 return false;
1221
1222         for (i = 0; i < 3; i++) {
1223                 if (((gamma1 >> i*8) & 0xff) >= ((gamma2 >> i*8) & 0xff))
1224                         return false;
1225         }
1226
1227         return true;
1228 }
1229
1230 static bool check_gamma5_errata(u32 gamma5)
1231 {
1232         int i;
1233
1234         for (i = 0; i < 3; i++) {
1235                 if (((gamma5 >> i*8) & 0xff) == 0x80)
1236                         return false;
1237         }
1238
1239         return true;
1240 }
1241
1242 static int check_gamma(struct drm_intel_overlay_attrs *attrs)
1243 {
1244         if (!check_gamma_bounds(0, attrs->gamma0) ||
1245             !check_gamma_bounds(attrs->gamma0, attrs->gamma1) ||
1246             !check_gamma_bounds(attrs->gamma1, attrs->gamma2) ||
1247             !check_gamma_bounds(attrs->gamma2, attrs->gamma3) ||
1248             !check_gamma_bounds(attrs->gamma3, attrs->gamma4) ||
1249             !check_gamma_bounds(attrs->gamma4, attrs->gamma5) ||
1250             !check_gamma_bounds(attrs->gamma5, 0x00ffffff))
1251                 return -EINVAL;
1252
1253         if (!check_gamma5_errata(attrs->gamma5))
1254                 return -EINVAL;
1255
1256         return 0;
1257 }
1258
1259 int intel_overlay_attrs(struct drm_device *dev, void *data,
1260                         struct drm_file *file_priv)
1261 {
1262         struct drm_intel_overlay_attrs *attrs = data;
1263         struct drm_i915_private *dev_priv = dev->dev_private;
1264         struct intel_overlay *overlay;
1265         struct overlay_registers __iomem *regs;
1266         int ret;
1267
1268         overlay = dev_priv->overlay;
1269         if (!overlay) {
1270                 DRM_DEBUG("userspace bug: no overlay\n");
1271                 return -ENODEV;
1272         }
1273
1274         drm_modeset_lock_all(dev);
1275         mutex_lock(&dev->struct_mutex);
1276
1277         ret = -EINVAL;
1278         if (!(attrs->flags & I915_OVERLAY_UPDATE_ATTRS)) {
1279                 attrs->color_key  = overlay->color_key;
1280                 attrs->brightness = overlay->brightness;
1281                 attrs->contrast   = overlay->contrast;
1282                 attrs->saturation = overlay->saturation;
1283
1284                 if (!IS_GEN2(dev)) {
1285                         attrs->gamma0 = I915_READ(OGAMC0);
1286                         attrs->gamma1 = I915_READ(OGAMC1);
1287                         attrs->gamma2 = I915_READ(OGAMC2);
1288                         attrs->gamma3 = I915_READ(OGAMC3);
1289                         attrs->gamma4 = I915_READ(OGAMC4);
1290                         attrs->gamma5 = I915_READ(OGAMC5);
1291                 }
1292         } else {
1293                 if (attrs->brightness < -128 || attrs->brightness > 127)
1294                         goto out_unlock;
1295                 if (attrs->contrast > 255)
1296                         goto out_unlock;
1297                 if (attrs->saturation > 1023)
1298                         goto out_unlock;
1299
1300                 overlay->color_key  = attrs->color_key;
1301                 overlay->brightness = attrs->brightness;
1302                 overlay->contrast   = attrs->contrast;
1303                 overlay->saturation = attrs->saturation;
1304
1305                 regs = intel_overlay_map_regs(overlay);
1306                 if (!regs) {
1307                         ret = -ENOMEM;
1308                         goto out_unlock;
1309                 }
1310
1311                 update_reg_attrs(overlay, regs);
1312
1313                 intel_overlay_unmap_regs(overlay, regs);
1314
1315                 if (attrs->flags & I915_OVERLAY_UPDATE_GAMMA) {
1316                         if (IS_GEN2(dev))
1317                                 goto out_unlock;
1318
1319                         if (overlay->active) {
1320                                 ret = -EBUSY;
1321                                 goto out_unlock;
1322                         }
1323
1324                         ret = check_gamma(attrs);
1325                         if (ret)
1326                                 goto out_unlock;
1327
1328                         I915_WRITE(OGAMC0, attrs->gamma0);
1329                         I915_WRITE(OGAMC1, attrs->gamma1);
1330                         I915_WRITE(OGAMC2, attrs->gamma2);
1331                         I915_WRITE(OGAMC3, attrs->gamma3);
1332                         I915_WRITE(OGAMC4, attrs->gamma4);
1333                         I915_WRITE(OGAMC5, attrs->gamma5);
1334                 }
1335         }
1336         overlay->color_key_enabled = (attrs->flags & I915_OVERLAY_DISABLE_DEST_COLORKEY) == 0;
1337
1338         ret = 0;
1339 out_unlock:
1340         mutex_unlock(&dev->struct_mutex);
1341         drm_modeset_unlock_all(dev);
1342
1343         return ret;
1344 }
1345
1346 void intel_setup_overlay(struct drm_device *dev)
1347 {
1348         struct drm_i915_private *dev_priv = dev->dev_private;
1349         struct intel_overlay *overlay;
1350         struct drm_i915_gem_object *reg_bo;
1351         struct overlay_registers __iomem *regs;
1352         int ret;
1353
1354         if (!HAS_OVERLAY(dev))
1355                 return;
1356
1357         overlay = kzalloc(sizeof(*overlay), GFP_KERNEL);
1358         if (!overlay)
1359                 return;
1360
1361         mutex_lock(&dev->struct_mutex);
1362         if (WARN_ON(dev_priv->overlay))
1363                 goto out_free;
1364
1365         overlay->dev = dev;
1366
1367         reg_bo = NULL;
1368         if (!OVERLAY_NEEDS_PHYSICAL(dev))
1369                 reg_bo = i915_gem_object_create_stolen(dev, PAGE_SIZE);
1370         if (reg_bo == NULL)
1371                 reg_bo = i915_gem_alloc_object(dev, PAGE_SIZE);
1372         if (reg_bo == NULL)
1373                 goto out_free;
1374         overlay->reg_bo = reg_bo;
1375
1376         if (OVERLAY_NEEDS_PHYSICAL(dev)) {
1377                 ret = i915_gem_object_attach_phys(reg_bo, PAGE_SIZE);
1378                 if (ret) {
1379                         DRM_ERROR("failed to attach phys overlay regs\n");
1380                         goto out_free_bo;
1381                 }
1382                 overlay->flip_addr = reg_bo->phys_handle->busaddr;
1383         } else {
1384                 ret = i915_gem_obj_ggtt_pin(reg_bo, PAGE_SIZE, PIN_MAPPABLE);
1385                 if (ret) {
1386                         DRM_ERROR("failed to pin overlay register bo\n");
1387                         goto out_free_bo;
1388                 }
1389                 overlay->flip_addr = i915_gem_obj_ggtt_offset(reg_bo);
1390
1391                 ret = i915_gem_object_set_to_gtt_domain(reg_bo, true);
1392                 if (ret) {
1393                         DRM_ERROR("failed to move overlay register bo into the GTT\n");
1394                         goto out_unpin_bo;
1395                 }
1396         }
1397
1398         /* init all values */
1399         overlay->color_key = 0x0101fe;
1400         overlay->color_key_enabled = true;
1401         overlay->brightness = -19;
1402         overlay->contrast = 75;
1403         overlay->saturation = 146;
1404
1405         regs = intel_overlay_map_regs(overlay);
1406         if (!regs)
1407                 goto out_unpin_bo;
1408
1409         memset_io(regs, 0, sizeof(struct overlay_registers));
1410         update_polyphase_filter(regs);
1411         update_reg_attrs(overlay, regs);
1412
1413         intel_overlay_unmap_regs(overlay, regs);
1414
1415         dev_priv->overlay = overlay;
1416         mutex_unlock(&dev->struct_mutex);
1417         DRM_INFO("initialized overlay support\n");
1418         return;
1419
1420 out_unpin_bo:
1421         if (!OVERLAY_NEEDS_PHYSICAL(dev))
1422                 i915_gem_object_ggtt_unpin(reg_bo);
1423 out_free_bo:
1424         drm_gem_object_unreference(&reg_bo->base);
1425 out_free:
1426         mutex_unlock(&dev->struct_mutex);
1427         kfree(overlay);
1428         return;
1429 }
1430
1431 void intel_cleanup_overlay(struct drm_device *dev)
1432 {
1433         struct drm_i915_private *dev_priv = dev->dev_private;
1434
1435         if (!dev_priv->overlay)
1436                 return;
1437
1438         /* The bo's should be free'd by the generic code already.
1439          * Furthermore modesetting teardown happens beforehand so the
1440          * hardware should be off already */
1441         WARN_ON(dev_priv->overlay->active);
1442
1443         drm_gem_object_unreference_unlocked(&dev_priv->overlay->reg_bo->base);
1444         kfree(dev_priv->overlay);
1445 }
1446
1447 struct intel_overlay_error_state {
1448         struct overlay_registers regs;
1449         unsigned long base;
1450         u32 dovsta;
1451         u32 isr;
1452 };
1453
1454 #if 0
1455 static struct overlay_registers __iomem *
1456 intel_overlay_map_regs_atomic(struct intel_overlay *overlay)
1457 {
1458         struct drm_i915_private *dev_priv = overlay->dev->dev_private;
1459         struct overlay_registers __iomem *regs;
1460
1461         if (OVERLAY_NEEDS_PHYSICAL(overlay->dev))
1462                 /* Cast to make sparse happy, but it's wc memory anyway, so
1463                  * equivalent to the wc io mapping on X86. */
1464                 regs = (struct overlay_registers __iomem *)
1465                         overlay->reg_bo->phys_handle->vaddr;
1466         else
1467                 regs = io_mapping_map_atomic_wc(dev_priv->gtt.mappable,
1468                                                 i915_gem_obj_ggtt_offset(overlay->reg_bo));
1469
1470         return regs;
1471 }
1472
1473 static void intel_overlay_unmap_regs_atomic(struct intel_overlay *overlay,
1474                                         struct overlay_registers __iomem *regs)
1475 {
1476         if (!OVERLAY_NEEDS_PHYSICAL(overlay->dev))
1477                 io_mapping_unmap_atomic(regs);
1478 }
1479
1480
1481 struct intel_overlay_error_state *
1482 intel_overlay_capture_error_state(struct drm_device *dev)
1483 {
1484         struct drm_i915_private *dev_priv = dev->dev_private;
1485         struct intel_overlay *overlay = dev_priv->overlay;
1486         struct intel_overlay_error_state *error;
1487         struct overlay_registers __iomem *regs;
1488
1489         if (!overlay || !overlay->active)
1490                 return NULL;
1491
1492         error = kmalloc(sizeof(*error), GFP_ATOMIC);
1493         if (error == NULL)
1494                 return NULL;
1495
1496         error->dovsta = I915_READ(DOVSTA);
1497         error->isr = I915_READ(ISR);
1498         if (OVERLAY_NEEDS_PHYSICAL(overlay->dev))
1499                 error->base = (__force long)overlay->reg_bo->phys_handle->vaddr;
1500         else
1501                 error->base = i915_gem_obj_ggtt_offset(overlay->reg_bo);
1502
1503         regs = intel_overlay_map_regs_atomic(overlay);
1504         if (!regs)
1505                 goto err;
1506
1507         memcpy_fromio(&error->regs, regs, sizeof(struct overlay_registers));
1508         intel_overlay_unmap_regs_atomic(overlay, regs);
1509
1510         return error;
1511
1512 err:
1513         kfree(error);
1514         return NULL;
1515 }
1516
1517 void
1518 intel_overlay_print_error_state(struct drm_i915_error_state_buf *m,
1519                                 struct intel_overlay_error_state *error)
1520 {
1521         i915_error_printf(m, "Overlay, status: 0x%08x, interrupt: 0x%08x\n",
1522                           error->dovsta, error->isr);
1523         i915_error_printf(m, "  Register file at 0x%08lx:\n",
1524                           error->base);
1525
1526 #define P(x) i915_error_printf(m, "    " #x ":  0x%08x\n", error->regs.x)
1527         P(OBUF_0Y);
1528         P(OBUF_1Y);
1529         P(OBUF_0U);
1530         P(OBUF_0V);
1531         P(OBUF_1U);
1532         P(OBUF_1V);
1533         P(OSTRIDE);
1534         P(YRGB_VPH);
1535         P(UV_VPH);
1536         P(HORZ_PH);
1537         P(INIT_PHS);
1538         P(DWINPOS);
1539         P(DWINSZ);
1540         P(SWIDTH);
1541         P(SWIDTHSW);
1542         P(SHEIGHT);
1543         P(YRGBSCALE);
1544         P(UVSCALE);
1545         P(OCLRC0);
1546         P(OCLRC1);
1547         P(DCLRKV);
1548         P(DCLRKM);
1549         P(SCLRKVH);
1550         P(SCLRKVL);
1551         P(SCLRKEN);
1552         P(OCONFIG);
1553         P(OCMD);
1554         P(OSTART_0Y);
1555         P(OSTART_1Y);
1556         P(OSTART_0U);
1557         P(OSTART_0V);
1558         P(OSTART_1U);
1559         P(OSTART_1V);
1560         P(OTILEOFF_0Y);
1561         P(OTILEOFF_1Y);
1562         P(OTILEOFF_0U);
1563         P(OTILEOFF_0V);
1564         P(OTILEOFF_1U);
1565         P(OTILEOFF_1V);
1566         P(FASTHSCALE);
1567         P(UVSCALEV);
1568 #undef P
1569 }
1570 #endif