sys/dev/netif/ig_hal/e1000_82541.c

   1 /******************************************************************************
   2
   3   Copyright (c) 2001-2015, Intel Corporation
   4   All rights reserved.
   5
   6   Redistribution and use in source and binary forms, with or without
   7   modification, are permitted provided that the following conditions are met:
   8
   9    1. Redistributions of source code must retain the above copyright notice,
  10       this list of conditions and the following disclaimer.
  11
  12    2. Redistributions in binary form must reproduce the above copyright
  13       notice, this list of conditions and the following disclaimer in the
  14       documentation and/or other materials provided with the distribution.
  15
  16    3. Neither the name of the Intel Corporation nor the names of its
  17       contributors may be used to endorse or promote products derived from
  18       this software without specific prior written permission.
  19
  20   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30   POSSIBILITY OF SUCH DAMAGE.
  31
  32 ******************************************************************************/
  33 /*$FreeBSD$*/
  34
  35 /*
  36  * 82541EI Gigabit Ethernet Controller
  37  * 82541ER Gigabit Ethernet Controller
  38  * 82541GI Gigabit Ethernet Controller
  39  * 82541PI Gigabit Ethernet Controller
  40  * 82547EI Gigabit Ethernet Controller
  41  * 82547GI Gigabit Ethernet Controller
  42  */
  43
  44 #include "e1000_api.h"
  45
  46 static s32  e1000_init_phy_params_82541(struct e1000_hw *hw);
  47 static s32  e1000_init_nvm_params_82541(struct e1000_hw *hw);
  48 static s32  e1000_init_mac_params_82541(struct e1000_hw *hw);
  49 static s32  e1000_reset_hw_82541(struct e1000_hw *hw);
  50 static s32  e1000_init_hw_82541(struct e1000_hw *hw);
  51 static s32  e1000_get_link_up_info_82541(struct e1000_hw *hw, u16 *speed,
  52                                          u16 *duplex);
  53 static s32  e1000_phy_hw_reset_82541(struct e1000_hw *hw);
  54 static s32  e1000_setup_copper_link_82541(struct e1000_hw *hw);
  55 static s32  e1000_check_for_link_82541(struct e1000_hw *hw);
  56 static s32  e1000_get_cable_length_igp_82541(struct e1000_hw *hw);
  57 static s32  e1000_set_d3_lplu_state_82541(struct e1000_hw *hw,
  58                                           bool active);
  59 static s32  e1000_setup_led_82541(struct e1000_hw *hw);
  60 static s32  e1000_cleanup_led_82541(struct e1000_hw *hw);
  61 static void e1000_clear_hw_cntrs_82541(struct e1000_hw *hw);
  62 static s32  e1000_config_dsp_after_link_change_82541(struct e1000_hw *hw,
  63                                                      bool link_up);
  64 static s32  e1000_phy_init_script_82541(struct e1000_hw *hw);
  65 static void e1000_power_down_phy_copper_82541(struct e1000_hw *hw);
  66
  67 static const u16 e1000_igp_cable_length_table[] = {
  68         5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 10, 10, 10, 10, 10,
  69         10, 10, 20, 20, 20, 20, 20, 25, 25, 25, 25, 25, 25, 25, 30, 30, 30, 30,
  70         40, 40, 40, 40, 40, 40, 40, 40, 40, 50, 50, 50, 50, 50, 50, 50, 60, 60,
  71         60, 60, 60, 60, 60, 60, 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80,
  72         80, 90, 90, 90, 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100,
  73         100, 100, 100, 100, 100, 100, 100, 100, 110, 110, 110, 110, 110, 110,
  74         110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 120, 120,
  75         120, 120, 120, 120, 120, 120, 120, 120};
  76 #define IGP01E1000_AGC_LENGTH_TABLE_SIZE \
  77                 (sizeof(e1000_igp_cable_length_table) / \
  78                  sizeof(e1000_igp_cable_length_table[0]))
  79
  80 /**
  81  *  e1000_init_phy_params_82541 - Init PHY func ptrs.
  82  *  @hw: pointer to the HW structure
  83  **/
  84 static s32 e1000_init_phy_params_82541(struct e1000_hw *hw)
  85 {
  86         struct e1000_phy_info *phy = &hw->phy;
  87         s32 ret_val;
  88
  89         DEBUGFUNC("e1000_init_phy_params_82541");
  90
  91         phy->addr               = 1;
  92         phy->autoneg_mask       = AUTONEG_ADVERTISE_SPEED_DEFAULT;
  93         phy->reset_delay_us     = 10000;
  94         phy->type               = e1000_phy_igp;
  95
  96         /* Function Pointers */
  97         phy->ops.check_polarity = e1000_check_polarity_igp;
  98         phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
  99         phy->ops.get_cable_length = e1000_get_cable_length_igp_82541;
 100         phy->ops.get_cfg_done   = e1000_get_cfg_done_generic;
 101         phy->ops.get_info       = e1000_get_phy_info_igp;
 102         phy->ops.read_reg       = e1000_read_phy_reg_igp;
 103         phy->ops.reset          = e1000_phy_hw_reset_82541;
 104         phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82541;
 105         phy->ops.write_reg      = e1000_write_phy_reg_igp;
 106         phy->ops.power_up       = e1000_power_up_phy_copper;
 107         phy->ops.power_down     = e1000_power_down_phy_copper_82541;
 108
 109         ret_val = e1000_get_phy_id(hw);
 110         if (ret_val)
 111                 goto out;
 112
 113         /* Verify phy id */
 114         if (phy->id != IGP01E1000_I_PHY_ID) {
 115                 ret_val = -E1000_ERR_PHY;
 116                 goto out;
 117         }
 118
 119 out:
 120         return ret_val;
 121 }
 122
 123 /**
 124  *  e1000_init_nvm_params_82541 - Init NVM func ptrs.
 125  *  @hw: pointer to the HW structure
 126  **/
 127 static s32 e1000_init_nvm_params_82541(struct e1000_hw *hw)
 128 {
 129         struct e1000_nvm_info *nvm = &hw->nvm;
 130         s32 ret_val = E1000_SUCCESS;
 131         u32 eecd = E1000_READ_REG(hw, E1000_EECD);
 132         u16 size;
 133
 134         DEBUGFUNC("e1000_init_nvm_params_82541");
 135
 136         switch (nvm->override) {
 137         case e1000_nvm_override_spi_large:
 138                 nvm->type = e1000_nvm_eeprom_spi;
 139                 eecd |= E1000_EECD_ADDR_BITS;
 140                 break;
 141         case e1000_nvm_override_spi_small:
 142                 nvm->type = e1000_nvm_eeprom_spi;
 143                 eecd &= ~E1000_EECD_ADDR_BITS;
 144                 break;
 145         case e1000_nvm_override_microwire_large:
 146                 nvm->type = e1000_nvm_eeprom_microwire;
 147                 eecd |= E1000_EECD_SIZE;
 148                 break;
 149         case e1000_nvm_override_microwire_small:
 150                 nvm->type = e1000_nvm_eeprom_microwire;
 151                 eecd &= ~E1000_EECD_SIZE;
 152                 break;
 153         default:
 154                 nvm->type = eecd & E1000_EECD_TYPE ? e1000_nvm_eeprom_spi
 155                             : e1000_nvm_eeprom_microwire;
 156                 break;
 157         }
 158
 159         if (nvm->type == e1000_nvm_eeprom_spi) {
 160                 nvm->address_bits = (eecd & E1000_EECD_ADDR_BITS) ? 16 : 8;
 161                 nvm->delay_usec = 1;
 162                 nvm->opcode_bits = 8;
 163                 nvm->page_size = (eecd & E1000_EECD_ADDR_BITS) ? 32 : 8;
 164
 165                 /* Function Pointers */
 166                 nvm->ops.acquire        = e1000_acquire_nvm_generic;
 167                 nvm->ops.read           = e1000_read_nvm_spi;
 168                 nvm->ops.release        = e1000_release_nvm_generic;
 169                 nvm->ops.update         = e1000_update_nvm_checksum_generic;
 170                 nvm->ops.valid_led_default = e1000_valid_led_default_generic;
 171                 nvm->ops.validate       = e1000_validate_nvm_checksum_generic;
 172                 nvm->ops.write          = e1000_write_nvm_spi;
 173
 174                 /*
 175                  * nvm->word_size must be discovered after the pointers
 176                  * are set so we can verify the size from the nvm image
 177                  * itself.  Temporarily set it to a dummy value so the
 178                  * read will work.
 179                  */
 180                 nvm->word_size = 64;
 181                 ret_val = nvm->ops.read(hw, NVM_CFG, 1, &size);
 182                 if (ret_val)
 183                         goto out;
 184                 size = (size & NVM_SIZE_MASK) >> NVM_SIZE_SHIFT;
 185                 /*
 186                  * if size != 0, it can be added to a constant and become
 187                  * the left-shift value to set the word_size.  Otherwise,
 188                  * word_size stays at 64.
 189                  */
 190                 if (size) {
 191                         size += NVM_WORD_SIZE_BASE_SHIFT_82541;
 192                         nvm->word_size = 1 << size;
 193                 }
 194         } else {
 195                 nvm->address_bits = (eecd & E1000_EECD_ADDR_BITS) ? 8 : 6;
 196                 nvm->delay_usec = 50;
 197                 nvm->opcode_bits = 3;
 198                 nvm->word_size = (eecd & E1000_EECD_ADDR_BITS) ? 256 : 64;
 199
 200                 /* Function Pointers */
 201                 nvm->ops.acquire        = e1000_acquire_nvm_generic;
 202                 nvm->ops.read           = e1000_read_nvm_microwire;
 203                 nvm->ops.release        = e1000_release_nvm_generic;
 204                 nvm->ops.update         = e1000_update_nvm_checksum_generic;
 205                 nvm->ops.valid_led_default = e1000_valid_led_default_generic;
 206                 nvm->ops.validate       = e1000_validate_nvm_checksum_generic;
 207                 nvm->ops.write          = e1000_write_nvm_microwire;
 208         }
 209
 210 out:
 211         return ret_val;
 212 }
 213
 214 /**
 215  *  e1000_init_mac_params_82541 - Init MAC func ptrs.
 216  *  @hw: pointer to the HW structure
 217  **/
 218 static s32 e1000_init_mac_params_82541(struct e1000_hw *hw)
 219 {
 220         struct e1000_mac_info *mac = &hw->mac;
 221
 222         DEBUGFUNC("e1000_init_mac_params_82541");
 223
 224         /* Set media type */
 225         hw->phy.media_type = e1000_media_type_copper;
 226         /* Set mta register count */
 227         mac->mta_reg_count = 128;
 228         /* Set rar entry count */
 229         mac->rar_entry_count = E1000_RAR_ENTRIES;
 230         /* Set if part includes ASF firmware */
 231         mac->asf_firmware_present = TRUE;
 232
 233         /* Function Pointers */
 234
 235         /* bus type/speed/width */
 236         mac->ops.get_bus_info = e1000_get_bus_info_pci_generic;
 237         /* function id */
 238         mac->ops.set_lan_id = e1000_set_lan_id_single_port;
 239         /* reset */
 240         mac->ops.reset_hw = e1000_reset_hw_82541;
 241         /* hw initialization */
 242         mac->ops.init_hw = e1000_init_hw_82541;
 243         /* link setup */
 244         mac->ops.setup_link = e1000_setup_link_generic;
 245         /* physical interface link setup */
 246         mac->ops.setup_physical_interface = e1000_setup_copper_link_82541;
 247         /* check for link */
 248         mac->ops.check_for_link = e1000_check_for_link_82541;
 249         /* link info */
 250         mac->ops.get_link_up_info = e1000_get_link_up_info_82541;
 251         /* multicast address update */
 252         mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
 253         /* writing VFTA */
 254         mac->ops.write_vfta = e1000_write_vfta_generic;
 255         /* clearing VFTA */
 256         mac->ops.clear_vfta = e1000_clear_vfta_generic;
 257         /* ID LED init */
 258         mac->ops.id_led_init = e1000_id_led_init_generic;
 259         /* setup LED */
 260         mac->ops.setup_led = e1000_setup_led_82541;
 261         /* cleanup LED */
 262         mac->ops.cleanup_led = e1000_cleanup_led_82541;
 263         /* turn on/off LED */
 264         mac->ops.led_on = e1000_led_on_generic;
 265         mac->ops.led_off = e1000_led_off_generic;
 266         /* clear hardware counters */
 267         mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82541;
 268
 269         return E1000_SUCCESS;
 270 }
 271
 272 /**
 273  *  e1000_init_function_pointers_82541 - Init func ptrs.
 274  *  @hw: pointer to the HW structure
 275  *
 276  *  Called to initialize all function pointers and parameters.
 277  **/
 278 void e1000_init_function_pointers_82541(struct e1000_hw *hw)
 279 {
 280         DEBUGFUNC("e1000_init_function_pointers_82541");
 281
 282         hw->mac.ops.init_params = e1000_init_mac_params_82541;
 283         hw->nvm.ops.init_params = e1000_init_nvm_params_82541;
 284         hw->phy.ops.init_params = e1000_init_phy_params_82541;
 285 }
 286
 287 /**
 288  *  e1000_reset_hw_82541 - Reset hardware
 289  *  @hw: pointer to the HW structure
 290  *
 291  *  This resets the hardware into a known state.
 292  **/
 293 static s32 e1000_reset_hw_82541(struct e1000_hw *hw)
 294 {
 295         u32 ledctl, ctrl, manc;
 296
 297         DEBUGFUNC("e1000_reset_hw_82541");
 298
 299         DEBUGOUT("Masking off all interrupts\n");
 300         E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF);
 301
 302         E1000_WRITE_REG(hw, E1000_RCTL, 0);
 303         E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
 304         E1000_WRITE_FLUSH(hw);
 305
 306         /*
 307          * Delay to allow any outstanding PCI transactions to complete
 308          * before resetting the device.
 309          */
 310         msec_delay(10);
 311
 312         ctrl = E1000_READ_REG(hw, E1000_CTRL);
 313
 314         /* Must reset the Phy before resetting the MAC */
 315         if ((hw->mac.type == e1000_82541) || (hw->mac.type == e1000_82547)) {
 316                 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_PHY_RST));
 317                 E1000_WRITE_FLUSH(hw);
 318                 msec_delay(5);
 319         }
 320
 321         DEBUGOUT("Issuing a global reset to 82541/82547 MAC\n");
 322         switch (hw->mac.type) {
 323         case e1000_82541:
 324         case e1000_82541_rev_2:
 325                 /*
 326                  * These controllers can't ack the 64-bit write when
 327                  * issuing the reset, so we use IO-mapping as a
 328                  * workaround to issue the reset.
 329                  */
 330                 E1000_WRITE_REG_IO(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
 331                 break;
 332         default:
 333                 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
 334                 break;
 335         }
 336
 337         /* Wait for NVM reload */
 338         msec_delay(20);
 339
 340         /* Disable HW ARPs on ASF enabled adapters */
 341         manc = E1000_READ_REG(hw, E1000_MANC);
 342         manc &= ~E1000_MANC_ARP_EN;
 343         E1000_WRITE_REG(hw, E1000_MANC, manc);
 344
 345         if ((hw->mac.type == e1000_82541) || (hw->mac.type == e1000_82547)) {
 346                 e1000_phy_init_script_82541(hw);
 347
 348                 /* Configure activity LED after Phy reset */
 349                 ledctl = E1000_READ_REG(hw, E1000_LEDCTL);
 350                 ledctl &= IGP_ACTIVITY_LED_MASK;
 351                 ledctl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
 352                 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl);
 353         }
 354
 355         /* Once again, mask the interrupts */
 356         DEBUGOUT("Masking off all interrupts\n");
 357         E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF);
 358
 359         /* Clear any pending interrupt events. */
 360         E1000_READ_REG(hw, E1000_ICR);
 361
 362         return E1000_SUCCESS;
 363 }
 364
 365 /**
 366  *  e1000_init_hw_82541 - Initialize hardware
 367  *  @hw: pointer to the HW structure
 368  *
 369  *  This inits the hardware readying it for operation.
 370  **/
 371 static s32 e1000_init_hw_82541(struct e1000_hw *hw)
 372 {
 373         struct e1000_mac_info *mac = &hw->mac;
 374         struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;
 375         u32 i, txdctl;
 376         s32 ret_val;
 377
 378         DEBUGFUNC("e1000_init_hw_82541");
 379
 380         /* Initialize identification LED */
 381         ret_val = mac->ops.id_led_init(hw);
 382         if (ret_val) {
 383                 DEBUGOUT("Error initializing identification LED\n");
 384                 /* This is not fatal and we should not stop init due to this */
 385         }
 386
 387         /* Storing the Speed Power Down  value for later use */
 388         ret_val = hw->phy.ops.read_reg(hw, IGP01E1000_GMII_FIFO,
 389                                        &dev_spec->spd_default);
 390         if (ret_val)
 391                 goto out;
 392
 393         /* Disabling VLAN filtering */
 394         DEBUGOUT("Initializing the IEEE VLAN\n");
 395         mac->ops.clear_vfta(hw);
 396
 397         /* Setup the receive address. */
 398         e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
 399
 400         /* Zero out the Multicast HASH table */
 401         DEBUGOUT("Zeroing the MTA\n");
 402         for (i = 0; i < mac->mta_reg_count; i++) {
 403                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
 404                 /*
 405                  * Avoid back to back register writes by adding the register
 406                  * read (flush).  This is to protect against some strange
 407                  * bridge configurations that may issue Memory Write Block
 408                  * (MWB) to our register space.
 409                  */
 410                 E1000_WRITE_FLUSH(hw);
 411         }
 412
 413         /* Setup link and flow control */
 414         ret_val = mac->ops.setup_link(hw);
 415
 416         txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0));
 417         txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
 418                   E1000_TXDCTL_FULL_TX_DESC_WB;
 419         E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl);
 420
 421         /*
 422          * Clear all of the statistics registers (clear on read).  It is
 423          * important that we do this after we have tried to establish link
 424          * because the symbol error count will increment wildly if there
 425          * is no link.
 426          */
 427         e1000_clear_hw_cntrs_82541(hw);
 428
 429 out:
 430         return ret_val;
 431 }
 432
 433 /**
 434  * e1000_get_link_up_info_82541 - Report speed and duplex
 435  * @hw: pointer to the HW structure
 436  * @speed: pointer to speed buffer
 437  * @duplex: pointer to duplex buffer
 438  *
 439  * Retrieve the current speed and duplex configuration.
 440  **/
 441 static s32 e1000_get_link_up_info_82541(struct e1000_hw *hw, u16 *speed,
 442                                         u16 *duplex)
 443 {
 444         struct e1000_phy_info *phy = &hw->phy;
 445         s32 ret_val;
 446         u16 data;
 447
 448         DEBUGFUNC("e1000_get_link_up_info_82541");
 449
 450         ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, duplex);
 451         if (ret_val)
 452                 goto out;
 453
 454         if (!phy->speed_downgraded)
 455                 goto out;
 456
 457         /*
 458          * IGP01 PHY may advertise full duplex operation after speed
 459          * downgrade even if it is operating at half duplex.
 460          * Here we set the duplex settings to match the duplex in the
 461          * link partner's capabilities.
 462          */
 463         ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_EXP, &data);
 464         if (ret_val)
 465                 goto out;
 466
 467         if (!(data & NWAY_ER_LP_NWAY_CAPS)) {
 468                 *duplex = HALF_DUPLEX;
 469         } else {
 470                 ret_val = phy->ops.read_reg(hw, PHY_LP_ABILITY, &data);
 471                 if (ret_val)
 472                         goto out;
 473
 474                 if (*speed == SPEED_100) {
 475                         if (!(data & NWAY_LPAR_100TX_FD_CAPS))
 476                                 *duplex = HALF_DUPLEX;
 477                 } else if (*speed == SPEED_10) {
 478                         if (!(data & NWAY_LPAR_10T_FD_CAPS))
 479                                 *duplex = HALF_DUPLEX;
 480                 }
 481         }
 482
 483 out:
 484         return ret_val;
 485 }
 486
 487 /**
 488  *  e1000_phy_hw_reset_82541 - PHY hardware reset
 489  *  @hw: pointer to the HW structure
 490  *
 491  *  Verify the reset block is not blocking us from resetting.  Acquire
 492  *  semaphore (if necessary) and read/set/write the device control reset
 493  *  bit in the PHY.  Wait the appropriate delay time for the device to
 494  *  reset and release the semaphore (if necessary).
 495  **/
 496 static s32 e1000_phy_hw_reset_82541(struct e1000_hw *hw)
 497 {
 498         s32 ret_val;
 499         u32 ledctl;
 500
 501         DEBUGFUNC("e1000_phy_hw_reset_82541");
 502
 503         ret_val = e1000_phy_hw_reset_generic(hw);
 504         if (ret_val)
 505                 goto out;
 506
 507         e1000_phy_init_script_82541(hw);
 508
 509         if ((hw->mac.type == e1000_82541) || (hw->mac.type == e1000_82547)) {
 510                 /* Configure activity LED after PHY reset */
 511                 ledctl = E1000_READ_REG(hw, E1000_LEDCTL);
 512                 ledctl &= IGP_ACTIVITY_LED_MASK;
 513                 ledctl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
 514                 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl);
 515         }
 516
 517 out:
 518         return ret_val;
 519 }
 520
 521 /**
 522  *  e1000_setup_copper_link_82541 - Configure copper link settings
 523  *  @hw: pointer to the HW structure
 524  *
 525  *  Calls the appropriate function to configure the link for auto-neg or forced
 526  *  speed and duplex.  Then we check for link, once link is established calls
 527  *  to configure collision distance and flow control are called.  If link is
 528  *  not established, we return -E1000_ERR_PHY (-2).
 529  **/
 530 static s32 e1000_setup_copper_link_82541(struct e1000_hw *hw)
 531 {
 532         struct e1000_phy_info *phy = &hw->phy;
 533         struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;
 534         s32  ret_val;
 535         u32 ctrl, ledctl;
 536
 537         DEBUGFUNC("e1000_setup_copper_link_82541");
 538
 539         ctrl = E1000_READ_REG(hw, E1000_CTRL);
 540         ctrl |= E1000_CTRL_SLU;
 541         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
 542         E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
 543
 544
 545         /* Earlier revs of the IGP phy require us to force MDI. */
 546         if (hw->mac.type == e1000_82541 || hw->mac.type == e1000_82547) {
 547                 dev_spec->dsp_config = e1000_dsp_config_disabled;
 548                 phy->mdix = 1;
 549         } else {
 550                 dev_spec->dsp_config = e1000_dsp_config_enabled;
 551         }
 552
 553         ret_val = e1000_copper_link_setup_igp(hw);
 554         if (ret_val)
 555                 goto out;
 556
 557         if (hw->mac.autoneg) {
 558                 if (dev_spec->ffe_config == e1000_ffe_config_active)
 559                         dev_spec->ffe_config = e1000_ffe_config_enabled;
 560         }
 561
 562         /* Configure activity LED after Phy reset */
 563         ledctl = E1000_READ_REG(hw, E1000_LEDCTL);
 564         ledctl &= IGP_ACTIVITY_LED_MASK;
 565         ledctl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
 566         E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl);
 567
 568         ret_val = e1000_setup_copper_link_generic(hw);
 569
 570 out:
 571         return ret_val;
 572 }
 573
 574 /**
 575  *  e1000_check_for_link_82541 - Check/Store link connection
 576  *  @hw: pointer to the HW structure
 577  *
 578  *  This checks the link condition of the adapter and stores the
 579  *  results in the hw->mac structure.
 580  **/
 581 static s32 e1000_check_for_link_82541(struct e1000_hw *hw)
 582 {
 583         struct e1000_mac_info *mac = &hw->mac;
 584         s32 ret_val;
 585         bool link;
 586
 587         DEBUGFUNC("e1000_check_for_link_82541");
 588
 589         /*
 590          * We only want to go out to the PHY registers to see if Auto-Neg
 591          * has completed and/or if our link status has changed.  The
 592          * get_link_status flag is set upon receiving a Link Status
 593          * Change or Rx Sequence Error interrupt.
 594          */
 595         if (!mac->get_link_status) {
 596                 ret_val = E1000_SUCCESS;
 597                 goto out;
 598         }
 599
 600         /*
 601          * First we want to see if the MII Status Register reports
 602          * link.  If so, then we want to get the current speed/duplex
 603          * of the PHY.
 604          */
 605         ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
 606         if (ret_val)
 607                 goto out;
 608
 609         if (!link) {
 610                 ret_val = e1000_config_dsp_after_link_change_82541(hw, FALSE);
 611                 goto out; /* No link detected */
 612         }
 613
 614         mac->get_link_status = FALSE;
 615
 616         /*
 617          * Check if there was DownShift, must be checked
 618          * immediately after link-up
 619          */
 620         e1000_check_downshift_generic(hw);
 621
 622         /*
 623          * If we are forcing speed/duplex, then we simply return since
 624          * we have already determined whether we have link or not.
 625          */
 626         if (!mac->autoneg) {
 627                 ret_val = -E1000_ERR_CONFIG;
 628                 goto out;
 629         }
 630
 631         ret_val = e1000_config_dsp_after_link_change_82541(hw, TRUE);
 632
 633         /*
 634          * Auto-Neg is enabled.  Auto Speed Detection takes care
 635          * of MAC speed/duplex configuration.  So we only need to
 636          * configure Collision Distance in the MAC.
 637          */
 638         mac->ops.config_collision_dist(hw);
 639
 640         /*
 641          * Configure Flow Control now that Auto-Neg has completed.
 642          * First, we need to restore the desired flow control
 643          * settings because we may have had to re-autoneg with a
 644          * different link partner.
 645          */
 646         ret_val = e1000_config_fc_after_link_up_generic(hw);
 647         if (ret_val)
 648                 DEBUGOUT("Error configuring flow control\n");
 649
 650 out:
 651         return ret_val;
 652 }
 653
 654 /**
 655  *  e1000_config_dsp_after_link_change_82541 - Config DSP after link
 656  *  @hw: pointer to the HW structure
 657  *  @link_up: boolean flag for link up status
 658  *
 659  *  Return E1000_ERR_PHY when failing to read/write the PHY, else E1000_SUCCESS
 660  *  at any other case.
 661  *
 662  *  82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a
 663  *  gigabit link is achieved to improve link quality.
 664  **/
 665 static s32 e1000_config_dsp_after_link_change_82541(struct e1000_hw *hw,
 666                                                     bool link_up)
 667 {
 668         struct e1000_phy_info *phy = &hw->phy;
 669         struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;
 670         s32 ret_val;
 671         u32 idle_errs = 0;
 672         u16 phy_data, phy_saved_data, speed, duplex, i;
 673         u16 ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20;
 674         u16 dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = {
 675                                                 IGP01E1000_PHY_AGC_PARAM_A,
 676                                                 IGP01E1000_PHY_AGC_PARAM_B,
 677                                                 IGP01E1000_PHY_AGC_PARAM_C,
 678                                                 IGP01E1000_PHY_AGC_PARAM_D};
 679
 680         DEBUGFUNC("e1000_config_dsp_after_link_change_82541");
 681
 682         if (link_up) {
 683                 ret_val = hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
 684                 if (ret_val) {
 685                         DEBUGOUT("Error getting link speed and duplex\n");
 686                         goto out;
 687                 }
 688
 689                 if (speed != SPEED_1000) {
 690                         ret_val = E1000_SUCCESS;
 691                         goto out;
 692                 }
 693
 694                 ret_val = phy->ops.get_cable_length(hw);
 695                 if (ret_val)
 696                         goto out;
 697
 698                 if ((dev_spec->dsp_config == e1000_dsp_config_enabled) &&
 699                     phy->min_cable_length >= 50) {
 700
 701                         for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
 702                                 ret_val = phy->ops.read_reg(hw,
 703                                                             dsp_reg_array[i],
 704                                                             &phy_data);
 705                                 if (ret_val)
 706                                         goto out;
 707
 708                                 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
 709
 710                                 ret_val = phy->ops.write_reg(hw,
 711                                                              dsp_reg_array[i],
 712                                                              phy_data);
 713                                 if (ret_val)
 714                                         goto out;
 715                         }
 716                         dev_spec->dsp_config = e1000_dsp_config_activated;
 717                 }
 718
 719                 if ((dev_spec->ffe_config != e1000_ffe_config_enabled) ||
 720                     (phy->min_cable_length >= 50)) {
 721                         ret_val = E1000_SUCCESS;
 722                         goto out;
 723                 }
 724
 725                 /* clear previous idle error counts */
 726                 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data);
 727                 if (ret_val)
 728                         goto out;
 729
 730                 for (i = 0; i < ffe_idle_err_timeout; i++) {
 731                         usec_delay(1000);
 732                         ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS,
 733                                                     &phy_data);
 734                         if (ret_val)
 735                                 goto out;
 736
 737                         idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT);
 738                         if (idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) {
 739                                 dev_spec->ffe_config = e1000_ffe_config_active;
 740
 741                                 ret_val = phy->ops.write_reg(hw,
 742                                                   IGP01E1000_PHY_DSP_FFE,
 743                                                   IGP01E1000_PHY_DSP_FFE_CM_CP);
 744                                 if (ret_val)
 745                                         goto out;
 746                                 break;
 747                         }
 748
 749                         if (idle_errs)
 750                                 ffe_idle_err_timeout =
 751                                                  FFE_IDLE_ERR_COUNT_TIMEOUT_100;
 752                 }
 753         } else {
 754                 if (dev_spec->dsp_config == e1000_dsp_config_activated) {
 755                         /*
 756                          * Save off the current value of register 0x2F5B
 757                          * to be restored at the end of the routines.
 758                          */
 759                         ret_val = phy->ops.read_reg(hw, 0x2F5B,
 760                                                     &phy_saved_data);
 761                         if (ret_val)
 762                                 goto out;
 763
 764                         /* Disable the PHY transmitter */
 765                         ret_val = phy->ops.write_reg(hw, 0x2F5B, 0x0003);
 766                         if (ret_val)
 767                                 goto out;
 768
 769                         msec_delay_irq(20);
 770
 771                         ret_val = phy->ops.write_reg(hw, 0x0000,
 772                                                      IGP01E1000_IEEE_FORCE_GIG);
 773                         if (ret_val)
 774                                 goto out;
 775                         for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
 776                                 ret_val = phy->ops.read_reg(hw,
 777                                                             dsp_reg_array[i],
 778                                                             &phy_data);
 779                                 if (ret_val)
 780                                         goto out;
 781
 782                                 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
 783                                 phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS;
 784
 785                                 ret_val = phy->ops.write_reg(hw,
 786                                                              dsp_reg_array[i],
 787                                                              phy_data);
 788                                 if (ret_val)
 789                                         goto out;
 790                         }
 791
 792                         ret_val = phy->ops.write_reg(hw, 0x0000,
 793                                                IGP01E1000_IEEE_RESTART_AUTONEG);
 794                         if (ret_val)
 795                                 goto out;
 796
 797                         msec_delay_irq(20);
 798
 799                         /* Now enable the transmitter */
 800                         ret_val = phy->ops.write_reg(hw, 0x2F5B,
 801                                                      phy_saved_data);
 802                         if (ret_val)
 803                                 goto out;
 804
 805                         dev_spec->dsp_config = e1000_dsp_config_enabled;
 806                 }
 807
 808                 if (dev_spec->ffe_config != e1000_ffe_config_active) {
 809                         ret_val = E1000_SUCCESS;
 810                         goto out;
 811                 }
 812
 813                 /*
 814                  * Save off the current value of register 0x2F5B
 815                  * to be restored at the end of the routines.
 816                  */
 817                 ret_val = phy->ops.read_reg(hw, 0x2F5B, &phy_saved_data);
 818                 if (ret_val)
 819                         goto out;
 820
 821                 /* Disable the PHY transmitter */
 822                 ret_val = phy->ops.write_reg(hw, 0x2F5B, 0x0003);
 823                 if (ret_val)
 824                         goto out;
 825
 826                 msec_delay_irq(20);
 827
 828                 ret_val = phy->ops.write_reg(hw, 0x0000,
 829                                              IGP01E1000_IEEE_FORCE_GIG);
 830                 if (ret_val)
 831                         goto out;
 832
 833                 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_DSP_FFE,
 834                                              IGP01E1000_PHY_DSP_FFE_DEFAULT);
 835                 if (ret_val)
 836                         goto out;
 837
 838                 ret_val = phy->ops.write_reg(hw, 0x0000,
 839                                              IGP01E1000_IEEE_RESTART_AUTONEG);
 840                 if (ret_val)
 841                         goto out;
 842
 843                 msec_delay_irq(20);
 844
 845                 /* Now enable the transmitter */
 846                 ret_val = phy->ops.write_reg(hw, 0x2F5B, phy_saved_data);
 847
 848                 if (ret_val)
 849                         goto out;
 850
 851                 dev_spec->ffe_config = e1000_ffe_config_enabled;
 852         }
 853
 854 out:
 855         return ret_val;
 856 }
 857
 858 /**
 859  *  e1000_get_cable_length_igp_82541 - Determine cable length for igp PHY
 860  *  @hw: pointer to the HW structure
 861  *
 862  *  The automatic gain control (agc) normalizes the amplitude of the
 863  *  received signal, adjusting for the attenuation produced by the
 864  *  cable.  By reading the AGC registers, which represent the
 865  *  combination of coarse and fine gain value, the value can be put
 866  *  into a lookup table to obtain the approximate cable length
 867  *  for each channel.
 868  **/
 869 static s32 e1000_get_cable_length_igp_82541(struct e1000_hw *hw)
 870 {
 871         struct e1000_phy_info *phy = &hw->phy;
 872         s32 ret_val = E1000_SUCCESS;
 873         u16 i, data;
 874         u16 cur_agc_value, agc_value = 0;
 875         u16 min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE;
 876         u16 agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = {IGP01E1000_PHY_AGC_A,
 877                                                          IGP01E1000_PHY_AGC_B,
 878                                                          IGP01E1000_PHY_AGC_C,
 879                                                          IGP01E1000_PHY_AGC_D};
 880
 881         DEBUGFUNC("e1000_get_cable_length_igp_82541");
 882
 883         /* Read the AGC registers for all channels */
 884         for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
 885                 ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &data);
 886                 if (ret_val)
 887                         goto out;
 888
 889                 cur_agc_value = data >> IGP01E1000_AGC_LENGTH_SHIFT;
 890
 891                 /* Bounds checking */
 892                 if ((cur_agc_value >= IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) ||
 893                     (cur_agc_value == 0)) {
 894                         ret_val = -E1000_ERR_PHY;
 895                         goto out;
 896                 }
 897
 898                 agc_value += cur_agc_value;
 899
 900                 if (min_agc_value > cur_agc_value)
 901                         min_agc_value = cur_agc_value;
 902         }
 903
 904         /* Remove the minimal AGC result for length < 50m */
 905         if (agc_value < IGP01E1000_PHY_CHANNEL_NUM * 50) {
 906                 agc_value -= min_agc_value;
 907                 /* Average the three remaining channels for the length. */
 908                 agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1);
 909         } else {
 910                 /* Average the channels for the length. */
 911                 agc_value /= IGP01E1000_PHY_CHANNEL_NUM;
 912         }
 913
 914         phy->min_cable_length = (e1000_igp_cable_length_table[agc_value] >
 915                                  IGP01E1000_AGC_RANGE)
 916                                 ? (e1000_igp_cable_length_table[agc_value] -
 917                                    IGP01E1000_AGC_RANGE)
 918                                 : 0;
 919         phy->max_cable_length = e1000_igp_cable_length_table[agc_value] +
 920                                 IGP01E1000_AGC_RANGE;
 921
 922         phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
 923
 924 out:
 925         return ret_val;
 926 }
 927
 928 /**
 929  *  e1000_set_d3_lplu_state_82541 - Sets low power link up state for D3
 930  *  @hw: pointer to the HW structure
 931  *  @active: boolean used to enable/disable lplu
 932  *
 933  *  Success returns 0, Failure returns 1
 934  *
 935  *  The low power link up (lplu) state is set to the power management level D3
 936  *  and SmartSpeed is disabled when active is TRUE, else clear lplu for D3
 937  *  and enable Smartspeed.  LPLU and Smartspeed are mutually exclusive.  LPLU
 938  *  is used during Dx states where the power conservation is most important.
 939  *  During driver activity, SmartSpeed should be enabled so performance is
 940  *  maintained.
 941  **/
 942 static s32 e1000_set_d3_lplu_state_82541(struct e1000_hw *hw, bool active)
 943 {
 944         struct e1000_phy_info *phy = &hw->phy;
 945         s32 ret_val;
 946         u16 data;
 947
 948         DEBUGFUNC("e1000_set_d3_lplu_state_82541");
 949
 950         switch (hw->mac.type) {
 951         case e1000_82541_rev_2:
 952         case e1000_82547_rev_2:
 953                 break;
 954         default:
 955                 ret_val = e1000_set_d3_lplu_state_generic(hw, active);
 956                 goto out;
 957                 break;
 958         }
 959
 960         ret_val = phy->ops.read_reg(hw, IGP01E1000_GMII_FIFO, &data);
 961         if (ret_val)
 962                 goto out;
 963
 964         if (!active) {
 965                 data &= ~IGP01E1000_GMII_FLEX_SPD;
 966                 ret_val = phy->ops.write_reg(hw, IGP01E1000_GMII_FIFO, data);
 967                 if (ret_val)
 968                         goto out;
 969
 970                 /*
 971                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
 972                  * during Dx states where the power conservation is most
 973                  * important.  During driver activity we should enable
 974                  * SmartSpeed, so performance is maintained.
 975                  */
 976                 if (phy->smart_speed == e1000_smart_speed_on) {
 977                         ret_val = phy->ops.read_reg(hw,
 978                                                     IGP01E1000_PHY_PORT_CONFIG,
 979                                                     &data);
 980                         if (ret_val)
 981                                 goto out;
 982
 983                         data |= IGP01E1000_PSCFR_SMART_SPEED;
 984                         ret_val = phy->ops.write_reg(hw,
 985                                                      IGP01E1000_PHY_PORT_CONFIG,
 986                                                      data);
 987                         if (ret_val)
 988                                 goto out;
 989                 } else if (phy->smart_speed == e1000_smart_speed_off) {
 990                         ret_val = phy->ops.read_reg(hw,
 991                                                     IGP01E1000_PHY_PORT_CONFIG,
 992                                                     &data);
 993                         if (ret_val)
 994                                 goto out;
 995
 996                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 997                         ret_val = phy->ops.write_reg(hw,
 998                                                      IGP01E1000_PHY_PORT_CONFIG,
 999                                                      data);
1000                         if (ret_val)
1001                                 goto out;
1002                 }
1003         } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1004                    (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1005                    (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1006                 data |= IGP01E1000_GMII_FLEX_SPD;
1007                 ret_val = phy->ops.write_reg(hw, IGP01E1000_GMII_FIFO, data);
1008                 if (ret_val)
1009                         goto out;
1010
1011                 /* When LPLU is enabled, we should disable SmartSpeed */
1012                 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1013                                             &data);
1014                 if (ret_val)
1015                         goto out;
1016
1017                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1018                 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1019                                              data);
1020         }
1021
1022 out:
1023         return ret_val;
1024 }
1025
1026 /**
1027  *  e1000_setup_led_82541 - Configures SW controllable LED
1028  *  @hw: pointer to the HW structure
1029  *
1030  *  This prepares the SW controllable LED for use and saves the current state
1031  *  of the LED so it can be later restored.
1032  **/
1033 static s32 e1000_setup_led_82541(struct e1000_hw *hw)
1034 {
1035         struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;
1036         s32 ret_val;
1037
1038         DEBUGFUNC("e1000_setup_led_82541");
1039
1040         ret_val = hw->phy.ops.read_reg(hw, IGP01E1000_GMII_FIFO,
1041                                        &dev_spec->spd_default);
1042         if (ret_val)
1043                 goto out;
1044
1045         ret_val = hw->phy.ops.write_reg(hw, IGP01E1000_GMII_FIFO,
1046                                         (u16)(dev_spec->spd_default &
1047                                         ~IGP01E1000_GMII_SPD));
1048         if (ret_val)
1049                 goto out;
1050
1051         E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
1052
1053 out:
1054         return ret_val;
1055 }
1056
1057 /**
1058  *  e1000_cleanup_led_82541 - Set LED config to default operation
1059  *  @hw: pointer to the HW structure
1060  *
1061  *  Remove the current LED configuration and set the LED configuration
1062  *  to the default value, saved from the EEPROM.
1063  **/
1064 static s32 e1000_cleanup_led_82541(struct e1000_hw *hw)
1065 {
1066         struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;
1067         s32 ret_val;
1068
1069         DEBUGFUNC("e1000_cleanup_led_82541");
1070
1071         ret_val = hw->phy.ops.write_reg(hw, IGP01E1000_GMII_FIFO,
1072                                         dev_spec->spd_default);
1073         if (ret_val)
1074                 goto out;
1075
1076         E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default);
1077
1078 out:
1079         return ret_val;
1080 }
1081
1082 /**
1083  *  e1000_phy_init_script_82541 - Initialize GbE PHY
1084  *  @hw: pointer to the HW structure
1085  *
1086  *  Initializes the IGP PHY.
1087  **/
1088 static s32 e1000_phy_init_script_82541(struct e1000_hw *hw)
1089 {
1090         struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;
1091         u32 ret_val;
1092         u16 phy_saved_data;
1093
1094         DEBUGFUNC("e1000_phy_init_script_82541");
1095
1096         if (!dev_spec->phy_init_script) {
1097                 ret_val = E1000_SUCCESS;
1098                 goto out;
1099         }
1100
1101         /* Delay after phy reset to enable NVM configuration to load */
1102         msec_delay(20);
1103
1104         /*
1105          * Save off the current value of register 0x2F5B to be restored at
1106          * the end of this routine.
1107          */
1108         ret_val = hw->phy.ops.read_reg(hw, 0x2F5B, &phy_saved_data);
1109
1110         /* Disabled the PHY transmitter */
1111         hw->phy.ops.write_reg(hw, 0x2F5B, 0x0003);
1112
1113         msec_delay(20);
1114
1115         hw->phy.ops.write_reg(hw, 0x0000, 0x0140);
1116
1117         msec_delay(5);
1118
1119         switch (hw->mac.type) {
1120         case e1000_82541:
1121         case e1000_82547:
1122                 hw->phy.ops.write_reg(hw, 0x1F95, 0x0001);
1123
1124                 hw->phy.ops.write_reg(hw, 0x1F71, 0xBD21);
1125
1126                 hw->phy.ops.write_reg(hw, 0x1F79, 0x0018);
1127
1128                 hw->phy.ops.write_reg(hw, 0x1F30, 0x1600);
1129
1130                 hw->phy.ops.write_reg(hw, 0x1F31, 0x0014);
1131
1132                 hw->phy.ops.write_reg(hw, 0x1F32, 0x161C);
1133
1134                 hw->phy.ops.write_reg(hw, 0x1F94, 0x0003);
1135
1136                 hw->phy.ops.write_reg(hw, 0x1F96, 0x003F);
1137
1138                 hw->phy.ops.write_reg(hw, 0x2010, 0x0008);
1139                 break;
1140         case e1000_82541_rev_2:
1141         case e1000_82547_rev_2:
1142                 hw->phy.ops.write_reg(hw, 0x1F73, 0x0099);
1143                 break;
1144         default:
1145                 break;
1146         }
1147
1148         hw->phy.ops.write_reg(hw, 0x0000, 0x3300);
1149
1150         msec_delay(20);
1151
1152         /* Now enable the transmitter */
1153         hw->phy.ops.write_reg(hw, 0x2F5B, phy_saved_data);
1154
1155         if (hw->mac.type == e1000_82547) {
1156                 u16 fused, fine, coarse;
1157
1158                 /* Move to analog registers page */
1159                 hw->phy.ops.read_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS,
1160                                      &fused);
1161
1162                 if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
1163                         hw->phy.ops.read_reg(hw, IGP01E1000_ANALOG_FUSE_STATUS,
1164                                              &fused);
1165
1166                         fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
1167                         coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
1168
1169                         if (coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
1170                                 coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10;
1171                                 fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
1172                         } else if (coarse ==
1173                                    IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
1174                                 fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
1175
1176                         fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
1177                                 (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
1178                                 (coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK);
1179
1180                         hw->phy.ops.write_reg(hw,
1181                                               IGP01E1000_ANALOG_FUSE_CONTROL,
1182                                               fused);
1183                         hw->phy.ops.write_reg(hw,
1184                                       IGP01E1000_ANALOG_FUSE_BYPASS,
1185                                       IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
1186                 }
1187         }
1188
1189 out:
1190         return ret_val;
1191 }
1192
1193 /**
1194  *  e1000_init_script_state_82541 - Enable/Disable PHY init script
1195  *  @hw: pointer to the HW structure
1196  *  @state: boolean value used to enable/disable PHY init script
1197  *
1198  *  Allows the driver to enable/disable the PHY init script, if the PHY is an
1199  *  IGP PHY.
1200  **/
1201 void e1000_init_script_state_82541(struct e1000_hw *hw, bool state)
1202 {
1203         struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;
1204
1205         DEBUGFUNC("e1000_init_script_state_82541");
1206
1207         if (hw->phy.type != e1000_phy_igp) {
1208                 DEBUGOUT("Initialization script not necessary.\n");
1209                 goto out;
1210         }
1211
1212         dev_spec->phy_init_script = state;
1213
1214 out:
1215         return;
1216 }
1217
1218 /**
1219  * e1000_power_down_phy_copper_82541 - Remove link in case of PHY power down
1220  * @hw: pointer to the HW structure
1221  *
1222  * In the case of a PHY power down to save power, or to turn off link during a
1223  * driver unload, or wake on lan is not enabled, remove the link.
1224  **/
1225 static void e1000_power_down_phy_copper_82541(struct e1000_hw *hw)
1226 {
1227         /* If the management interface is not enabled, then power down */
1228         if (!(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_SMBUS_EN))
1229                 e1000_power_down_phy_copper(hw);
1230
1231         return;
1232 }
1233
1234 /**
1235  *  e1000_clear_hw_cntrs_82541 - Clear device specific hardware counters
1236  *  @hw: pointer to the HW structure
1237  *
1238  *  Clears the hardware counters by reading the counter registers.
1239  **/
1240 static void e1000_clear_hw_cntrs_82541(struct e1000_hw *hw)
1241 {
1242         DEBUGFUNC("e1000_clear_hw_cntrs_82541");
1243
1244         e1000_clear_hw_cntrs_base_generic(hw);
1245
1246         E1000_READ_REG(hw, E1000_PRC64);
1247         E1000_READ_REG(hw, E1000_PRC127);
1248         E1000_READ_REG(hw, E1000_PRC255);
1249         E1000_READ_REG(hw, E1000_PRC511);
1250         E1000_READ_REG(hw, E1000_PRC1023);
1251         E1000_READ_REG(hw, E1000_PRC1522);
1252         E1000_READ_REG(hw, E1000_PTC64);
1253         E1000_READ_REG(hw, E1000_PTC127);
1254         E1000_READ_REG(hw, E1000_PTC255);
1255         E1000_READ_REG(hw, E1000_PTC511);
1256         E1000_READ_REG(hw, E1000_PTC1023);
1257         E1000_READ_REG(hw, E1000_PTC1522);
1258
1259         E1000_READ_REG(hw, E1000_ALGNERRC);
1260         E1000_READ_REG(hw, E1000_RXERRC);
1261         E1000_READ_REG(hw, E1000_TNCRS);
1262         E1000_READ_REG(hw, E1000_CEXTERR);
1263         E1000_READ_REG(hw, E1000_TSCTC);
1264         E1000_READ_REG(hw, E1000_TSCTFC);
1265
1266         E1000_READ_REG(hw, E1000_MGTPRC);
1267         E1000_READ_REG(hw, E1000_MGTPDC);
1268         E1000_READ_REG(hw, E1000_MGTPTC);
1269 }