2 * Copyright (c) 2000, 2002 M. Warner Losh. All Rights Reserved.
3 * Copyright (c) 1997 Ted Faber All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice immediately at the beginning of the file, without modification,
11 * this list of conditions, and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. Absolutely no warranty of function or purpose is made by the author
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 * $FreeBSD: src/sys/pccard/pcic_pci.c,v 1.54.2.22 2003/02/26 18:42:00 imp Exp $
30 * $DragonFly: src/sys/bus/pccard/Attic/pcic_pci.c,v 1.3 2003/08/07 21:16:46 dillon Exp $
33 #include <sys/param.h>
35 #include <sys/kernel.h>
36 #include <sys/module.h>
37 #include <sys/sysctl.h>
38 #include <sys/systm.h>
40 #include <bus/pci/pcireg.h>
41 #include <bus/pci/pcivar.h>
49 #include <bus/pccard/pccardvar.h>
52 #define PRVERB(x) do { \
53 if (bootverbose) { device_printf x; } \
56 static int pcic_pci_get_memory(device_t dev);
58 SYSCTL_DECL(_hw_pcic);
60 static int pcic_ignore_function_1 = 0;
61 TUNABLE_INT("hw.pcic.ignore_function_1", &pcic_ignore_function_1);
62 SYSCTL_INT(_hw_pcic, OID_AUTO, ignore_function_1, CTLFLAG_RD,
63 &pcic_ignore_function_1, 0,
64 "When set, driver ignores pci function 1 of the bridge. This option\n\
65 is obsolete and will be deleted before FreeBSD 4.8.");
68 * The following should be a hint, so we can do it on a per device
69 * instance, but this is convenient. Do not set this unless pci
70 * routing doesn't work. It is purposely vague and undocumented
71 * at the moment. Sadly, this seems to be needed way too often.
73 static int pcic_intr_path = (int)pcic_iw_pci;
74 TUNABLE_INT("hw.pcic.intr_path", &pcic_intr_path);
75 SYSCTL_INT(_hw_pcic, OID_AUTO, intr_path, CTLFLAG_RD, &pcic_intr_path, 0,
76 "Which path to send the interrupts over. Normally interrupts for\n\
77 cardbus bridges are routed over the PCI bus (2). However, some laptops\n\
78 will hang when using PCI interrupts due to bugs in this code. Those\n\
79 bugs can be worked around by forcings ISA interrupts (1).");
81 static int pcic_init_routing = 0;
82 TUNABLE_INT("hw.pcic.init_routing", &pcic_init_routing);
83 SYSCTL_INT(_hw_pcic, OID_AUTO, init_routing, CTLFLAG_RD,
84 &pcic_init_routing, 0,
85 "Force the interrupt routing to be initialized on those bridges where\n\
86 doing so will cause probelms. This is very rare and generally is not\n\
87 needed. The default of 0 is almost always appropriate. Only set to 1 if\n\
88 instructed to do so for debugging. Only TI bridges are affected by this\n\
89 option, and what the code does is of dubious value. This option is obsolete\n\
90 and will be deleted before FreeBSD 4.8.");
92 static int pcic_ignore_pci = 0;
93 TUNABLE_INT("hw.pcic.ignore_pci", &pcic_ignore_pci);
94 SYSCTL_INT(_hw_pcic, OID_AUTO, ignore_pci, CTLFLAG_RD,
96 "When set, driver ignores pci cardbus bridges it would otherwise claim.\n\
97 Generally speaking, this option is not needed for anything other than as an\n\
100 static int pcic_pd6729_intr_path = (int)pcic_iw_isa;
101 TUNABLE_INT("hw.pcic.pd6729_intr_path", &pcic_pd6729_intr_path);
102 SYSCTL_INT(_hw_pcic, OID_AUTO, pd6729_intr_path, CTLFLAG_RD,
103 &pcic_pd6729_intr_path, 0,
104 "Determine the interrupt path or method for Cirrus Logic PD6729 and\n\
105 similar I/O space based pcmcia bridge. Chips on a PCI expansion card need\n\
106 a value of 2, while chips installed in a laptop need a value of 1 (which is\n\
107 also the default). This is similar to hw.pcic.intr_path, but separate so\n\
108 that it can default to ISA when intr_path defaults to PCI.");
110 static int pcic_ti12xx_enable_pci_clock = 0;
111 TUNABLE_INT("hw.pcic.ti12xx_enable_pci_clock", &pcic_ti12xx_enable_pci_clock);
112 SYSCTL_INT(_hw_pcic, OID_AUTO, ti12xx_enable_pci_clock, CTLFLAG_RD,
113 &pcic_ti12xx_enable_pci_clock, 0,
114 "Some TI-12xx parts need to have the PCI clock enabled. These designs do\n\
115 not provide a clock themselves. Most of the reference boards have the\n\
116 required oscillator parts, so the number of machines that needs this to be\n\
117 set is vanishingly small.");
119 static void pcic_pci_cardbus_init(device_t);
120 static pcic_intr_way_t pcic_pci_gen_func;
121 static pcic_intr_way_t pcic_pci_gen_csc;
122 static pcic_intr_mapirq_t pcic_pci_gen_mapirq;
124 static pcic_intr_way_t pcic_pci_oz67xx_func;
125 static pcic_intr_way_t pcic_pci_oz67xx_csc;
126 static pcic_init_t pcic_pci_oz67xx_init;
128 static pcic_intr_way_t pcic_pci_oz68xx_func;
129 static pcic_intr_way_t pcic_pci_oz68xx_csc;
130 static pcic_init_t pcic_pci_oz68xx_init;
132 static pcic_intr_way_t pcic_pci_pd6729_func;
133 static pcic_intr_way_t pcic_pci_pd6729_csc;
134 static pcic_init_t pcic_pci_pd6729_init;
136 static pcic_intr_way_t pcic_pci_pd68xx_func;
137 static pcic_intr_way_t pcic_pci_pd68xx_csc;
138 static pcic_init_t pcic_pci_pd68xx_init;
140 static pcic_intr_way_t pcic_pci_ricoh_func;
141 static pcic_intr_way_t pcic_pci_ricoh_csc;
142 static pcic_init_t pcic_pci_ricoh_init;
144 static pcic_intr_way_t pcic_pci_ti113x_func;
145 static pcic_intr_way_t pcic_pci_ti113x_csc;
146 static pcic_init_t pcic_pci_ti_init;
148 static pcic_intr_way_t pcic_pci_ti12xx_func;
149 static pcic_intr_way_t pcic_pci_ti12xx_csc;
151 static pcic_intr_way_t pcic_pci_topic_func;
152 static pcic_intr_way_t pcic_pci_topic_csc;
153 static pcic_init_t pcic_pci_topic_init;
155 static struct pcic_chip pcic_pci_oz67xx_chip = {
156 pcic_pci_oz67xx_func,
162 static struct pcic_chip pcic_pci_oz68xx_chip = {
163 pcic_pci_oz68xx_func,
169 static struct pcic_chip pcic_pci_pd6729_chip = {
170 pcic_pci_pd6729_func,
176 static struct pcic_chip pcic_pci_pd68xx_chip = {
177 pcic_pci_pd68xx_func,
183 static struct pcic_chip pcic_pci_ricoh_chip = {
190 static struct pcic_chip pcic_pci_ti113x_chip = {
191 pcic_pci_ti113x_func,
197 static struct pcic_chip pcic_pci_ti12xx_chip = {
198 pcic_pci_ti12xx_func,
204 static struct pcic_chip pcic_pci_topic_chip = {
211 static struct pcic_chip pcic_pci_generic_chip = {
215 pcic_pci_cardbus_init
218 /* Chipset specific flags */
219 #define TI_NO_MFUNC 0x10000
221 struct pcic_pci_table
227 struct pcic_chip *chip;
228 } pcic_pci_devs[] = {
229 { PCIC_ID_OMEGA_82C094, "Omega 82C094G",
230 PCIC_I82365, PCIC_DF_POWER, &pcic_pci_pd6729_chip },
231 { PCIC_ID_CLPD6729, "Cirrus Logic PD6729/6730 PCI-PCMCIA Bridge",
232 PCIC_PD6729, PCIC_PD_POWER, &pcic_pci_pd6729_chip },
233 { PCIC_ID_CLPD6832, "Cirrus Logic PD6832 PCI-CardBus Bridge",
234 PCIC_PD673X, PCIC_CARDBUS_POWER, &pcic_pci_pd68xx_chip },
235 { PCIC_ID_CLPD6833, "Cirrus Logic PD6833 PCI-CardBus Bridge",
236 PCIC_PD673X, PCIC_CARDBUS_POWER, &pcic_pci_pd68xx_chip },
237 { PCIC_ID_CLPD6834, "Cirrus Logic PD6834 PCI-CardBus Bridge",
238 PCIC_PD673X, PCIC_CARDBUS_POWER, &pcic_pci_pd68xx_chip },
239 { PCIC_ID_OZ6729, "O2micro OZ6729 PC-Card Bridge",
240 PCIC_I82365, PCIC_AB_POWER, &pcic_pci_oz67xx_chip },
241 { PCIC_ID_OZ6730, "O2micro OZ6730 PC-Card Bridge",
242 PCIC_I82365, PCIC_AB_POWER, &pcic_pci_oz67xx_chip },
243 { PCIC_ID_OZ6832, "O2micro 6832/6833 PCI-Cardbus Bridge",
244 PCIC_I82365, PCIC_CARDBUS_POWER, &pcic_pci_oz68xx_chip },
245 { PCIC_ID_OZ6860, "O2micro 6836/6860 PCI-Cardbus Bridge",
246 PCIC_I82365, PCIC_CARDBUS_POWER, &pcic_pci_oz68xx_chip },
247 { PCIC_ID_OZ6872, "O2micro 6812/6872 PCI-Cardbus Bridge",
248 PCIC_I82365, PCIC_CARDBUS_POWER, &pcic_pci_oz68xx_chip },
249 { PCIC_ID_OZ6912, "O2micro 6912 PCI-Cardbus Bridge",
250 PCIC_I82365, PCIC_CARDBUS_POWER, &pcic_pci_oz68xx_chip },
251 { PCIC_ID_OZ6922, "O2micro 6922 PCI-Cardbus Bridge",
252 PCIC_I82365, PCIC_AB_POWER, &pcic_pci_oz68xx_chip },
253 { PCIC_ID_OZ6933, "O2micro 6933 PCI-Cardbus Bridge",
254 PCIC_I82365, PCIC_AB_POWER, &pcic_pci_oz68xx_chip },
255 { PCIC_ID_RICOH_RL5C465, "Ricoh RL5C465 PCI-CardBus Bridge",
256 PCIC_RF5C296, PCIC_CARDBUS_POWER, &pcic_pci_ricoh_chip },
257 { PCIC_ID_RICOH_RL5C475, "Ricoh RL5C475 PCI-CardBus Bridge",
258 PCIC_RF5C296, PCIC_CARDBUS_POWER, &pcic_pci_ricoh_chip },
259 { PCIC_ID_RICOH_RL5C476, "Ricoh RL5C476 PCI-CardBus Bridge",
260 PCIC_RF5C296, PCIC_CARDBUS_POWER, &pcic_pci_ricoh_chip },
261 { PCIC_ID_RICOH_RL5C477, "Ricoh RL5C477 PCI-CardBus Bridge",
262 PCIC_RF5C296, PCIC_CARDBUS_POWER, &pcic_pci_ricoh_chip },
263 { PCIC_ID_RICOH_RL5C478, "Ricoh RL5C478 PCI-CardBus Bridge",
264 PCIC_RF5C296, PCIC_CARDBUS_POWER, &pcic_pci_ricoh_chip },
265 { PCIC_ID_SMC_34C90, "SMC 34C90 PCI-CardBus Bridge",
266 PCIC_RF5C296, PCIC_CARDBUS_POWER, &pcic_pci_generic_chip },
267 { PCIC_ID_TI1031, "TI PCI-1031 PCI-PCMCIA Bridge",
268 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti113x_chip },
269 { PCIC_ID_TI1130, "TI PCI-1130 PCI-CardBus Bridge",
270 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti113x_chip },
271 { PCIC_ID_TI1131, "TI PCI-1131 PCI-CardBus Bridge",
272 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti113x_chip },
273 { PCIC_ID_TI1210, "TI PCI-1210 PCI-CardBus Bridge",
274 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
275 { PCIC_ID_TI1211, "TI PCI-1211 PCI-CardBus Bridge",
276 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
277 { PCIC_ID_TI1220, "TI PCI-1220 PCI-CardBus Bridge",
278 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
279 { PCIC_ID_TI1221, "TI PCI-1221 PCI-CardBus Bridge",
280 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
281 { PCIC_ID_TI1225, "TI PCI-1225 PCI-CardBus Bridge",
282 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
283 { PCIC_ID_TI1250, "TI PCI-1250 PCI-CardBus Bridge",
284 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER | TI_NO_MFUNC,
285 &pcic_pci_ti12xx_chip },
286 { PCIC_ID_TI1251, "TI PCI-1251 PCI-CardBus Bridge",
287 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER | TI_NO_MFUNC,
288 &pcic_pci_ti12xx_chip },
289 { PCIC_ID_TI1251B, "TI PCI-1251B PCI-CardBus Bridge",
290 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER | TI_NO_MFUNC,
291 &pcic_pci_ti12xx_chip },
292 { PCIC_ID_TI1260, "TI PCI-1260 PCI-CardBus Bridge",
293 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
294 { PCIC_ID_TI1260B, "TI PCI-1260B PCI-CardBus Bridge",
295 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
296 { PCIC_ID_TI1410, "TI PCI-1410 PCI-CardBus Bridge",
297 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
298 { PCIC_ID_TI1420, "TI PCI-1420 PCI-CardBus Bridge",
299 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
300 { PCIC_ID_TI1421, "TI PCI-1421 PCI-CardBus Bridge",
301 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
302 { PCIC_ID_TI1450, "TI PCI-1450 PCI-CardBus Bridge",
303 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER | TI_NO_MFUNC,
304 &pcic_pci_ti12xx_chip },
305 { PCIC_ID_TI1451, "TI PCI-1451 PCI-CardBus Bridge",
306 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
307 { PCIC_ID_TI1510, "TI PCI-1510 PCI-CardBus Bridge",
308 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
309 { PCIC_ID_TI1520, "TI PCI-1520 PCI-CardBus Bridge",
310 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
311 { PCIC_ID_TI4410, "TI PCI-4410 PCI-CardBus Bridge",
312 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
313 { PCIC_ID_TI4450, "TI PCI-4450 PCI-CardBus Bridge",
314 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
315 { PCIC_ID_TI4451, "TI PCI-4451 PCI-CardBus Bridge",
316 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
317 { PCIC_ID_TI4510, "TI PCI-4510 PCI-CardBus Bridge",
318 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
319 { PCIC_ID_TOPIC95, "Toshiba ToPIC95 PCI-CardBus Bridge",
320 PCIC_I82365, PCIC_CARDBUS_POWER, &pcic_pci_topic_chip },
321 { PCIC_ID_TOPIC95B, "Toshiba ToPIC95B PCI-CardBus Bridge",
322 PCIC_I82365, PCIC_CARDBUS_POWER, &pcic_pci_topic_chip },
323 { PCIC_ID_TOPIC97, "Toshiba ToPIC97 PCI-CardBus Bridge",
324 PCIC_I82365, PCIC_CARDBUS_POWER, &pcic_pci_topic_chip },
325 { PCIC_ID_TOPIC100, "Toshiba ToPIC100 PCI-CardBus Bridge",
326 PCIC_I82365, PCIC_CARDBUS_POWER, &pcic_pci_topic_chip },
327 { 0, NULL, 0, 0, NULL }
331 * Read a register from the PCIC.
334 pcic_pci_getb2(struct pcic_slot *sp, int reg)
336 return (bus_space_read_1(sp->bst, sp->bsh, sp->offset + reg));
340 * Write a register on the PCIC
343 pcic_pci_putb2(struct pcic_slot *sp, int reg, unsigned char val)
345 bus_space_write_1(sp->bst, sp->bsh, sp->offset + reg, val);
349 * lookup inside the table
351 static struct pcic_pci_table *
352 pcic_pci_lookup(u_int32_t devid, struct pcic_pci_table *tbl)
355 if (tbl->devid == devid)
363 * The standard way to control fuction interrupts is via bit 7 in the BCR
364 * register. Some data sheets indicate that this is just for "intterupts"
365 * while others are clear that it is for function interrupts. When this
366 * bit is set, function interrupts are routed via the ExCA register. When
367 * this bit is clear, they are routed via the PCI bus, usually via the int
368 * in the INTPIN register.
371 pcic_pci_gen_func(struct pcic_slot *sp, enum pcic_intr_way way)
375 bcr = pci_read_config(sp->sc->dev, CB_PCI_BRIDGE_CTRL, 2);
376 if (way == pcic_iw_pci)
377 bcr &= ~CB_BCR_INT_EXCA;
379 bcr |= CB_BCR_INT_EXCA;
380 pci_write_config(sp->sc->dev, CB_PCI_BRIDGE_CTRL, bcr, 2);
385 pcic_pci_gen_csc(struct pcic_slot *sp, enum pcic_intr_way way)
391 * The O2micro OZ67xx chips functions.
394 pcic_pci_oz67xx_func(struct pcic_slot *sp, enum pcic_intr_way way)
396 return (pcic_pci_gen_func(sp, way));
400 pcic_pci_oz67xx_csc(struct pcic_slot *sp, enum pcic_intr_way way)
403 * Need datasheet to find out what's going on. However, the
404 * 68xx datasheets are so vague that it is hard to know what
405 * the right thing to do is.
413 pcic_pci_oz67xx_init(device_t dev)
415 device_printf(dev, "Warning: O2micro OZ67xx chips may not work\n");
416 pcic_pci_cardbus_init(dev);
420 * The O2micro OZ68xx chips functions.
423 pcic_pci_oz68xx_func(struct pcic_slot *sp, enum pcic_intr_way way)
425 return (pcic_pci_gen_func(sp, way));
429 pcic_pci_oz68xx_csc(struct pcic_slot *sp, enum pcic_intr_way way)
432 * The 68xx datasheets make it hard to know what the right thing
433 * to do here is. We do what we know, which is nothing, and
441 pcic_pci_oz68xx_init(device_t dev)
444 * This is almost certainly incomplete.
446 device_printf(dev, "Warning: O2micro OZ68xx chips may not work\n");
447 pcic_pci_cardbus_init(dev);
451 * The Cirrus Logic PD6729/30. These are weird beasts, so be careful.
452 * They are ISA parts glued to the PCI bus and do not follow the yenta
453 * specification for cardbus bridges. They seem to be similar to the
454 * intel parts that were also cloned by o2micro and maybe others, but
455 * they are so much more common that the author doesn't have experience
456 * with them to know for sure.
459 pcic_pci_pd6729_func(struct pcic_slot *sp, enum pcic_intr_way way)
462 * For pci interrupts, we need to set bit 3 of extension register
463 * 3 to 1. For ISA interrupts, we need to clear it.
465 sp->putb(sp, PCIC_EXT_IND, PCIC_EXTCTRL1);
466 if (way == pcic_iw_pci)
467 pcic_setb(sp, PCIC_EXTENDED, PCIC_EC1_CARD_IRQ_INV);
469 pcic_clrb(sp, PCIC_EXTENDED, PCIC_EC1_CARD_IRQ_INV);
475 pcic_pci_pd6729_csc(struct pcic_slot *sp, enum pcic_intr_way way)
478 * For pci interrupts, we need to set bit 4 of extension register
479 * 3 to 1. For ISA interrupts, we need to clear it.
481 sp->putb(sp, PCIC_EXT_IND, PCIC_EXTCTRL1);
482 if (way == pcic_iw_pci)
483 pcic_setb(sp, PCIC_EXTENDED, PCIC_EC1_CSC_IRQ_INV);
485 pcic_clrb(sp, PCIC_EXTENDED, PCIC_EC1_CSC_IRQ_INV);
492 pcic_pci_pd6729_init(device_t dev)
494 struct pcic_softc *sc = device_get_softc(dev);
497 * Tell the chip to do its routing thing.
499 pcic_pci_pd6729_func(&sc->slots[0], sc->func_route);
500 pcic_pci_pd6729_csc(&sc->slots[0], sc->csc_route);
504 * Set up the CL-PD6832, 6833 and 6834.
507 pcic_pci_pd68xx_func(struct pcic_slot *sp, enum pcic_intr_way way)
509 return (pcic_pci_gen_func(sp, way));
513 pcic_pci_pd68xx_csc(struct pcic_slot *sp, enum pcic_intr_way way)
515 struct pcic_softc *sc = sp->sc;
516 device_t dev = sc->dev;
517 u_int32_t device_id = pci_get_devid(dev);
522 * CLPD6832 management interrupt enable bit is bit 11
523 * (MGMT_IRQ_ENA) in bridge control register(offset 0x3d).
524 * When on, card status interrupts are ISA controlled by
525 * the ExCA register 0x05.
527 * The CLPD6833 does things differently. It doesn't have bit
528 * 11 in the bridge control register. Instead, this
529 * functionality appears to be in the "Configuration
530 * Miscellaneous 1" register bit 1.
532 * I'm assuming that the CLPD6834 does things like the '33
534 if (device_id == PCIC_ID_CLPD6832) {
535 bcr = pci_read_config(dev, CB_PCI_BRIDGE_CTRL, 2);
536 if (way == pcic_iw_pci)
537 bcr &= ~CLPD6832_BCR_MGMT_IRQ_ENA;
539 bcr |= CLPD6832_BCR_MGMT_IRQ_ENA;
540 pci_write_config(dev, CB_PCI_BRIDGE_CTRL, bcr, 2);
542 if (device_id != PCIC_ID_CLPD6832) {
543 cm1 = pci_read_config(dev, CLPD6833_CFG_MISC_1, 4);
544 if (way == pcic_iw_pci)
545 cm1 &= ~CLPD6833_CM1_MGMT_EXCA_ENA;
547 cm1 |= CLPD6833_CM1_MGMT_EXCA_ENA;
548 pci_write_config(dev, CLPD6833_CFG_MISC_1, cm1, 4);
554 pcic_pci_pd68xx_init(device_t dev)
556 pcic_pci_cardbus_init(dev);
560 pcic_pci_ricoh_func(struct pcic_slot *sp, enum pcic_intr_way way)
562 return (pcic_pci_gen_func(sp, way));
566 pcic_pci_ricoh_csc(struct pcic_slot *sp, enum pcic_intr_way way)
568 struct pcic_softc *sc = sp->sc;
569 device_t dev = sc->dev;
573 * For CSC interrupts via ISA, we can't do that exactly.
574 * However, we can disable INT# routing, which is usually what
575 * we want. This is bit 7 in the field. Note, bit 6 looks
576 * interesting, but appears to be unnecessary.
578 mcr2 = pci_read_config(dev, R5C47X_MISC_CONTROL_REGISTER_2, 2);
579 if (way == pcic_iw_pci)
580 mcr2 &= ~R5C47X_MCR2_CSC_TO_INTX_DISABLE;
582 mcr2 |= R5C47X_MCR2_CSC_TO_INTX_DISABLE;
583 pci_write_config(dev, R5C47X_MISC_CONTROL_REGISTER_2, mcr2, 2);
589 pcic_pci_ricoh_init(device_t dev)
592 u_int32_t device_id = pci_get_devid(dev);
595 case PCIC_ID_RICOH_RL5C465:
596 case PCIC_ID_RICOH_RL5C466:
598 * Ricoh chips have a legacy bridge enable different than most
599 * Code cribbed from NEWBUS's bridge code since I can't find a
600 * datasheet for them that has register definitions.
602 brgcntl = pci_read_config(dev, CB_PCI_BRIDGE_CTRL, 2);
603 brgcntl &= ~(CB_BCR_RL_3E2_EN | CB_BCR_RL_3E0_EN);
604 pci_write_config(dev, CB_PCI_BRIDGE_CTRL, brgcntl, 2);
607 pcic_pci_cardbus_init(dev);
611 * TI 1030, 1130, and 1131.
614 pcic_pci_ti113x_func(struct pcic_slot *sp, enum pcic_intr_way way)
617 device_t dev = sp->sc->dev;
620 * The TI-1130 (and 1030 and 1131) have a different interrupt
621 * routing control than the newer chips. assume we're not
622 * routing either csc or func interrupts via PCI, but enable
623 * as necessary when we find someone uses PCI interrupts. In
624 * order to get any pci interrupts, PCI_IRQ_ENA (bit 5) must
625 * be set. If either PCI_IREQ (bit 4) or PCI_CSC (bit 3) are
626 * set, then set bit 5 at the same time, since setting them
627 * enables the PCI interrupt routing.
629 * It also appears necessary to set the function routing bit
630 * in the bridge control register, but cardbus_init does that
633 cardcntl = pci_read_config(dev, TI113X_PCI_CARD_CONTROL, 1);
634 if (way == pcic_iw_pci)
635 cardcntl |= TI113X_CARDCNTL_PCI_IREQ;
637 cardcntl &= ~TI113X_CARDCNTL_PCI_IREQ;
638 if (cardcntl & (TI113X_CARDCNTL_PCI_IREQ | TI113X_CARDCNTL_PCI_CSC))
639 cardcntl |= TI113X_CARDCNTL_PCI_IRQ_ENA;
641 cardcntl &= ~TI113X_CARDCNTL_PCI_IRQ_ENA;
642 pci_write_config(dev, TI113X_PCI_CARD_CONTROL, cardcntl, 1);
644 return (pcic_pci_gen_func(sp, way));
648 pcic_pci_ti113x_csc(struct pcic_slot *sp, enum pcic_intr_way way)
651 device_t dev = sp->sc->dev;
654 * The TI-1130 (and 1030 and 1131) have a different interrupt
655 * routing control than the newer cards. assume we're not
656 * routing PCI, but enable as necessary when we find someone
657 * uses PCI interrupts. In order to get any pci interrupts,
658 * PCI_IRQ_ENA (bit 5) must be set. If either PCI_IREQ (bit
659 * 4) or PCI_CSC (bit 3) are set, then set bit 5 at the same
660 * time, since setting them enables the PCI interrupt routing.
662 * It also appears necessary to set the function routing bit
663 * in the bridge control register, but cardbus_init does that
666 cardcntl = pci_read_config(dev, TI113X_PCI_CARD_CONTROL, 1);
667 if (way == pcic_iw_pci)
668 cardcntl |= TI113X_CARDCNTL_PCI_CSC;
670 cardcntl &= ~TI113X_CARDCNTL_PCI_CSC;
671 if (cardcntl & (TI113X_CARDCNTL_PCI_IREQ | TI113X_CARDCNTL_PCI_CSC))
672 cardcntl |= TI113X_CARDCNTL_PCI_IRQ_ENA;
674 cardcntl &= ~TI113X_CARDCNTL_PCI_IRQ_ENA;
675 pci_write_config(dev, TI113X_PCI_CARD_CONTROL, cardcntl, 1);
681 pcic_pci_ti12xx_func(struct pcic_slot *sp, enum pcic_intr_way way)
683 u_int32_t syscntl, devcntl, cardcntl, mfunc;
684 device_t dev = sp->sc->dev;
686 syscntl = pci_read_config(dev, TI113X_PCI_SYSTEM_CONTROL, 4);
687 devcntl = pci_read_config(dev, TI113X_PCI_DEVICE_CONTROL, 1);
688 cardcntl = pci_read_config(dev, TI113X_PCI_CARD_CONTROL, 1);
691 * Special code for the Orinoco cards (and a few others). They
692 * seem to need this special code to make them work only over pci
693 * interrupts. Sadly, doing this code also causes problems for
694 * many laptops, so we have to make it controlled by a tunable.
695 * Actually, experience has shown that this rarely, if ever,
698 if (way == pcic_iw_pci) {
700 * pcic_init_routing seems to do nothing useful towards
701 * fixing the hang problems. I plan on removing it in
704 if (pcic_init_routing) {
705 devcntl &= ~TI113X_DEVCNTL_INTR_MASK;
706 pci_write_config(dev, TI113X_PCI_DEVICE_CONTROL,
708 syscntl |= TI113X_SYSCNTL_INTRTIE;
712 * I've had reports that we need the pci clock enabled,
713 * provide a hook to do so. The number of cards that
714 * require this is quite small.
716 if (pcic_ti12xx_enable_pci_clock) {
717 syscntl |= TI12XX_SYSCNTL_PCI_CLOCK;
718 pci_write_config(dev, TI113X_PCI_SYSTEM_CONTROL,
723 * Some PCI add-in cards don't have good EEPROMs on them,
724 * so they get this MUX register wrong. The MUX register
725 * defaults to 0, which is usually wrong for this register,
726 * so we initialize it to make sense.
728 * We don't bother to turn it off in the ISA case since it
729 * is an initialization issue.
731 * A few weird TI bridges don't have MFUNC, so filter
734 if ((sp->sc->flags & TI_NO_MFUNC) == 0) {
735 mfunc = pci_read_config(dev, TI12XX_PCI_MFUNC, 4);
737 mfunc = (mfunc & ~TI12XX_MFUNC_PIN0) |
738 TI12XX_MFUNC_PIN0_INTA;
739 if ((syscntl & TI113X_SYSCNTL_INTRTIE) == 0)
740 mfunc = (mfunc & ~TI12XX_MFUNC_PIN1) |
741 TI12XX_MFUNC_PIN1_INTB;
742 pci_write_config(dev, TI12XX_PCI_MFUNC, mfunc,
748 return (pcic_pci_gen_func(sp, way));
752 pcic_pci_ti12xx_csc(struct pcic_slot *sp, enum pcic_intr_way way)
755 * Nothing happens here. The TI12xx parts will route the
756 * CSC interrupt via PCI if ExCA register tells it to use
757 * interrupt 0. And via IRQ otherwise (except for reserved
758 * values which may or may not do anything).
760 * We just hope for the best here that doing nothing is the
767 * TI PCI-CardBus Host Adapter specific function code.
768 * This function is separated from pcic_pci_attach().
769 * Takeshi Shibagaki(shiba@jp.freebsd.org).
772 pcic_pci_ti_init(device_t dev)
774 u_int32_t syscntl, diagctl, devcntl, cardcntl;
775 u_int32_t device_id = pci_get_devid(dev);
776 int ti113x = (device_id == PCIC_ID_TI1031) ||
777 (device_id == PCIC_ID_TI1130) ||
778 (device_id == PCIC_ID_TI1131);
780 syscntl = pci_read_config(dev, TI113X_PCI_SYSTEM_CONTROL, 4);
781 devcntl = pci_read_config(dev, TI113X_PCI_DEVICE_CONTROL, 1);
782 cardcntl = pci_read_config(dev, TI113X_PCI_CARD_CONTROL, 1);
785 device_printf(dev, "TI113X PCI Config Reg: ");
786 if (syscntl & TI113X_SYSCNTL_CLKRUN_ENA) {
787 if (syscntl & TI113X_SYSCNTL_CLKRUN_SEL)
788 printf("[clkrun irq 12]");
790 printf("[clkrun irq 10]");
793 device_printf(dev, "TI12XX PCI Config Reg: ");
796 * Turn on async CSC interrupts. This appears to
797 * be the default, but the old, pre pci-aware, code
798 * did this and it appears PAO does as well.
800 diagctl = pci_read_config(dev, TI12XX_PCI_DIAGNOSTIC, 1);
801 diagctl |= TI12XX_DIAG_CSC_INTR;
802 pci_write_config(dev, TI12XX_PCI_DIAGNOSTIC, diagctl, 1);
805 * Turn off Zoom Video. Some cards have this enabled,
806 * some do not but it causes problems when enabled. This
807 * register doesn't exist on the 1130 (and likely the 1131,
808 * but without a datasheet it is impossible to know).
809 * Some 12xx chips may not have it, but setting it is
810 * believed to be harmless on those models.
812 pci_write_config(dev, TI12XX_PCI_MULTIMEDIA_CONTROL, 0, 4);
814 if (cardcntl & TI113X_CARDCNTL_RING_ENA)
815 printf("[ring enable]");
816 if (cardcntl & TI113X_CARDCNTL_SPKR_ENA)
817 printf("[speaker enable]");
818 if (syscntl & TI113X_SYSCNTL_PWRSAVINGS)
819 printf("[pwr save]");
820 switch(devcntl & TI113X_DEVCNTL_INTR_MASK){
821 case TI113X_DEVCNTL_INTR_ISA :
822 printf("[CSC parallel isa irq]");
824 case TI113X_DEVCNTL_INTR_SERIAL :
825 printf("[CSC serial isa irq]");
827 case TI113X_DEVCNTL_INTR_NONE :
828 printf("[pci only]");
830 case TI12XX_DEVCNTL_INTR_ALLSERIAL :
831 printf("[FUNC pci int + CSC serial isa irq]");
835 pcic_pci_cardbus_init(dev);
839 * Code for TOPIC chips
842 pcic_pci_topic_func(struct pcic_slot *sp, enum pcic_intr_way way)
844 #ifdef THIS_BRAEKS_THINGS
845 device_t dev = sp->sc->dev;
848 scr = pci_read_config(dev, TOPIC_SOCKET_CTRL, 4);
849 if (way == pcic_iw_pci)
850 scr |= TOPIC_SOCKET_CTRL_SCR_IRQSEL;
852 scr &= ~TOPIC_SOCKET_CTRL_SCR_IRQSEL;
853 pci_write_config(dev, TOPIC_SLOT_CTRL, scr, 4);
855 return (pcic_pci_gen_func(sp, way));
859 pcic_pci_topic_csc(struct pcic_slot *sp, enum pcic_intr_way way)
861 device_t dev = sp->sc->dev;
865 device_id = pci_get_devid(dev);
866 if (device_id == PCIC_ID_TOPIC100 || device_id == PCIC_ID_TOPIC97) {
867 scr = pci_read_config(dev, TOPIC_SLOT_CTRL, 4);
868 if (way == pcic_iw_pci)
869 scr |= TOPIC97_SLOT_CTRL_PCIINT;
871 scr &= ~TOPIC97_SLOT_CTRL_PCIINT;
872 pci_write_config(dev, TOPIC_SLOT_CTRL, scr, 4);
879 pcic_pci_topic_init(device_t dev)
881 struct pcic_softc *sc = device_get_softc(dev);
885 device_id = pci_get_devid(dev);
886 reg = pci_read_config(dev, TOPIC_SLOT_CTRL, 4);
887 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN |
888 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS);
889 reg &= ~TOPIC_SLOT_CTRL_SWDETECT;
890 if (device_id == PCIC_ID_TOPIC100 || device_id == PCIC_ID_TOPIC97) {
891 reg |= TOPIC97_SLOT_CTRL_PCIINT;
892 reg &= ~(TOPIC97_SLOT_CTRL_STSIRQP | TOPIC97_SLOT_CTRL_IRQP);
894 pci_write_config(dev, TOPIC_SLOT_CTRL, reg, 4);
895 pcic_pci_cardbus_init(dev);
897 if (device_id == PCIC_ID_TOPIC100 || device_id == PCIC_ID_TOPIC97) {
899 * We need to enable voltage sense and 3V cards explicitly
900 * in the bridge. The datasheets I have for both the
901 * ToPIC 97 and 100 both lists these ports. Without
902 * datasheets for the ToPIC95s, I can't tell if we need
903 * to do it there or not.
905 pcic_setb(&sc->slots[0], PCIC_TOPIC_FCR,
906 PCIC_FCR_3V_EN | PCIC_FCR_VS_EN);
911 pcic_pci_cardbus_init(device_t dev)
913 struct pcic_softc *sc = device_get_softc(dev);
917 unit = device_get_unit(dev);
919 brgcntl = pci_read_config(dev, CB_PCI_BRIDGE_CTRL, 2);
920 brgcntl |= CB_BCR_WRITE_POST_EN | CB_BCR_MASTER_ABORT;
921 pci_write_config(dev, CB_PCI_BRIDGE_CTRL, brgcntl, 2);
923 /* Turn off legacy address */
924 pci_write_config(dev, CB_PCI_LEGACY16_IOADDR, 0, 2);
927 * Write zeros into the remaining memory I/O windows. This
928 * seems to turn off the pci configuration of these things and
929 * make the cardbus bridge use the values for memory
930 * programmed into the pcic registers.
932 pci_write_config(dev, CB_PCI_MEMBASE0, 0, 4);
933 pci_write_config(dev, CB_PCI_MEMLIMIT0, 0, 4);
934 pci_write_config(dev, CB_PCI_MEMBASE1, 0, 4);
935 pci_write_config(dev, CB_PCI_MEMLIMIT1, 0, 4);
936 pci_write_config(dev, CB_PCI_IOBASE0, 0, 4);
937 pci_write_config(dev, CB_PCI_IOLIMIT0, 0, 4);
938 pci_write_config(dev, CB_PCI_IOBASE1, 0, 4);
939 pci_write_config(dev, CB_PCI_IOLIMIT1, 0, 4);
942 * Tell the chip to do its routing thing.
944 sc->chip->func_intr_way(&sc->slots[0], sc->func_route);
945 sc->chip->csc_intr_way(&sc->slots[0], sc->csc_route);
951 pcic_pci_cardtype(u_int32_t stat)
953 if (stat & CB_SS_NOTCARD)
954 return ("unrecognized by bridge");
955 if ((stat & (CB_SS_16BIT | CB_SS_CB)) == (CB_SS_16BIT | CB_SS_CB))
956 return ("16-bit and 32-bit (can't happen)");
957 if (stat & CB_SS_16BIT)
958 return ("16-bit pccard");
960 return ("32-bit cardbus");
961 return ("none (can't happen)");
965 * Card insertion and removal code. The insertion events need to be
966 * debounced so that the noisy insertion/removal events don't result
967 * in the hardware being initialized many times, only to be torn down
968 * as well. This may also cause races with pccardd. Instead, we wait
969 * for the insertion signal to be stable for 0.5 seconds before we declare
970 * it to be a real insertion event. Removal is also debounced. We turn
971 * off interrupt servicing during the settling time to prevent infinite
972 * loops in the driver.
974 * Note: We only handle the card detect change events. We don't handle
975 * power events and status change events.
978 pcic_cd_change(void *arg)
980 struct pcic_softc *sc = (struct pcic_softc *) arg;
981 struct pcic_slot *sp = &sc->slots[0];
985 stat = bus_space_read_4(sp->bst, sp->bsh, CB_SOCKET_STATE);
987 /* Status changed while present; remove the card from the system. */
988 if (sc->cd_present) {
990 pccard_event(sp->slt, card_removed);
992 /* Nothing to do if the debounced state is 'not present'. */
993 if ((stat & CB_SS_CD) != 0)
997 if (bootverbose && (stat & CB_SS_BADVCC) != 0)
998 device_printf(sc->dev, "BAD Vcc request: 0x%x\n", stat);
999 if ((stat & CB_SS_16BIT) == 0)
1000 device_printf(sp->sc->dev, "Card type %s is unsupported\n",
1001 pcic_pci_cardtype(stat));
1003 pccard_event(sp->slt, card_inserted);
1007 pcic_pci_intr(void *arg)
1009 struct pcic_softc *sc = (struct pcic_softc *) arg;
1010 struct pcic_slot *sp = &sc->slots[0];
1013 event = bus_space_read_4(sp->bst, sp->bsh, CB_SOCKET_EVENT);
1016 device_printf(sc->dev, "Event mask 0x%x\n", event);
1019 * Treat all card-detect signal transitions the same way
1020 * since we can't reliably tell if this is an insert or a
1021 * remove event. Stop the card from getting interrupts and
1022 * defer the insert/remove event until the CB_SOCKET_STATE
1023 * signals have had time to settle.
1025 if ((event & CB_SE_CD) != 0) {
1026 if (sc->cd_pending) {
1027 untimeout(pcic_cd_change, arg, sc->cd_ch);
1031 sc->cd_ch = timeout(pcic_cd_change, arg, hz/2);
1032 sc->func_intr = NULL;
1035 /* Ack the interrupt */
1036 bus_space_write_4(sp->bst, sp->bsh, 0, event);
1040 * Some TI chips also require us to read the old ExCA register for
1041 * card status change when we route CSC via PCI! So, we go ahead
1042 * and read it to clear the bits. Maybe we should check the status
1043 * ala the ISA interrupt handler, but those changes should be caught
1046 * We have to check it every interrupt because these bits can sometimes
1047 * show up indepentently of the CB_SOCKET_EVENT register above.
1049 sp->getb(sp, PCIC_STAT_CHG);
1053 * Return the ID string for the controller if the vendor/product id
1054 * matches, NULL otherwise.
1057 pcic_pci_probe(device_t dev)
1062 u_int32_t device_id;
1063 struct pcic_pci_table *itm;
1064 struct resource *res;
1067 if (pcic_ignore_pci)
1069 device_id = pci_get_devid(dev);
1071 itm = pcic_pci_lookup(device_id, &pcic_pci_devs[0]);
1072 if (pcic_ignore_function_1 && pci_get_function(dev) == 1) {
1074 PRVERB((dev, "Ignoring function 1\n"));
1079 if (desc == NULL && pci_get_class(dev) == PCIC_BRIDGE) {
1080 subclass = pci_get_subclass(dev);
1081 progif = pci_get_progif(dev);
1082 if (subclass == PCIS_BRIDGE_PCMCIA && progif == 0)
1083 desc = "Generic PCI-PCMCIA Bridge";
1084 if (subclass == PCIS_BRIDGE_CARDBUS && progif == 0)
1085 desc = "YENTA PCI-CardBus Bridge";
1086 if (bootverbose && desc)
1087 printf("Found unknown %s devid 0x%x\n", desc, device_id);
1091 device_set_desc(dev, desc);
1094 * Take us out of power down mode, if necessary. It also
1095 * appears that even reading the power register is enough on
1096 * some systems to cause correct behavior.
1098 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1099 /* Reset the power state. */
1100 device_printf(dev, "chip is in D%d power mode "
1101 "-- setting to D0\n", pci_get_powerstate(dev));
1102 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1106 * Allocated/deallocate interrupt. This forces the PCI BIOS or
1107 * other MD method to route the interrupts to this card.
1108 * This so we get the interrupt number in the probe message.
1109 * We only need to route interrupts when we're doing pci
1110 * parallel interrupt routing.
1112 * We use two different variables for the memory based and I/O
1113 * based cards, so the check here is a little more complex than
1114 * one would otherwise hope.
1116 * XXX The bus code for PCI really should do this for us.
1118 if ((pcic_intr_path == pcic_iw_pci &&
1119 device_id != PCIC_ID_CLPD6729) ||
1120 (pcic_pd6729_intr_path == pcic_iw_pci &&
1121 device_id == PCIC_ID_CLPD6729)) {
1125 * IRQ 0 is invalid on x86, but not other platforms.
1126 * If we have irq 0, then write 255 to force a new, non-
1127 * bogus one to be assigned. I think that in -current
1128 * the code in this ifdef may be obsolete with the new
1129 * invalid mapping that we're doing in the pci layer -- imp
1131 if (pci_get_irq(dev) == 0) {
1132 pci_set_irq(dev, 255);
1133 pci_write_config(dev, PCIR_INTLINE, 255, 1);
1136 res = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
1139 bus_release_resource(dev, SYS_RES_IRQ, rid, res);
1146 pcic_pci_shutdown(device_t dev)
1149 * More reports of things working w/o this code than with it.
1152 struct pcic_softc *sc;
1153 struct pcic_slot *sp;
1155 sc = (struct pcic_softc *) device_get_softc(dev);
1159 * Turn off the power to the slot in an attempt to
1160 * keep the system from hanging on reboot. We also turn off
1161 * card interrupts in an attempt to control interrupt storms.
1162 * on some (all?) this has the effect of also turning off
1163 * card status change interrupts. A side effect of writing 0
1164 * to INT_GEN is that the card is placed into "reset" mode
1165 * where nothing happens until it is taken out of "reset"
1168 * Also, turn off the generation of status interrupts too.
1170 sp->putb(sp, PCIC_INT_GEN, 0);
1171 sp->putb(sp, PCIC_STAT_INT, 0);
1172 sp->putb(sp, PCIC_POWER, 0);
1176 * Writing to INT_GEN can cause an interrupt, so we blindly
1177 * ack all possible interrupts here. Reading the stat change
1178 * shouldn't be necessary, but some TI chipsets need it in the
1179 * normal course of operations, so we do it here too. We can't
1180 * lose any interrupts after this point, so go ahead and ack
1181 * everything. The bits in INT_GEN clear upon reading them.
1182 * We also set the interrupt mask to 0, in an effort to avoid
1183 * getting further interrupts.
1185 bus_space_write_4(sp->bst, sp->bsh, CB_SOCKET_MASK, 0);
1186 bus_space_write_4(sp->bst, sp->bsh, CB_SOCKET_EVENT, 0xffffffff);
1187 sp->getb(sp, PCIC_STAT_CHG);
1192 * Print out the config space
1195 pcic_pci_print_config(device_t dev)
1199 device_printf(dev, "PCI Configuration space:");
1200 for (i = 0; i < 256; i += 4) {
1202 printf("\n 0x%02x: ", i);
1203 printf("0x%08x ", pci_read_config(dev, i, 4));
1209 * Generic pci interrupt attach routine. It tries to understand all parts,
1210 * and do sane things for those parts it does not understand.
1213 pcic_pci_attach(device_t dev)
1215 u_int32_t device_id = pci_get_devid(dev);
1217 struct pcic_slot *sp;
1218 struct pcic_softc *sc;
1221 struct pcic_pci_table *itm;
1224 struct resource *r = NULL;
1227 driver_intr_t *intr = NULL;
1230 * In sys/pci/pcireg.h, PCIR_COMMAND must be separated
1231 * PCI_COMMAND_REG(0x04) and PCI_STATUS_REG(0x06).
1232 * Takeshi Shibagaki(shiba@jp.freebsd.org).
1234 command = pci_read_config(dev, PCIR_COMMAND, 4);
1235 command |= PCIM_CMD_PORTEN | PCIM_CMD_MEMEN;
1236 pci_write_config(dev, PCIR_COMMAND, command, 4);
1238 sc = (struct pcic_softc *) device_get_softc(dev);
1241 sockbase = pci_read_config(dev, 0x10, 4);
1242 if (sockbase & 0x1) {
1243 sc->iorid = CB_PCI_SOCKET_BASE;
1244 sc->iores = bus_alloc_resource(dev, SYS_RES_IOPORT,
1245 &sc->iorid, 0, ~0, 1, RF_ACTIVE | RF_SHAREABLE);
1246 if (sc->iores == NULL)
1249 sc->flags = PCIC_PD_POWER;
1250 itm = pcic_pci_lookup(device_id, &pcic_pci_devs[0]);
1251 for (i = 0; i < 2; i++) {
1252 sp[i].bst = rman_get_bustag(sc->iores);
1253 sp[i].bsh = rman_get_bushandle(sc->iores);
1256 sp[i].getb = pcic_getb_io;
1257 sp[i].putb = pcic_putb_io;
1258 sp[i].offset = i * PCIC_SLOT_SIZE;
1259 sp[i].controller = itm ? itm->type : PCIC_PD6729;
1260 if ((sp[i].getb(&sp[i], PCIC_ID_REV) & 0xc0) == 0x80)
1261 sp[i].slt = (struct slot *) 1;
1263 sc->csc_route = sc->func_route = pcic_pd6729_intr_path;
1265 sc->flags = itm->flags;
1267 * We have to use the ISA interrupt routine for status
1268 * changes since we don't have any "yenta" pci registers.
1269 * We have to do this even when we're using pci type
1270 * interrupts because on these cards the interrupts are
1271 * cleared in the same way that the ISA cards clear them.
1273 intr = pcic_isa_intr;
1275 sc->memrid = CB_PCI_SOCKET_BASE;
1276 sc->memres = bus_alloc_resource(dev, SYS_RES_MEMORY,
1277 &sc->memrid, 0, ~0, 1, RF_ACTIVE);
1278 if (sc->memres == NULL && pcic_pci_get_memory(dev) != 0)
1280 sp->getb = pcic_pci_getb2;
1281 sp->putb = pcic_pci_putb2;
1282 sp->offset = CB_EXCA_OFFSET;
1283 sp->bst = rman_get_bustag(sc->memres);
1284 sp->bsh = rman_get_bushandle(sc->memres);
1285 itm = pcic_pci_lookup(device_id, &pcic_pci_devs[0]);
1287 sp->controller = itm->type;
1289 sc->flags = itm->flags;
1291 /* By default, assume we're a D step compatible */
1292 sp->controller = PCIC_I82365SL_DF;
1294 sc->flags = PCIC_CARDBUS_POWER;
1296 /* All memory mapped cardbus bridges have these registers */
1297 sc->flags |= PCIC_YENTA_HIGH_MEMORY;
1298 sp->slt = (struct slot *) 1;
1299 sc->csc_route = pcic_intr_path;
1300 sc->func_route = pcic_intr_path;
1301 stat = bus_space_read_4(sp->bst, sp->bsh, CB_SOCKET_STATE);
1302 sc->cd_present = (stat & CB_SS_CD) == 0;
1306 sc->chip = itm->chip;
1308 sc->chip = &pcic_pci_generic_chip;
1310 if (sc->csc_route == pcic_iw_pci) {
1312 r = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
1313 RF_ACTIVE | RF_SHAREABLE);
1315 sc->csc_route = pcic_iw_isa;
1316 sc->func_route = pcic_iw_isa;
1318 "No PCI interrupt routed, trying ISA.\n");
1321 intr = pcic_pci_intr;
1322 irq = rman_get_start(r);
1325 if (sc->csc_route == pcic_iw_isa) {
1327 irq = pcic_override_irq;
1329 r = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, irq,
1333 "Can't route ISA CSC interrupt.\n");
1338 "Management interrupt on ISA IRQ %ld\n", irq);
1340 intr = pcic_isa_intr;
1342 sc->slot_poll = pcic_timeout;
1343 sc->timeout_ch = timeout(sc->slot_poll, sc, hz/2);
1344 device_printf(dev, "Polling mode\n");
1350 * Initialize AFTER we figure out what kind of interrupt we're
1351 * going to be using, if any.
1354 panic("Bug: sc->chip not set!\n");
1355 sc->chip->init(dev);
1358 * Now install the interrupt handler, if necessary.
1364 error = bus_setup_intr(dev, r, INTR_TYPE_AV, intr, sc, &sc->ih);
1371 pcic_pci_print_config(dev);
1372 return (pcic_attach(dev));
1376 pcic_pci_detach(device_t dev)
1378 return (EBUSY); /* Can't detach this device */
1382 * The PCI bus should do this for us. However, it doesn't quite yet, so
1383 * we cope by doing it ourselves. If it ever does, this code can go quietly
1384 * into that good night.
1387 pcic_pci_get_memory(device_t dev)
1389 struct pcic_softc *sc;
1392 sc = (struct pcic_softc *) device_get_softc(dev);
1393 sockbase = pci_read_config(dev, sc->memrid, 4);
1394 if (sockbase >= 0x100000 && sockbase < 0xfffffff0) {
1395 device_printf(dev, "Could not map register memory 0x%x\n",
1399 pci_write_config(dev, sc->memrid, 0xffffffff, 4);
1400 sockbase = pci_read_config(dev, sc->memrid, 4);
1401 sockbase = (sockbase & 0xfffffff0) & -(sockbase & 0xfffffff0);
1402 #define CARDBUS_SYS_RES_MEMORY_START 0x88000000
1403 #define CARDBUS_SYS_RES_MEMORY_END 0xFFFFFFFF
1404 sc->memres = bus_generic_alloc_resource(device_get_parent(dev),
1405 dev, SYS_RES_MEMORY, &sc->memrid,
1406 CARDBUS_SYS_RES_MEMORY_START, CARDBUS_SYS_RES_MEMORY_END,
1407 sockbase, RF_ACTIVE | rman_make_alignment_flags(sockbase));
1408 if (sc->memres == NULL) {
1409 device_printf(dev, "Could not grab register memory\n");
1412 sockbase = rman_get_start(sc->memres);
1413 pci_write_config(dev, sc->memrid, sockbase, 4);
1414 device_printf(dev, "PCI Memory allocated: 0x%08x\n", sockbase);
1419 pcic_pci_gen_mapirq(struct pcic_slot *sp, int irq)
1422 * If we're doing ISA interrupt routing, then just go to the
1423 * generic ISA routine. Also, irq 0 means turn off the interrupts
1426 if (sp->sc->func_route == pcic_iw_isa || irq == 0)
1427 return (pcic_isa_mapirq(sp, irq));
1430 * Ohterwise we're doing PCI interrupts. For those cardbus bridges
1431 * that follow yenta (and the one pcmcia bridge that does), we don't
1432 * do a thing to get the IRQ mapped into the system. However,
1433 * for other controllers that are PCI, but not yetna compliant, we
1434 * need to do some special mapping.
1436 * XXX Maybe we shouldn't assume INTA#, but rather as the function
1437 * XXX what Intline to use.
1439 if (sp->controller == PCIC_PD6729) {
1446 sp->putb(sp, PCIC_INT_GEN, /* Assume INTA# */
1447 (sp->getb(sp, PCIC_INT_GEN) & 0xF0) | 3);
1454 pcic_pci_func_intr(void *arg)
1456 struct pcic_softc *sc = (struct pcic_softc *) arg;
1457 struct pcic_slot *sp = &sc->slots[0];
1462 * The 6729 controller is a weird one, and we have to use
1463 * the ISA registers to check to see if the card is there.
1464 * Otherwise we look at the PCI state register to find out
1465 * if the card is there.
1467 if (sp->controller == PCIC_PD6729) {
1468 if ((sp->getb(sp, PCIC_STATUS) & PCIC_CD) == PCIC_CD)
1472 stat = bus_space_read_4(sp->bst, sp->bsh, CB_SOCKET_STATE);
1473 if ((stat & CB_SS_CD) == 0 && sc->func_intr != 0)
1476 if (doit && sc->func_intr != NULL)
1477 sc->func_intr(sc->func_arg);
1481 pcic_pci_setup_intr(device_t dev, device_t child, struct resource *irq,
1482 int flags, driver_intr_t *intr, void *arg, void **cookiep)
1484 struct pcic_softc *sc = device_get_softc(dev);
1485 struct pcic_slot *sp = &sc->slots[0];
1488 if (sc->func_route == pcic_iw_isa)
1489 return(pcic_setup_intr(dev, child, irq, flags, intr, arg,
1492 #if __FreeBSD_version >= 500000
1493 if ((flags & INTR_FAST) != 0)
1495 if ((flags & INTR_TYPE_FAST) != 0)
1498 if (sc->func_intr != NULL) {
1499 device_printf(child, "Can't establish another ISR\n");
1503 err = bus_generic_setup_intr(dev, child, irq, flags,
1504 pcic_pci_func_intr, sc, cookiep);
1507 sc->chip->map_irq(sp, rman_get_start(irq));
1508 sc->func_intr = intr;
1514 pcic_pci_teardown_intr(device_t dev, device_t child, struct resource *irq,
1517 struct pcic_softc *sc = device_get_softc(dev);
1519 if (sc->func_route == pcic_iw_isa)
1520 return (pcic_teardown_intr(dev, child, irq, cookie));
1521 sc->func_intr = NULL;
1522 return (bus_generic_teardown_intr(dev, child, irq, cookie));
1526 pcic_pci_resume(device_t dev)
1528 struct pcic_softc *sc = device_get_softc(dev);
1531 * Some BIOSes will not save the BARs for the pci chips, so we
1532 * must do it ourselves. If the BAR is reset to 0 for an I/O
1533 * device, it will read back as 0x1, so no explicit test for
1534 * memory devices are needed.
1536 * Note: The PCI bus code should do this automatically for us on
1537 * suspend/resume, but until it does, we have to cope.
1539 if (pci_read_config(dev, CB_PCI_SOCKET_BASE, 4) == 0)
1540 pci_write_config(dev, CB_PCI_SOCKET_BASE,
1541 rman_get_start(sc->memres), 4);
1542 return (bus_generic_resume(dev));
1545 static device_method_t pcic_pci_methods[] = {
1546 /* Device interface */
1547 DEVMETHOD(device_probe, pcic_pci_probe),
1548 DEVMETHOD(device_attach, pcic_pci_attach),
1549 DEVMETHOD(device_detach, pcic_pci_detach),
1550 DEVMETHOD(device_suspend, bus_generic_suspend),
1551 DEVMETHOD(device_resume, pcic_pci_resume),
1552 DEVMETHOD(device_shutdown, pcic_pci_shutdown),
1555 DEVMETHOD(bus_print_child, bus_generic_print_child),
1556 DEVMETHOD(bus_alloc_resource, pcic_alloc_resource),
1557 DEVMETHOD(bus_release_resource, bus_generic_release_resource),
1558 DEVMETHOD(bus_activate_resource, pcic_activate_resource),
1559 DEVMETHOD(bus_deactivate_resource, pcic_deactivate_resource),
1560 DEVMETHOD(bus_setup_intr, pcic_pci_setup_intr),
1561 DEVMETHOD(bus_teardown_intr, pcic_pci_teardown_intr),
1563 /* Card interface */
1564 DEVMETHOD(card_set_res_flags, pcic_set_res_flags),
1565 DEVMETHOD(card_get_res_flags, pcic_get_res_flags),
1566 DEVMETHOD(card_set_memory_offset, pcic_set_memory_offset),
1567 DEVMETHOD(card_get_memory_offset, pcic_get_memory_offset),
1572 static driver_t pcic_pci_driver = {
1575 sizeof(struct pcic_softc)
1578 DRIVER_MODULE(pcic, pci, pcic_pci_driver, pcic_devclass, 0, 0);