2 * Copyright (c) 2004 Joerg Sonnenberger <joerg@bec.de>. All rights reserved.
4 * Copyright (c) 2001-2008, Intel Corporation
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * 3. Neither the name of the Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived from
19 * this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
34 * Copyright (c) 2005 The DragonFly Project. All rights reserved.
36 * This code is derived from software contributed to The DragonFly Project
37 * by Matthew Dillon <dillon@backplane.com>
39 * Redistribution and use in source and binary forms, with or without
40 * modification, are permitted provided that the following conditions
43 * 1. Redistributions of source code must retain the above copyright
44 * notice, this list of conditions and the following disclaimer.
45 * 2. Redistributions in binary form must reproduce the above copyright
46 * notice, this list of conditions and the following disclaimer in
47 * the documentation and/or other materials provided with the
49 * 3. Neither the name of The DragonFly Project nor the names of its
50 * contributors may be used to endorse or promote products derived
51 * from this software without specific, prior written permission.
53 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
54 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
55 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
56 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
57 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
58 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
59 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
60 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
61 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
62 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
63 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
67 #include "opt_ifpoll.h"
70 #include <sys/param.h>
72 #include <sys/endian.h>
73 #include <sys/interrupt.h>
74 #include <sys/kernel.h>
76 #include <sys/malloc.h>
80 #include <sys/serialize.h>
81 #include <sys/serialize2.h>
82 #include <sys/socket.h>
83 #include <sys/sockio.h>
84 #include <sys/sysctl.h>
85 #include <sys/systm.h>
88 #include <net/ethernet.h>
90 #include <net/if_arp.h>
91 #include <net/if_dl.h>
92 #include <net/if_media.h>
93 #include <net/ifq_var.h>
94 #include <net/toeplitz.h>
95 #include <net/toeplitz2.h>
96 #include <net/vlan/if_vlan_var.h>
97 #include <net/vlan/if_vlan_ether.h>
98 #include <net/if_poll.h>
100 #include <netinet/in_systm.h>
101 #include <netinet/in.h>
102 #include <netinet/ip.h>
103 #include <netinet/tcp.h>
104 #include <netinet/udp.h>
106 #include <bus/pci/pcivar.h>
107 #include <bus/pci/pcireg.h>
109 #include <dev/netif/ig_hal/e1000_api.h>
110 #include <dev/netif/ig_hal/e1000_82571.h>
111 #include <dev/netif/ig_hal/e1000_dragonfly.h>
112 #include <dev/netif/emx/if_emx.h>
117 #define EMX_RSS_DPRINTF(sc, lvl, fmt, ...) \
119 if (sc->rss_debug >= lvl) \
120 if_printf(&sc->arpcom.ac_if, fmt, __VA_ARGS__); \
122 #else /* !EMX_RSS_DEBUG */
123 #define EMX_RSS_DPRINTF(sc, lvl, fmt, ...) ((void)0)
124 #endif /* EMX_RSS_DEBUG */
126 #define EMX_NAME "Intel(R) PRO/1000 "
128 #define EMX_DEVICE(id) \
129 { EMX_VENDOR_ID, E1000_DEV_ID_##id, EMX_NAME #id }
130 #define EMX_DEVICE_NULL { 0, 0, NULL }
132 static const struct emx_device {
137 EMX_DEVICE(82571EB_COPPER),
138 EMX_DEVICE(82571EB_FIBER),
139 EMX_DEVICE(82571EB_SERDES),
140 EMX_DEVICE(82571EB_SERDES_DUAL),
141 EMX_DEVICE(82571EB_SERDES_QUAD),
142 EMX_DEVICE(82571EB_QUAD_COPPER),
143 EMX_DEVICE(82571EB_QUAD_COPPER_BP),
144 EMX_DEVICE(82571EB_QUAD_COPPER_LP),
145 EMX_DEVICE(82571EB_QUAD_FIBER),
146 EMX_DEVICE(82571PT_QUAD_COPPER),
148 EMX_DEVICE(82572EI_COPPER),
149 EMX_DEVICE(82572EI_FIBER),
150 EMX_DEVICE(82572EI_SERDES),
154 EMX_DEVICE(82573E_IAMT),
157 EMX_DEVICE(80003ES2LAN_COPPER_SPT),
158 EMX_DEVICE(80003ES2LAN_SERDES_SPT),
159 EMX_DEVICE(80003ES2LAN_COPPER_DPT),
160 EMX_DEVICE(80003ES2LAN_SERDES_DPT),
165 EMX_DEVICE(PCH_LPT_I217_LM),
166 EMX_DEVICE(PCH_LPT_I217_V),
167 EMX_DEVICE(PCH_LPTLP_I218_LM),
168 EMX_DEVICE(PCH_LPTLP_I218_V),
169 EMX_DEVICE(PCH_I218_LM2),
170 EMX_DEVICE(PCH_I218_V2),
171 EMX_DEVICE(PCH_I218_LM3),
172 EMX_DEVICE(PCH_I218_V3),
173 EMX_DEVICE(PCH_SPT_I219_LM),
174 EMX_DEVICE(PCH_SPT_I219_V),
175 EMX_DEVICE(PCH_SPT_I219_LM2),
176 EMX_DEVICE(PCH_SPT_I219_V2),
178 /* required last entry */
182 static int emx_probe(device_t);
183 static int emx_attach(device_t);
184 static int emx_detach(device_t);
185 static int emx_shutdown(device_t);
186 static int emx_suspend(device_t);
187 static int emx_resume(device_t);
189 static void emx_init(void *);
190 static void emx_stop(struct emx_softc *);
191 static int emx_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
192 static void emx_start(struct ifnet *, struct ifaltq_subque *);
194 static void emx_npoll(struct ifnet *, struct ifpoll_info *);
195 static void emx_npoll_status(struct ifnet *);
196 static void emx_npoll_tx(struct ifnet *, void *, int);
197 static void emx_npoll_rx(struct ifnet *, void *, int);
199 static void emx_watchdog(struct ifaltq_subque *);
200 static void emx_media_status(struct ifnet *, struct ifmediareq *);
201 static int emx_media_change(struct ifnet *);
202 static void emx_timer(void *);
203 static void emx_serialize(struct ifnet *, enum ifnet_serialize);
204 static void emx_deserialize(struct ifnet *, enum ifnet_serialize);
205 static int emx_tryserialize(struct ifnet *, enum ifnet_serialize);
207 static void emx_serialize_assert(struct ifnet *, enum ifnet_serialize,
211 static void emx_intr(void *);
212 static void emx_intr_mask(void *);
213 static void emx_intr_body(struct emx_softc *, boolean_t);
214 static void emx_rxeof(struct emx_rxdata *, int);
215 static void emx_txeof(struct emx_txdata *);
216 static void emx_tx_collect(struct emx_txdata *);
217 static void emx_tx_purge(struct emx_softc *);
218 static void emx_enable_intr(struct emx_softc *);
219 static void emx_disable_intr(struct emx_softc *);
221 static int emx_dma_alloc(struct emx_softc *);
222 static void emx_dma_free(struct emx_softc *);
223 static void emx_init_tx_ring(struct emx_txdata *);
224 static int emx_init_rx_ring(struct emx_rxdata *);
225 static void emx_free_tx_ring(struct emx_txdata *);
226 static void emx_free_rx_ring(struct emx_rxdata *);
227 static int emx_create_tx_ring(struct emx_txdata *);
228 static int emx_create_rx_ring(struct emx_rxdata *);
229 static void emx_destroy_tx_ring(struct emx_txdata *, int);
230 static void emx_destroy_rx_ring(struct emx_rxdata *, int);
231 static int emx_newbuf(struct emx_rxdata *, int, int);
232 static int emx_encap(struct emx_txdata *, struct mbuf **, int *, int *);
233 static int emx_txcsum(struct emx_txdata *, struct mbuf *,
234 uint32_t *, uint32_t *);
235 static int emx_tso_pullup(struct emx_txdata *, struct mbuf **);
236 static int emx_tso_setup(struct emx_txdata *, struct mbuf *,
237 uint32_t *, uint32_t *);
238 static int emx_get_txring_inuse(const struct emx_softc *, boolean_t);
240 static int emx_is_valid_eaddr(const uint8_t *);
241 static int emx_reset(struct emx_softc *);
242 static void emx_setup_ifp(struct emx_softc *);
243 static void emx_init_tx_unit(struct emx_softc *);
244 static void emx_init_rx_unit(struct emx_softc *);
245 static void emx_update_stats(struct emx_softc *);
246 static void emx_set_promisc(struct emx_softc *);
247 static void emx_disable_promisc(struct emx_softc *);
248 static void emx_set_multi(struct emx_softc *);
249 static void emx_update_link_status(struct emx_softc *);
250 static void emx_smartspeed(struct emx_softc *);
251 static void emx_set_itr(struct emx_softc *, uint32_t);
252 static void emx_disable_aspm(struct emx_softc *);
254 static void emx_print_debug_info(struct emx_softc *);
255 static void emx_print_nvm_info(struct emx_softc *);
256 static void emx_print_hw_stats(struct emx_softc *);
258 static int emx_sysctl_stats(SYSCTL_HANDLER_ARGS);
259 static int emx_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
260 static int emx_sysctl_int_throttle(SYSCTL_HANDLER_ARGS);
261 static int emx_sysctl_tx_intr_nsegs(SYSCTL_HANDLER_ARGS);
262 static int emx_sysctl_tx_wreg_nsegs(SYSCTL_HANDLER_ARGS);
264 static int emx_sysctl_npoll_rxoff(SYSCTL_HANDLER_ARGS);
265 static int emx_sysctl_npoll_txoff(SYSCTL_HANDLER_ARGS);
267 static void emx_add_sysctl(struct emx_softc *);
269 static void emx_serialize_skipmain(struct emx_softc *);
270 static void emx_deserialize_skipmain(struct emx_softc *);
272 /* Management and WOL Support */
273 static void emx_get_mgmt(struct emx_softc *);
274 static void emx_rel_mgmt(struct emx_softc *);
275 static void emx_get_hw_control(struct emx_softc *);
276 static void emx_rel_hw_control(struct emx_softc *);
277 static void emx_enable_wol(device_t);
279 static device_method_t emx_methods[] = {
280 /* Device interface */
281 DEVMETHOD(device_probe, emx_probe),
282 DEVMETHOD(device_attach, emx_attach),
283 DEVMETHOD(device_detach, emx_detach),
284 DEVMETHOD(device_shutdown, emx_shutdown),
285 DEVMETHOD(device_suspend, emx_suspend),
286 DEVMETHOD(device_resume, emx_resume),
290 static driver_t emx_driver = {
293 sizeof(struct emx_softc),
296 static devclass_t emx_devclass;
298 DECLARE_DUMMY_MODULE(if_emx);
299 MODULE_DEPEND(emx, ig_hal, 1, 1, 1);
300 DRIVER_MODULE(if_emx, pci, emx_driver, emx_devclass, NULL, NULL);
305 static int emx_int_throttle_ceil = EMX_DEFAULT_ITR;
306 static int emx_rxd = EMX_DEFAULT_RXD;
307 static int emx_txd = EMX_DEFAULT_TXD;
308 static int emx_smart_pwr_down = 0;
309 static int emx_rxr = 0;
310 static int emx_txr = 1;
312 /* Controls whether promiscuous also shows bad packets */
313 static int emx_debug_sbp = 0;
315 static int emx_82573_workaround = 1;
316 static int emx_msi_enable = 1;
318 static char emx_flowctrl[IFM_ETH_FC_STRLEN] = IFM_ETH_FC_RXPAUSE;
320 TUNABLE_INT("hw.emx.int_throttle_ceil", &emx_int_throttle_ceil);
321 TUNABLE_INT("hw.emx.rxd", &emx_rxd);
322 TUNABLE_INT("hw.emx.rxr", &emx_rxr);
323 TUNABLE_INT("hw.emx.txd", &emx_txd);
324 TUNABLE_INT("hw.emx.txr", &emx_txr);
325 TUNABLE_INT("hw.emx.smart_pwr_down", &emx_smart_pwr_down);
326 TUNABLE_INT("hw.emx.sbp", &emx_debug_sbp);
327 TUNABLE_INT("hw.emx.82573_workaround", &emx_82573_workaround);
328 TUNABLE_INT("hw.emx.msi.enable", &emx_msi_enable);
329 TUNABLE_STR("hw.emx.flow_ctrl", emx_flowctrl, sizeof(emx_flowctrl));
331 /* Global used in WOL setup with multiport cards */
332 static int emx_global_quad_port_a = 0;
334 /* Set this to one to display debug statistics */
335 static int emx_display_debug_stats = 0;
337 #if !defined(KTR_IF_EMX)
338 #define KTR_IF_EMX KTR_ALL
340 KTR_INFO_MASTER(if_emx);
341 KTR_INFO(KTR_IF_EMX, if_emx, intr_beg, 0, "intr begin");
342 KTR_INFO(KTR_IF_EMX, if_emx, intr_end, 1, "intr end");
343 KTR_INFO(KTR_IF_EMX, if_emx, pkt_receive, 4, "rx packet");
344 KTR_INFO(KTR_IF_EMX, if_emx, pkt_txqueue, 5, "tx packet");
345 KTR_INFO(KTR_IF_EMX, if_emx, pkt_txclean, 6, "tx clean");
346 #define logif(name) KTR_LOG(if_emx_ ## name)
349 emx_setup_rxdesc(emx_rxdesc_t *rxd, const struct emx_rxbuf *rxbuf)
351 rxd->rxd_bufaddr = htole64(rxbuf->paddr);
352 /* DD bit must be cleared */
353 rxd->rxd_staterr = 0;
357 emx_rxcsum(uint32_t staterr, struct mbuf *mp)
359 /* Ignore Checksum bit is set */
360 if (staterr & E1000_RXD_STAT_IXSM)
363 if ((staterr & (E1000_RXD_STAT_IPCS | E1000_RXDEXT_STATERR_IPE)) ==
365 mp->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | CSUM_IP_VALID;
367 if ((staterr & (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) ==
368 E1000_RXD_STAT_TCPCS) {
369 mp->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
371 CSUM_FRAG_NOT_CHECKED;
372 mp->m_pkthdr.csum_data = htons(0xffff);
376 static __inline struct pktinfo *
377 emx_rssinfo(struct mbuf *m, struct pktinfo *pi,
378 uint32_t mrq, uint32_t hash, uint32_t staterr)
380 switch (mrq & EMX_RXDMRQ_RSSTYPE_MASK) {
381 case EMX_RXDMRQ_IPV4_TCP:
382 pi->pi_netisr = NETISR_IP;
384 pi->pi_l3proto = IPPROTO_TCP;
387 case EMX_RXDMRQ_IPV6_TCP:
388 pi->pi_netisr = NETISR_IPV6;
390 pi->pi_l3proto = IPPROTO_TCP;
393 case EMX_RXDMRQ_IPV4:
394 if (staterr & E1000_RXD_STAT_IXSM)
398 (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) ==
399 E1000_RXD_STAT_TCPCS) {
400 pi->pi_netisr = NETISR_IP;
402 pi->pi_l3proto = IPPROTO_UDP;
410 m_sethash(m, toeplitz_hash(hash));
415 emx_probe(device_t dev)
417 const struct emx_device *d;
420 vid = pci_get_vendor(dev);
421 did = pci_get_device(dev);
423 for (d = emx_devices; d->desc != NULL; ++d) {
424 if (vid == d->vid && did == d->did) {
425 device_set_desc(dev, d->desc);
426 device_set_async_attach(dev, TRUE);
434 emx_attach(device_t dev)
436 struct emx_softc *sc = device_get_softc(dev);
437 int error = 0, i, throttle, msi_enable, tx_ring_max;
439 uint16_t eeprom_data, device_id, apme_mask;
440 driver_intr_t *intr_func;
441 char flowctrl[IFM_ETH_FC_STRLEN];
443 int offset, offset_def;
449 for (i = 0; i < EMX_NRX_RING; ++i) {
450 sc->rx_data[i].sc = sc;
451 sc->rx_data[i].idx = i;
457 for (i = 0; i < EMX_NTX_RING; ++i) {
458 sc->tx_data[i].sc = sc;
459 sc->tx_data[i].idx = i;
463 * Initialize serializers
465 lwkt_serialize_init(&sc->main_serialize);
466 for (i = 0; i < EMX_NTX_RING; ++i)
467 lwkt_serialize_init(&sc->tx_data[i].tx_serialize);
468 for (i = 0; i < EMX_NRX_RING; ++i)
469 lwkt_serialize_init(&sc->rx_data[i].rx_serialize);
472 * Initialize serializer array
476 KKASSERT(i < EMX_NSERIALIZE);
477 sc->serializes[i++] = &sc->main_serialize;
479 KKASSERT(i < EMX_NSERIALIZE);
480 sc->serializes[i++] = &sc->tx_data[0].tx_serialize;
481 KKASSERT(i < EMX_NSERIALIZE);
482 sc->serializes[i++] = &sc->tx_data[1].tx_serialize;
484 KKASSERT(i < EMX_NSERIALIZE);
485 sc->serializes[i++] = &sc->rx_data[0].rx_serialize;
486 KKASSERT(i < EMX_NSERIALIZE);
487 sc->serializes[i++] = &sc->rx_data[1].rx_serialize;
489 KKASSERT(i == EMX_NSERIALIZE);
491 ifmedia_init(&sc->media, IFM_IMASK | IFM_ETH_FCMASK,
492 emx_media_change, emx_media_status);
493 callout_init_mp(&sc->timer);
495 sc->dev = sc->osdep.dev = dev;
498 * Determine hardware and mac type
500 sc->hw.vendor_id = pci_get_vendor(dev);
501 sc->hw.device_id = pci_get_device(dev);
502 sc->hw.revision_id = pci_get_revid(dev);
503 sc->hw.subsystem_vendor_id = pci_get_subvendor(dev);
504 sc->hw.subsystem_device_id = pci_get_subdevice(dev);
506 if (e1000_set_mac_type(&sc->hw))
509 /* Enable bus mastering */
510 pci_enable_busmaster(dev);
515 sc->memory_rid = EMX_BAR_MEM;
516 sc->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
517 &sc->memory_rid, RF_ACTIVE);
518 if (sc->memory == NULL) {
519 device_printf(dev, "Unable to allocate bus resource: memory\n");
523 sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->memory);
524 sc->osdep.mem_bus_space_handle = rman_get_bushandle(sc->memory);
526 /* XXX This is quite goofy, it is not actually used */
527 sc->hw.hw_addr = (uint8_t *)&sc->osdep.mem_bus_space_handle;
530 * Don't enable MSI-X on 82574, see:
531 * 82574 specification update errata #15
533 * Don't enable MSI on 82571/82572, see:
534 * 82571/82572 specification update errata #63
536 msi_enable = emx_msi_enable;
538 (sc->hw.mac.type == e1000_82571 ||
539 sc->hw.mac.type == e1000_82572))
545 sc->intr_type = pci_alloc_1intr(dev, msi_enable,
546 &sc->intr_rid, &intr_flags);
548 if (sc->intr_type == PCI_INTR_TYPE_LEGACY) {
551 unshared = device_getenv_int(dev, "irq.unshared", 0);
553 sc->flags |= EMX_FLAG_SHARED_INTR;
555 device_printf(dev, "IRQ shared\n");
557 intr_flags &= ~RF_SHAREABLE;
559 device_printf(dev, "IRQ unshared\n");
563 sc->intr_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->intr_rid,
565 if (sc->intr_res == NULL) {
566 device_printf(dev, "Unable to allocate bus resource: %s\n",
567 sc->intr_type == PCI_INTR_TYPE_MSI ? "MSI" : "legacy intr");
569 /* Retry with MSI. */
571 sc->flags &= ~EMX_FLAG_SHARED_INTR;
578 /* Save PCI command register for Shared Code */
579 sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
580 sc->hw.back = &sc->osdep;
583 * For I217/I218, we need to map the flash memory and this
584 * must happen after the MAC is identified.
586 if (sc->hw.mac.type == e1000_pch_lpt) {
587 sc->flash_rid = EMX_BAR_FLASH;
589 sc->flash = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
590 &sc->flash_rid, RF_ACTIVE);
591 if (sc->flash == NULL) {
592 device_printf(dev, "Mapping of Flash failed\n");
596 sc->osdep.flash_bus_space_tag = rman_get_bustag(sc->flash);
597 sc->osdep.flash_bus_space_handle =
598 rman_get_bushandle(sc->flash);
601 * This is used in the shared code
602 * XXX this goof is actually not used.
604 sc->hw.flash_address = (uint8_t *)sc->flash;
607 /* Do Shared Code initialization */
608 if (e1000_setup_init_funcs(&sc->hw, TRUE)) {
609 device_printf(dev, "Setup of Shared code failed\n");
613 e1000_get_bus_info(&sc->hw);
615 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG;
616 sc->hw.phy.autoneg_wait_to_complete = FALSE;
617 sc->hw.phy.autoneg_advertised = EMX_AUTONEG_ADV_DEFAULT;
620 * Interrupt throttle rate
622 throttle = device_getenv_int(dev, "int_throttle_ceil",
623 emx_int_throttle_ceil);
625 sc->int_throttle_ceil = 0;
628 throttle = EMX_DEFAULT_ITR;
630 /* Recalculate the tunable value to get the exact frequency. */
631 throttle = 1000000000 / 256 / throttle;
633 /* Upper 16bits of ITR is reserved and should be zero */
634 if (throttle & 0xffff0000)
635 throttle = 1000000000 / 256 / EMX_DEFAULT_ITR;
637 sc->int_throttle_ceil = 1000000000 / 256 / throttle;
640 e1000_init_script_state_82541(&sc->hw, TRUE);
641 e1000_set_tbi_compatibility_82543(&sc->hw, TRUE);
644 if (sc->hw.phy.media_type == e1000_media_type_copper) {
645 sc->hw.phy.mdix = EMX_AUTO_ALL_MODES;
646 sc->hw.phy.disable_polarity_correction = FALSE;
647 sc->hw.phy.ms_type = EMX_MASTER_SLAVE;
650 /* Set the frame limits assuming standard ethernet sized frames. */
651 sc->hw.mac.max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN;
653 /* This controls when hardware reports transmit completion status. */
654 sc->hw.mac.report_tx_early = 1;
656 /* Calculate # of RX rings */
657 sc->rx_ring_cnt = device_getenv_int(dev, "rxr", emx_rxr);
658 sc->rx_ring_cnt = if_ring_count2(sc->rx_ring_cnt, EMX_NRX_RING);
661 * Calculate # of TX rings
664 if (sc->hw.mac.type == e1000_82571 ||
665 sc->hw.mac.type == e1000_82572 ||
666 sc->hw.mac.type == e1000_80003es2lan ||
667 sc->hw.mac.type == e1000_pch_lpt ||
668 sc->hw.mac.type == e1000_pch_spt ||
669 sc->hw.mac.type == e1000_82574)
670 tx_ring_max = EMX_NTX_RING;
671 sc->tx_ring_cnt = device_getenv_int(dev, "txr", emx_txr);
672 sc->tx_ring_cnt = if_ring_count2(sc->tx_ring_cnt, tx_ring_max);
674 /* Allocate RX/TX rings' busdma(9) stuffs */
675 error = emx_dma_alloc(sc);
679 /* Allocate multicast array memory. */
680 sc->mta = kmalloc(ETH_ADDR_LEN * EMX_MCAST_ADDR_MAX,
683 /* Indicate SOL/IDER usage */
684 if (e1000_check_reset_block(&sc->hw)) {
686 "PHY reset is blocked due to SOL/IDER session.\n");
689 /* Disable EEE on I217/I218 */
690 sc->hw.dev_spec.ich8lan.eee_disable = 1;
693 * Start from a known state, this is important in reading the
694 * nvm and mac from that.
696 e1000_reset_hw(&sc->hw);
698 /* Make sure we have a good EEPROM before we read from it */
699 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
701 * Some PCI-E parts fail the first check due to
702 * the link being in sleep state, call it again,
703 * if it fails a second time its a real issue.
705 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
707 "The EEPROM Checksum Is Not Valid\n");
713 /* Copy the permanent MAC address out of the EEPROM */
714 if (e1000_read_mac_addr(&sc->hw) < 0) {
715 device_printf(dev, "EEPROM read error while reading MAC"
720 if (!emx_is_valid_eaddr(sc->hw.mac.addr)) {
721 device_printf(dev, "Invalid MAC address\n");
726 /* Disable ULP support */
727 e1000_disable_ulp_lpt_lp(&sc->hw, TRUE);
729 /* Determine if we have to control management hardware */
730 if (e1000_enable_mng_pass_thru(&sc->hw))
731 sc->flags |= EMX_FLAG_HAS_MGMT;
736 apme_mask = EMX_EEPROM_APME;
738 switch (sc->hw.mac.type) {
740 sc->flags |= EMX_FLAG_HAS_AMT;
745 case e1000_80003es2lan:
746 if (sc->hw.bus.func == 1) {
747 e1000_read_nvm(&sc->hw,
748 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
750 e1000_read_nvm(&sc->hw,
751 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
756 e1000_read_nvm(&sc->hw,
757 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
760 if (eeprom_data & apme_mask)
761 sc->wol = E1000_WUFC_MAG | E1000_WUFC_MC;
764 * We have the eeprom settings, now apply the special cases
765 * where the eeprom may be wrong or the board won't support
766 * wake on lan on a particular port
768 device_id = pci_get_device(dev);
770 case E1000_DEV_ID_82571EB_FIBER:
772 * Wake events only supported on port A for dual fiber
773 * regardless of eeprom setting
775 if (E1000_READ_REG(&sc->hw, E1000_STATUS) &
780 case E1000_DEV_ID_82571EB_QUAD_COPPER:
781 case E1000_DEV_ID_82571EB_QUAD_FIBER:
782 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:
783 /* if quad port sc, disable WoL on all but port A */
784 if (emx_global_quad_port_a != 0)
786 /* Reset for multiple quad port adapters */
787 if (++emx_global_quad_port_a == 4)
788 emx_global_quad_port_a = 0;
792 /* XXX disable wol */
797 * NPOLLING RX CPU offset
799 if (sc->rx_ring_cnt == ncpus2) {
802 offset_def = (sc->rx_ring_cnt * device_get_unit(dev)) % ncpus2;
803 offset = device_getenv_int(dev, "npoll.rxoff", offset_def);
804 if (offset >= ncpus2 ||
805 offset % sc->rx_ring_cnt != 0) {
806 device_printf(dev, "invalid npoll.rxoff %d, use %d\n",
811 sc->rx_npoll_off = offset;
814 * NPOLLING TX CPU offset
816 if (sc->tx_ring_cnt == ncpus2) {
819 offset_def = (sc->tx_ring_cnt * device_get_unit(dev)) % ncpus2;
820 offset = device_getenv_int(dev, "npoll.txoff", offset_def);
821 if (offset >= ncpus2 ||
822 offset % sc->tx_ring_cnt != 0) {
823 device_printf(dev, "invalid npoll.txoff %d, use %d\n",
828 sc->tx_npoll_off = offset;
830 sc->tx_ring_inuse = emx_get_txring_inuse(sc, FALSE);
832 /* Setup flow control. */
833 device_getenv_string(dev, "flow_ctrl", flowctrl, sizeof(flowctrl),
835 sc->ifm_flowctrl = ifmedia_str2ethfc(flowctrl);
837 /* Setup OS specific network interface */
840 /* Add sysctl tree, must after em_setup_ifp() */
843 /* Reset the hardware */
844 error = emx_reset(sc);
847 * Some 82573 parts fail the first reset, call it again,
848 * if it fails a second time its a real issue.
850 error = emx_reset(sc);
852 device_printf(dev, "Unable to reset the hardware\n");
853 ether_ifdetach(&sc->arpcom.ac_if);
858 /* Initialize statistics */
859 emx_update_stats(sc);
861 sc->hw.mac.get_link_status = 1;
862 emx_update_link_status(sc);
864 /* Non-AMT based hardware can now take control from firmware */
865 if ((sc->flags & (EMX_FLAG_HAS_MGMT | EMX_FLAG_HAS_AMT)) ==
867 emx_get_hw_control(sc);
870 * Missing Interrupt Following ICR read:
872 * 82571/82572 specification update errata #76
873 * 82573 specification update errata #31
874 * 82574 specification update errata #12
876 intr_func = emx_intr;
877 if ((sc->flags & EMX_FLAG_SHARED_INTR) &&
878 (sc->hw.mac.type == e1000_82571 ||
879 sc->hw.mac.type == e1000_82572 ||
880 sc->hw.mac.type == e1000_82573 ||
881 sc->hw.mac.type == e1000_82574))
882 intr_func = emx_intr_mask;
884 error = bus_setup_intr(dev, sc->intr_res, INTR_MPSAFE, intr_func, sc,
885 &sc->intr_tag, &sc->main_serialize);
887 device_printf(dev, "Failed to register interrupt handler");
888 ether_ifdetach(&sc->arpcom.ac_if);
898 emx_detach(device_t dev)
900 struct emx_softc *sc = device_get_softc(dev);
902 if (device_is_attached(dev)) {
903 struct ifnet *ifp = &sc->arpcom.ac_if;
905 ifnet_serialize_all(ifp);
909 e1000_phy_hw_reset(&sc->hw);
912 emx_rel_hw_control(sc);
915 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
916 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
920 bus_teardown_intr(dev, sc->intr_res, sc->intr_tag);
922 ifnet_deserialize_all(ifp);
925 } else if (sc->memory != NULL) {
926 emx_rel_hw_control(sc);
929 ifmedia_removeall(&sc->media);
930 bus_generic_detach(dev);
932 if (sc->intr_res != NULL) {
933 bus_release_resource(dev, SYS_RES_IRQ, sc->intr_rid,
937 if (sc->intr_type == PCI_INTR_TYPE_MSI)
938 pci_release_msi(dev);
940 if (sc->memory != NULL) {
941 bus_release_resource(dev, SYS_RES_MEMORY, sc->memory_rid,
945 if (sc->flash != NULL) {
946 bus_release_resource(dev, SYS_RES_MEMORY, sc->flash_rid,
953 kfree(sc->mta, M_DEVBUF);
959 emx_shutdown(device_t dev)
961 return emx_suspend(dev);
965 emx_suspend(device_t dev)
967 struct emx_softc *sc = device_get_softc(dev);
968 struct ifnet *ifp = &sc->arpcom.ac_if;
970 ifnet_serialize_all(ifp);
975 emx_rel_hw_control(sc);
978 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
979 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
983 ifnet_deserialize_all(ifp);
985 return bus_generic_suspend(dev);
989 emx_resume(device_t dev)
991 struct emx_softc *sc = device_get_softc(dev);
992 struct ifnet *ifp = &sc->arpcom.ac_if;
995 ifnet_serialize_all(ifp);
999 for (i = 0; i < sc->tx_ring_inuse; ++i)
1000 ifsq_devstart_sched(sc->tx_data[i].ifsq);
1002 ifnet_deserialize_all(ifp);
1004 return bus_generic_resume(dev);
1008 emx_start(struct ifnet *ifp, struct ifaltq_subque *ifsq)
1010 struct emx_softc *sc = ifp->if_softc;
1011 struct emx_txdata *tdata = ifsq_get_priv(ifsq);
1012 struct mbuf *m_head;
1013 int idx = -1, nsegs = 0;
1015 KKASSERT(tdata->ifsq == ifsq);
1016 ASSERT_SERIALIZED(&tdata->tx_serialize);
1018 if ((ifp->if_flags & IFF_RUNNING) == 0 || ifsq_is_oactive(ifsq))
1021 if (!sc->link_active || (tdata->tx_flags & EMX_TXFLAG_ENABLED) == 0) {
1026 while (!ifsq_is_empty(ifsq)) {
1027 /* Now do we at least have a minimal? */
1028 if (EMX_IS_OACTIVE(tdata)) {
1029 emx_tx_collect(tdata);
1030 if (EMX_IS_OACTIVE(tdata)) {
1031 ifsq_set_oactive(ifsq);
1037 m_head = ifsq_dequeue(ifsq);
1041 if (emx_encap(tdata, &m_head, &nsegs, &idx)) {
1042 IFNET_STAT_INC(ifp, oerrors, 1);
1043 emx_tx_collect(tdata);
1048 * TX interrupt are aggressively aggregated, so increasing
1049 * opackets at TX interrupt time will make the opackets
1050 * statistics vastly inaccurate; we do the opackets increment
1053 IFNET_STAT_INC(ifp, opackets, 1);
1055 if (nsegs >= tdata->tx_wreg_nsegs) {
1056 E1000_WRITE_REG(&sc->hw, E1000_TDT(tdata->idx), idx);
1061 /* Send a copy of the frame to the BPF listener */
1062 ETHER_BPF_MTAP(ifp, m_head);
1064 /* Set timeout in case hardware has problems transmitting. */
1065 tdata->tx_watchdog.wd_timer = EMX_TX_TIMEOUT;
1068 E1000_WRITE_REG(&sc->hw, E1000_TDT(tdata->idx), idx);
1072 emx_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
1074 struct emx_softc *sc = ifp->if_softc;
1075 struct ifreq *ifr = (struct ifreq *)data;
1076 uint16_t eeprom_data = 0;
1077 int max_frame_size, mask, reinit;
1080 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1084 switch (sc->hw.mac.type) {
1087 * 82573 only supports jumbo frames
1088 * if ASPM is disabled.
1090 e1000_read_nvm(&sc->hw, NVM_INIT_3GIO_3, 1,
1092 if (eeprom_data & NVM_WORD1A_ASPM_MASK) {
1093 max_frame_size = ETHER_MAX_LEN;
1098 /* Limit Jumbo Frame size */
1104 case e1000_80003es2lan:
1105 max_frame_size = 9234;
1109 max_frame_size = MAX_JUMBO_FRAME_SIZE;
1112 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN -
1118 ifp->if_mtu = ifr->ifr_mtu;
1119 sc->hw.mac.max_frame_size = ifp->if_mtu + ETHER_HDR_LEN +
1122 if (ifp->if_flags & IFF_RUNNING)
1127 if (ifp->if_flags & IFF_UP) {
1128 if ((ifp->if_flags & IFF_RUNNING)) {
1129 if ((ifp->if_flags ^ sc->if_flags) &
1130 (IFF_PROMISC | IFF_ALLMULTI)) {
1131 emx_disable_promisc(sc);
1132 emx_set_promisc(sc);
1137 } else if (ifp->if_flags & IFF_RUNNING) {
1140 sc->if_flags = ifp->if_flags;
1145 if (ifp->if_flags & IFF_RUNNING) {
1146 emx_disable_intr(sc);
1148 #ifdef IFPOLL_ENABLE
1149 if (!(ifp->if_flags & IFF_NPOLLING))
1151 emx_enable_intr(sc);
1156 /* Check SOL/IDER usage */
1157 if (e1000_check_reset_block(&sc->hw)) {
1158 device_printf(sc->dev, "Media change is"
1159 " blocked due to SOL/IDER session.\n");
1165 error = ifmedia_ioctl(ifp, ifr, &sc->media, command);
1170 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1171 if (mask & IFCAP_RXCSUM) {
1172 ifp->if_capenable ^= IFCAP_RXCSUM;
1175 if (mask & IFCAP_VLAN_HWTAGGING) {
1176 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1179 if (mask & IFCAP_TXCSUM) {
1180 ifp->if_capenable ^= IFCAP_TXCSUM;
1181 if (ifp->if_capenable & IFCAP_TXCSUM)
1182 ifp->if_hwassist |= EMX_CSUM_FEATURES;
1184 ifp->if_hwassist &= ~EMX_CSUM_FEATURES;
1186 if (mask & IFCAP_TSO) {
1187 ifp->if_capenable ^= IFCAP_TSO;
1188 if (ifp->if_capenable & IFCAP_TSO)
1189 ifp->if_hwassist |= CSUM_TSO;
1191 ifp->if_hwassist &= ~CSUM_TSO;
1193 if (mask & IFCAP_RSS)
1194 ifp->if_capenable ^= IFCAP_RSS;
1195 if (reinit && (ifp->if_flags & IFF_RUNNING))
1200 error = ether_ioctl(ifp, command, data);
1207 emx_watchdog(struct ifaltq_subque *ifsq)
1209 struct emx_txdata *tdata = ifsq_get_priv(ifsq);
1210 struct ifnet *ifp = ifsq_get_ifp(ifsq);
1211 struct emx_softc *sc = ifp->if_softc;
1214 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1217 * The timer is set to 5 every time start queues a packet.
1218 * Then txeof keeps resetting it as long as it cleans at
1219 * least one descriptor.
1220 * Finally, anytime all descriptors are clean the timer is
1224 if (E1000_READ_REG(&sc->hw, E1000_TDT(tdata->idx)) ==
1225 E1000_READ_REG(&sc->hw, E1000_TDH(tdata->idx))) {
1227 * If we reach here, all TX jobs are completed and
1228 * the TX engine should have been idled for some time.
1229 * We don't need to call ifsq_devstart_sched() here.
1231 ifsq_clr_oactive(ifsq);
1232 tdata->tx_watchdog.wd_timer = 0;
1237 * If we are in this routine because of pause frames, then
1238 * don't reset the hardware.
1240 if (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_TXOFF) {
1241 tdata->tx_watchdog.wd_timer = EMX_TX_TIMEOUT;
1245 if_printf(ifp, "TX %d watchdog timeout -- resetting\n", tdata->idx);
1247 IFNET_STAT_INC(ifp, oerrors, 1);
1250 for (i = 0; i < sc->tx_ring_inuse; ++i)
1251 ifsq_devstart_sched(sc->tx_data[i].ifsq);
1257 struct emx_softc *sc = xsc;
1258 struct ifnet *ifp = &sc->arpcom.ac_if;
1259 device_t dev = sc->dev;
1263 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1267 /* Get the latest mac address, User can use a LAA */
1268 bcopy(IF_LLADDR(ifp), sc->hw.mac.addr, ETHER_ADDR_LEN);
1270 /* Put the address into the Receive Address Array */
1271 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0);
1274 * With the 82571 sc, RAR[0] may be overwritten
1275 * when the other port is reset, we make a duplicate
1276 * in RAR[14] for that eventuality, this assures
1277 * the interface continues to function.
1279 if (sc->hw.mac.type == e1000_82571) {
1280 e1000_set_laa_state_82571(&sc->hw, TRUE);
1281 e1000_rar_set(&sc->hw, sc->hw.mac.addr,
1282 E1000_RAR_ENTRIES - 1);
1285 /* Initialize the hardware */
1286 if (emx_reset(sc)) {
1287 device_printf(dev, "Unable to reset the hardware\n");
1288 /* XXX emx_stop()? */
1291 emx_update_link_status(sc);
1293 /* Setup VLAN support, basic and offload if available */
1294 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
1296 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) {
1299 ctrl = E1000_READ_REG(&sc->hw, E1000_CTRL);
1300 ctrl |= E1000_CTRL_VME;
1301 E1000_WRITE_REG(&sc->hw, E1000_CTRL, ctrl);
1304 /* Configure for OS presence */
1308 #ifdef IFPOLL_ENABLE
1309 if (ifp->if_flags & IFF_NPOLLING)
1312 sc->tx_ring_inuse = emx_get_txring_inuse(sc, polling);
1313 ifq_set_subq_mask(&ifp->if_snd, sc->tx_ring_inuse - 1);
1315 /* Prepare transmit descriptors and buffers */
1316 for (i = 0; i < sc->tx_ring_inuse; ++i)
1317 emx_init_tx_ring(&sc->tx_data[i]);
1318 emx_init_tx_unit(sc);
1320 /* Setup Multicast table */
1323 /* Prepare receive descriptors and buffers */
1324 for (i = 0; i < sc->rx_ring_cnt; ++i) {
1325 if (emx_init_rx_ring(&sc->rx_data[i])) {
1327 "Could not setup receive structures\n");
1332 emx_init_rx_unit(sc);
1334 /* Don't lose promiscuous settings */
1335 emx_set_promisc(sc);
1337 ifp->if_flags |= IFF_RUNNING;
1338 for (i = 0; i < sc->tx_ring_inuse; ++i) {
1339 ifsq_clr_oactive(sc->tx_data[i].ifsq);
1340 ifsq_watchdog_start(&sc->tx_data[i].tx_watchdog);
1343 callout_reset(&sc->timer, hz, emx_timer, sc);
1344 e1000_clear_hw_cntrs_base_generic(&sc->hw);
1346 /* MSI/X configuration for 82574 */
1347 if (sc->hw.mac.type == e1000_82574) {
1350 tmp = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
1351 tmp |= E1000_CTRL_EXT_PBA_CLR;
1352 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, tmp);
1355 * Set the IVAR - interrupt vector routing.
1356 * Each nibble represents a vector, high bit
1357 * is enable, other 3 bits are the MSIX table
1358 * entry, we map RXQ0 to 0, TXQ0 to 1, and
1359 * Link (other) to 2, hence the magic number.
1361 E1000_WRITE_REG(&sc->hw, E1000_IVAR, 0x800A0908);
1365 * Only enable interrupts if we are not polling, make sure
1366 * they are off otherwise.
1369 emx_disable_intr(sc);
1371 emx_enable_intr(sc);
1373 /* AMT based hardware can now take control from firmware */
1374 if ((sc->flags & (EMX_FLAG_HAS_MGMT | EMX_FLAG_HAS_AMT)) ==
1375 (EMX_FLAG_HAS_MGMT | EMX_FLAG_HAS_AMT))
1376 emx_get_hw_control(sc);
1382 emx_intr_body(xsc, TRUE);
1386 emx_intr_body(struct emx_softc *sc, boolean_t chk_asserted)
1388 struct ifnet *ifp = &sc->arpcom.ac_if;
1392 ASSERT_SERIALIZED(&sc->main_serialize);
1394 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
1396 if (chk_asserted && (reg_icr & E1000_ICR_INT_ASSERTED) == 0) {
1402 * XXX: some laptops trigger several spurious interrupts
1403 * on emx(4) when in the resume cycle. The ICR register
1404 * reports all-ones value in this case. Processing such
1405 * interrupts would lead to a freeze. I don't know why.
1407 if (reg_icr == 0xffffffff) {
1412 if (ifp->if_flags & IFF_RUNNING) {
1414 (E1000_ICR_RXT0 | E1000_ICR_RXDMT0 | E1000_ICR_RXO)) {
1417 for (i = 0; i < sc->rx_ring_cnt; ++i) {
1418 lwkt_serialize_enter(
1419 &sc->rx_data[i].rx_serialize);
1420 emx_rxeof(&sc->rx_data[i], -1);
1421 lwkt_serialize_exit(
1422 &sc->rx_data[i].rx_serialize);
1425 if (reg_icr & E1000_ICR_TXDW) {
1426 struct emx_txdata *tdata = &sc->tx_data[0];
1428 lwkt_serialize_enter(&tdata->tx_serialize);
1430 if (!ifsq_is_empty(tdata->ifsq))
1431 ifsq_devstart(tdata->ifsq);
1432 lwkt_serialize_exit(&tdata->tx_serialize);
1436 /* Link status change */
1437 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
1438 emx_serialize_skipmain(sc);
1440 callout_stop(&sc->timer);
1441 sc->hw.mac.get_link_status = 1;
1442 emx_update_link_status(sc);
1444 /* Deal with TX cruft when link lost */
1447 callout_reset(&sc->timer, hz, emx_timer, sc);
1449 emx_deserialize_skipmain(sc);
1452 if (reg_icr & E1000_ICR_RXO)
1459 emx_intr_mask(void *xsc)
1461 struct emx_softc *sc = xsc;
1463 E1000_WRITE_REG(&sc->hw, E1000_IMC, 0xffffffff);
1466 * ICR.INT_ASSERTED bit will never be set if IMS is 0,
1467 * so don't check it.
1469 emx_intr_body(sc, FALSE);
1470 E1000_WRITE_REG(&sc->hw, E1000_IMS, IMS_ENABLE_MASK);
1474 emx_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
1476 struct emx_softc *sc = ifp->if_softc;
1478 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1480 emx_update_link_status(sc);
1482 ifmr->ifm_status = IFM_AVALID;
1483 ifmr->ifm_active = IFM_ETHER;
1485 if (!sc->link_active) {
1486 if (sc->hw.mac.autoneg)
1487 ifmr->ifm_active |= IFM_NONE;
1489 ifmr->ifm_active |= sc->media.ifm_media;
1493 ifmr->ifm_status |= IFM_ACTIVE;
1494 if (sc->ifm_flowctrl & IFM_ETH_FORCEPAUSE)
1495 ifmr->ifm_active |= sc->ifm_flowctrl;
1497 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
1498 sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
1499 ifmr->ifm_active |= IFM_1000_SX | IFM_FDX;
1501 switch (sc->link_speed) {
1503 ifmr->ifm_active |= IFM_10_T;
1506 ifmr->ifm_active |= IFM_100_TX;
1510 ifmr->ifm_active |= IFM_1000_T;
1513 if (sc->link_duplex == FULL_DUPLEX)
1514 ifmr->ifm_active |= IFM_FDX;
1516 ifmr->ifm_active |= IFM_HDX;
1518 if (ifmr->ifm_active & IFM_FDX)
1519 ifmr->ifm_active |= e1000_fc2ifmedia(sc->hw.fc.current_mode);
1523 emx_media_change(struct ifnet *ifp)
1525 struct emx_softc *sc = ifp->if_softc;
1526 struct ifmedia *ifm = &sc->media;
1528 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1530 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1533 switch (IFM_SUBTYPE(ifm->ifm_media)) {
1535 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG;
1536 sc->hw.phy.autoneg_advertised = EMX_AUTONEG_ADV_DEFAULT;
1541 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG;
1542 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
1546 if (IFM_OPTIONS(ifm->ifm_media) & IFM_FDX) {
1547 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL;
1549 if (IFM_OPTIONS(ifm->ifm_media) &
1550 (IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE)) {
1552 if_printf(ifp, "Flow control is not "
1553 "allowed for half-duplex\n");
1557 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF;
1559 sc->hw.mac.autoneg = FALSE;
1560 sc->hw.phy.autoneg_advertised = 0;
1564 if (IFM_OPTIONS(ifm->ifm_media) & IFM_FDX) {
1565 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL;
1567 if (IFM_OPTIONS(ifm->ifm_media) &
1568 (IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE)) {
1570 if_printf(ifp, "Flow control is not "
1571 "allowed for half-duplex\n");
1575 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF;
1577 sc->hw.mac.autoneg = FALSE;
1578 sc->hw.phy.autoneg_advertised = 0;
1583 if_printf(ifp, "Unsupported media type %d\n",
1584 IFM_SUBTYPE(ifm->ifm_media));
1588 sc->ifm_flowctrl = ifm->ifm_media & IFM_ETH_FCMASK;
1590 if (ifp->if_flags & IFF_RUNNING)
1597 emx_encap(struct emx_txdata *tdata, struct mbuf **m_headp,
1598 int *segs_used, int *idx)
1600 bus_dma_segment_t segs[EMX_MAX_SCATTER];
1602 struct emx_txbuf *tx_buffer, *tx_buffer_mapped;
1603 struct e1000_tx_desc *ctxd = NULL;
1604 struct mbuf *m_head = *m_headp;
1605 uint32_t txd_upper, txd_lower, cmd = 0;
1606 int maxsegs, nsegs, i, j, first, last = 0, error;
1608 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
1609 error = emx_tso_pullup(tdata, m_headp);
1615 txd_upper = txd_lower = 0;
1618 * Capture the first descriptor index, this descriptor
1619 * will have the index of the EOP which is the only one
1620 * that now gets a DONE bit writeback.
1622 first = tdata->next_avail_tx_desc;
1623 tx_buffer = &tdata->tx_buf[first];
1624 tx_buffer_mapped = tx_buffer;
1625 map = tx_buffer->map;
1627 maxsegs = tdata->num_tx_desc_avail - EMX_TX_RESERVED;
1628 KASSERT(maxsegs >= tdata->spare_tx_desc, ("not enough spare TX desc"));
1629 if (maxsegs > EMX_MAX_SCATTER)
1630 maxsegs = EMX_MAX_SCATTER;
1632 error = bus_dmamap_load_mbuf_defrag(tdata->txtag, map, m_headp,
1633 segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
1639 bus_dmamap_sync(tdata->txtag, map, BUS_DMASYNC_PREWRITE);
1642 tdata->tx_nsegs += nsegs;
1643 *segs_used += nsegs;
1645 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
1646 /* TSO will consume one TX desc */
1647 i = emx_tso_setup(tdata, m_head, &txd_upper, &txd_lower);
1648 tdata->tx_nsegs += i;
1650 } else if (m_head->m_pkthdr.csum_flags & EMX_CSUM_FEATURES) {
1651 /* TX csum offloading will consume one TX desc */
1652 i = emx_txcsum(tdata, m_head, &txd_upper, &txd_lower);
1653 tdata->tx_nsegs += i;
1657 /* Handle VLAN tag */
1658 if (m_head->m_flags & M_VLANTAG) {
1659 /* Set the vlan id. */
1660 txd_upper |= (htole16(m_head->m_pkthdr.ether_vlantag) << 16);
1661 /* Tell hardware to add tag */
1662 txd_lower |= htole32(E1000_TXD_CMD_VLE);
1665 i = tdata->next_avail_tx_desc;
1667 /* Set up our transmit descriptors */
1668 for (j = 0; j < nsegs; j++) {
1669 tx_buffer = &tdata->tx_buf[i];
1670 ctxd = &tdata->tx_desc_base[i];
1672 ctxd->buffer_addr = htole64(segs[j].ds_addr);
1673 ctxd->lower.data = htole32(E1000_TXD_CMD_IFCS |
1674 txd_lower | segs[j].ds_len);
1675 ctxd->upper.data = htole32(txd_upper);
1678 if (++i == tdata->num_tx_desc)
1682 tdata->next_avail_tx_desc = i;
1684 KKASSERT(tdata->num_tx_desc_avail > nsegs);
1685 tdata->num_tx_desc_avail -= nsegs;
1687 tx_buffer->m_head = m_head;
1688 tx_buffer_mapped->map = tx_buffer->map;
1689 tx_buffer->map = map;
1691 if (tdata->tx_nsegs >= tdata->tx_intr_nsegs) {
1692 tdata->tx_nsegs = 0;
1695 * Report Status (RS) is turned on
1696 * every tx_intr_nsegs descriptors.
1698 cmd = E1000_TXD_CMD_RS;
1701 * Keep track of the descriptor, which will
1702 * be written back by hardware.
1704 tdata->tx_dd[tdata->tx_dd_tail] = last;
1705 EMX_INC_TXDD_IDX(tdata->tx_dd_tail);
1706 KKASSERT(tdata->tx_dd_tail != tdata->tx_dd_head);
1710 * Last Descriptor of Packet needs End Of Packet (EOP)
1712 ctxd->lower.data |= htole32(E1000_TXD_CMD_EOP | cmd);
1715 * Defer TDT updating, until enough descriptors are setup
1719 #ifdef EMX_TSS_DEBUG
1727 emx_set_promisc(struct emx_softc *sc)
1729 struct ifnet *ifp = &sc->arpcom.ac_if;
1732 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1734 if (ifp->if_flags & IFF_PROMISC) {
1735 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1736 /* Turn this on if you want to see bad packets */
1738 reg_rctl |= E1000_RCTL_SBP;
1739 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1740 } else if (ifp->if_flags & IFF_ALLMULTI) {
1741 reg_rctl |= E1000_RCTL_MPE;
1742 reg_rctl &= ~E1000_RCTL_UPE;
1743 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1748 emx_disable_promisc(struct emx_softc *sc)
1752 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1754 reg_rctl &= ~E1000_RCTL_UPE;
1755 reg_rctl &= ~E1000_RCTL_MPE;
1756 reg_rctl &= ~E1000_RCTL_SBP;
1757 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1761 emx_set_multi(struct emx_softc *sc)
1763 struct ifnet *ifp = &sc->arpcom.ac_if;
1764 struct ifmultiaddr *ifma;
1765 uint32_t reg_rctl = 0;
1770 bzero(mta, ETH_ADDR_LEN * EMX_MCAST_ADDR_MAX);
1772 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1773 if (ifma->ifma_addr->sa_family != AF_LINK)
1776 if (mcnt == EMX_MCAST_ADDR_MAX)
1779 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1780 &mta[mcnt * ETHER_ADDR_LEN], ETHER_ADDR_LEN);
1784 if (mcnt >= EMX_MCAST_ADDR_MAX) {
1785 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1786 reg_rctl |= E1000_RCTL_MPE;
1787 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1789 e1000_update_mc_addr_list(&sc->hw, mta, mcnt);
1794 * This routine checks for link status and updates statistics.
1797 emx_timer(void *xsc)
1799 struct emx_softc *sc = xsc;
1800 struct ifnet *ifp = &sc->arpcom.ac_if;
1802 lwkt_serialize_enter(&sc->main_serialize);
1804 emx_update_link_status(sc);
1805 emx_update_stats(sc);
1807 /* Reset LAA into RAR[0] on 82571 */
1808 if (e1000_get_laa_state_82571(&sc->hw) == TRUE)
1809 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0);
1811 if (emx_display_debug_stats && (ifp->if_flags & IFF_RUNNING))
1812 emx_print_hw_stats(sc);
1816 callout_reset(&sc->timer, hz, emx_timer, sc);
1818 lwkt_serialize_exit(&sc->main_serialize);
1822 emx_update_link_status(struct emx_softc *sc)
1824 struct e1000_hw *hw = &sc->hw;
1825 struct ifnet *ifp = &sc->arpcom.ac_if;
1826 device_t dev = sc->dev;
1827 uint32_t link_check = 0;
1829 /* Get the cached link value or read phy for real */
1830 switch (hw->phy.media_type) {
1831 case e1000_media_type_copper:
1832 if (hw->mac.get_link_status) {
1833 /* Do the work to read phy */
1834 e1000_check_for_link(hw);
1835 link_check = !hw->mac.get_link_status;
1836 if (link_check) /* ESB2 fix */
1837 e1000_cfg_on_link_up(hw);
1843 case e1000_media_type_fiber:
1844 e1000_check_for_link(hw);
1845 link_check = E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU;
1848 case e1000_media_type_internal_serdes:
1849 e1000_check_for_link(hw);
1850 link_check = sc->hw.mac.serdes_has_link;
1853 case e1000_media_type_unknown:
1858 /* Now check for a transition */
1859 if (link_check && sc->link_active == 0) {
1860 e1000_get_speed_and_duplex(hw, &sc->link_speed,
1864 * Check if we should enable/disable SPEED_MODE bit on
1867 if (sc->link_speed != SPEED_1000 &&
1868 (hw->mac.type == e1000_82571 ||
1869 hw->mac.type == e1000_82572)) {
1872 tarc0 = E1000_READ_REG(hw, E1000_TARC(0));
1873 tarc0 &= ~EMX_TARC_SPEED_MODE;
1874 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0);
1877 char flowctrl[IFM_ETH_FC_STRLEN];
1879 e1000_fc2str(hw->fc.current_mode, flowctrl,
1881 device_printf(dev, "Link is up %d Mbps %s, "
1882 "Flow control: %s\n",
1884 (sc->link_duplex == FULL_DUPLEX) ?
1885 "Full Duplex" : "Half Duplex",
1888 if (sc->ifm_flowctrl & IFM_ETH_FORCEPAUSE)
1889 e1000_force_flowctrl(hw, sc->ifm_flowctrl);
1890 sc->link_active = 1;
1892 ifp->if_baudrate = sc->link_speed * 1000000;
1893 ifp->if_link_state = LINK_STATE_UP;
1894 if_link_state_change(ifp);
1895 } else if (!link_check && sc->link_active == 1) {
1896 ifp->if_baudrate = sc->link_speed = 0;
1897 sc->link_duplex = 0;
1899 device_printf(dev, "Link is Down\n");
1900 sc->link_active = 0;
1901 ifp->if_link_state = LINK_STATE_DOWN;
1902 if_link_state_change(ifp);
1907 emx_stop(struct emx_softc *sc)
1909 struct ifnet *ifp = &sc->arpcom.ac_if;
1912 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1914 emx_disable_intr(sc);
1916 callout_stop(&sc->timer);
1918 ifp->if_flags &= ~IFF_RUNNING;
1919 for (i = 0; i < sc->tx_ring_cnt; ++i) {
1920 struct emx_txdata *tdata = &sc->tx_data[i];
1922 ifsq_clr_oactive(tdata->ifsq);
1923 ifsq_watchdog_stop(&tdata->tx_watchdog);
1924 tdata->tx_flags &= ~EMX_TXFLAG_ENABLED;
1928 * Disable multiple receive queues.
1931 * We should disable multiple receive queues before
1932 * resetting the hardware.
1934 E1000_WRITE_REG(&sc->hw, E1000_MRQC, 0);
1936 e1000_reset_hw(&sc->hw);
1937 E1000_WRITE_REG(&sc->hw, E1000_WUC, 0);
1939 for (i = 0; i < sc->tx_ring_cnt; ++i)
1940 emx_free_tx_ring(&sc->tx_data[i]);
1941 for (i = 0; i < sc->rx_ring_cnt; ++i)
1942 emx_free_rx_ring(&sc->rx_data[i]);
1946 emx_reset(struct emx_softc *sc)
1948 device_t dev = sc->dev;
1949 uint16_t rx_buffer_size;
1952 /* Set up smart power down as default off on newer adapters. */
1953 if (!emx_smart_pwr_down &&
1954 (sc->hw.mac.type == e1000_82571 ||
1955 sc->hw.mac.type == e1000_82572)) {
1956 uint16_t phy_tmp = 0;
1958 /* Speed up time to link by disabling smart power down. */
1959 e1000_read_phy_reg(&sc->hw,
1960 IGP02E1000_PHY_POWER_MGMT, &phy_tmp);
1961 phy_tmp &= ~IGP02E1000_PM_SPD;
1962 e1000_write_phy_reg(&sc->hw,
1963 IGP02E1000_PHY_POWER_MGMT, phy_tmp);
1967 * Packet Buffer Allocation (PBA)
1968 * Writing PBA sets the receive portion of the buffer
1969 * the remainder is used for the transmit buffer.
1971 switch (sc->hw.mac.type) {
1972 /* Total Packet Buffer on these is 48K */
1975 case e1000_80003es2lan:
1976 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1979 case e1000_82573: /* 82573: Total Packet Buffer is 32K */
1980 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
1984 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
1989 pba = E1000_PBA_26K;
1993 /* Devices before 82547 had a Packet Buffer of 64K. */
1994 if (sc->hw.mac.max_frame_size > 8192)
1995 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
1997 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */
1999 E1000_WRITE_REG(&sc->hw, E1000_PBA, pba);
2002 * These parameters control the automatic generation (Tx) and
2003 * response (Rx) to Ethernet PAUSE frames.
2004 * - High water mark should allow for at least two frames to be
2005 * received after sending an XOFF.
2006 * - Low water mark works best when it is very near the high water mark.
2007 * This allows the receiver to restart by sending XON when it has
2008 * drained a bit. Here we use an arbitary value of 1500 which will
2009 * restart after one full frame is pulled from the buffer. There
2010 * could be several smaller frames in the buffer and if so they will
2011 * not trigger the XON until their total number reduces the buffer
2013 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
2015 rx_buffer_size = (E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff) << 10;
2017 sc->hw.fc.high_water = rx_buffer_size -
2018 roundup2(sc->hw.mac.max_frame_size, 1024);
2019 sc->hw.fc.low_water = sc->hw.fc.high_water - 1500;
2021 sc->hw.fc.pause_time = EMX_FC_PAUSE_TIME;
2022 sc->hw.fc.send_xon = TRUE;
2023 sc->hw.fc.requested_mode = e1000_ifmedia2fc(sc->ifm_flowctrl);
2026 * Device specific overrides/settings
2028 if (sc->hw.mac.type == e1000_pch_lpt ||
2029 sc->hw.mac.type == e1000_pch_spt) {
2030 sc->hw.fc.high_water = 0x5C20;
2031 sc->hw.fc.low_water = 0x5048;
2032 sc->hw.fc.pause_time = 0x0650;
2033 sc->hw.fc.refresh_time = 0x0400;
2034 /* Jumbos need adjusted PBA */
2035 if (sc->arpcom.ac_if.if_mtu > ETHERMTU)
2036 E1000_WRITE_REG(&sc->hw, E1000_PBA, 12);
2038 E1000_WRITE_REG(&sc->hw, E1000_PBA, 26);
2039 } else if (sc->hw.mac.type == e1000_80003es2lan) {
2040 sc->hw.fc.pause_time = 0xFFFF;
2043 /* Issue a global reset */
2044 e1000_reset_hw(&sc->hw);
2045 E1000_WRITE_REG(&sc->hw, E1000_WUC, 0);
2046 emx_disable_aspm(sc);
2048 if (e1000_init_hw(&sc->hw) < 0) {
2049 device_printf(dev, "Hardware Initialization Failed\n");
2053 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
2054 e1000_get_phy_info(&sc->hw);
2055 e1000_check_for_link(&sc->hw);
2061 emx_setup_ifp(struct emx_softc *sc)
2063 struct ifnet *ifp = &sc->arpcom.ac_if;
2066 if_initname(ifp, device_get_name(sc->dev),
2067 device_get_unit(sc->dev));
2069 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2070 ifp->if_init = emx_init;
2071 ifp->if_ioctl = emx_ioctl;
2072 ifp->if_start = emx_start;
2073 #ifdef IFPOLL_ENABLE
2074 ifp->if_npoll = emx_npoll;
2076 ifp->if_serialize = emx_serialize;
2077 ifp->if_deserialize = emx_deserialize;
2078 ifp->if_tryserialize = emx_tryserialize;
2080 ifp->if_serialize_assert = emx_serialize_assert;
2083 ifp->if_nmbclusters = sc->rx_ring_cnt * sc->rx_data[0].num_rx_desc;
2085 ifq_set_maxlen(&ifp->if_snd, sc->tx_data[0].num_tx_desc - 1);
2086 ifq_set_ready(&ifp->if_snd);
2087 ifq_set_subq_cnt(&ifp->if_snd, sc->tx_ring_cnt);
2089 ifp->if_mapsubq = ifq_mapsubq_mask;
2090 ifq_set_subq_mask(&ifp->if_snd, 0);
2092 ether_ifattach(ifp, sc->hw.mac.addr, NULL);
2094 ifp->if_capabilities = IFCAP_HWCSUM |
2095 IFCAP_VLAN_HWTAGGING |
2098 if (sc->rx_ring_cnt > 1)
2099 ifp->if_capabilities |= IFCAP_RSS;
2100 ifp->if_capenable = ifp->if_capabilities;
2101 ifp->if_hwassist = EMX_CSUM_FEATURES | CSUM_TSO;
2104 * Tell the upper layer(s) we support long frames.
2106 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
2108 for (i = 0; i < sc->tx_ring_cnt; ++i) {
2109 struct ifaltq_subque *ifsq = ifq_get_subq(&ifp->if_snd, i);
2110 struct emx_txdata *tdata = &sc->tx_data[i];
2112 ifsq_set_cpuid(ifsq, rman_get_cpuid(sc->intr_res));
2113 ifsq_set_priv(ifsq, tdata);
2114 ifsq_set_hw_serialize(ifsq, &tdata->tx_serialize);
2117 ifsq_watchdog_init(&tdata->tx_watchdog, ifsq, emx_watchdog);
2121 * Specify the media types supported by this sc and register
2122 * callbacks to update media and link information
2124 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
2125 sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
2126 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX | IFM_FDX,
2129 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T, 0, NULL);
2130 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T | IFM_FDX,
2132 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX, 0, NULL);
2133 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX,
2135 if (sc->hw.phy.type != e1000_phy_ife) {
2136 ifmedia_add(&sc->media,
2137 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
2140 ifmedia_add(&sc->media, IFM_ETHER | IFM_AUTO, 0, NULL);
2141 ifmedia_set(&sc->media, IFM_ETHER | IFM_AUTO | sc->ifm_flowctrl);
2145 * Workaround for SmartSpeed on 82541 and 82547 controllers
2148 emx_smartspeed(struct emx_softc *sc)
2152 if (sc->link_active || sc->hw.phy.type != e1000_phy_igp ||
2153 sc->hw.mac.autoneg == 0 ||
2154 (sc->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0)
2157 if (sc->smartspeed == 0) {
2159 * If Master/Slave config fault is asserted twice,
2160 * we assume back-to-back
2162 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp);
2163 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT))
2165 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp);
2166 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) {
2167 e1000_read_phy_reg(&sc->hw,
2168 PHY_1000T_CTRL, &phy_tmp);
2169 if (phy_tmp & CR_1000T_MS_ENABLE) {
2170 phy_tmp &= ~CR_1000T_MS_ENABLE;
2171 e1000_write_phy_reg(&sc->hw,
2172 PHY_1000T_CTRL, phy_tmp);
2174 if (sc->hw.mac.autoneg &&
2175 !e1000_phy_setup_autoneg(&sc->hw) &&
2176 !e1000_read_phy_reg(&sc->hw,
2177 PHY_CONTROL, &phy_tmp)) {
2178 phy_tmp |= MII_CR_AUTO_NEG_EN |
2179 MII_CR_RESTART_AUTO_NEG;
2180 e1000_write_phy_reg(&sc->hw,
2181 PHY_CONTROL, phy_tmp);
2186 } else if (sc->smartspeed == EMX_SMARTSPEED_DOWNSHIFT) {
2187 /* If still no link, perhaps using 2/3 pair cable */
2188 e1000_read_phy_reg(&sc->hw, PHY_1000T_CTRL, &phy_tmp);
2189 phy_tmp |= CR_1000T_MS_ENABLE;
2190 e1000_write_phy_reg(&sc->hw, PHY_1000T_CTRL, phy_tmp);
2191 if (sc->hw.mac.autoneg &&
2192 !e1000_phy_setup_autoneg(&sc->hw) &&
2193 !e1000_read_phy_reg(&sc->hw, PHY_CONTROL, &phy_tmp)) {
2194 phy_tmp |= MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG;
2195 e1000_write_phy_reg(&sc->hw, PHY_CONTROL, phy_tmp);
2199 /* Restart process after EMX_SMARTSPEED_MAX iterations */
2200 if (sc->smartspeed++ == EMX_SMARTSPEED_MAX)
2205 emx_create_tx_ring(struct emx_txdata *tdata)
2207 device_t dev = tdata->sc->dev;
2208 struct emx_txbuf *tx_buffer;
2209 int error, i, tsize, ntxd;
2212 * Validate number of transmit descriptors. It must not exceed
2213 * hardware maximum, and must be multiple of E1000_DBA_ALIGN.
2215 ntxd = device_getenv_int(dev, "txd", emx_txd);
2216 if ((ntxd * sizeof(struct e1000_tx_desc)) % EMX_DBA_ALIGN != 0 ||
2217 ntxd > EMX_MAX_TXD || ntxd < EMX_MIN_TXD) {
2218 device_printf(dev, "Using %d TX descriptors instead of %d!\n",
2219 EMX_DEFAULT_TXD, ntxd);
2220 tdata->num_tx_desc = EMX_DEFAULT_TXD;
2222 tdata->num_tx_desc = ntxd;
2226 * Allocate Transmit Descriptor ring
2228 tsize = roundup2(tdata->num_tx_desc * sizeof(struct e1000_tx_desc),
2230 tdata->tx_desc_base = bus_dmamem_coherent_any(tdata->sc->parent_dtag,
2231 EMX_DBA_ALIGN, tsize, BUS_DMA_WAITOK,
2232 &tdata->tx_desc_dtag, &tdata->tx_desc_dmap,
2233 &tdata->tx_desc_paddr);
2234 if (tdata->tx_desc_base == NULL) {
2235 device_printf(dev, "Unable to allocate tx_desc memory\n");
2239 tsize = __VM_CACHELINE_ALIGN(
2240 sizeof(struct emx_txbuf) * tdata->num_tx_desc);
2241 tdata->tx_buf = kmalloc_cachealign(tsize, M_DEVBUF, M_WAITOK | M_ZERO);
2244 * Create DMA tags for tx buffers
2246 error = bus_dma_tag_create(tdata->sc->parent_dtag, /* parent */
2247 1, 0, /* alignment, bounds */
2248 BUS_SPACE_MAXADDR, /* lowaddr */
2249 BUS_SPACE_MAXADDR, /* highaddr */
2250 NULL, NULL, /* filter, filterarg */
2251 EMX_TSO_SIZE, /* maxsize */
2252 EMX_MAX_SCATTER, /* nsegments */
2253 EMX_MAX_SEGSIZE, /* maxsegsize */
2254 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW |
2255 BUS_DMA_ONEBPAGE, /* flags */
2258 device_printf(dev, "Unable to allocate TX DMA tag\n");
2259 kfree(tdata->tx_buf, M_DEVBUF);
2260 tdata->tx_buf = NULL;
2265 * Create DMA maps for tx buffers
2267 for (i = 0; i < tdata->num_tx_desc; i++) {
2268 tx_buffer = &tdata->tx_buf[i];
2270 error = bus_dmamap_create(tdata->txtag,
2271 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
2274 device_printf(dev, "Unable to create TX DMA map\n");
2275 emx_destroy_tx_ring(tdata, i);
2281 * Setup TX parameters
2283 tdata->spare_tx_desc = EMX_TX_SPARE;
2284 tdata->tx_wreg_nsegs = EMX_DEFAULT_TXWREG;
2287 * Keep following relationship between spare_tx_desc, oact_tx_desc
2288 * and tx_intr_nsegs:
2289 * (spare_tx_desc + EMX_TX_RESERVED) <=
2290 * oact_tx_desc <= EMX_TX_OACTIVE_MAX <= tx_intr_nsegs
2292 tdata->oact_tx_desc = tdata->num_tx_desc / 8;
2293 if (tdata->oact_tx_desc > EMX_TX_OACTIVE_MAX)
2294 tdata->oact_tx_desc = EMX_TX_OACTIVE_MAX;
2295 if (tdata->oact_tx_desc < tdata->spare_tx_desc + EMX_TX_RESERVED)
2296 tdata->oact_tx_desc = tdata->spare_tx_desc + EMX_TX_RESERVED;
2298 tdata->tx_intr_nsegs = tdata->num_tx_desc / 16;
2299 if (tdata->tx_intr_nsegs < tdata->oact_tx_desc)
2300 tdata->tx_intr_nsegs = tdata->oact_tx_desc;
2303 * Pullup extra 4bytes into the first data segment for TSO, see:
2304 * 82571/82572 specification update errata #7
2306 * Same applies to I217 (and maybe I218 and I219).
2309 * 4bytes instead of 2bytes, which are mentioned in the errata,
2310 * are pulled; mainly to keep rest of the data properly aligned.
2312 if (tdata->sc->hw.mac.type == e1000_82571 ||
2313 tdata->sc->hw.mac.type == e1000_82572 ||
2314 tdata->sc->hw.mac.type == e1000_pch_lpt ||
2315 tdata->sc->hw.mac.type == e1000_pch_spt)
2316 tdata->tx_flags |= EMX_TXFLAG_TSO_PULLEX;
2322 emx_init_tx_ring(struct emx_txdata *tdata)
2324 /* Clear the old ring contents */
2325 bzero(tdata->tx_desc_base,
2326 sizeof(struct e1000_tx_desc) * tdata->num_tx_desc);
2329 tdata->next_avail_tx_desc = 0;
2330 tdata->next_tx_to_clean = 0;
2331 tdata->num_tx_desc_avail = tdata->num_tx_desc;
2333 tdata->tx_flags |= EMX_TXFLAG_ENABLED;
2334 if (tdata->sc->tx_ring_inuse > 1) {
2335 tdata->tx_flags |= EMX_TXFLAG_FORCECTX;
2337 if_printf(&tdata->sc->arpcom.ac_if,
2338 "TX %d force ctx setup\n", tdata->idx);
2344 emx_init_tx_unit(struct emx_softc *sc)
2346 uint32_t tctl, tarc, tipg = 0, txdctl;
2349 for (i = 0; i < sc->tx_ring_inuse; ++i) {
2350 struct emx_txdata *tdata = &sc->tx_data[i];
2353 /* Setup the Base and Length of the Tx Descriptor Ring */
2354 bus_addr = tdata->tx_desc_paddr;
2355 E1000_WRITE_REG(&sc->hw, E1000_TDLEN(i),
2356 tdata->num_tx_desc * sizeof(struct e1000_tx_desc));
2357 E1000_WRITE_REG(&sc->hw, E1000_TDBAH(i),
2358 (uint32_t)(bus_addr >> 32));
2359 E1000_WRITE_REG(&sc->hw, E1000_TDBAL(i),
2360 (uint32_t)bus_addr);
2361 /* Setup the HW Tx Head and Tail descriptor pointers */
2362 E1000_WRITE_REG(&sc->hw, E1000_TDT(i), 0);
2363 E1000_WRITE_REG(&sc->hw, E1000_TDH(i), 0);
2366 /* Set the default values for the Tx Inter Packet Gap timer */
2367 switch (sc->hw.mac.type) {
2368 case e1000_80003es2lan:
2369 tipg = DEFAULT_82543_TIPG_IPGR1;
2370 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 <<
2371 E1000_TIPG_IPGR2_SHIFT;
2375 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
2376 sc->hw.phy.media_type == e1000_media_type_internal_serdes)
2377 tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
2379 tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
2380 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
2381 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
2385 E1000_WRITE_REG(&sc->hw, E1000_TIPG, tipg);
2387 /* NOTE: 0 is not allowed for TIDV */
2388 E1000_WRITE_REG(&sc->hw, E1000_TIDV, 1);
2389 E1000_WRITE_REG(&sc->hw, E1000_TADV, 0);
2392 * Errata workaround (obtained from Linux). This is necessary
2393 * to make multiple TX queues work on 82574.
2394 * XXX can't find it in any published errata though.
2396 txdctl = E1000_READ_REG(&sc->hw, E1000_TXDCTL(0));
2397 E1000_WRITE_REG(&sc->hw, E1000_TXDCTL(1), txdctl);
2399 if (sc->hw.mac.type == e1000_82571 ||
2400 sc->hw.mac.type == e1000_82572) {
2401 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(0));
2402 tarc |= EMX_TARC_SPEED_MODE;
2403 E1000_WRITE_REG(&sc->hw, E1000_TARC(0), tarc);
2404 } else if (sc->hw.mac.type == e1000_80003es2lan) {
2405 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(0));
2407 E1000_WRITE_REG(&sc->hw, E1000_TARC(0), tarc);
2408 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(1));
2410 E1000_WRITE_REG(&sc->hw, E1000_TARC(1), tarc);
2413 /* Program the Transmit Control Register */
2414 tctl = E1000_READ_REG(&sc->hw, E1000_TCTL);
2415 tctl &= ~E1000_TCTL_CT;
2416 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
2417 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2418 tctl |= E1000_TCTL_MULR;
2420 /* This write will effectively turn on the transmit unit. */
2421 E1000_WRITE_REG(&sc->hw, E1000_TCTL, tctl);
2423 if (sc->hw.mac.type == e1000_82571 ||
2424 sc->hw.mac.type == e1000_82572 ||
2425 sc->hw.mac.type == e1000_80003es2lan) {
2426 /* Bit 28 of TARC1 must be cleared when MULR is enabled */
2427 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(1));
2429 E1000_WRITE_REG(&sc->hw, E1000_TARC(1), tarc);
2432 if (sc->tx_ring_inuse > 1) {
2433 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(0));
2434 tarc &= ~EMX_TARC_COUNT_MASK;
2436 E1000_WRITE_REG(&sc->hw, E1000_TARC(0), tarc);
2438 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(1));
2439 tarc &= ~EMX_TARC_COUNT_MASK;
2441 E1000_WRITE_REG(&sc->hw, E1000_TARC(1), tarc);
2446 emx_destroy_tx_ring(struct emx_txdata *tdata, int ndesc)
2448 struct emx_txbuf *tx_buffer;
2451 /* Free Transmit Descriptor ring */
2452 if (tdata->tx_desc_base) {
2453 bus_dmamap_unload(tdata->tx_desc_dtag, tdata->tx_desc_dmap);
2454 bus_dmamem_free(tdata->tx_desc_dtag, tdata->tx_desc_base,
2455 tdata->tx_desc_dmap);
2456 bus_dma_tag_destroy(tdata->tx_desc_dtag);
2458 tdata->tx_desc_base = NULL;
2461 if (tdata->tx_buf == NULL)
2464 for (i = 0; i < ndesc; i++) {
2465 tx_buffer = &tdata->tx_buf[i];
2467 KKASSERT(tx_buffer->m_head == NULL);
2468 bus_dmamap_destroy(tdata->txtag, tx_buffer->map);
2470 bus_dma_tag_destroy(tdata->txtag);
2472 kfree(tdata->tx_buf, M_DEVBUF);
2473 tdata->tx_buf = NULL;
2477 * The offload context needs to be set when we transfer the first
2478 * packet of a particular protocol (TCP/UDP). This routine has been
2479 * enhanced to deal with inserted VLAN headers.
2481 * If the new packet's ether header length, ip header length and
2482 * csum offloading type are same as the previous packet, we should
2483 * avoid allocating a new csum context descriptor; mainly to take
2484 * advantage of the pipeline effect of the TX data read request.
2486 * This function returns number of TX descrptors allocated for
2490 emx_txcsum(struct emx_txdata *tdata, struct mbuf *mp,
2491 uint32_t *txd_upper, uint32_t *txd_lower)
2493 struct e1000_context_desc *TXD;
2494 int curr_txd, ehdrlen, csum_flags;
2495 uint32_t cmd, hdr_len, ip_hlen;
2497 csum_flags = mp->m_pkthdr.csum_flags & EMX_CSUM_FEATURES;
2498 ip_hlen = mp->m_pkthdr.csum_iphlen;
2499 ehdrlen = mp->m_pkthdr.csum_lhlen;
2501 if ((tdata->tx_flags & EMX_TXFLAG_FORCECTX) == 0 &&
2502 tdata->csum_lhlen == ehdrlen && tdata->csum_iphlen == ip_hlen &&
2503 tdata->csum_flags == csum_flags) {
2505 * Same csum offload context as the previous packets;
2508 *txd_upper = tdata->csum_txd_upper;
2509 *txd_lower = tdata->csum_txd_lower;
2514 * Setup a new csum offload context.
2517 curr_txd = tdata->next_avail_tx_desc;
2518 TXD = (struct e1000_context_desc *)&tdata->tx_desc_base[curr_txd];
2522 /* Setup of IP header checksum. */
2523 if (csum_flags & CSUM_IP) {
2525 * Start offset for header checksum calculation.
2526 * End offset for header checksum calculation.
2527 * Offset of place to put the checksum.
2529 TXD->lower_setup.ip_fields.ipcss = ehdrlen;
2530 TXD->lower_setup.ip_fields.ipcse =
2531 htole16(ehdrlen + ip_hlen - 1);
2532 TXD->lower_setup.ip_fields.ipcso =
2533 ehdrlen + offsetof(struct ip, ip_sum);
2534 cmd |= E1000_TXD_CMD_IP;
2535 *txd_upper |= E1000_TXD_POPTS_IXSM << 8;
2537 hdr_len = ehdrlen + ip_hlen;
2539 if (csum_flags & CSUM_TCP) {
2541 * Start offset for payload checksum calculation.
2542 * End offset for payload checksum calculation.
2543 * Offset of place to put the checksum.
2545 TXD->upper_setup.tcp_fields.tucss = hdr_len;
2546 TXD->upper_setup.tcp_fields.tucse = htole16(0);
2547 TXD->upper_setup.tcp_fields.tucso =
2548 hdr_len + offsetof(struct tcphdr, th_sum);
2549 cmd |= E1000_TXD_CMD_TCP;
2550 *txd_upper |= E1000_TXD_POPTS_TXSM << 8;
2551 } else if (csum_flags & CSUM_UDP) {
2553 * Start offset for header checksum calculation.
2554 * End offset for header checksum calculation.
2555 * Offset of place to put the checksum.
2557 TXD->upper_setup.tcp_fields.tucss = hdr_len;
2558 TXD->upper_setup.tcp_fields.tucse = htole16(0);
2559 TXD->upper_setup.tcp_fields.tucso =
2560 hdr_len + offsetof(struct udphdr, uh_sum);
2561 *txd_upper |= E1000_TXD_POPTS_TXSM << 8;
2564 *txd_lower = E1000_TXD_CMD_DEXT | /* Extended descr type */
2565 E1000_TXD_DTYP_D; /* Data descr */
2567 /* Save the information for this csum offloading context */
2568 tdata->csum_lhlen = ehdrlen;
2569 tdata->csum_iphlen = ip_hlen;
2570 tdata->csum_flags = csum_flags;
2571 tdata->csum_txd_upper = *txd_upper;
2572 tdata->csum_txd_lower = *txd_lower;
2574 TXD->tcp_seg_setup.data = htole32(0);
2575 TXD->cmd_and_length =
2576 htole32(E1000_TXD_CMD_IFCS | E1000_TXD_CMD_DEXT | cmd);
2578 if (++curr_txd == tdata->num_tx_desc)
2581 KKASSERT(tdata->num_tx_desc_avail > 0);
2582 tdata->num_tx_desc_avail--;
2584 tdata->next_avail_tx_desc = curr_txd;
2589 emx_txeof(struct emx_txdata *tdata)
2591 struct emx_txbuf *tx_buffer;
2592 int first, num_avail;
2594 if (tdata->tx_dd_head == tdata->tx_dd_tail)
2597 if (tdata->num_tx_desc_avail == tdata->num_tx_desc)
2600 num_avail = tdata->num_tx_desc_avail;
2601 first = tdata->next_tx_to_clean;
2603 while (tdata->tx_dd_head != tdata->tx_dd_tail) {
2604 int dd_idx = tdata->tx_dd[tdata->tx_dd_head];
2605 struct e1000_tx_desc *tx_desc;
2607 tx_desc = &tdata->tx_desc_base[dd_idx];
2608 if (tx_desc->upper.fields.status & E1000_TXD_STAT_DD) {
2609 EMX_INC_TXDD_IDX(tdata->tx_dd_head);
2611 if (++dd_idx == tdata->num_tx_desc)
2614 while (first != dd_idx) {
2619 tx_buffer = &tdata->tx_buf[first];
2620 if (tx_buffer->m_head) {
2621 bus_dmamap_unload(tdata->txtag,
2623 m_freem(tx_buffer->m_head);
2624 tx_buffer->m_head = NULL;
2627 if (++first == tdata->num_tx_desc)
2634 tdata->next_tx_to_clean = first;
2635 tdata->num_tx_desc_avail = num_avail;
2637 if (tdata->tx_dd_head == tdata->tx_dd_tail) {
2638 tdata->tx_dd_head = 0;
2639 tdata->tx_dd_tail = 0;
2642 if (!EMX_IS_OACTIVE(tdata)) {
2643 ifsq_clr_oactive(tdata->ifsq);
2645 /* All clean, turn off the timer */
2646 if (tdata->num_tx_desc_avail == tdata->num_tx_desc)
2647 tdata->tx_watchdog.wd_timer = 0;
2652 emx_tx_collect(struct emx_txdata *tdata)
2654 struct emx_txbuf *tx_buffer;
2655 int tdh, first, num_avail, dd_idx = -1;
2657 if (tdata->num_tx_desc_avail == tdata->num_tx_desc)
2660 tdh = E1000_READ_REG(&tdata->sc->hw, E1000_TDH(tdata->idx));
2661 if (tdh == tdata->next_tx_to_clean)
2664 if (tdata->tx_dd_head != tdata->tx_dd_tail)
2665 dd_idx = tdata->tx_dd[tdata->tx_dd_head];
2667 num_avail = tdata->num_tx_desc_avail;
2668 first = tdata->next_tx_to_clean;
2670 while (first != tdh) {
2675 tx_buffer = &tdata->tx_buf[first];
2676 if (tx_buffer->m_head) {
2677 bus_dmamap_unload(tdata->txtag,
2679 m_freem(tx_buffer->m_head);
2680 tx_buffer->m_head = NULL;
2683 if (first == dd_idx) {
2684 EMX_INC_TXDD_IDX(tdata->tx_dd_head);
2685 if (tdata->tx_dd_head == tdata->tx_dd_tail) {
2686 tdata->tx_dd_head = 0;
2687 tdata->tx_dd_tail = 0;
2690 dd_idx = tdata->tx_dd[tdata->tx_dd_head];
2694 if (++first == tdata->num_tx_desc)
2697 tdata->next_tx_to_clean = first;
2698 tdata->num_tx_desc_avail = num_avail;
2700 if (!EMX_IS_OACTIVE(tdata)) {
2701 ifsq_clr_oactive(tdata->ifsq);
2703 /* All clean, turn off the timer */
2704 if (tdata->num_tx_desc_avail == tdata->num_tx_desc)
2705 tdata->tx_watchdog.wd_timer = 0;
2710 * When Link is lost sometimes there is work still in the TX ring
2711 * which will result in a watchdog, rather than allow that do an
2712 * attempted cleanup and then reinit here. Note that this has been
2713 * seens mostly with fiber adapters.
2716 emx_tx_purge(struct emx_softc *sc)
2720 if (sc->link_active)
2723 for (i = 0; i < sc->tx_ring_inuse; ++i) {
2724 struct emx_txdata *tdata = &sc->tx_data[i];
2726 if (tdata->tx_watchdog.wd_timer) {
2727 emx_tx_collect(tdata);
2728 if (tdata->tx_watchdog.wd_timer) {
2729 if_printf(&sc->arpcom.ac_if,
2730 "Link lost, TX pending, reinit\n");
2739 emx_newbuf(struct emx_rxdata *rdata, int i, int init)
2742 bus_dma_segment_t seg;
2744 struct emx_rxbuf *rx_buffer;
2747 m = m_getcl(init ? M_WAITOK : M_NOWAIT, MT_DATA, M_PKTHDR);
2750 if_printf(&rdata->sc->arpcom.ac_if,
2751 "Unable to allocate RX mbuf\n");
2755 m->m_len = m->m_pkthdr.len = MCLBYTES;
2757 if (rdata->sc->hw.mac.max_frame_size <= MCLBYTES - ETHER_ALIGN)
2758 m_adj(m, ETHER_ALIGN);
2760 error = bus_dmamap_load_mbuf_segment(rdata->rxtag,
2761 rdata->rx_sparemap, m,
2762 &seg, 1, &nseg, BUS_DMA_NOWAIT);
2766 if_printf(&rdata->sc->arpcom.ac_if,
2767 "Unable to load RX mbuf\n");
2772 rx_buffer = &rdata->rx_buf[i];
2773 if (rx_buffer->m_head != NULL)
2774 bus_dmamap_unload(rdata->rxtag, rx_buffer->map);
2776 map = rx_buffer->map;
2777 rx_buffer->map = rdata->rx_sparemap;
2778 rdata->rx_sparemap = map;
2780 rx_buffer->m_head = m;
2781 rx_buffer->paddr = seg.ds_addr;
2783 emx_setup_rxdesc(&rdata->rx_desc[i], rx_buffer);
2788 emx_create_rx_ring(struct emx_rxdata *rdata)
2790 device_t dev = rdata->sc->dev;
2791 struct emx_rxbuf *rx_buffer;
2792 int i, error, rsize, nrxd;
2795 * Validate number of receive descriptors. It must not exceed
2796 * hardware maximum, and must be multiple of E1000_DBA_ALIGN.
2798 nrxd = device_getenv_int(dev, "rxd", emx_rxd);
2799 if ((nrxd * sizeof(emx_rxdesc_t)) % EMX_DBA_ALIGN != 0 ||
2800 nrxd > EMX_MAX_RXD || nrxd < EMX_MIN_RXD) {
2801 device_printf(dev, "Using %d RX descriptors instead of %d!\n",
2802 EMX_DEFAULT_RXD, nrxd);
2803 rdata->num_rx_desc = EMX_DEFAULT_RXD;
2805 rdata->num_rx_desc = nrxd;
2809 * Allocate Receive Descriptor ring
2811 rsize = roundup2(rdata->num_rx_desc * sizeof(emx_rxdesc_t),
2813 rdata->rx_desc = bus_dmamem_coherent_any(rdata->sc->parent_dtag,
2814 EMX_DBA_ALIGN, rsize, BUS_DMA_WAITOK,
2815 &rdata->rx_desc_dtag, &rdata->rx_desc_dmap,
2816 &rdata->rx_desc_paddr);
2817 if (rdata->rx_desc == NULL) {
2818 device_printf(dev, "Unable to allocate rx_desc memory\n");
2822 rsize = __VM_CACHELINE_ALIGN(
2823 sizeof(struct emx_rxbuf) * rdata->num_rx_desc);
2824 rdata->rx_buf = kmalloc_cachealign(rsize, M_DEVBUF, M_WAITOK | M_ZERO);
2827 * Create DMA tag for rx buffers
2829 error = bus_dma_tag_create(rdata->sc->parent_dtag, /* parent */
2830 1, 0, /* alignment, bounds */
2831 BUS_SPACE_MAXADDR, /* lowaddr */
2832 BUS_SPACE_MAXADDR, /* highaddr */
2833 NULL, NULL, /* filter, filterarg */
2834 MCLBYTES, /* maxsize */
2836 MCLBYTES, /* maxsegsize */
2837 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, /* flags */
2840 device_printf(dev, "Unable to allocate RX DMA tag\n");
2841 kfree(rdata->rx_buf, M_DEVBUF);
2842 rdata->rx_buf = NULL;
2847 * Create spare DMA map for rx buffers
2849 error = bus_dmamap_create(rdata->rxtag, BUS_DMA_WAITOK,
2850 &rdata->rx_sparemap);
2852 device_printf(dev, "Unable to create spare RX DMA map\n");
2853 bus_dma_tag_destroy(rdata->rxtag);
2854 kfree(rdata->rx_buf, M_DEVBUF);
2855 rdata->rx_buf = NULL;
2860 * Create DMA maps for rx buffers
2862 for (i = 0; i < rdata->num_rx_desc; i++) {
2863 rx_buffer = &rdata->rx_buf[i];
2865 error = bus_dmamap_create(rdata->rxtag, BUS_DMA_WAITOK,
2868 device_printf(dev, "Unable to create RX DMA map\n");
2869 emx_destroy_rx_ring(rdata, i);
2877 emx_free_rx_ring(struct emx_rxdata *rdata)
2881 for (i = 0; i < rdata->num_rx_desc; i++) {
2882 struct emx_rxbuf *rx_buffer = &rdata->rx_buf[i];
2884 if (rx_buffer->m_head != NULL) {
2885 bus_dmamap_unload(rdata->rxtag, rx_buffer->map);
2886 m_freem(rx_buffer->m_head);
2887 rx_buffer->m_head = NULL;
2891 if (rdata->fmp != NULL)
2892 m_freem(rdata->fmp);
2898 emx_free_tx_ring(struct emx_txdata *tdata)
2902 for (i = 0; i < tdata->num_tx_desc; i++) {
2903 struct emx_txbuf *tx_buffer = &tdata->tx_buf[i];
2905 if (tx_buffer->m_head != NULL) {
2906 bus_dmamap_unload(tdata->txtag, tx_buffer->map);
2907 m_freem(tx_buffer->m_head);
2908 tx_buffer->m_head = NULL;
2912 tdata->tx_flags &= ~EMX_TXFLAG_FORCECTX;
2914 tdata->csum_flags = 0;
2915 tdata->csum_lhlen = 0;
2916 tdata->csum_iphlen = 0;
2917 tdata->csum_thlen = 0;
2918 tdata->csum_mss = 0;
2919 tdata->csum_pktlen = 0;
2921 tdata->tx_dd_head = 0;
2922 tdata->tx_dd_tail = 0;
2923 tdata->tx_nsegs = 0;
2927 emx_init_rx_ring(struct emx_rxdata *rdata)
2931 /* Reset descriptor ring */
2932 bzero(rdata->rx_desc, sizeof(emx_rxdesc_t) * rdata->num_rx_desc);
2934 /* Allocate new ones. */
2935 for (i = 0; i < rdata->num_rx_desc; i++) {
2936 error = emx_newbuf(rdata, i, 1);
2941 /* Setup our descriptor pointers */
2942 rdata->next_rx_desc_to_check = 0;
2948 emx_init_rx_unit(struct emx_softc *sc)
2950 struct ifnet *ifp = &sc->arpcom.ac_if;
2952 uint32_t rctl, itr, rfctl;
2956 * Make sure receives are disabled while setting
2957 * up the descriptor ring
2959 rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
2960 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
2963 * Set the interrupt throttling rate. Value is calculated
2964 * as ITR = 1 / (INT_THROTTLE_CEIL * 256ns)
2966 if (sc->int_throttle_ceil)
2967 itr = 1000000000 / 256 / sc->int_throttle_ceil;
2970 emx_set_itr(sc, itr);
2972 /* Use extended RX descriptor */
2973 rfctl = E1000_RFCTL_EXTEN;
2975 /* Disable accelerated ackknowledge */
2976 if (sc->hw.mac.type == e1000_82574)
2977 rfctl |= E1000_RFCTL_ACK_DIS;
2979 E1000_WRITE_REG(&sc->hw, E1000_RFCTL, rfctl);
2982 * Receive Checksum Offload for TCP and UDP
2984 * Checksum offloading is also enabled if multiple receive
2985 * queue is to be supported, since we need it to figure out
2988 if ((ifp->if_capenable & IFCAP_RXCSUM) ||
2989 sc->rx_ring_cnt > 1) {
2992 rxcsum = E1000_READ_REG(&sc->hw, E1000_RXCSUM);
2996 * PCSD must be enabled to enable multiple
2999 rxcsum |= E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL |
3001 E1000_WRITE_REG(&sc->hw, E1000_RXCSUM, rxcsum);
3005 * Configure multiple receive queue (RSS)
3007 if (sc->rx_ring_cnt > 1) {
3008 uint8_t key[EMX_NRSSRK * EMX_RSSRK_SIZE];
3011 KASSERT(sc->rx_ring_cnt == EMX_NRX_RING,
3012 ("invalid number of RX ring (%d)", sc->rx_ring_cnt));
3016 * When we reach here, RSS has already been disabled
3017 * in emx_stop(), so we could safely configure RSS key
3018 * and redirect table.
3024 toeplitz_get_key(key, sizeof(key));
3025 for (i = 0; i < EMX_NRSSRK; ++i) {
3028 rssrk = EMX_RSSRK_VAL(key, i);
3029 EMX_RSS_DPRINTF(sc, 1, "rssrk%d 0x%08x\n", i, rssrk);
3031 E1000_WRITE_REG(&sc->hw, E1000_RSSRK(i), rssrk);
3035 * Configure RSS redirect table in following fashion:
3036 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)]
3039 for (i = 0; i < EMX_RETA_SIZE; ++i) {
3042 q = (i % sc->rx_ring_cnt) << EMX_RETA_RINGIDX_SHIFT;
3043 reta |= q << (8 * i);
3045 EMX_RSS_DPRINTF(sc, 1, "reta 0x%08x\n", reta);
3047 for (i = 0; i < EMX_NRETA; ++i)
3048 E1000_WRITE_REG(&sc->hw, E1000_RETA(i), reta);
3051 * Enable multiple receive queues.
3052 * Enable IPv4 RSS standard hash functions.
3053 * Disable RSS interrupt.
3055 E1000_WRITE_REG(&sc->hw, E1000_MRQC,
3056 E1000_MRQC_ENABLE_RSS_2Q |
3057 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3058 E1000_MRQC_RSS_FIELD_IPV4);
3062 * XXX TEMPORARY WORKAROUND: on some systems with 82573
3063 * long latencies are observed, like Lenovo X60. This
3064 * change eliminates the problem, but since having positive
3065 * values in RDTR is a known source of problems on other
3066 * platforms another solution is being sought.
3068 if (emx_82573_workaround && sc->hw.mac.type == e1000_82573) {
3069 E1000_WRITE_REG(&sc->hw, E1000_RADV, EMX_RADV_82573);
3070 E1000_WRITE_REG(&sc->hw, E1000_RDTR, EMX_RDTR_82573);
3073 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3074 struct emx_rxdata *rdata = &sc->rx_data[i];
3077 * Setup the Base and Length of the Rx Descriptor Ring
3079 bus_addr = rdata->rx_desc_paddr;
3080 E1000_WRITE_REG(&sc->hw, E1000_RDLEN(i),
3081 rdata->num_rx_desc * sizeof(emx_rxdesc_t));
3082 E1000_WRITE_REG(&sc->hw, E1000_RDBAH(i),
3083 (uint32_t)(bus_addr >> 32));
3084 E1000_WRITE_REG(&sc->hw, E1000_RDBAL(i),
3085 (uint32_t)bus_addr);
3088 * Setup the HW Rx Head and Tail Descriptor Pointers
3090 E1000_WRITE_REG(&sc->hw, E1000_RDH(i), 0);
3091 E1000_WRITE_REG(&sc->hw, E1000_RDT(i),
3092 sc->rx_data[i].num_rx_desc - 1);
3095 if (sc->hw.mac.type >= e1000_pch2lan) {
3096 if (ifp->if_mtu > ETHERMTU)
3097 e1000_lv_jumbo_workaround_ich8lan(&sc->hw, TRUE);
3099 e1000_lv_jumbo_workaround_ich8lan(&sc->hw, FALSE);
3102 /* Setup the Receive Control Register */
3103 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
3104 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO |
3105 E1000_RCTL_RDMTS_HALF | E1000_RCTL_SECRC |
3106 (sc->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
3108 /* Make sure VLAN Filters are off */
3109 rctl &= ~E1000_RCTL_VFE;
3111 /* Don't store bad paket */
3112 rctl &= ~E1000_RCTL_SBP;
3115 rctl |= E1000_RCTL_SZ_2048;
3117 if (ifp->if_mtu > ETHERMTU)
3118 rctl |= E1000_RCTL_LPE;
3120 rctl &= ~E1000_RCTL_LPE;
3122 /* Enable Receives */
3123 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl);
3127 emx_destroy_rx_ring(struct emx_rxdata *rdata, int ndesc)
3129 struct emx_rxbuf *rx_buffer;
3132 /* Free Receive Descriptor ring */
3133 if (rdata->rx_desc) {
3134 bus_dmamap_unload(rdata->rx_desc_dtag, rdata->rx_desc_dmap);
3135 bus_dmamem_free(rdata->rx_desc_dtag, rdata->rx_desc,
3136 rdata->rx_desc_dmap);
3137 bus_dma_tag_destroy(rdata->rx_desc_dtag);
3139 rdata->rx_desc = NULL;
3142 if (rdata->rx_buf == NULL)
3145 for (i = 0; i < ndesc; i++) {
3146 rx_buffer = &rdata->rx_buf[i];
3148 KKASSERT(rx_buffer->m_head == NULL);
3149 bus_dmamap_destroy(rdata->rxtag, rx_buffer->map);
3151 bus_dmamap_destroy(rdata->rxtag, rdata->rx_sparemap);
3152 bus_dma_tag_destroy(rdata->rxtag);
3154 kfree(rdata->rx_buf, M_DEVBUF);
3155 rdata->rx_buf = NULL;
3159 emx_rxeof(struct emx_rxdata *rdata, int count)
3161 struct ifnet *ifp = &rdata->sc->arpcom.ac_if;
3163 emx_rxdesc_t *current_desc;
3165 int i, cpuid = mycpuid;
3167 i = rdata->next_rx_desc_to_check;
3168 current_desc = &rdata->rx_desc[i];
3169 staterr = le32toh(current_desc->rxd_staterr);
3171 if (!(staterr & E1000_RXD_STAT_DD))
3174 while ((staterr & E1000_RXD_STAT_DD) && count != 0) {
3175 struct pktinfo *pi = NULL, pi0;
3176 struct emx_rxbuf *rx_buf = &rdata->rx_buf[i];
3177 struct mbuf *m = NULL;
3182 mp = rx_buf->m_head;
3185 * Can't defer bus_dmamap_sync(9) because TBI_ACCEPT
3186 * needs to access the last received byte in the mbuf.
3188 bus_dmamap_sync(rdata->rxtag, rx_buf->map,
3189 BUS_DMASYNC_POSTREAD);
3191 len = le16toh(current_desc->rxd_length);
3192 if (staterr & E1000_RXD_STAT_EOP) {
3199 if (!(staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK)) {
3201 uint32_t mrq, rss_hash;
3204 * Save several necessary information,
3205 * before emx_newbuf() destroy it.
3207 if ((staterr & E1000_RXD_STAT_VP) && eop)
3208 vlan = le16toh(current_desc->rxd_vlan);
3210 mrq = le32toh(current_desc->rxd_mrq);
3211 rss_hash = le32toh(current_desc->rxd_rss);
3213 EMX_RSS_DPRINTF(rdata->sc, 10,
3214 "ring%d, mrq 0x%08x, rss_hash 0x%08x\n",
3215 rdata->idx, mrq, rss_hash);
3217 if (emx_newbuf(rdata, i, 0) != 0) {
3218 IFNET_STAT_INC(ifp, iqdrops, 1);
3222 /* Assign correct length to the current fragment */
3225 if (rdata->fmp == NULL) {
3226 mp->m_pkthdr.len = len;
3227 rdata->fmp = mp; /* Store the first mbuf */
3231 * Chain mbuf's together
3233 rdata->lmp->m_next = mp;
3234 rdata->lmp = rdata->lmp->m_next;
3235 rdata->fmp->m_pkthdr.len += len;
3239 rdata->fmp->m_pkthdr.rcvif = ifp;
3240 IFNET_STAT_INC(ifp, ipackets, 1);
3242 if (ifp->if_capenable & IFCAP_RXCSUM)
3243 emx_rxcsum(staterr, rdata->fmp);
3245 if (staterr & E1000_RXD_STAT_VP) {
3246 rdata->fmp->m_pkthdr.ether_vlantag =
3248 rdata->fmp->m_flags |= M_VLANTAG;
3254 if (ifp->if_capenable & IFCAP_RSS) {
3255 pi = emx_rssinfo(m, &pi0, mrq,
3258 #ifdef EMX_RSS_DEBUG
3263 IFNET_STAT_INC(ifp, ierrors, 1);
3265 emx_setup_rxdesc(current_desc, rx_buf);
3266 if (rdata->fmp != NULL) {
3267 m_freem(rdata->fmp);
3275 ifp->if_input(ifp, m, pi, cpuid);
3277 /* Advance our pointers to the next descriptor. */
3278 if (++i == rdata->num_rx_desc)
3281 current_desc = &rdata->rx_desc[i];
3282 staterr = le32toh(current_desc->rxd_staterr);
3284 rdata->next_rx_desc_to_check = i;
3286 /* Advance the E1000's Receive Queue "Tail Pointer". */
3288 i = rdata->num_rx_desc - 1;
3289 E1000_WRITE_REG(&rdata->sc->hw, E1000_RDT(rdata->idx), i);
3293 emx_enable_intr(struct emx_softc *sc)
3295 uint32_t ims_mask = IMS_ENABLE_MASK;
3297 lwkt_serialize_handler_enable(&sc->main_serialize);
3300 if (sc->hw.mac.type == e1000_82574) {
3301 E1000_WRITE_REG(hw, EMX_EIAC, EM_MSIX_MASK);
3302 ims_mask |= EM_MSIX_MASK;
3305 E1000_WRITE_REG(&sc->hw, E1000_IMS, ims_mask);
3309 emx_disable_intr(struct emx_softc *sc)
3311 if (sc->hw.mac.type == e1000_82574)
3312 E1000_WRITE_REG(&sc->hw, EMX_EIAC, 0);
3313 E1000_WRITE_REG(&sc->hw, E1000_IMC, 0xffffffff);
3315 lwkt_serialize_handler_disable(&sc->main_serialize);
3319 * Bit of a misnomer, what this really means is
3320 * to enable OS management of the system... aka
3321 * to disable special hardware management features
3324 emx_get_mgmt(struct emx_softc *sc)
3326 /* A shared code workaround */
3327 if (sc->flags & EMX_FLAG_HAS_MGMT) {
3328 int manc2h = E1000_READ_REG(&sc->hw, E1000_MANC2H);
3329 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
3331 /* disable hardware interception of ARP */
3332 manc &= ~(E1000_MANC_ARP_EN);
3334 /* enable receiving management packets to the host */
3335 manc |= E1000_MANC_EN_MNG2HOST;
3336 #define E1000_MNG2HOST_PORT_623 (1 << 5)
3337 #define E1000_MNG2HOST_PORT_664 (1 << 6)
3338 manc2h |= E1000_MNG2HOST_PORT_623;
3339 manc2h |= E1000_MNG2HOST_PORT_664;
3340 E1000_WRITE_REG(&sc->hw, E1000_MANC2H, manc2h);
3342 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
3347 * Give control back to hardware management
3348 * controller if there is one.
3351 emx_rel_mgmt(struct emx_softc *sc)
3353 if (sc->flags & EMX_FLAG_HAS_MGMT) {
3354 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
3356 /* re-enable hardware interception of ARP */
3357 manc |= E1000_MANC_ARP_EN;
3358 manc &= ~E1000_MANC_EN_MNG2HOST;
3360 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
3365 * emx_get_hw_control() sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
3366 * For ASF and Pass Through versions of f/w this means that
3367 * the driver is loaded. For AMT version (only with 82573)
3368 * of the f/w this means that the network i/f is open.
3371 emx_get_hw_control(struct emx_softc *sc)
3373 /* Let firmware know the driver has taken over */
3374 if (sc->hw.mac.type == e1000_82573) {
3377 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM);
3378 E1000_WRITE_REG(&sc->hw, E1000_SWSM,
3379 swsm | E1000_SWSM_DRV_LOAD);
3383 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
3384 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
3385 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
3387 sc->flags |= EMX_FLAG_HW_CTRL;
3391 * emx_rel_hw_control() resets {CTRL_EXT|FWSM}:DRV_LOAD bit.
3392 * For ASF and Pass Through versions of f/w this means that the
3393 * driver is no longer loaded. For AMT version (only with 82573)
3394 * of the f/w this means that the network i/f is closed.
3397 emx_rel_hw_control(struct emx_softc *sc)
3399 if ((sc->flags & EMX_FLAG_HW_CTRL) == 0)
3401 sc->flags &= ~EMX_FLAG_HW_CTRL;
3403 /* Let firmware taken over control of h/w */
3404 if (sc->hw.mac.type == e1000_82573) {
3407 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM);
3408 E1000_WRITE_REG(&sc->hw, E1000_SWSM,
3409 swsm & ~E1000_SWSM_DRV_LOAD);
3413 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
3414 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
3415 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
3420 emx_is_valid_eaddr(const uint8_t *addr)
3422 char zero_addr[ETHER_ADDR_LEN] = { 0, 0, 0, 0, 0, 0 };
3424 if ((addr[0] & 1) || !bcmp(addr, zero_addr, ETHER_ADDR_LEN))
3431 * Enable PCI Wake On Lan capability
3434 emx_enable_wol(device_t dev)
3436 uint16_t cap, status;
3439 /* First find the capabilities pointer*/
3440 cap = pci_read_config(dev, PCIR_CAP_PTR, 2);
3442 /* Read the PM Capabilities */
3443 id = pci_read_config(dev, cap, 1);
3444 if (id != PCIY_PMG) /* Something wrong */
3448 * OK, we have the power capabilities,
3449 * so now get the status register
3451 cap += PCIR_POWER_STATUS;
3452 status = pci_read_config(dev, cap, 2);
3453 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
3454 pci_write_config(dev, cap, status, 2);
3458 emx_update_stats(struct emx_softc *sc)
3460 struct ifnet *ifp = &sc->arpcom.ac_if;
3462 if (sc->hw.phy.media_type == e1000_media_type_copper ||
3463 (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_LU)) {
3464 sc->stats.symerrs += E1000_READ_REG(&sc->hw, E1000_SYMERRS);
3465 sc->stats.sec += E1000_READ_REG(&sc->hw, E1000_SEC);
3467 sc->stats.crcerrs += E1000_READ_REG(&sc->hw, E1000_CRCERRS);
3468 sc->stats.mpc += E1000_READ_REG(&sc->hw, E1000_MPC);
3469 sc->stats.scc += E1000_READ_REG(&sc->hw, E1000_SCC);
3470 sc->stats.ecol += E1000_READ_REG(&sc->hw, E1000_ECOL);
3472 sc->stats.mcc += E1000_READ_REG(&sc->hw, E1000_MCC);
3473 sc->stats.latecol += E1000_READ_REG(&sc->hw, E1000_LATECOL);
3474 sc->stats.colc += E1000_READ_REG(&sc->hw, E1000_COLC);
3475 sc->stats.dc += E1000_READ_REG(&sc->hw, E1000_DC);
3476 sc->stats.rlec += E1000_READ_REG(&sc->hw, E1000_RLEC);
3477 sc->stats.xonrxc += E1000_READ_REG(&sc->hw, E1000_XONRXC);
3478 sc->stats.xontxc += E1000_READ_REG(&sc->hw, E1000_XONTXC);
3479 sc->stats.xoffrxc += E1000_READ_REG(&sc->hw, E1000_XOFFRXC);
3480 sc->stats.xofftxc += E1000_READ_REG(&sc->hw, E1000_XOFFTXC);
3481 sc->stats.fcruc += E1000_READ_REG(&sc->hw, E1000_FCRUC);
3482 sc->stats.prc64 += E1000_READ_REG(&sc->hw, E1000_PRC64);
3483 sc->stats.prc127 += E1000_READ_REG(&sc->hw, E1000_PRC127);
3484 sc->stats.prc255 += E1000_READ_REG(&sc->hw, E1000_PRC255);
3485 sc->stats.prc511 += E1000_READ_REG(&sc->hw, E1000_PRC511);
3486 sc->stats.prc1023 += E1000_READ_REG(&sc->hw, E1000_PRC1023);
3487 sc->stats.prc1522 += E1000_READ_REG(&sc->hw, E1000_PRC1522);
3488 sc->stats.gprc += E1000_READ_REG(&sc->hw, E1000_GPRC);
3489 sc->stats.bprc += E1000_READ_REG(&sc->hw, E1000_BPRC);
3490 sc->stats.mprc += E1000_READ_REG(&sc->hw, E1000_MPRC);
3491 sc->stats.gptc += E1000_READ_REG(&sc->hw, E1000_GPTC);
3493 /* For the 64-bit byte counters the low dword must be read first. */
3494 /* Both registers clear on the read of the high dword */
3496 sc->stats.gorc += E1000_READ_REG(&sc->hw, E1000_GORCH);
3497 sc->stats.gotc += E1000_READ_REG(&sc->hw, E1000_GOTCH);
3499 sc->stats.rnbc += E1000_READ_REG(&sc->hw, E1000_RNBC);
3500 sc->stats.ruc += E1000_READ_REG(&sc->hw, E1000_RUC);
3501 sc->stats.rfc += E1000_READ_REG(&sc->hw, E1000_RFC);
3502 sc->stats.roc += E1000_READ_REG(&sc->hw, E1000_ROC);
3503 sc->stats.rjc += E1000_READ_REG(&sc->hw, E1000_RJC);
3505 sc->stats.tor += E1000_READ_REG(&sc->hw, E1000_TORH);
3506 sc->stats.tot += E1000_READ_REG(&sc->hw, E1000_TOTH);
3508 sc->stats.tpr += E1000_READ_REG(&sc->hw, E1000_TPR);
3509 sc->stats.tpt += E1000_READ_REG(&sc->hw, E1000_TPT);
3510 sc->stats.ptc64 += E1000_READ_REG(&sc->hw, E1000_PTC64);
3511 sc->stats.ptc127 += E1000_READ_REG(&sc->hw, E1000_PTC127);
3512 sc->stats.ptc255 += E1000_READ_REG(&sc->hw, E1000_PTC255);
3513 sc->stats.ptc511 += E1000_READ_REG(&sc->hw, E1000_PTC511);
3514 sc->stats.ptc1023 += E1000_READ_REG(&sc->hw, E1000_PTC1023);
3515 sc->stats.ptc1522 += E1000_READ_REG(&sc->hw, E1000_PTC1522);
3516 sc->stats.mptc += E1000_READ_REG(&sc->hw, E1000_MPTC);
3517 sc->stats.bptc += E1000_READ_REG(&sc->hw, E1000_BPTC);
3519 sc->stats.algnerrc += E1000_READ_REG(&sc->hw, E1000_ALGNERRC);
3520 sc->stats.rxerrc += E1000_READ_REG(&sc->hw, E1000_RXERRC);
3521 sc->stats.tncrs += E1000_READ_REG(&sc->hw, E1000_TNCRS);
3522 sc->stats.cexterr += E1000_READ_REG(&sc->hw, E1000_CEXTERR);
3523 sc->stats.tsctc += E1000_READ_REG(&sc->hw, E1000_TSCTC);
3524 sc->stats.tsctfc += E1000_READ_REG(&sc->hw, E1000_TSCTFC);
3526 IFNET_STAT_SET(ifp, collisions, sc->stats.colc);
3529 IFNET_STAT_SET(ifp, ierrors,
3530 sc->stats.rxerrc + sc->stats.crcerrs + sc->stats.algnerrc +
3531 sc->stats.ruc + sc->stats.roc + sc->stats.mpc + sc->stats.cexterr);
3534 IFNET_STAT_SET(ifp, oerrors, sc->stats.ecol + sc->stats.latecol);
3538 emx_print_debug_info(struct emx_softc *sc)
3540 device_t dev = sc->dev;
3541 uint8_t *hw_addr = sc->hw.hw_addr;
3544 device_printf(dev, "Adapter hardware address = %p \n", hw_addr);
3545 device_printf(dev, "CTRL = 0x%x RCTL = 0x%x \n",
3546 E1000_READ_REG(&sc->hw, E1000_CTRL),
3547 E1000_READ_REG(&sc->hw, E1000_RCTL));
3548 device_printf(dev, "Packet buffer = Tx=%dk Rx=%dk \n",
3549 ((E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff0000) >> 16),\
3550 (E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff) );
3551 device_printf(dev, "Flow control watermarks high = %d low = %d\n",
3552 sc->hw.fc.high_water, sc->hw.fc.low_water);
3553 device_printf(dev, "tx_int_delay = %d, tx_abs_int_delay = %d\n",
3554 E1000_READ_REG(&sc->hw, E1000_TIDV),
3555 E1000_READ_REG(&sc->hw, E1000_TADV));
3556 device_printf(dev, "rx_int_delay = %d, rx_abs_int_delay = %d\n",
3557 E1000_READ_REG(&sc->hw, E1000_RDTR),
3558 E1000_READ_REG(&sc->hw, E1000_RADV));
3560 for (i = 0; i < sc->tx_ring_cnt; ++i) {
3561 device_printf(dev, "hw %d tdh = %d, hw tdt = %d\n", i,
3562 E1000_READ_REG(&sc->hw, E1000_TDH(i)),
3563 E1000_READ_REG(&sc->hw, E1000_TDT(i)));
3565 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3566 device_printf(dev, "hw %d rdh = %d, hw rdt = %d\n", i,
3567 E1000_READ_REG(&sc->hw, E1000_RDH(i)),
3568 E1000_READ_REG(&sc->hw, E1000_RDT(i)));
3571 for (i = 0; i < sc->tx_ring_cnt; ++i) {
3572 device_printf(dev, "TX %d Tx descriptors avail = %d\n", i,
3573 sc->tx_data[i].num_tx_desc_avail);
3574 device_printf(dev, "TX %d TSO segments = %lu\n", i,
3575 sc->tx_data[i].tso_segments);
3576 device_printf(dev, "TX %d TSO ctx reused = %lu\n", i,
3577 sc->tx_data[i].tso_ctx_reused);
3582 emx_print_hw_stats(struct emx_softc *sc)
3584 device_t dev = sc->dev;
3586 device_printf(dev, "Excessive collisions = %lld\n",
3587 (long long)sc->stats.ecol);
3588 #if (DEBUG_HW > 0) /* Dont output these errors normally */
3589 device_printf(dev, "Symbol errors = %lld\n",
3590 (long long)sc->stats.symerrs);
3592 device_printf(dev, "Sequence errors = %lld\n",
3593 (long long)sc->stats.sec);
3594 device_printf(dev, "Defer count = %lld\n",
3595 (long long)sc->stats.dc);
3596 device_printf(dev, "Missed Packets = %lld\n",
3597 (long long)sc->stats.mpc);
3598 device_printf(dev, "Receive No Buffers = %lld\n",
3599 (long long)sc->stats.rnbc);
3600 /* RLEC is inaccurate on some hardware, calculate our own. */
3601 device_printf(dev, "Receive Length Errors = %lld\n",
3602 ((long long)sc->stats.roc + (long long)sc->stats.ruc));
3603 device_printf(dev, "Receive errors = %lld\n",
3604 (long long)sc->stats.rxerrc);
3605 device_printf(dev, "Crc errors = %lld\n",
3606 (long long)sc->stats.crcerrs);
3607 device_printf(dev, "Alignment errors = %lld\n",
3608 (long long)sc->stats.algnerrc);
3609 device_printf(dev, "Collision/Carrier extension errors = %lld\n",
3610 (long long)sc->stats.cexterr);
3611 device_printf(dev, "RX overruns = %ld\n", sc->rx_overruns);
3612 device_printf(dev, "XON Rcvd = %lld\n",
3613 (long long)sc->stats.xonrxc);
3614 device_printf(dev, "XON Xmtd = %lld\n",
3615 (long long)sc->stats.xontxc);
3616 device_printf(dev, "XOFF Rcvd = %lld\n",
3617 (long long)sc->stats.xoffrxc);
3618 device_printf(dev, "XOFF Xmtd = %lld\n",
3619 (long long)sc->stats.xofftxc);
3620 device_printf(dev, "Good Packets Rcvd = %lld\n",
3621 (long long)sc->stats.gprc);
3622 device_printf(dev, "Good Packets Xmtd = %lld\n",
3623 (long long)sc->stats.gptc);
3627 emx_print_nvm_info(struct emx_softc *sc)
3629 uint16_t eeprom_data;
3632 /* Its a bit crude, but it gets the job done */
3633 kprintf("\nInterface EEPROM Dump:\n");
3634 kprintf("Offset\n0x0000 ");
3635 for (i = 0, j = 0; i < 32; i++, j++) {
3636 if (j == 8) { /* Make the offset block */
3638 kprintf("\n0x00%x0 ",row);
3640 e1000_read_nvm(&sc->hw, i, 1, &eeprom_data);
3641 kprintf("%04x ", eeprom_data);
3647 emx_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
3649 struct emx_softc *sc;
3654 error = sysctl_handle_int(oidp, &result, 0, req);
3655 if (error || !req->newptr)
3658 sc = (struct emx_softc *)arg1;
3659 ifp = &sc->arpcom.ac_if;
3661 ifnet_serialize_all(ifp);
3664 emx_print_debug_info(sc);
3667 * This value will cause a hex dump of the
3668 * first 32 16-bit words of the EEPROM to
3672 emx_print_nvm_info(sc);
3674 ifnet_deserialize_all(ifp);
3680 emx_sysctl_stats(SYSCTL_HANDLER_ARGS)
3685 error = sysctl_handle_int(oidp, &result, 0, req);
3686 if (error || !req->newptr)
3690 struct emx_softc *sc = (struct emx_softc *)arg1;
3691 struct ifnet *ifp = &sc->arpcom.ac_if;
3693 ifnet_serialize_all(ifp);
3694 emx_print_hw_stats(sc);
3695 ifnet_deserialize_all(ifp);
3701 emx_add_sysctl(struct emx_softc *sc)
3703 struct sysctl_ctx_list *ctx;
3704 struct sysctl_oid *tree;
3705 #if defined(EMX_RSS_DEBUG) || defined(EMX_TSS_DEBUG)
3710 ctx = device_get_sysctl_ctx(sc->dev);
3711 tree = device_get_sysctl_tree(sc->dev);
3712 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree),
3713 OID_AUTO, "debug", CTLTYPE_INT|CTLFLAG_RW, sc, 0,
3714 emx_sysctl_debug_info, "I", "Debug Information");
3716 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree),
3717 OID_AUTO, "stats", CTLTYPE_INT|CTLFLAG_RW, sc, 0,
3718 emx_sysctl_stats, "I", "Statistics");
3720 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree),
3721 OID_AUTO, "rxd", CTLFLAG_RD, &sc->rx_data[0].num_rx_desc, 0,
3723 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree),
3724 OID_AUTO, "txd", CTLFLAG_RD, &sc->tx_data[0].num_tx_desc, 0,
3727 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree),
3728 OID_AUTO, "int_throttle_ceil", CTLTYPE_INT|CTLFLAG_RW, sc, 0,
3729 emx_sysctl_int_throttle, "I", "interrupt throttling rate");
3730 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree),
3731 OID_AUTO, "tx_intr_nsegs", CTLTYPE_INT|CTLFLAG_RW, sc, 0,
3732 emx_sysctl_tx_intr_nsegs, "I", "# segments per TX interrupt");
3733 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree),
3734 OID_AUTO, "tx_wreg_nsegs", CTLTYPE_INT|CTLFLAG_RW, sc, 0,
3735 emx_sysctl_tx_wreg_nsegs, "I",
3736 "# segments sent before write to hardware register");
3738 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree),
3739 OID_AUTO, "rx_ring_cnt", CTLFLAG_RD, &sc->rx_ring_cnt, 0,
3741 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree),
3742 OID_AUTO, "tx_ring_cnt", CTLFLAG_RD, &sc->tx_ring_cnt, 0,
3744 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree),
3745 OID_AUTO, "tx_ring_inuse", CTLFLAG_RD, &sc->tx_ring_inuse, 0,
3746 "# of TX rings used");
3748 #ifdef IFPOLL_ENABLE
3749 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree),
3750 OID_AUTO, "npoll_rxoff", CTLTYPE_INT|CTLFLAG_RW,
3751 sc, 0, emx_sysctl_npoll_rxoff, "I",
3752 "NPOLLING RX cpu offset");
3753 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree),
3754 OID_AUTO, "npoll_txoff", CTLTYPE_INT|CTLFLAG_RW,
3755 sc, 0, emx_sysctl_npoll_txoff, "I",
3756 "NPOLLING TX cpu offset");
3759 #ifdef EMX_RSS_DEBUG
3760 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree),
3761 OID_AUTO, "rss_debug", CTLFLAG_RW, &sc->rss_debug,
3762 0, "RSS debug level");
3763 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3764 ksnprintf(pkt_desc, sizeof(pkt_desc), "rx%d_pkt", i);
3765 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
3766 pkt_desc, CTLFLAG_RW, &sc->rx_data[i].rx_pkts,
3770 #ifdef EMX_TSS_DEBUG
3771 for (i = 0; i < sc->tx_ring_cnt; ++i) {
3772 ksnprintf(pkt_desc, sizeof(pkt_desc), "tx%d_pkt", i);
3773 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
3774 pkt_desc, CTLFLAG_RW, &sc->tx_data[i].tx_pkts,
3781 emx_sysctl_int_throttle(SYSCTL_HANDLER_ARGS)
3783 struct emx_softc *sc = (void *)arg1;
3784 struct ifnet *ifp = &sc->arpcom.ac_if;
3785 int error, throttle;
3787 throttle = sc->int_throttle_ceil;
3788 error = sysctl_handle_int(oidp, &throttle, 0, req);
3789 if (error || req->newptr == NULL)
3791 if (throttle < 0 || throttle > 1000000000 / 256)
3796 * Set the interrupt throttling rate in 256ns increments,
3797 * recalculate sysctl value assignment to get exact frequency.
3799 throttle = 1000000000 / 256 / throttle;
3801 /* Upper 16bits of ITR is reserved and should be zero */
3802 if (throttle & 0xffff0000)
3806 ifnet_serialize_all(ifp);
3809 sc->int_throttle_ceil = 1000000000 / 256 / throttle;
3811 sc->int_throttle_ceil = 0;
3813 if (ifp->if_flags & IFF_RUNNING)
3814 emx_set_itr(sc, throttle);
3816 ifnet_deserialize_all(ifp);
3819 if_printf(ifp, "Interrupt moderation set to %d/sec\n",
3820 sc->int_throttle_ceil);
3826 emx_sysctl_tx_intr_nsegs(SYSCTL_HANDLER_ARGS)
3828 struct emx_softc *sc = (void *)arg1;
3829 struct ifnet *ifp = &sc->arpcom.ac_if;
3830 struct emx_txdata *tdata = &sc->tx_data[0];
3833 segs = tdata->tx_intr_nsegs;
3834 error = sysctl_handle_int(oidp, &segs, 0, req);
3835 if (error || req->newptr == NULL)
3840 ifnet_serialize_all(ifp);
3843 * Don't allow tx_intr_nsegs to become:
3844 * o Less the oact_tx_desc
3845 * o Too large that no TX desc will cause TX interrupt to
3846 * be generated (OACTIVE will never recover)
3847 * o Too small that will cause tx_dd[] overflow
3849 if (segs < tdata->oact_tx_desc ||
3850 segs >= tdata->num_tx_desc - tdata->oact_tx_desc ||
3851 segs < tdata->num_tx_desc / EMX_TXDD_SAFE) {
3857 for (i = 0; i < sc->tx_ring_cnt; ++i)
3858 sc->tx_data[i].tx_intr_nsegs = segs;
3861 ifnet_deserialize_all(ifp);
3867 emx_sysctl_tx_wreg_nsegs(SYSCTL_HANDLER_ARGS)
3869 struct emx_softc *sc = (void *)arg1;
3870 struct ifnet *ifp = &sc->arpcom.ac_if;
3871 int error, nsegs, i;
3873 nsegs = sc->tx_data[0].tx_wreg_nsegs;
3874 error = sysctl_handle_int(oidp, &nsegs, 0, req);
3875 if (error || req->newptr == NULL)
3878 ifnet_serialize_all(ifp);
3879 for (i = 0; i < sc->tx_ring_cnt; ++i)
3880 sc->tx_data[i].tx_wreg_nsegs =nsegs;
3881 ifnet_deserialize_all(ifp);
3886 #ifdef IFPOLL_ENABLE
3889 emx_sysctl_npoll_rxoff(SYSCTL_HANDLER_ARGS)
3891 struct emx_softc *sc = (void *)arg1;
3892 struct ifnet *ifp = &sc->arpcom.ac_if;
3895 off = sc->rx_npoll_off;
3896 error = sysctl_handle_int(oidp, &off, 0, req);
3897 if (error || req->newptr == NULL)
3902 ifnet_serialize_all(ifp);
3903 if (off >= ncpus2 || off % sc->rx_ring_cnt != 0) {
3907 sc->rx_npoll_off = off;
3909 ifnet_deserialize_all(ifp);
3915 emx_sysctl_npoll_txoff(SYSCTL_HANDLER_ARGS)
3917 struct emx_softc *sc = (void *)arg1;
3918 struct ifnet *ifp = &sc->arpcom.ac_if;
3921 off = sc->tx_npoll_off;
3922 error = sysctl_handle_int(oidp, &off, 0, req);
3923 if (error || req->newptr == NULL)
3928 ifnet_serialize_all(ifp);
3929 if (off >= ncpus2 || off % sc->tx_ring_cnt != 0) {
3933 sc->tx_npoll_off = off;
3935 ifnet_deserialize_all(ifp);
3940 #endif /* IFPOLL_ENABLE */
3943 emx_dma_alloc(struct emx_softc *sc)
3948 * Create top level busdma tag
3950 error = bus_dma_tag_create(NULL, 1, 0,
3951 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3953 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT,
3954 0, &sc->parent_dtag);
3956 device_printf(sc->dev, "could not create top level DMA tag\n");
3961 * Allocate transmit descriptors ring and buffers
3963 for (i = 0; i < sc->tx_ring_cnt; ++i) {
3964 error = emx_create_tx_ring(&sc->tx_data[i]);
3966 device_printf(sc->dev,
3967 "Could not setup transmit structures\n");
3973 * Allocate receive descriptors ring and buffers
3975 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3976 error = emx_create_rx_ring(&sc->rx_data[i]);
3978 device_printf(sc->dev,
3979 "Could not setup receive structures\n");
3987 emx_dma_free(struct emx_softc *sc)
3991 for (i = 0; i < sc->tx_ring_cnt; ++i) {
3992 emx_destroy_tx_ring(&sc->tx_data[i],
3993 sc->tx_data[i].num_tx_desc);
3996 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3997 emx_destroy_rx_ring(&sc->rx_data[i],
3998 sc->rx_data[i].num_rx_desc);
4001 /* Free top level busdma tag */
4002 if (sc->parent_dtag != NULL)
4003 bus_dma_tag_destroy(sc->parent_dtag);
4007 emx_serialize(struct ifnet *ifp, enum ifnet_serialize slz)
4009 struct emx_softc *sc = ifp->if_softc;
4011 ifnet_serialize_array_enter(sc->serializes, EMX_NSERIALIZE, slz);
4015 emx_deserialize(struct ifnet *ifp, enum ifnet_serialize slz)
4017 struct emx_softc *sc = ifp->if_softc;
4019 ifnet_serialize_array_exit(sc->serializes, EMX_NSERIALIZE, slz);
4023 emx_tryserialize(struct ifnet *ifp, enum ifnet_serialize slz)
4025 struct emx_softc *sc = ifp->if_softc;
4027 return ifnet_serialize_array_try(sc->serializes, EMX_NSERIALIZE, slz);
4031 emx_serialize_skipmain(struct emx_softc *sc)
4033 lwkt_serialize_array_enter(sc->serializes, EMX_NSERIALIZE, 1);
4037 emx_deserialize_skipmain(struct emx_softc *sc)
4039 lwkt_serialize_array_exit(sc->serializes, EMX_NSERIALIZE, 1);
4045 emx_serialize_assert(struct ifnet *ifp, enum ifnet_serialize slz,
4046 boolean_t serialized)
4048 struct emx_softc *sc = ifp->if_softc;
4050 ifnet_serialize_array_assert(sc->serializes, EMX_NSERIALIZE,
4054 #endif /* INVARIANTS */
4056 #ifdef IFPOLL_ENABLE
4059 emx_npoll_status(struct ifnet *ifp)
4061 struct emx_softc *sc = ifp->if_softc;
4064 ASSERT_SERIALIZED(&sc->main_serialize);
4066 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
4067 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
4068 callout_stop(&sc->timer);
4069 sc->hw.mac.get_link_status = 1;
4070 emx_update_link_status(sc);
4071 callout_reset(&sc->timer, hz, emx_timer, sc);
4076 emx_npoll_tx(struct ifnet *ifp, void *arg, int cycle __unused)
4078 struct emx_txdata *tdata = arg;
4080 ASSERT_SERIALIZED(&tdata->tx_serialize);
4083 if (!ifsq_is_empty(tdata->ifsq))
4084 ifsq_devstart(tdata->ifsq);
4088 emx_npoll_rx(struct ifnet *ifp __unused, void *arg, int cycle)
4090 struct emx_rxdata *rdata = arg;
4092 ASSERT_SERIALIZED(&rdata->rx_serialize);
4094 emx_rxeof(rdata, cycle);
4098 emx_npoll(struct ifnet *ifp, struct ifpoll_info *info)
4100 struct emx_softc *sc = ifp->if_softc;
4103 ASSERT_IFNET_SERIALIZED_ALL(ifp);
4108 info->ifpi_status.status_func = emx_npoll_status;
4109 info->ifpi_status.serializer = &sc->main_serialize;
4111 txr_cnt = emx_get_txring_inuse(sc, TRUE);
4112 off = sc->tx_npoll_off;
4113 for (i = 0; i < txr_cnt; ++i) {
4114 struct emx_txdata *tdata = &sc->tx_data[i];
4117 KKASSERT(idx < ncpus2);
4118 info->ifpi_tx[idx].poll_func = emx_npoll_tx;
4119 info->ifpi_tx[idx].arg = tdata;
4120 info->ifpi_tx[idx].serializer = &tdata->tx_serialize;
4121 ifsq_set_cpuid(tdata->ifsq, idx);
4124 off = sc->rx_npoll_off;
4125 for (i = 0; i < sc->rx_ring_cnt; ++i) {
4126 struct emx_rxdata *rdata = &sc->rx_data[i];
4129 KKASSERT(idx < ncpus2);
4130 info->ifpi_rx[idx].poll_func = emx_npoll_rx;
4131 info->ifpi_rx[idx].arg = rdata;
4132 info->ifpi_rx[idx].serializer = &rdata->rx_serialize;
4135 if (ifp->if_flags & IFF_RUNNING) {
4136 if (txr_cnt == sc->tx_ring_inuse)
4137 emx_disable_intr(sc);
4142 for (i = 0; i < sc->tx_ring_cnt; ++i) {
4143 struct emx_txdata *tdata = &sc->tx_data[i];
4145 ifsq_set_cpuid(tdata->ifsq,
4146 rman_get_cpuid(sc->intr_res));
4149 if (ifp->if_flags & IFF_RUNNING) {
4150 txr_cnt = emx_get_txring_inuse(sc, FALSE);
4151 if (txr_cnt == sc->tx_ring_inuse)
4152 emx_enable_intr(sc);
4159 #endif /* IFPOLL_ENABLE */
4162 emx_set_itr(struct emx_softc *sc, uint32_t itr)
4164 E1000_WRITE_REG(&sc->hw, E1000_ITR, itr);
4165 if (sc->hw.mac.type == e1000_82574) {
4169 * When using MSIX interrupts we need to
4170 * throttle using the EITR register
4172 for (i = 0; i < 4; ++i)
4173 E1000_WRITE_REG(&sc->hw, E1000_EITR_82574(i), itr);
4178 * Disable the L0s, 82574L Errata #20
4181 emx_disable_aspm(struct emx_softc *sc)
4183 uint16_t link_cap, link_ctrl, disable;
4184 uint8_t pcie_ptr, reg;
4185 device_t dev = sc->dev;
4187 switch (sc->hw.mac.type) {
4192 * 82573 specification update
4193 * errata #8 disable L0s
4194 * errata #41 disable L1
4196 * 82571/82572 specification update
4197 # errata #13 disable L1
4198 * errata #68 disable L0s
4200 disable = PCIEM_LNKCTL_ASPM_L0S | PCIEM_LNKCTL_ASPM_L1;
4205 * 82574 specification update errata #20
4207 * There is no need to disable L1
4209 disable = PCIEM_LNKCTL_ASPM_L0S;
4216 pcie_ptr = pci_get_pciecap_ptr(dev);
4220 link_cap = pci_read_config(dev, pcie_ptr + PCIER_LINKCAP, 2);
4221 if ((link_cap & PCIEM_LNKCAP_ASPM_MASK) == 0)
4225 if_printf(&sc->arpcom.ac_if, "disable ASPM %#02x\n", disable);
4227 reg = pcie_ptr + PCIER_LINKCTRL;
4228 link_ctrl = pci_read_config(dev, reg, 2);
4229 link_ctrl &= ~disable;
4230 pci_write_config(dev, reg, link_ctrl, 2);
4234 emx_tso_pullup(struct emx_txdata *tdata, struct mbuf **mp)
4236 int iphlen, hoff, thoff, ex = 0;
4241 KASSERT(M_WRITABLE(m), ("TSO mbuf not writable"));
4243 iphlen = m->m_pkthdr.csum_iphlen;
4244 thoff = m->m_pkthdr.csum_thlen;
4245 hoff = m->m_pkthdr.csum_lhlen;
4247 KASSERT(iphlen > 0, ("invalid ip hlen"));
4248 KASSERT(thoff > 0, ("invalid tcp hlen"));
4249 KASSERT(hoff > 0, ("invalid ether hlen"));
4251 if (tdata->tx_flags & EMX_TXFLAG_TSO_PULLEX)
4254 if (m->m_len < hoff + iphlen + thoff + ex) {
4255 m = m_pullup(m, hoff + iphlen + thoff + ex);
4262 ip = mtodoff(m, struct ip *, hoff);
4269 emx_tso_setup(struct emx_txdata *tdata, struct mbuf *mp,
4270 uint32_t *txd_upper, uint32_t *txd_lower)
4272 struct e1000_context_desc *TXD;
4273 int hoff, iphlen, thoff, hlen;
4274 int mss, pktlen, curr_txd;
4276 #ifdef EMX_TSO_DEBUG
4277 tdata->tso_segments++;
4280 iphlen = mp->m_pkthdr.csum_iphlen;
4281 thoff = mp->m_pkthdr.csum_thlen;
4282 hoff = mp->m_pkthdr.csum_lhlen;
4283 mss = mp->m_pkthdr.tso_segsz;
4284 pktlen = mp->m_pkthdr.len;
4286 if ((tdata->tx_flags & EMX_TXFLAG_FORCECTX) == 0 &&
4287 tdata->csum_flags == CSUM_TSO &&
4288 tdata->csum_iphlen == iphlen &&
4289 tdata->csum_lhlen == hoff &&
4290 tdata->csum_thlen == thoff &&
4291 tdata->csum_mss == mss &&
4292 tdata->csum_pktlen == pktlen) {
4293 *txd_upper = tdata->csum_txd_upper;
4294 *txd_lower = tdata->csum_txd_lower;
4295 #ifdef EMX_TSO_DEBUG
4296 tdata->tso_ctx_reused++;
4300 hlen = hoff + iphlen + thoff;
4303 * Setup a new TSO context.
4306 curr_txd = tdata->next_avail_tx_desc;
4307 TXD = (struct e1000_context_desc *)&tdata->tx_desc_base[curr_txd];
4309 *txd_lower = E1000_TXD_CMD_DEXT | /* Extended descr type */
4310 E1000_TXD_DTYP_D | /* Data descr type */
4311 E1000_TXD_CMD_TSE; /* Do TSE on this packet */
4313 /* IP and/or TCP header checksum calculation and insertion. */
4314 *txd_upper = (E1000_TXD_POPTS_IXSM | E1000_TXD_POPTS_TXSM) << 8;
4317 * Start offset for header checksum calculation.
4318 * End offset for header checksum calculation.
4319 * Offset of place put the checksum.
4321 TXD->lower_setup.ip_fields.ipcss = hoff;
4322 TXD->lower_setup.ip_fields.ipcse = htole16(hoff + iphlen - 1);
4323 TXD->lower_setup.ip_fields.ipcso = hoff + offsetof(struct ip, ip_sum);
4326 * Start offset for payload checksum calculation.
4327 * End offset for payload checksum calculation.
4328 * Offset of place to put the checksum.
4330 TXD->upper_setup.tcp_fields.tucss = hoff + iphlen;
4331 TXD->upper_setup.tcp_fields.tucse = 0;
4332 TXD->upper_setup.tcp_fields.tucso =
4333 hoff + iphlen + offsetof(struct tcphdr, th_sum);
4336 * Payload size per packet w/o any headers.
4337 * Length of all headers up to payload.
4339 TXD->tcp_seg_setup.fields.mss = htole16(mss);
4340 TXD->tcp_seg_setup.fields.hdr_len = hlen;
4341 TXD->cmd_and_length = htole32(E1000_TXD_CMD_IFCS |
4342 E1000_TXD_CMD_DEXT | /* Extended descr */
4343 E1000_TXD_CMD_TSE | /* TSE context */
4344 E1000_TXD_CMD_IP | /* Do IP csum */
4345 E1000_TXD_CMD_TCP | /* Do TCP checksum */
4346 (pktlen - hlen)); /* Total len */
4348 /* Save the information for this TSO context */
4349 tdata->csum_flags = CSUM_TSO;
4350 tdata->csum_lhlen = hoff;
4351 tdata->csum_iphlen = iphlen;
4352 tdata->csum_thlen = thoff;
4353 tdata->csum_mss = mss;
4354 tdata->csum_pktlen = pktlen;
4355 tdata->csum_txd_upper = *txd_upper;
4356 tdata->csum_txd_lower = *txd_lower;
4358 if (++curr_txd == tdata->num_tx_desc)
4361 KKASSERT(tdata->num_tx_desc_avail > 0);
4362 tdata->num_tx_desc_avail--;
4364 tdata->next_avail_tx_desc = curr_txd;
4369 emx_get_txring_inuse(const struct emx_softc *sc, boolean_t polling)
4372 return sc->tx_ring_cnt;