2 * Copyright (c) 2002-2006 Sam Leffler, Errno Consulting
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20 * GNU General Public License ("GPL") version 2 as published by the Free
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36 * $FreeBSD: src/sys/dev/ath/if_athvar.h,v 1.27.2.7 2006/07/10 01:15:24 sam Exp $
37 * $DragonFly: src/sys/dev/netif/ath/ath/if_athvar.h,v 1.3 2007/02/22 05:17:09 sephe Exp $
41 * Defintions for the Atheros Wireless LAN controller driver.
43 #ifndef _DEV_ATH_ATHVAR_H
44 #define _DEV_ATH_ATHVAR_H
46 #include <dev/netif/ath/hal/ath_hal/ah.h>
47 #include <dev/netif/ath/hal/ath_hal/ah_desc.h>
48 #include <netproto/802_11/ieee80211_radiotap.h>
49 #include <dev/netif/ath/ath/if_athioctl.h>
50 #include <dev/netif/ath/ath/if_athrate.h>
52 #define ATH_TIMEOUT 1000
55 #define ATH_RXBUF 40 /* number of RX buffers */
58 #define ATH_TXBUF 100 /* number of TX buffers */
60 #define ATH_TXDESC 10 /* number of descriptors per buffer */
61 #define ATH_TXMAXTRY 11 /* max number of transmit attempts */
62 #define ATH_TXMGTTRY 4 /* xmit attempts for mgt/ctl frames */
63 #define ATH_TXINTR_PERIOD 5 /* max number of batched tx descriptors */
65 #define ATH_BEACON_AIFS_DEFAULT 0 /* default aifs for ap beacon q */
66 #define ATH_BEACON_CWMIN_DEFAULT 0 /* default cwmin for ap beacon q */
67 #define ATH_BEACON_CWMAX_DEFAULT 0 /* default cwmax for ap beacon q */
70 * The key cache is used for h/w cipher state and also for
71 * tracking station state such as the current tx antenna.
72 * We also setup a mapping table between key cache slot indices
73 * and station state to short-circuit node lookups on rx.
74 * Different parts have different size key caches. We handle
75 * up to ATH_KEYMAX entries (could dynamically allocate state).
77 #define ATH_KEYMAX 128 /* max key cache size we handle */
78 #define ATH_KEYBYTES (ATH_KEYMAX/NBBY) /* storage space in bytes */
80 /* driver-specific node state */
82 struct ieee80211_node an_node; /* base class */
83 uint32_t an_avgrssi; /* average rssi over all rx frames */
84 /* variable-length rate control state follows */
86 #define ATH_NODE(ni) ((struct ath_node *)(ni))
87 #define ATH_NODE_CONST(ni) ((const struct ath_node *)(ni))
89 #define ATH_RSSI_LPF_LEN 10
90 #define ATH_RSSI_DUMMY_MARKER 0x127
91 #define ATH_EP_MUL(x, mul) ((x) * (mul))
92 #define ATH_RSSI_IN(x) (ATH_EP_MUL((x), HAL_RSSI_EP_MULTIPLIER))
93 #define ATH_LPF_RSSI(x, y, len) \
94 ((x != ATH_RSSI_DUMMY_MARKER) ? (((x) * ((len) - 1) + (y)) / (len)) : (y))
95 #define ATH_RSSI_LPF(x, y) do { \
97 x = ATH_LPF_RSSI((x), ATH_RSSI_IN((y)), ATH_RSSI_LPF_LEN); \
101 STAILQ_ENTRY(ath_buf) bf_list;
103 int bf_flags; /* tx descriptor flags */
104 struct ath_desc *bf_desc; /* virtual addr of desc */
105 struct ath_desc_status bf_status; /* tx/rx status */
106 bus_addr_t bf_daddr; /* physical addr of desc */
107 bus_dmamap_t bf_dmamap; /* DMA map for mbuf chain */
108 struct mbuf *bf_m; /* mbuf for buf */
109 struct ieee80211_node *bf_node; /* pointer to the node */
110 bus_size_t bf_mapsize;
111 #define ATH_MAX_SCATTER ATH_TXDESC /* max(tx,rx,beacon) desc's */
112 bus_dma_segment_t bf_segs[ATH_MAX_SCATTER];
114 typedef STAILQ_HEAD(, ath_buf) ath_bufhead;
117 * DMA state for tx/rx descriptors.
121 struct ath_desc *dd_desc; /* descriptors */
122 bus_addr_t dd_desc_paddr; /* physical addr of dd_desc */
123 bus_size_t dd_desc_len; /* size of dd_desc */
124 bus_dma_segment_t dd_dseg;
125 bus_dma_tag_t dd_dmat; /* bus DMA tag */
126 bus_dmamap_t dd_dmamap; /* DMA map for descriptors */
127 struct ath_buf *dd_bufptr; /* associated buffers */
131 * Data transmit queue state. One of these exists for each
132 * hardware transmit queue. Packets sent to us from above
133 * are assigned to queues based on their priority. Not all
134 * devices support a complete set of hardware transmit queues.
135 * For those devices the array sc_ac2q will map multiple
136 * priorities to fewer hardware queues (typically all to one
140 u_int axq_qnum; /* hardware q number */
141 u_int axq_depth; /* queue depth (stat only) */
142 u_int axq_intrcnt; /* interrupt count */
143 uint32_t *axq_link; /* link ptr in last TX desc */
144 STAILQ_HEAD(, ath_buf) axq_q; /* transmit queue */
145 char axq_name[12]; /* e.g. "ath0_txq4" */
148 #define ATH_TXQ_INSERT_TAIL(_tq, _elm, _field) do { \
149 STAILQ_INSERT_TAIL(&(_tq)->axq_q, (_elm), _field); \
150 (_tq)->axq_depth++; \
152 #define ATH_TXQ_REMOVE_HEAD(_tq, _field) do { \
153 STAILQ_REMOVE_HEAD(&(_tq)->axq_q, _field); \
154 (_tq)->axq_depth--; \
160 struct ieee80211com sc_ic; /* IEEE 802.11 common */
162 struct resource *sc_irq; /* irq resource */
163 void *sc_ih; /* interrupt handler */
166 struct ath_stats sc_stats; /* interface statistics */
169 void (*sc_recv_mgmt)(struct ieee80211com *,
171 struct ieee80211_node *,
173 int (*sc_newstate)(struct ieee80211com *,
174 enum ieee80211_state, int);
175 void (*sc_node_free)(struct ieee80211_node *);
177 HAL_BUS_TAG sc_st; /* bus space tag */
178 HAL_BUS_HANDLE sc_sh; /* bus space handle */
179 bus_dma_tag_t sc_dmat; /* bus DMA tag */
180 struct ath_hal *sc_ah; /* Atheros HAL */
181 struct ath_ratectrl *sc_rc; /* tx rate control support */
182 struct ath_tx99 *sc_tx99; /* tx99 adjunct state */
183 void (*sc_setdefantenna)(struct ath_softc *, u_int);
184 void (*sc_tx_proc)(struct ath_softc *);
185 unsigned int sc_invalid : 1, /* disable hardware accesses */
186 sc_mrretry : 1, /* multi-rate retry support */
187 sc_softled : 1, /* enable LED gpio status */
188 sc_splitmic: 1, /* split TKIP MIC keys */
189 sc_needmib : 1, /* enable MIB stats intr */
190 sc_diversity : 1,/* enable rx diversity */
191 sc_hasveol : 1, /* tx VEOL support */
192 sc_ledstate: 1, /* LED on/off state */
193 sc_blinking: 1, /* LED blink operation active */
194 sc_mcastkey: 1, /* mcast key cache search */
195 sc_syncbeacon:1,/* sync/resync beacon timers */
196 sc_hasclrkey:1; /* CLR key supported */
198 const HAL_RATE_TABLE *sc_rates[IEEE80211_MODE_MAX];
199 const HAL_RATE_TABLE *sc_currates; /* current rate table */
200 enum ieee80211_phymode sc_curmode; /* current phy mode */
201 HAL_OPMODE sc_opmode; /* current operating mode */
202 uint16_t sc_curtxpow; /* current tx power limit */
203 HAL_CHANNEL sc_curchan; /* current h/w channel */
204 uint8_t sc_rixmap[256]; /* IEEE to h/w rate table ix */
206 uint8_t ieeerate; /* IEEE rate */
207 uint8_t rxflags; /* radiotap rx flags */
208 uint8_t txflags; /* radiotap tx flags */
209 uint16_t ledon; /* softled on time */
210 uint16_t ledoff; /* softled off time */
211 } sc_hwmap[32]; /* h/w rate ix mappings */
212 uint8_t sc_minrateix; /* min h/w rate index */
213 uint8_t sc_mcastrix; /* mcast h/w rate index */
214 uint8_t sc_protrix; /* protection rate index */
215 u_int sc_mcastrate; /* ieee rate for mcastrateix */
216 u_int sc_txantenna; /* tx antenna (fixed or auto) */
217 HAL_INT sc_imask; /* interrupt mask copy */
218 u_int sc_keymax; /* size of key cache */
219 uint8_t sc_keymap[ATH_KEYBYTES];/* key use bit map */
221 u_int sc_ledpin; /* GPIO pin for driving LED */
222 u_int sc_ledon; /* pin setting for LED on */
223 u_int sc_ledidle; /* idle polling interval */
224 int sc_ledevent; /* time of last LED event */
225 uint8_t sc_rxrate; /* current rx rate for LED */
226 uint8_t sc_txrate; /* current tx rate for LED */
227 uint16_t sc_ledoff; /* off time for current blink */
228 struct callout sc_ledtimer; /* led off timer */
230 u_int sc_rfsilentpin; /* GPIO pin for rfkill int */
231 u_int sc_rfsilentpol; /* pin setting for rfkill on */
233 struct bpf_if *sc_drvbpf;
235 struct ath_tx_radiotap_header th;
240 struct ath_rx_radiotap_header th;
244 u_int sc_monpass; /* frames to pass in mon.mode */
246 struct ath_descdma sc_rxdma; /* RX descriptos */
247 ath_bufhead sc_rxbuf; /* receive buffer */
248 uint32_t *sc_rxlink; /* link ptr in last RX desc */
249 uint8_t sc_defant; /* current default antenna */
250 uint8_t sc_rxotherant; /* rx's on non-default antenna*/
251 uint64_t sc_lastrx; /* tsf at last rx'd frame */
253 struct ath_descdma sc_txdma; /* TX descriptors */
254 ath_bufhead sc_txbuf; /* transmit buffer */
255 char sc_txname[12]; /* e.g. "ath0_buf" */
256 int sc_tx_timer; /* transmit timeout */
257 u_int sc_txqsetup; /* h/w queues setup */
258 u_int sc_txintrperiod;/* tx interrupt batching */
259 struct ath_txq sc_txq[HAL_NUM_TX_QUEUES];
260 struct ath_txq *sc_ac2q[5]; /* WME AC -> h/w q map */
262 struct ath_descdma sc_bdma; /* beacon descriptors */
263 ath_bufhead sc_bbuf; /* beacon buffers */
264 u_int sc_bhalq; /* HAL q for outgoing beacons */
265 u_int sc_bmisscount; /* missed beacon transmits */
266 uint32_t sc_ant_tx[8]; /* recent tx frames/antenna */
267 struct ath_txq *sc_cabq; /* tx q for cab frames */
268 struct ieee80211_beacon_offsets sc_boff;/* dynamic update state */
270 OK, /* no change needed */
271 UPDATE, /* update pending */
272 COMMIT /* beacon sent, commit change */
273 } sc_updateslot; /* slot time update fsm */
274 struct ath_txq sc_mcastq; /* mcast xmits w/ ps sta's */
276 struct callout sc_cal_ch; /* callout handle for cals */
277 int sc_calinterval; /* current polling interval */
278 int sc_caltries; /* cals at current interval */
279 HAL_NODE_STATS sc_halstats; /* station-mode rssi stats */
280 struct callout sc_scan_ch; /* callout handle for scan */
281 struct callout sc_dfs_ch; /* callout handle for dfs */
283 struct sysctl_ctx_list sc_sysctl_ctx;
284 struct sysctl_oid *sc_sysctl_tree;
286 #define sc_tx_th u_tx_rt.th
287 #define sc_rx_th u_rx_rt.th
289 #define IS_ATH_TXQ_SETUP(sc, i) ((sc)->sc_txqsetup & (1 << (i)))
290 #define ATH_TXQ_SETUP(sc, i) \
291 do { (sc)->sc_txqsetup |= (1 << (i)); } while (0)
293 int ath_attach(uint16_t, struct ath_softc *);
294 int ath_detach(struct ath_softc *);
295 void ath_resume(struct ath_softc *);
296 void ath_suspend(struct ath_softc *);
297 void ath_shutdown(struct ath_softc *);
298 void ath_intr(void *);
301 * HAL definitions to comply with local coding convention.
303 #define ath_hal_detach(_ah) \
304 ((*(_ah)->ah_detach)((_ah)))
305 #define ath_hal_reset(_ah, _opmode, _chan, _outdoor, _pstatus) \
306 ((*(_ah)->ah_reset)((_ah), (_opmode), (_chan), (_outdoor), (_pstatus)))
307 #define ath_hal_getratetable(_ah, _mode) \
308 ((*(_ah)->ah_getRateTable)((_ah), (_mode)))
309 #define ath_hal_getmac(_ah, _mac) \
310 ((*(_ah)->ah_getMacAddress)((_ah), (_mac)))
311 #define ath_hal_setmac(_ah, _mac) \
312 ((*(_ah)->ah_setMacAddress)((_ah), (_mac)))
313 #define ath_hal_intrset(_ah, _mask) \
314 ((*(_ah)->ah_setInterrupts)((_ah), (_mask)))
315 #define ath_hal_intrget(_ah) \
316 ((*(_ah)->ah_getInterrupts)((_ah)))
317 #define ath_hal_intrpend(_ah) \
318 ((*(_ah)->ah_isInterruptPending)((_ah)))
319 #define ath_hal_getisr(_ah, _pmask) \
320 ((*(_ah)->ah_getPendingInterrupts)((_ah), (_pmask)))
321 #define ath_hal_updatetxtriglevel(_ah, _inc) \
322 ((*(_ah)->ah_updateTxTrigLevel)((_ah), (_inc)))
323 #define ath_hal_setpower(_ah, _mode) \
324 ((*(_ah)->ah_setPowerMode)((_ah), (_mode), AH_TRUE))
325 #define ath_hal_keycachesize(_ah) \
326 ((*(_ah)->ah_getKeyCacheSize)((_ah)))
327 #define ath_hal_keyreset(_ah, _ix) \
328 ((*(_ah)->ah_resetKeyCacheEntry)((_ah), (_ix)))
329 #define ath_hal_keyset(_ah, _ix, _pk, _mac) \
330 ((*(_ah)->ah_setKeyCacheEntry)((_ah), (_ix), (_pk), (_mac), AH_FALSE))
331 #define ath_hal_keyisvalid(_ah, _ix) \
332 (((*(_ah)->ah_isKeyCacheEntryValid)((_ah), (_ix))))
333 #define ath_hal_keysetmac(_ah, _ix, _mac) \
334 ((*(_ah)->ah_setKeyCacheEntryMac)((_ah), (_ix), (_mac)))
335 #define ath_hal_getrxfilter(_ah) \
336 ((*(_ah)->ah_getRxFilter)((_ah)))
337 #define ath_hal_setrxfilter(_ah, _filter) \
338 ((*(_ah)->ah_setRxFilter)((_ah), (_filter)))
339 #define ath_hal_setmcastfilter(_ah, _mfilt0, _mfilt1) \
340 ((*(_ah)->ah_setMulticastFilter)((_ah), (_mfilt0), (_mfilt1)))
341 #define ath_hal_waitforbeacon(_ah, _bf) \
342 ((*(_ah)->ah_waitForBeaconDone)((_ah), (_bf)->bf_daddr))
343 #define ath_hal_putrxbuf(_ah, _bufaddr) \
344 ((*(_ah)->ah_setRxDP)((_ah), (_bufaddr)))
345 #define ath_hal_gettsf32(_ah) \
346 ((*(_ah)->ah_getTsf32)((_ah)))
347 #define ath_hal_gettsf64(_ah) \
348 ((*(_ah)->ah_getTsf64)((_ah)))
349 #define ath_hal_resettsf(_ah) \
350 ((*(_ah)->ah_resetTsf)((_ah)))
351 #define ath_hal_rxena(_ah) \
352 ((*(_ah)->ah_enableReceive)((_ah)))
353 #define ath_hal_puttxbuf(_ah, _q, _bufaddr) \
354 ((*(_ah)->ah_setTxDP)((_ah), (_q), (_bufaddr)))
355 #define ath_hal_gettxbuf(_ah, _q) \
356 ((*(_ah)->ah_getTxDP)((_ah), (_q)))
357 #define ath_hal_numtxpending(_ah, _q) \
358 ((*(_ah)->ah_numTxPending)((_ah), (_q)))
359 #define ath_hal_getrxbuf(_ah) \
360 ((*(_ah)->ah_getRxDP)((_ah)))
361 #define ath_hal_txstart(_ah, _q) \
362 ((*(_ah)->ah_startTxDma)((_ah), (_q)))
363 #define ath_hal_setchannel(_ah, _chan) \
364 ((*(_ah)->ah_setChannel)((_ah), (_chan)))
365 #define ath_hal_calibrate(_ah, _chan, _iqcal) \
366 ((*(_ah)->ah_perCalibration)((_ah), (_chan), (_iqcal)))
367 #define ath_hal_setledstate(_ah, _state) \
368 ((*(_ah)->ah_setLedState)((_ah), (_state)))
369 #define ath_hal_beaconinit(_ah, _nextb, _bperiod) \
370 ((*(_ah)->ah_beaconInit)((_ah), (_nextb), (_bperiod)))
371 #define ath_hal_beaconreset(_ah) \
372 ((*(_ah)->ah_resetStationBeaconTimers)((_ah)))
373 #define ath_hal_beacontimers(_ah, _bs) \
374 ((*(_ah)->ah_setStationBeaconTimers)((_ah), (_bs)))
375 #define ath_hal_setassocid(_ah, _bss, _associd) \
376 ((*(_ah)->ah_writeAssocid)((_ah), (_bss), (_associd)))
377 #define ath_hal_phydisable(_ah) \
378 ((*(_ah)->ah_phyDisable)((_ah)))
379 #define ath_hal_setopmode(_ah) \
380 ((*(_ah)->ah_setPCUConfig)((_ah)))
381 #define ath_hal_stoptxdma(_ah, _qnum) \
382 ((*(_ah)->ah_stopTxDma)((_ah), (_qnum)))
383 #define ath_hal_stoppcurecv(_ah) \
384 ((*(_ah)->ah_stopPcuReceive)((_ah)))
385 #define ath_hal_startpcurecv(_ah) \
386 ((*(_ah)->ah_startPcuReceive)((_ah)))
387 #define ath_hal_stopdmarecv(_ah) \
388 ((*(_ah)->ah_stopDmaReceive)((_ah)))
389 #define ath_hal_getfatalstate(_ah, _outdata, _outsize) \
390 ath_hal_getdiagstate(_ah, 29, NULL, 0, (void **)(_outdata), _outsize)
391 #define ath_hal_getdiagstate(_ah, _id, _indata, _insize, _outdata, _outsize) \
392 ((*(_ah)->ah_getDiagState)((_ah), (_id), \
393 (_indata), (_insize), (_outdata), (_outsize)))
394 #define ath_hal_setuptxqueue(_ah, _type, _irq) \
395 ((*(_ah)->ah_setupTxQueue)((_ah), (_type), (_irq)))
396 #define ath_hal_resettxqueue(_ah, _q) \
397 ((*(_ah)->ah_resetTxQueue)((_ah), (_q)))
398 #define ath_hal_releasetxqueue(_ah, _q) \
399 ((*(_ah)->ah_releaseTxQueue)((_ah), (_q)))
400 #define ath_hal_gettxqueueprops(_ah, _q, _qi) \
401 ((*(_ah)->ah_getTxQueueProps)((_ah), (_q), (_qi)))
402 #define ath_hal_settxqueueprops(_ah, _q, _qi) \
403 ((*(_ah)->ah_setTxQueueProps)((_ah), (_q), (_qi)))
404 #define ath_hal_getrfgain(_ah) \
405 ((*(_ah)->ah_getRfGain)((_ah)))
406 #define ath_hal_getdefantenna(_ah) \
407 ((*(_ah)->ah_getDefAntenna)((_ah)))
408 #define ath_hal_setdefantenna(_ah, _ant) \
409 ((*(_ah)->ah_setDefAntenna)((_ah), (_ant)))
410 #define ath_hal_rxmonitor(_ah, _arg, _chan) \
411 ((*(_ah)->ah_rxMonitor)((_ah), (_arg), (_chan)))
412 #define ath_hal_mibevent(_ah, _stats) \
413 ((*(_ah)->ah_procMibEvent)((_ah), (_stats)))
414 #define ath_hal_setslottime(_ah, _us) \
415 ((*(_ah)->ah_setSlotTime)((_ah), (_us)))
416 #define ath_hal_getslottime(_ah) \
417 ((*(_ah)->ah_getSlotTime)((_ah)))
418 #define ath_hal_setacktimeout(_ah, _us) \
419 ((*(_ah)->ah_setAckTimeout)((_ah), (_us)))
420 #define ath_hal_getacktimeout(_ah) \
421 ((*(_ah)->ah_getAckTimeout)((_ah)))
422 #define ath_hal_setctstimeout(_ah, _us) \
423 ((*(_ah)->ah_setCTSTimeout)((_ah), (_us)))
424 #define ath_hal_getctstimeout(_ah) \
425 ((*(_ah)->ah_getCTSTimeout)((_ah)))
426 #define ath_hal_getcapability(_ah, _cap, _param, _result) \
427 ((*(_ah)->ah_getCapability)((_ah), (_cap), (_param), (_result)))
428 #define ath_hal_setcapability(_ah, _cap, _param, _v, _status) \
429 ((*(_ah)->ah_setCapability)((_ah), (_cap), (_param), (_v), (_status)))
430 #define ath_hal_ciphersupported(_ah, _cipher) \
431 (ath_hal_getcapability(_ah, HAL_CAP_CIPHER, _cipher, NULL) == HAL_OK)
432 #define ath_hal_getregdomain(_ah, _prd) \
433 (ath_hal_getcapability(_ah, HAL_CAP_REG_DMN, 0, (_prd)) == HAL_OK)
434 #define ath_hal_setregdomain(_ah, _rd) \
435 ((*(_ah)->ah_setRegulatoryDomain)((_ah), (_rd), NULL))
436 #define ath_hal_getcountrycode(_ah, _pcc) \
437 (*(_pcc) = (_ah)->ah_countryCode)
438 #define ath_hal_hastkipsplit(_ah) \
439 (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 0, NULL) == HAL_OK)
440 #define ath_hal_gettkipsplit(_ah) \
441 (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, NULL) == HAL_OK)
442 #define ath_hal_settkipsplit(_ah, _v) \
443 ath_hal_setcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, _v, NULL)
444 #define ath_hal_hwphycounters(_ah) \
445 (ath_hal_getcapability(_ah, HAL_CAP_PHYCOUNTERS, 0, NULL) == HAL_OK)
446 #define ath_hal_hasdiversity(_ah) \
447 (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 0, NULL) == HAL_OK)
448 #define ath_hal_getdiversity(_ah) \
449 (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 1, NULL) == HAL_OK)
450 #define ath_hal_setdiversity(_ah, _v) \
451 ath_hal_setcapability(_ah, HAL_CAP_DIVERSITY, 1, _v, NULL)
452 #define ath_hal_getdiag(_ah, _pv) \
453 (ath_hal_getcapability(_ah, HAL_CAP_DIAG, 0, _pv) == HAL_OK)
454 #define ath_hal_setdiag(_ah, _v) \
455 ath_hal_setcapability(_ah, HAL_CAP_DIAG, 0, _v, NULL)
456 #define ath_hal_getnumtxqueues(_ah, _pv) \
457 (ath_hal_getcapability(_ah, HAL_CAP_NUM_TXQUEUES, 0, _pv) == HAL_OK)
458 #define ath_hal_hasveol(_ah) \
459 (ath_hal_getcapability(_ah, HAL_CAP_VEOL, 0, NULL) == HAL_OK)
460 #define ath_hal_hastxpowlimit(_ah) \
461 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 0, NULL) == HAL_OK)
462 #define ath_hal_settxpowlimit(_ah, _pow) \
463 ((*(_ah)->ah_setTxPowerLimit)((_ah), (_pow)))
464 #define ath_hal_gettxpowlimit(_ah, _ppow) \
465 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 1, _ppow) == HAL_OK)
466 #define ath_hal_getmaxtxpow(_ah, _ppow) \
467 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 2, _ppow) == HAL_OK)
468 #define ath_hal_gettpscale(_ah, _scale) \
469 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 3, _scale) == HAL_OK)
470 #define ath_hal_settpscale(_ah, _v) \
471 ath_hal_setcapability(_ah, HAL_CAP_TXPOW, 3, _v, NULL)
472 #define ath_hal_hastpc(_ah) \
473 (ath_hal_getcapability(_ah, HAL_CAP_TPC, 0, NULL) == HAL_OK)
474 #define ath_hal_gettpc(_ah) \
475 (ath_hal_getcapability(_ah, HAL_CAP_TPC, 1, NULL) == HAL_OK)
476 #define ath_hal_settpc(_ah, _v) \
477 ath_hal_setcapability(_ah, HAL_CAP_TPC, 1, _v, NULL)
478 #define ath_hal_hasbursting(_ah) \
479 (ath_hal_getcapability(_ah, HAL_CAP_BURST, 0, NULL) == HAL_OK)
481 #define ath_hal_hasmcastkeysearch(_ah) \
482 (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 0, NULL) == HAL_OK)
483 #define ath_hal_getmcastkeysearch(_ah) \
484 (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 1, NULL) == HAL_OK)
486 #define ath_hal_getmcastkeysearch(_ah) 0
488 #define ath_hal_hasrfsilent(_ah) \
489 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 0, NULL) == HAL_OK)
490 #define ath_hal_getrfkill(_ah) \
491 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 1, NULL) == HAL_OK)
492 #define ath_hal_setrfkill(_ah, _onoff) \
493 ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 1, _onoff, NULL)
494 #define ath_hal_getrfsilent(_ah, _prfsilent) \
495 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 2, _prfsilent) == HAL_OK)
496 #define ath_hal_setrfsilent(_ah, _rfsilent) \
497 ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 2, _rfsilent, NULL)
498 #define ath_hal_gettpack(_ah, _ptpack) \
499 (ath_hal_getcapability(_ah, HAL_CAP_TPC_ACK, 0, _ptpack) == HAL_OK)
500 #define ath_hal_settpack(_ah, _tpack) \
501 ath_hal_setcapability(_ah, HAL_CAP_TPC_ACK, 0, _tpack, NULL)
502 #define ath_hal_gettpcts(_ah, _ptpcts) \
503 (ath_hal_getcapability(_ah, HAL_CAP_TPC_CTS, 0, _ptpcts) == HAL_OK)
504 #define ath_hal_settpcts(_ah, _tpcts) \
505 ath_hal_setcapability(_ah, HAL_CAP_TPC_CTS, 0, _tpcts, NULL)
506 #if HAL_ABI_VERSION < 0x05120700
507 #define ath_hal_process_noisefloor(_ah)
508 #define ath_hal_getchannoise(_ah, _c) (-96)
509 #define HAL_CAP_TPC_ACK 100
510 #define HAL_CAP_TPC_CTS 101
512 #define ath_hal_getchannoise(_ah, _c) \
513 ((*(_ah)->ah_getChanNoise)((_ah), (_c)))
515 #if HAL_ABI_VERSION < 0x05122200
516 #define HAL_TXQ_TXOKINT_ENABLE TXQ_FLAG_TXOKINT_ENABLE
517 #define HAL_TXQ_TXERRINT_ENABLE TXQ_FLAG_TXERRINT_ENABLE
518 #define HAL_TXQ_TXDESCINT_ENABLE TXQ_FLAG_TXDESCINT_ENABLE
519 #define HAL_TXQ_TXEOLINT_ENABLE TXQ_FLAG_TXEOLINT_ENABLE
520 #define HAL_TXQ_TXURNINT_ENABLE TXQ_FLAG_TXURNINT_ENABLE
523 #define ath_hal_setuprxdesc(_ah, _ds, _size, _intreq) \
524 ((*(_ah)->ah_setupRxDesc)((_ah), (_ds), (_size), (_intreq)))
525 #define ath_hal_rxprocdesc(_ah, _ds, _dspa, _dsnext, _rs) \
526 ((*(_ah)->ah_procRxDesc)((_ah), (_ds), (_dspa), (_dsnext), 0, (_rs)))
527 #define ath_hal_setuptxdesc(_ah, _ds, _plen, _hlen, _atype, _txpow, \
528 _txr0, _txtr0, _keyix, _ant, _flags, \
529 _rtsrate, _rtsdura) \
530 ((*(_ah)->ah_setupTxDesc)((_ah), (_ds), (_plen), (_hlen), (_atype), \
531 (_txpow), (_txr0), (_txtr0), (_keyix), (_ant), \
532 (_flags), (_rtsrate), (_rtsdura), 0, 0, 0))
533 #define ath_hal_setupxtxdesc(_ah, _ds, \
534 _txr1, _txtr1, _txr2, _txtr2, _txr3, _txtr3) \
535 ((*(_ah)->ah_setupXTxDesc)((_ah), (_ds), \
536 (_txr1), (_txtr1), (_txr2), (_txtr2), (_txr3), (_txtr3)))
537 #define ath_hal_filltxdesc(_ah, _ds, _l, _first, _last, _ds0) \
538 ((*(_ah)->ah_fillTxDesc)((_ah), (_ds), (_l), (_first), (_last), (_ds0)))
539 #define ath_hal_txprocdesc(_ah, _ds, _ts) \
540 ((*(_ah)->ah_procTxDesc)((_ah), (_ds), (_ts)))
541 #define ath_hal_gettxintrtxqs(_ah, _txqs) \
542 ((*(_ah)->ah_getTxIntrQueue)((_ah), (_txqs)))
544 #define ath_hal_gpioCfgOutput(_ah, _gpio) \
545 ((*(_ah)->ah_gpioCfgOutput)((_ah), (_gpio)))
546 #define ath_hal_gpioset(_ah, _gpio, _b) \
547 ((*(_ah)->ah_gpioSet)((_ah), (_gpio), (_b)))
548 #define ath_hal_gpioget(_ah, _gpio) \
549 ((*(_ah)->ah_gpioGet)((_ah), (_gpio)))
550 #define ath_hal_gpiosetintr(_ah, _gpio, _b) \
551 ((*(_ah)->ah_gpioSetIntr)((_ah), (_gpio), (_b)))
553 #define ath_hal_radar_wait(_ah, _chan) \
554 ((*(_ah)->ah_radarWait)((_ah), (_chan)))
556 #endif /* _DEV_ATH_ATHVAR_H */