1 /* Subroutines for insn-output.c for Intel X86.
2 Copyright (C) 1988, 92, 94-98, 1999 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
21 /* $FreeBSD: src/contrib/gcc/config/i386/i386.c,v 1.7 2000/01/29 13:06:33 obrien Exp $ */
22 /* $DragonFly: src/contrib/gcc/config/i386/Attic/i386.c,v 1.2 2003/06/17 04:24:01 dillon Exp $ */
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-flags.h"
35 #include "insn-attr.h"
44 #ifdef EXTRA_CONSTRAINT
45 /* If EXTRA_CONSTRAINT is defined, then the 'S'
46 constraint in REG_CLASS_FROM_LETTER will no longer work, and various
47 asm statements that need 'S' for class SIREG will break. */
48 error EXTRA_CONSTRAINT conflicts with S constraint letter
49 /* The previous line used to be #error, but some compilers barf
50 even if the conditional was untrue. */
53 #ifndef CHECK_STACK_LIMIT
54 #define CHECK_STACK_LIMIT -1
57 #define PIC_REG_USED \
58 (flag_pic && (current_function_uses_pic_offset_table \
59 || current_function_uses_const_pool \
60 || profile_flag || profile_block_flag))
62 /* Type of an operand for ix86_{binary,unary}_operator_ok */
70 /* Processor costs (relative to an add) */
71 struct processor_costs i386_cost = { /* 386 specific costs */
72 1, /* cost of an add instruction */
73 1, /* cost of a lea instruction */
74 3, /* variable shift costs */
75 2, /* constant shift costs */
76 6, /* cost of starting a multiply */
77 1, /* cost of multiply per each bit set */
78 23 /* cost of a divide/mod */
81 struct processor_costs i486_cost = { /* 486 specific costs */
82 1, /* cost of an add instruction */
83 1, /* cost of a lea instruction */
84 3, /* variable shift costs */
85 2, /* constant shift costs */
86 12, /* cost of starting a multiply */
87 1, /* cost of multiply per each bit set */
88 40 /* cost of a divide/mod */
91 struct processor_costs pentium_cost = {
92 1, /* cost of an add instruction */
93 1, /* cost of a lea instruction */
94 4, /* variable shift costs */
95 1, /* constant shift costs */
96 11, /* cost of starting a multiply */
97 0, /* cost of multiply per each bit set */
98 25 /* cost of a divide/mod */
101 struct processor_costs pentiumpro_cost = {
102 1, /* cost of an add instruction */
103 1, /* cost of a lea instruction */
104 3, /* variable shift costs */
105 1, /* constant shift costs */
106 4, /* cost of starting a multiply */
107 0, /* cost of multiply per each bit set */
108 17 /* cost of a divide/mod */
111 /* We use decoding time together with execution time.
112 To get correct vale add 1 for short decodable, 2 for long decodable
113 and 4 for vector decodable instruction to execution time and divide
114 by two (because CPU is able to do two insns at a time). */
116 struct processor_costs k6_cost = {
117 1, /* cost of an add instruction */
118 1, /* cost of a lea instruction */
119 1, /* variable shift costs */
120 1, /* constant shift costs */
121 3, /* cost of starting a multiply */
122 0, /* cost of multiply per each bit set */
123 20 /* cost of a divide/mod */
126 struct processor_costs *ix86_cost = &pentium_cost;
128 /* Processor feature/optimization bitmasks. */
129 #define m_386 (1<<PROCESSOR_I386)
130 #define m_486 (1<<PROCESSOR_I486)
131 #define m_PENT (1<<PROCESSOR_PENTIUM)
132 #define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
133 #define m_K6 (1<<PROCESSOR_K6)
135 const int x86_use_leave = m_386 | m_K6;
136 const int x86_push_memory = m_386 | m_K6;
137 const int x86_zero_extend_with_and = m_486 | m_PENT;
138 const int x86_movx = m_386 | m_PPRO | m_K6;
139 const int x86_double_with_add = ~(m_386 | m_PENT | m_PPRO);
140 const int x86_use_bit_test = m_386;
141 const int x86_unroll_strlen = m_486 | m_PENT | m_PPRO;
142 const int x86_use_q_reg = m_PENT | m_PPRO | m_K6;
143 const int x86_use_any_reg = m_486;
144 const int x86_cmove = m_PPRO;
145 const int x86_deep_branch = m_PPRO| m_K6;
147 #define AT_BP(mode) (gen_rtx_MEM ((mode), frame_pointer_rtx))
149 extern FILE *asm_out_file;
150 extern char *strcat ();
152 static void ix86_epilogue PROTO((int));
153 static void ix86_prologue PROTO((int));
155 char *singlemove_string ();
156 char *output_move_const_single ();
157 char *output_fp_cc0_set ();
159 char *hi_reg_name[] = HI_REGISTER_NAMES;
160 char *qi_reg_name[] = QI_REGISTER_NAMES;
161 char *qi_high_reg_name[] = QI_HIGH_REGISTER_NAMES;
163 /* Array of the smallest class containing reg number REGNO, indexed by
164 REGNO. Used by REGNO_REG_CLASS in i386.h. */
166 enum reg_class regclass_map[FIRST_PSEUDO_REGISTER] =
169 AREG, DREG, CREG, BREG,
171 SIREG, DIREG, INDEX_REGS, GENERAL_REGS,
173 FP_TOP_REG, FP_SECOND_REG, FLOAT_REGS, FLOAT_REGS,
174 FLOAT_REGS, FLOAT_REGS, FLOAT_REGS, FLOAT_REGS,
179 /* Test and compare insns in i386.md store the information needed to
180 generate branch and scc insns here. */
182 struct rtx_def *i386_compare_op0 = NULL_RTX;
183 struct rtx_def *i386_compare_op1 = NULL_RTX;
184 struct rtx_def *(*i386_compare_gen)(), *(*i386_compare_gen_eq)();
186 /* which cpu are we scheduling for */
187 enum processor_type ix86_cpu;
189 /* which instruction set architecture to use. */
192 /* Strings to hold which cpu and instruction set architecture to use. */
193 char *ix86_cpu_string; /* for -mcpu=<xxx> */
194 char *ix86_arch_string; /* for -march=<xxx> */
196 /* Register allocation order */
197 char *i386_reg_alloc_order;
198 static char regs_allocated[FIRST_PSEUDO_REGISTER];
200 /* # of registers to use to pass arguments. */
201 char *i386_regparm_string;
203 /* i386_regparm_string as a number */
206 /* Alignment to use for loops and jumps: */
208 /* Power of two alignment for loops. */
209 char *i386_align_loops_string;
211 /* Power of two alignment for non-loop jumps. */
212 char *i386_align_jumps_string;
214 /* Power of two alignment for stack boundary in bytes. */
215 char *i386_preferred_stack_boundary_string;
217 /* Preferred alignment for stack boundary in bits. */
218 int i386_preferred_stack_boundary;
220 /* Values 1-5: see jump.c */
221 int i386_branch_cost;
222 char *i386_branch_cost_string;
224 /* Power of two alignment for functions. */
225 int i386_align_funcs;
226 char *i386_align_funcs_string;
228 /* Power of two alignment for loops. */
229 int i386_align_loops;
231 /* Power of two alignment for non-loop jumps. */
232 int i386_align_jumps;
234 /* Sometimes certain combinations of command options do not make
235 sense on a particular target machine. You can define a macro
236 `OVERRIDE_OPTIONS' to take account of this. This macro, if
237 defined, is executed once just after all the command options have
240 Don't use this macro to turn on various extra optimizations for
241 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
251 char *name; /* Canonical processor name. */
252 enum processor_type processor; /* Processor type enum value. */
253 struct processor_costs *cost; /* Processor costs */
254 int target_enable; /* Target flags to enable. */
255 int target_disable; /* Target flags to disable. */
256 } processor_target_table[] = {
257 {PROCESSOR_I386_STRING, PROCESSOR_I386, &i386_cost, 0, 0},
258 {PROCESSOR_I486_STRING, PROCESSOR_I486, &i486_cost, 0, 0},
259 {PROCESSOR_I586_STRING, PROCESSOR_PENTIUM, &pentium_cost, 0, 0},
260 {PROCESSOR_PENTIUM_STRING, PROCESSOR_PENTIUM, &pentium_cost, 0, 0},
261 {PROCESSOR_I686_STRING, PROCESSOR_PENTIUMPRO, &pentiumpro_cost, 0, 0},
262 {PROCESSOR_PENTIUMPRO_STRING, PROCESSOR_PENTIUMPRO,
263 &pentiumpro_cost, 0, 0},
264 {PROCESSOR_K6_STRING, PROCESSOR_K6, &k6_cost, 0, 0}
267 int ptt_size = sizeof (processor_target_table) / sizeof (struct ptt);
269 #ifdef SUBTARGET_OVERRIDE_OPTIONS
270 SUBTARGET_OVERRIDE_OPTIONS;
273 /* Validate registers in register allocation order. */
274 if (i386_reg_alloc_order)
276 for (i = 0; (ch = i386_reg_alloc_order[i]) != '\0'; i++)
282 case 'a': regno = 0; break;
283 case 'd': regno = 1; break;
284 case 'c': regno = 2; break;
285 case 'b': regno = 3; break;
286 case 'S': regno = 4; break;
287 case 'D': regno = 5; break;
288 case 'B': regno = 6; break;
290 default: fatal ("Register '%c' is unknown", ch);
293 if (regs_allocated[regno])
294 fatal ("Register '%c' already specified in allocation order", ch);
296 regs_allocated[regno] = 1;
300 if (ix86_arch_string == 0)
302 ix86_arch_string = PROCESSOR_PENTIUM_STRING;
303 if (ix86_cpu_string == 0)
304 ix86_cpu_string = PROCESSOR_DEFAULT_STRING;
307 for (i = 0; i < ptt_size; i++)
308 if (! strcmp (ix86_arch_string, processor_target_table[i].name))
310 ix86_arch = processor_target_table[i].processor;
311 if (ix86_cpu_string == 0)
312 ix86_cpu_string = processor_target_table[i].name;
318 error ("bad value (%s) for -march= switch", ix86_arch_string);
319 ix86_arch_string = PROCESSOR_PENTIUM_STRING;
320 ix86_arch = PROCESSOR_DEFAULT;
323 if (ix86_cpu_string == 0)
324 ix86_cpu_string = PROCESSOR_DEFAULT_STRING;
326 for (j = 0; j < ptt_size; j++)
327 if (! strcmp (ix86_cpu_string, processor_target_table[j].name))
329 ix86_cpu = processor_target_table[j].processor;
330 ix86_cost = processor_target_table[j].cost;
331 if (i > j && (int) ix86_arch >= (int) PROCESSOR_K6)
332 error ("-mcpu=%s does not support -march=%s",
333 ix86_cpu_string, ix86_arch_string);
335 target_flags |= processor_target_table[j].target_enable;
336 target_flags &= ~processor_target_table[j].target_disable;
342 error ("bad value (%s) for -mcpu= switch", ix86_cpu_string);
343 ix86_cpu_string = PROCESSOR_DEFAULT_STRING;
344 ix86_cpu = PROCESSOR_DEFAULT;
347 /* Validate -mregparm= value. */
348 if (i386_regparm_string)
350 i386_regparm = atoi (i386_regparm_string);
351 if (i386_regparm < 0 || i386_regparm > REGPARM_MAX)
352 fatal ("-mregparm=%d is not between 0 and %d",
353 i386_regparm, REGPARM_MAX);
356 /* The 486 suffers more from non-aligned cache line fills, and the
357 larger code size results in a larger cache foot-print and more misses.
358 The 486 has a 16 byte cache line, pentium and pentiumpro have a 32 byte
360 def_align = (TARGET_486) ? 4 : 2;
362 /* Validate -malign-loops= value, or provide default. */
363 #ifdef ASM_OUTPUT_MAX_SKIP_ALIGN
364 i386_align_loops = 4;
366 i386_align_loops = 2;
368 if (i386_align_loops_string)
370 i386_align_loops = atoi (i386_align_loops_string);
371 if (i386_align_loops < 0 || i386_align_loops > MAX_CODE_ALIGN)
372 fatal ("-malign-loops=%d is not between 0 and %d",
373 i386_align_loops, MAX_CODE_ALIGN);
376 /* Validate -malign-jumps= value, or provide default. */
377 #ifdef ASM_OUTPUT_MAX_SKIP_ALIGN
378 i386_align_jumps = 4;
380 i386_align_jumps = def_align;
382 if (i386_align_jumps_string)
384 i386_align_jumps = atoi (i386_align_jumps_string);
385 if (i386_align_jumps < 0 || i386_align_jumps > MAX_CODE_ALIGN)
386 fatal ("-malign-jumps=%d is not between 0 and %d",
387 i386_align_jumps, MAX_CODE_ALIGN);
390 /* Validate -malign-functions= value, or provide default. */
391 i386_align_funcs = def_align;
392 if (i386_align_funcs_string)
394 i386_align_funcs = atoi (i386_align_funcs_string);
395 if (i386_align_funcs < 0 || i386_align_funcs > MAX_CODE_ALIGN)
396 fatal ("-malign-functions=%d is not between 0 and %d",
397 i386_align_funcs, MAX_CODE_ALIGN);
400 /* Validate -mpreferred_stack_boundary= value, or provide default.
401 The default of 128 bits is for Pentium III's SSE __m128. */
402 i386_preferred_stack_boundary = 128;
403 if (i386_preferred_stack_boundary_string)
405 i = atoi (i386_preferred_stack_boundary_string);
407 fatal ("-mpreferred_stack_boundary=%d is not between 2 and 31", i);
408 i386_preferred_stack_boundary = (1 << i) * BITS_PER_UNIT;
411 /* Validate -mbranch-cost= value, or provide default. */
412 i386_branch_cost = 1;
413 if (i386_branch_cost_string)
415 i386_branch_cost = atoi (i386_branch_cost_string);
416 if (i386_branch_cost < 0 || i386_branch_cost > 5)
417 fatal ("-mbranch-cost=%d is not between 0 and 5", i386_branch_cost);
420 /* Keep nonleaf frame pointers. */
421 if (TARGET_OMIT_LEAF_FRAME_POINTER)
422 flag_omit_frame_pointer = 1;
425 /* A C statement (sans semicolon) to choose the order in which to
426 allocate hard registers for pseudo-registers local to a basic
429 Store the desired register order in the array `reg_alloc_order'.
430 Element 0 should be the register to allocate first; element 1, the
431 next register; and so on.
433 The macro body should not assume anything about the contents of
434 `reg_alloc_order' before execution of the macro.
436 On most machines, it is not necessary to define this macro. */
439 order_regs_for_local_alloc ()
443 /* User specified the register allocation order. */
445 if (i386_reg_alloc_order)
447 for (i = order = 0; (ch = i386_reg_alloc_order[i]) != '\0'; i++)
453 case 'a': regno = 0; break;
454 case 'd': regno = 1; break;
455 case 'c': regno = 2; break;
456 case 'b': regno = 3; break;
457 case 'S': regno = 4; break;
458 case 'D': regno = 5; break;
459 case 'B': regno = 6; break;
462 reg_alloc_order[order++] = regno;
465 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
467 if (! regs_allocated[i])
468 reg_alloc_order[order++] = i;
472 /* If user did not specify a register allocation order, use natural order. */
475 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
476 reg_alloc_order[i] = i;
481 optimization_options (level, size)
483 int size ATTRIBUTE_UNUSED;
485 /* For -O2 and beyond, turn off -fschedule-insns by default. It tends to
486 make the problem with not enough registers even worse. */
487 #ifdef INSN_SCHEDULING
489 flag_schedule_insns = 0;
493 /* Sign-extend a 16-bit constant */
496 i386_sext16_if_const (op)
499 if (GET_CODE (op) == CONST_INT)
501 HOST_WIDE_INT val = INTVAL (op);
502 HOST_WIDE_INT sext_val;
504 sext_val = val | ~0xffff;
506 sext_val = val & 0xffff;
508 op = GEN_INT (sext_val);
513 /* Return nonzero if the rtx is aligned */
516 i386_aligned_reg_p (regno)
519 return (regno == STACK_POINTER_REGNUM
520 || (! flag_omit_frame_pointer && regno == FRAME_POINTER_REGNUM));
527 /* Registers and immediate operands are always "aligned". */
528 if (GET_CODE (op) != MEM)
531 /* Don't even try to do any aligned optimizations with volatiles. */
532 if (MEM_VOLATILE_P (op))
535 /* Get address of memory operand. */
538 switch (GET_CODE (op))
545 /* Match "reg + offset" */
547 if (GET_CODE (XEXP (op, 1)) != CONST_INT)
549 if (INTVAL (XEXP (op, 1)) & 3)
553 if (GET_CODE (op) != REG)
556 /* ... fall through ... */
559 return i386_aligned_reg_p (REGNO (op));
568 /* Return nonzero if INSN looks like it won't compute useful cc bits
569 as a side effect. This information is only a hint. */
572 i386_cc_probably_useless_p (insn)
575 return ! next_cc0_user (insn);
578 /* Return nonzero if IDENTIFIER with arguments ARGS is a valid machine specific
579 attribute for DECL. The attributes in ATTRIBUTES have previously been
583 i386_valid_decl_attribute_p (decl, attributes, identifier, args)
584 tree decl ATTRIBUTE_UNUSED;
585 tree attributes ATTRIBUTE_UNUSED;
586 tree identifier ATTRIBUTE_UNUSED;
587 tree args ATTRIBUTE_UNUSED;
592 /* Return nonzero if IDENTIFIER with arguments ARGS is a valid machine specific
593 attribute for TYPE. The attributes in ATTRIBUTES have previously been
597 i386_valid_type_attribute_p (type, attributes, identifier, args)
599 tree attributes ATTRIBUTE_UNUSED;
603 if (TREE_CODE (type) != FUNCTION_TYPE
604 && TREE_CODE (type) != METHOD_TYPE
605 && TREE_CODE (type) != FIELD_DECL
606 && TREE_CODE (type) != TYPE_DECL)
609 /* Stdcall attribute says callee is responsible for popping arguments
610 if they are not variable. */
611 if (is_attribute_p ("stdcall", identifier))
612 return (args == NULL_TREE);
614 /* Cdecl attribute says the callee is a normal C declaration. */
615 if (is_attribute_p ("cdecl", identifier))
616 return (args == NULL_TREE);
618 /* Regparm attribute specifies how many integer arguments are to be
619 passed in registers. */
620 if (is_attribute_p ("regparm", identifier))
624 if (! args || TREE_CODE (args) != TREE_LIST
625 || TREE_CHAIN (args) != NULL_TREE
626 || TREE_VALUE (args) == NULL_TREE)
629 cst = TREE_VALUE (args);
630 if (TREE_CODE (cst) != INTEGER_CST)
633 if (TREE_INT_CST_HIGH (cst) != 0
634 || TREE_INT_CST_LOW (cst) < 0
635 || TREE_INT_CST_LOW (cst) > REGPARM_MAX)
644 /* Return 0 if the attributes for two types are incompatible, 1 if they
645 are compatible, and 2 if they are nearly compatible (which causes a
646 warning to be generated). */
649 i386_comp_type_attributes (type1, type2)
653 /* Check for mismatch of non-default calling convention. */
654 char *rtdstr = TARGET_RTD ? "cdecl" : "stdcall";
656 if (TREE_CODE (type1) != FUNCTION_TYPE)
659 /* Check for mismatched return types (cdecl vs stdcall). */
660 if (!lookup_attribute (rtdstr, TYPE_ATTRIBUTES (type1))
661 != !lookup_attribute (rtdstr, TYPE_ATTRIBUTES (type2)))
667 /* Value is the number of bytes of arguments automatically
668 popped when returning from a subroutine call.
669 FUNDECL is the declaration node of the function (as a tree),
670 FUNTYPE is the data type of the function (as a tree),
671 or for a library call it is an identifier node for the subroutine name.
672 SIZE is the number of bytes of arguments passed on the stack.
674 On the 80386, the RTD insn may be used to pop them if the number
675 of args is fixed, but if the number is variable then the caller
676 must pop them all. RTD can't be used for library calls now
677 because the library is compiled with the Unix compiler.
678 Use of RTD is a selectable option, since it is incompatible with
679 standard Unix calling sequences. If the option is not selected,
680 the caller must always pop the args.
682 The attribute stdcall is equivalent to RTD on a per module basis. */
685 i386_return_pops_args (fundecl, funtype, size)
690 int rtd = TARGET_RTD && (!fundecl || TREE_CODE (fundecl) != IDENTIFIER_NODE);
692 /* Cdecl functions override -mrtd, and never pop the stack. */
693 if (! lookup_attribute ("cdecl", TYPE_ATTRIBUTES (funtype))) {
695 /* Stdcall functions will pop the stack if not variable args. */
696 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (funtype)))
700 && (TYPE_ARG_TYPES (funtype) == NULL_TREE
701 || (TREE_VALUE (tree_last (TYPE_ARG_TYPES (funtype)))
706 /* Lose any fake structure return argument. */
707 if (aggregate_value_p (TREE_TYPE (funtype)))
708 return GET_MODE_SIZE (Pmode);
714 /* Argument support functions. */
716 /* Initialize a variable CUM of type CUMULATIVE_ARGS
717 for a call to a function whose data type is FNTYPE.
718 For a library call, FNTYPE is 0. */
721 init_cumulative_args (cum, fntype, libname)
722 CUMULATIVE_ARGS *cum; /* Argument info to initialize */
723 tree fntype; /* tree ptr for function decl */
724 rtx libname; /* SYMBOL_REF of library name or 0 */
726 static CUMULATIVE_ARGS zero_cum;
727 tree param, next_param;
729 if (TARGET_DEBUG_ARG)
731 fprintf (stderr, "\ninit_cumulative_args (");
733 fprintf (stderr, "fntype code = %s, ret code = %s",
734 tree_code_name[(int) TREE_CODE (fntype)],
735 tree_code_name[(int) TREE_CODE (TREE_TYPE (fntype))]);
737 fprintf (stderr, "no fntype");
740 fprintf (stderr, ", libname = %s", XSTR (libname, 0));
745 /* Set up the number of registers to use for passing arguments. */
746 cum->nregs = i386_regparm;
749 tree attr = lookup_attribute ("regparm", TYPE_ATTRIBUTES (fntype));
752 cum->nregs = TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (attr)));
755 /* Determine if this function has variable arguments. This is
756 indicated by the last argument being 'void_type_mode' if there
757 are no variable arguments. If there are variable arguments, then
758 we won't pass anything in registers */
762 for (param = (fntype) ? TYPE_ARG_TYPES (fntype) : 0;
763 param != 0; param = next_param)
765 next_param = TREE_CHAIN (param);
766 if (next_param == 0 && TREE_VALUE (param) != void_type_node)
771 if (TARGET_DEBUG_ARG)
772 fprintf (stderr, ", nregs=%d )\n", cum->nregs);
777 /* Update the data in CUM to advance over an argument
778 of mode MODE and data type TYPE.
779 (TYPE is null for libcalls where that information may not be available.) */
782 function_arg_advance (cum, mode, type, named)
783 CUMULATIVE_ARGS *cum; /* current arg information */
784 enum machine_mode mode; /* current arg mode */
785 tree type; /* type of the argument or 0 if lib support */
786 int named; /* whether or not the argument was named */
789 = (mode == BLKmode) ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
790 int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
792 if (TARGET_DEBUG_ARG)
794 "function_adv (sz=%d, wds=%2d, nregs=%d, mode=%s, named=%d)\n\n",
795 words, cum->words, cum->nregs, GET_MODE_NAME (mode), named);
810 /* Define where to put the arguments to a function.
811 Value is zero to push the argument on the stack,
812 or a hard register in which to store the argument.
814 MODE is the argument's machine mode.
815 TYPE is the data type of the argument (as a tree).
816 This is null for libcalls where that information may
818 CUM is a variable of type CUMULATIVE_ARGS which gives info about
819 the preceding args and about the function being called.
820 NAMED is nonzero if this argument is a named parameter
821 (otherwise it is an extra parameter matching an ellipsis). */
824 function_arg (cum, mode, type, named)
825 CUMULATIVE_ARGS *cum; /* current arg information */
826 enum machine_mode mode; /* current arg mode */
827 tree type; /* type of the argument or 0 if lib support */
828 int named; /* != 0 for normal args, == 0 for ... args */
832 = (mode == BLKmode) ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
833 int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
837 /* For now, pass fp/complex values on the stack. */
846 if (words <= cum->nregs)
847 ret = gen_rtx_REG (mode, cum->regno);
851 if (TARGET_DEBUG_ARG)
854 "function_arg (size=%d, wds=%2d, nregs=%d, mode=%4s, named=%d",
855 words, cum->words, cum->nregs, GET_MODE_NAME (mode), named);
858 fprintf (stderr, ", reg=%%e%s", reg_names[ REGNO(ret) ]);
860 fprintf (stderr, ", stack");
862 fprintf (stderr, " )\n");
868 /* For an arg passed partly in registers and partly in memory,
869 this is the number of registers used.
870 For args passed entirely in registers or entirely in memory, zero. */
873 function_arg_partial_nregs (cum, mode, type, named)
874 CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED; /* current arg information */
875 enum machine_mode mode ATTRIBUTE_UNUSED; /* current arg mode */
876 tree type ATTRIBUTE_UNUSED; /* type of the argument or 0 if lib support */
877 int named ATTRIBUTE_UNUSED; /* != 0 for normal args, == 0 for ... args */
883 singlemove_string (operands)
887 if (GET_CODE (operands[0]) == MEM
888 && GET_CODE (x = XEXP (operands[0], 0)) == PRE_DEC)
890 if (XEXP (x, 0) != stack_pointer_rtx)
894 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
895 return output_move_const_single (operands);
896 else if (GET_CODE (operands[0]) == REG || GET_CODE (operands[1]) == REG)
897 return AS2 (mov%L0,%1,%0);
898 else if (CONSTANT_P (operands[1]))
899 return AS2 (mov%L0,%1,%0);
902 output_asm_insn ("push%L1 %1", operands);
907 /* Output an insn to add the constant N to the register X. */
918 output_asm_insn (AS1 (dec%L0,%0), xops);
920 output_asm_insn (AS1 (inc%L0,%0), xops);
921 else if (n < 0 || n == 128)
923 xops[1] = GEN_INT (-n);
924 output_asm_insn (AS2 (sub%L0,%1,%0), xops);
928 xops[1] = GEN_INT (n);
929 output_asm_insn (AS2 (add%L0,%1,%0), xops);
933 /* Output assembler code to perform a doubleword move insn
934 with operands OPERANDS. */
937 output_move_double (operands)
940 enum {REGOP, OFFSOP, MEMOP, PUSHOP, POPOP, CNSTOP, RNDOP } optype0, optype1;
944 int dest_overlapped_low = 0;
945 int size = GET_MODE_SIZE (GET_MODE (operands[0]));
950 /* First classify both operands. */
952 if (REG_P (operands[0]))
954 else if (offsettable_memref_p (operands[0]))
956 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
958 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
960 else if (GET_CODE (operands[0]) == MEM)
965 if (REG_P (operands[1]))
967 else if (CONSTANT_P (operands[1]))
969 else if (offsettable_memref_p (operands[1]))
971 else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC)
973 else if (GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
975 else if (GET_CODE (operands[1]) == MEM)
980 /* Check for the cases that are not supposed to happen
981 either due to the operand constraints or the fact
982 that all memory operands on the x86 are offsettable.
983 Abort if we get one, because generating code for these
986 if (optype0 == RNDOP || optype1 == RNDOP
987 || optype0 == MEMOP || optype1 == MEMOP)
990 /* If one operand is decrementing and one is incrementing
991 decrement the former register explicitly
992 and change that operand into ordinary indexing. */
994 if (optype0 == PUSHOP && optype1 == POPOP)
996 /* ??? Can this ever happen on i386? */
997 operands[0] = XEXP (XEXP (operands[0], 0), 0);
998 asm_add (-size, operands[0]);
999 if (GET_MODE (operands[1]) == XFmode)
1000 operands[0] = gen_rtx_MEM (XFmode, operands[0]);
1001 else if (GET_MODE (operands[0]) == DFmode)
1002 operands[0] = gen_rtx_MEM (DFmode, operands[0]);
1004 operands[0] = gen_rtx_MEM (DImode, operands[0]);
1008 if (optype0 == POPOP && optype1 == PUSHOP)
1010 /* ??? Can this ever happen on i386? */
1011 operands[1] = XEXP (XEXP (operands[1], 0), 0);
1012 asm_add (-size, operands[1]);
1013 if (GET_MODE (operands[1]) == XFmode)
1014 operands[1] = gen_rtx_MEM (XFmode, operands[1]);
1015 else if (GET_MODE (operands[1]) == DFmode)
1016 operands[1] = gen_rtx_MEM (DFmode, operands[1]);
1018 operands[1] = gen_rtx_MEM (DImode, operands[1]);
1022 /* Ok, we can do one word at a time.
1023 Normally we do the low-numbered word first,
1024 but if either operand is autodecrementing then we
1025 do the high-numbered word first.
1027 In either case, set up in LATEHALF the operands to use
1028 for the high-numbered word and in some cases alter the
1029 operands in OPERANDS to be suitable for the low-numbered word. */
1033 if (optype0 == REGOP)
1035 middlehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1036 latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 2);
1038 else if (optype0 == OFFSOP)
1040 middlehalf[0] = adj_offsettable_operand (operands[0], 4);
1041 latehalf[0] = adj_offsettable_operand (operands[0], 8);
1045 middlehalf[0] = operands[0];
1046 latehalf[0] = operands[0];
1049 if (optype1 == REGOP)
1051 middlehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
1052 latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 2);
1054 else if (optype1 == OFFSOP)
1056 middlehalf[1] = adj_offsettable_operand (operands[1], 4);
1057 latehalf[1] = adj_offsettable_operand (operands[1], 8);
1059 else if (optype1 == CNSTOP)
1061 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1063 REAL_VALUE_TYPE r; long l[3];
1065 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
1066 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, l);
1067 operands[1] = GEN_INT (l[0]);
1068 middlehalf[1] = GEN_INT (l[1]);
1069 latehalf[1] = GEN_INT (l[2]);
1071 else if (CONSTANT_P (operands[1]))
1072 /* No non-CONST_DOUBLE constant should ever appear here. */
1077 middlehalf[1] = operands[1];
1078 latehalf[1] = operands[1];
1084 /* Size is not 12. */
1086 if (optype0 == REGOP)
1087 latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1088 else if (optype0 == OFFSOP)
1089 latehalf[0] = adj_offsettable_operand (operands[0], 4);
1091 latehalf[0] = operands[0];
1093 if (optype1 == REGOP)
1094 latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
1095 else if (optype1 == OFFSOP)
1096 latehalf[1] = adj_offsettable_operand (operands[1], 4);
1097 else if (optype1 == CNSTOP)
1098 split_double (operands[1], &operands[1], &latehalf[1]);
1100 latehalf[1] = operands[1];
1103 /* If insn is effectively movd N (sp),-(sp) then we will do the
1104 high word first. We should use the adjusted operand 1
1105 (which is N+4 (sp) or N+8 (sp))
1106 for the low word and middle word as well,
1107 to compensate for the first decrement of sp. */
1108 if (optype0 == PUSHOP
1109 && REGNO (XEXP (XEXP (operands[0], 0), 0)) == STACK_POINTER_REGNUM
1110 && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1]))
1111 middlehalf[1] = operands[1] = latehalf[1];
1113 /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)),
1114 if the upper part of reg N does not appear in the MEM, arrange to
1115 emit the move late-half first. Otherwise, compute the MEM address
1116 into the upper part of N and use that as a pointer to the memory
1118 if (optype0 == REGOP && optype1 == OFFSOP)
1120 if (reg_mentioned_p (operands[0], XEXP (operands[1], 0))
1121 && reg_mentioned_p (latehalf[0], XEXP (operands[1], 0)))
1123 /* If both halves of dest are used in the src memory address,
1124 compute the address into latehalf of dest. */
1126 xops[0] = latehalf[0];
1127 xops[1] = XEXP (operands[1], 0);
1128 output_asm_insn (AS2 (lea%L0,%a1,%0), xops);
1129 if (GET_MODE (operands[1]) == XFmode)
1131 operands[1] = gen_rtx_MEM (XFmode, latehalf[0]);
1132 middlehalf[1] = adj_offsettable_operand (operands[1], size-8);
1133 latehalf[1] = adj_offsettable_operand (operands[1], size-4);
1137 operands[1] = gen_rtx_MEM (DImode, latehalf[0]);
1138 latehalf[1] = adj_offsettable_operand (operands[1], size-4);
1143 && reg_mentioned_p (middlehalf[0], XEXP (operands[1], 0)))
1145 /* Check for two regs used by both source and dest. */
1146 if (reg_mentioned_p (operands[0], XEXP (operands[1], 0))
1147 || reg_mentioned_p (latehalf[0], XEXP (operands[1], 0)))
1150 /* Only the middle reg conflicts; simply put it last. */
1151 output_asm_insn (singlemove_string (operands), operands);
1152 output_asm_insn (singlemove_string (latehalf), latehalf);
1153 output_asm_insn (singlemove_string (middlehalf), middlehalf);
1157 else if (reg_mentioned_p (operands[0], XEXP (operands[1], 0)))
1158 /* If the low half of dest is mentioned in the source memory
1159 address, the arrange to emit the move late half first. */
1160 dest_overlapped_low = 1;
1163 /* If one or both operands autodecrementing,
1164 do the two words, high-numbered first. */
1166 /* Likewise, the first move would clobber the source of the second one,
1167 do them in the other order. This happens only for registers;
1168 such overlap can't happen in memory unless the user explicitly
1169 sets it up, and that is an undefined circumstance. */
1172 if (optype0 == PUSHOP || optype1 == PUSHOP
1173 || (optype0 == REGOP && optype1 == REGOP
1174 && REGNO (operands[0]) == REGNO (latehalf[1]))
1175 || dest_overlapped_low)
1178 if (optype0 == PUSHOP || optype1 == PUSHOP
1179 || (optype0 == REGOP && optype1 == REGOP
1180 && ((middlehalf[1] && REGNO (operands[0]) == REGNO (middlehalf[1]))
1181 || REGNO (operands[0]) == REGNO (latehalf[1])))
1182 || dest_overlapped_low)
1184 /* Do the high-numbered word. */
1185 output_asm_insn (singlemove_string (latehalf), latehalf);
1188 output_asm_insn (singlemove_string (middlehalf), middlehalf);
1190 /* Do low-numbered word. */
1191 return singlemove_string (operands);
1194 /* Normal case: do the two words, low-numbered first. */
1196 output_asm_insn (singlemove_string (operands), operands);
1198 /* Do the middle one of the three words for long double */
1200 output_asm_insn (singlemove_string (middlehalf), middlehalf);
1202 /* Do the high-numbered word. */
1203 output_asm_insn (singlemove_string (latehalf), latehalf);
1208 #define MAX_TMPS 2 /* max temporary registers used */
1210 /* Output the appropriate code to move push memory on the stack */
1213 output_move_pushmem (operands, insn, length, tmp_start, n_operands)
1225 } tmp_info[MAX_TMPS];
1227 rtx src = operands[1];
1230 int stack_p = reg_overlap_mentioned_p (stack_pointer_rtx, src);
1231 int stack_offset = 0;
1235 if (! offsettable_memref_p (src))
1236 fatal_insn ("Source is not offsettable", insn);
1238 if ((length & 3) != 0)
1239 fatal_insn ("Pushing non-word aligned size", insn);
1241 /* Figure out which temporary registers we have available */
1242 for (i = tmp_start; i < n_operands; i++)
1244 if (GET_CODE (operands[i]) == REG)
1246 if (reg_overlap_mentioned_p (operands[i], src))
1249 tmp_info[ max_tmps++ ].xops[1] = operands[i];
1250 if (max_tmps == MAX_TMPS)
1256 for (offset = length - 4; offset >= 0; offset -= 4)
1258 xops[0] = adj_offsettable_operand (src, offset + stack_offset);
1259 output_asm_insn (AS1(push%L0,%0), xops);
1265 for (offset = length - 4; offset >= 0; )
1267 for (num_tmps = 0; num_tmps < max_tmps && offset >= 0; num_tmps++)
1269 tmp_info[num_tmps].load = AS2(mov%L0,%0,%1);
1270 tmp_info[num_tmps].push = AS1(push%L0,%1);
1271 tmp_info[num_tmps].xops[0]
1272 = adj_offsettable_operand (src, offset + stack_offset);
1276 for (i = 0; i < num_tmps; i++)
1277 output_asm_insn (tmp_info[i].load, tmp_info[i].xops);
1279 for (i = 0; i < num_tmps; i++)
1280 output_asm_insn (tmp_info[i].push, tmp_info[i].xops);
1283 stack_offset += 4*num_tmps;
1290 standard_80387_constant_p (x)
1293 #if ! defined (REAL_IS_NOT_DOUBLE) || defined (REAL_ARITHMETIC)
1298 if (setjmp (handler))
1301 set_float_handler (handler);
1302 REAL_VALUE_FROM_CONST_DOUBLE (d, x);
1303 is0 = REAL_VALUES_EQUAL (d, dconst0) && !REAL_VALUE_MINUS_ZERO (d);
1304 is1 = REAL_VALUES_EQUAL (d, dconst1);
1305 set_float_handler (NULL_PTR);
1313 /* Note that on the 80387, other constants, such as pi,
1314 are much slower to load as standard constants
1315 than to load from doubles in memory! */
1316 /* ??? Not true on K6: all constants are equal cost. */
1323 output_move_const_single (operands)
1326 if (FP_REG_P (operands[0]))
1328 int conval = standard_80387_constant_p (operands[1]);
1337 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1339 REAL_VALUE_TYPE r; long l;
1341 if (GET_MODE (operands[1]) == XFmode)
1344 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
1345 REAL_VALUE_TO_TARGET_SINGLE (r, l);
1346 operands[1] = GEN_INT (l);
1349 return singlemove_string (operands);
1352 /* Returns 1 if OP is either a symbol reference or a sum of a symbol
1353 reference and a constant. */
1356 symbolic_operand (op, mode)
1358 enum machine_mode mode ATTRIBUTE_UNUSED;
1360 switch (GET_CODE (op))
1368 return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
1369 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
1370 && GET_CODE (XEXP (op, 1)) == CONST_INT);
1377 /* Return nonzero if OP is a constant shift count small enough to
1378 encode into an lea instruction. */
1381 small_shift_operand (op, mode)
1383 enum machine_mode mode ATTRIBUTE_UNUSED;
1385 return (GET_CODE (op) == CONST_INT && INTVAL (op) > 0 && INTVAL (op) < 4);
1388 /* Test for a valid operand for a call instruction.
1389 Don't allow the arg pointer register or virtual regs
1390 since they may change into reg + const, which the patterns
1391 can't handle yet. */
1394 call_insn_operand (op, mode)
1396 enum machine_mode mode ATTRIBUTE_UNUSED;
1398 if (GET_CODE (op) == MEM
1399 && ((CONSTANT_ADDRESS_P (XEXP (op, 0))
1400 /* This makes a difference for PIC. */
1401 && general_operand (XEXP (op, 0), Pmode))
1402 || (GET_CODE (XEXP (op, 0)) == REG
1403 && XEXP (op, 0) != arg_pointer_rtx
1404 && ! (REGNO (XEXP (op, 0)) >= FIRST_PSEUDO_REGISTER
1405 && REGNO (XEXP (op, 0)) <= LAST_VIRTUAL_REGISTER))))
1411 /* Like call_insn_operand but allow (mem (symbol_ref ...))
1415 expander_call_insn_operand (op, mode)
1417 enum machine_mode mode ATTRIBUTE_UNUSED;
1419 if (GET_CODE (op) == MEM
1420 && (CONSTANT_ADDRESS_P (XEXP (op, 0))
1421 || (GET_CODE (XEXP (op, 0)) == REG
1422 && XEXP (op, 0) != arg_pointer_rtx
1423 && ! (REGNO (XEXP (op, 0)) >= FIRST_PSEUDO_REGISTER
1424 && REGNO (XEXP (op, 0)) <= LAST_VIRTUAL_REGISTER))))
1430 /* Return 1 if OP is a comparison operator that can use the condition code
1431 generated by an arithmetic operation. */
1434 arithmetic_comparison_operator (op, mode)
1436 enum machine_mode mode;
1440 if (mode != VOIDmode && mode != GET_MODE (op))
1443 code = GET_CODE (op);
1444 if (GET_RTX_CLASS (code) != '<')
1447 return (code != GT && code != LE);
1451 ix86_logical_operator (op, mode)
1453 enum machine_mode mode ATTRIBUTE_UNUSED;
1455 return GET_CODE (op) == AND || GET_CODE (op) == IOR || GET_CODE (op) == XOR;
1459 /* Returns 1 if OP contains a symbol reference */
1462 symbolic_reference_mentioned_p (op)
1468 if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
1471 fmt = GET_RTX_FORMAT (GET_CODE (op));
1472 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
1478 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
1479 if (symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
1483 else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i)))
1490 /* Attempt to expand a binary operator. Make the expansion closer to the
1491 actual machine, then just general_operand, which will allow 3 separate
1492 memory references (one output, two input) in a single insn. Return
1493 whether the insn fails, or succeeds. */
1496 ix86_expand_binary_operator (code, mode, operands)
1498 enum machine_mode mode;
1503 /* Recognize <var1> = <value> <op> <var1> for commutative operators */
1504 if (GET_RTX_CLASS (code) == 'c'
1505 && (rtx_equal_p (operands[0], operands[2])
1506 || immediate_operand (operands[1], mode)))
1508 rtx temp = operands[1];
1509 operands[1] = operands[2];
1513 /* If optimizing, copy to regs to improve CSE */
1514 if (TARGET_PSEUDO && optimize
1515 && ((reload_in_progress | reload_completed) == 0))
1517 if (GET_CODE (operands[1]) == MEM
1518 && ! rtx_equal_p (operands[0], operands[1]))
1519 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]);
1521 if (GET_CODE (operands[2]) == MEM)
1522 operands[2] = force_reg (GET_MODE (operands[2]), operands[2]);
1524 if (GET_CODE (operands[1]) == CONST_INT && code == MINUS)
1526 rtx temp = gen_reg_rtx (GET_MODE (operands[0]));
1528 emit_move_insn (temp, operands[1]);
1534 if (!ix86_binary_operator_ok (code, mode, operands))
1536 /* If not optimizing, try to make a valid insn (optimize code
1537 previously did this above to improve chances of CSE) */
1539 if ((! TARGET_PSEUDO || !optimize)
1540 && ((reload_in_progress | reload_completed) == 0)
1541 && (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM))
1544 if (GET_CODE (operands[1]) == MEM
1545 && ! rtx_equal_p (operands[0], operands[1]))
1547 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]);
1551 if (GET_CODE (operands[2]) == MEM)
1553 operands[2] = force_reg (GET_MODE (operands[2]), operands[2]);
1557 if (GET_CODE (operands[1]) == CONST_INT && code == MINUS)
1559 rtx temp = gen_reg_rtx (GET_MODE (operands[0]));
1561 emit_move_insn (temp, operands[1]);
1566 if (modified && ! ix86_binary_operator_ok (code, mode, operands))
1576 /* Return TRUE or FALSE depending on whether the binary operator meets the
1577 appropriate constraints. */
1580 ix86_binary_operator_ok (code, mode, operands)
1582 enum machine_mode mode ATTRIBUTE_UNUSED;
1585 return (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
1586 && (GET_CODE (operands[1]) != CONST_INT || GET_RTX_CLASS (code) == 'c');
1589 /* Attempt to expand a unary operator. Make the expansion closer to the
1590 actual machine, then just general_operand, which will allow 2 separate
1591 memory references (one output, one input) in a single insn. Return
1592 whether the insn fails, or succeeds. */
1595 ix86_expand_unary_operator (code, mode, operands)
1597 enum machine_mode mode;
1600 /* If optimizing, copy to regs to improve CSE */
1603 && ((reload_in_progress | reload_completed) == 0)
1604 && GET_CODE (operands[1]) == MEM)
1605 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]);
1607 if (! ix86_unary_operator_ok (code, mode, operands))
1609 if ((! TARGET_PSEUDO || optimize == 0)
1610 && ((reload_in_progress | reload_completed) == 0)
1611 && GET_CODE (operands[1]) == MEM)
1613 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]);
1614 if (! ix86_unary_operator_ok (code, mode, operands))
1624 /* Return TRUE or FALSE depending on whether the unary operator meets the
1625 appropriate constraints. */
1628 ix86_unary_operator_ok (code, mode, operands)
1629 enum rtx_code code ATTRIBUTE_UNUSED;
1630 enum machine_mode mode ATTRIBUTE_UNUSED;
1631 rtx operands[2] ATTRIBUTE_UNUSED;
1636 static rtx pic_label_rtx;
1637 static char pic_label_name [256];
1638 static int pic_label_no = 0;
1640 /* This function generates code for -fpic that loads %ebx with
1641 the return address of the caller and then returns. */
1644 asm_output_function_prefix (file, name)
1646 char *name ATTRIBUTE_UNUSED;
1649 xops[0] = pic_offset_table_rtx;
1650 xops[1] = stack_pointer_rtx;
1652 /* Deep branch prediction favors having a return for every call. */
1653 if (PIC_REG_USED && TARGET_DEEP_BRANCH_PREDICTION)
1657 if (pic_label_rtx == 0)
1659 pic_label_rtx = gen_label_rtx ();
1660 ASM_GENERATE_INTERNAL_LABEL (pic_label_name, "LPR", pic_label_no++);
1661 LABEL_NAME (pic_label_rtx) = pic_label_name;
1664 prologue_node = make_node (FUNCTION_DECL);
1665 DECL_RESULT (prologue_node) = 0;
1667 /* This used to call ASM_DECLARE_FUNCTION_NAME() but since it's an
1668 internal (non-global) label that's being emitted, it didn't make
1669 sense to have .type information for local labels. This caused
1670 the SCO OpenServer 5.0.4 ELF assembler grief (why are you giving
1671 me debug info for a label that you're declaring non-global?) this
1672 was changed to call ASM_OUTPUT_LABEL() instead. */
1675 ASM_OUTPUT_LABEL (file, pic_label_name);
1676 output_asm_insn ("movl (%1),%0", xops);
1677 output_asm_insn ("ret", xops);
1681 /* Generate the assembly code for function entry.
1682 FILE is an stdio stream to output the code to.
1683 SIZE is an int: how many units of temporary storage to allocate. */
1686 function_prologue (file, size)
1687 FILE *file ATTRIBUTE_UNUSED;
1688 int size ATTRIBUTE_UNUSED;
1690 if (TARGET_SCHEDULE_PROLOGUE)
1699 /* Expand the prologue into a bunch of separate insns. */
1702 ix86_expand_prologue ()
1704 if (! TARGET_SCHEDULE_PROLOGUE)
1711 load_pic_register (do_rtl)
1716 if (TARGET_DEEP_BRANCH_PREDICTION)
1718 xops[0] = pic_offset_table_rtx;
1719 if (pic_label_rtx == 0)
1721 pic_label_rtx = gen_label_rtx ();
1722 ASM_GENERATE_INTERNAL_LABEL (pic_label_name, "LPR", pic_label_no++);
1723 LABEL_NAME (pic_label_rtx) = pic_label_name;
1726 xops[1] = gen_rtx_MEM (QImode,
1727 gen_rtx (SYMBOL_REF, Pmode,
1728 LABEL_NAME (pic_label_rtx)));
1732 emit_insn (gen_prologue_get_pc (xops[0], xops[1]));
1733 emit_insn (gen_prologue_set_got (xops[0],
1734 #ifdef YES_UNDERSCORES
1735 gen_rtx_SYMBOL_REF (Pmode,
1736 "$__GLOBAL_OFFSET_TABLE_"),
1738 gen_rtx_SYMBOL_REF (Pmode,
1739 "$_GLOBAL_OFFSET_TABLE_"),
1745 output_asm_insn (AS1 (call,%X1), xops);
1746 output_asm_insn ("addl $%__GLOBAL_OFFSET_TABLE_,%0", xops);
1753 xops[0] = pic_offset_table_rtx;
1754 xops[1] = gen_label_rtx ();
1758 /* We can't put a raw CODE_LABEL into the RTL, and we can't emit
1759 a new CODE_LABEL after reload, so we need a single pattern to
1760 emit the 3 necessary instructions. */
1761 emit_insn (gen_prologue_get_pc_and_set_got (xops[0]));
1765 output_asm_insn (AS1 (call,%P1), xops);
1766 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
1767 CODE_LABEL_NUMBER (xops[1]));
1768 output_asm_insn (AS1 (pop%L0,%0), xops);
1769 output_asm_insn ("addl $%__GLOBAL_OFFSET_TABLE_+[.-%P1],%0", xops);
1773 /* When -fpic, we must emit a scheduling barrier, so that the instruction
1774 that restores %ebx (which is PIC_OFFSET_TABLE_REGNUM), does not get
1775 moved before any instruction which implicitly uses the got. */
1778 emit_insn (gen_blockage ());
1781 /* Compute the size of local storage taking into consideration the
1782 desired stack alignment which is to be maintained. Also determine
1783 the number of registers saved below the local storage. */
1786 ix86_compute_frame_size (size, nregs_on_stack)
1788 int *nregs_on_stack;
1794 int pic_reg_used = PIC_REG_USED;
1795 HOST_WIDE_INT total_size;
1797 limit = frame_pointer_needed
1798 ? FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM;
1802 for (regno = limit - 1; regno >= 0; regno--)
1803 if ((regs_ever_live[regno] && ! call_used_regs[regno])
1804 || (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used))
1808 total_size = size + (nregs * UNITS_PER_WORD);
1810 #ifdef PREFERRED_STACK_BOUNDARY
1813 int preferred_alignment = PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT;
1816 if (frame_pointer_needed)
1817 offset += UNITS_PER_WORD;
1819 total_size += offset;
1821 padding = ((total_size + preferred_alignment - 1)
1822 & -preferred_alignment) - total_size;
1824 if (padding < (((offset + preferred_alignment - 1)
1825 & -preferred_alignment) - offset))
1826 padding += preferred_alignment;
1828 /* Don't bother aligning the stack of a leaf function
1829 which doesn't allocate any stack slots. */
1830 if (size == 0 && current_function_is_leaf)
1836 *nregs_on_stack = nregs;
1838 return size + padding;
1842 ix86_prologue (do_rtl)
1848 int pic_reg_used = PIC_REG_USED;
1849 HOST_WIDE_INT tsize = ix86_compute_frame_size (get_frame_size (), (int *)0);
1851 int cfa_offset = INCOMING_FRAME_SP_OFFSET, cfa_store_offset = cfa_offset;
1853 xops[0] = stack_pointer_rtx;
1854 xops[1] = frame_pointer_rtx;
1855 xops[2] = GEN_INT (tsize);
1857 if (frame_pointer_needed)
1861 insn = emit_insn (gen_rtx (SET, VOIDmode,
1862 gen_rtx_MEM (SImode,
1863 gen_rtx (PRE_DEC, SImode,
1864 stack_pointer_rtx)),
1865 frame_pointer_rtx));
1867 RTX_FRAME_RELATED_P (insn) = 1;
1868 insn = emit_move_insn (xops[1], xops[0]);
1869 RTX_FRAME_RELATED_P (insn) = 1;
1874 output_asm_insn ("push%L1 %1", xops);
1875 #ifdef INCOMING_RETURN_ADDR_RTX
1876 if (dwarf2out_do_frame ())
1878 char *l = dwarf2out_cfi_label ();
1880 cfa_store_offset += 4;
1881 cfa_offset = cfa_store_offset;
1882 dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, cfa_offset);
1883 dwarf2out_reg_save (l, FRAME_POINTER_REGNUM, - cfa_store_offset);
1887 output_asm_insn (AS2 (mov%L0,%0,%1), xops);
1888 #ifdef INCOMING_RETURN_ADDR_RTX
1889 if (dwarf2out_do_frame ())
1890 dwarf2out_def_cfa ("", FRAME_POINTER_REGNUM, cfa_offset);
1897 else if (! TARGET_STACK_PROBE || tsize < CHECK_STACK_LIMIT)
1901 insn = emit_insn (gen_prologue_set_stack_ptr (xops[2]));
1902 RTX_FRAME_RELATED_P (insn) = 1;
1906 output_asm_insn (AS2 (sub%L0,%2,%0), xops);
1907 #ifdef INCOMING_RETURN_ADDR_RTX
1908 if (dwarf2out_do_frame ())
1910 cfa_store_offset += tsize;
1911 if (! frame_pointer_needed)
1913 cfa_offset = cfa_store_offset;
1914 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM, cfa_offset);
1922 xops[3] = gen_rtx_REG (SImode, 0);
1924 emit_move_insn (xops[3], xops[2]);
1926 output_asm_insn (AS2 (mov%L0,%2,%3), xops);
1928 xops[3] = gen_rtx_MEM (FUNCTION_MODE,
1929 gen_rtx (SYMBOL_REF, Pmode, "_alloca"));
1932 emit_call_insn (gen_rtx (CALL, VOIDmode, xops[3], const0_rtx));
1934 output_asm_insn (AS1 (call,%P3), xops);
1937 /* Note If use enter it is NOT reversed args.
1938 This one is not reversed from intel!!
1939 I think enter is slower. Also sdb doesn't like it.
1940 But if you want it the code is:
1942 xops[3] = const0_rtx;
1943 output_asm_insn ("enter %2,%3", xops);
1947 limit = (frame_pointer_needed ? FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM);
1948 for (regno = limit - 1; regno >= 0; regno--)
1949 if ((regs_ever_live[regno] && ! call_used_regs[regno])
1950 || (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used))
1952 xops[0] = gen_rtx_REG (SImode, regno);
1955 insn = emit_insn (gen_rtx (SET, VOIDmode,
1956 gen_rtx_MEM (SImode,
1957 gen_rtx (PRE_DEC, SImode,
1958 stack_pointer_rtx)),
1961 RTX_FRAME_RELATED_P (insn) = 1;
1965 output_asm_insn ("push%L0 %0", xops);
1966 #ifdef INCOMING_RETURN_ADDR_RTX
1967 if (dwarf2out_do_frame ())
1969 char *l = dwarf2out_cfi_label ();
1971 cfa_store_offset += 4;
1972 if (! frame_pointer_needed)
1974 cfa_offset = cfa_store_offset;
1975 dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, cfa_offset);
1978 dwarf2out_reg_save (l, regno, - cfa_store_offset);
1984 #ifdef SUBTARGET_PROLOGUE
1989 load_pic_register (do_rtl);
1991 /* If we are profiling, make sure no instructions are scheduled before
1992 the call to mcount. However, if -fpic, the above call will have
1994 if ((profile_flag || profile_block_flag)
1995 && ! pic_reg_used && do_rtl)
1996 emit_insn (gen_blockage ());
1999 /* Return 1 if it is appropriate to emit `ret' instructions in the
2000 body of a function. Do this only if the epilogue is simple, needing a
2001 couple of insns. Prior to reloading, we can't tell how many registers
2002 must be saved, so return 0 then. Return 0 if there is no frame
2003 marker to de-allocate.
2005 If NON_SAVING_SETJMP is defined and true, then it is not possible
2006 for the epilogue to be simple, so return 0. This is a special case
2007 since NON_SAVING_SETJMP will not cause regs_ever_live to change
2008 until final, but jump_optimize may need to know sooner if a
2012 ix86_can_use_return_insn_p ()
2016 int reglimit = (frame_pointer_needed
2017 ? FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM);
2019 #ifdef TARGET_PROFILER_EPILOGUE
2020 if (TARGET_PROFILER_EPILOGUE)
2024 #ifdef NON_SAVING_SETJMP
2025 if (NON_SAVING_SETJMP && current_function_calls_setjmp)
2029 if (! reload_completed)
2032 for (regno = reglimit - 1; regno >= 0; regno--)
2033 if ((regs_ever_live[regno] && ! call_used_regs[regno])
2034 || (regno == PIC_OFFSET_TABLE_REGNUM && PIC_REG_USED))
2037 return nregs == 0 || ! frame_pointer_needed;
2040 /* This function generates the assembly code for function exit.
2041 FILE is an stdio stream to output the code to.
2042 SIZE is an int: how many units of temporary storage to deallocate. */
2045 function_epilogue (file, size)
2046 FILE *file ATTRIBUTE_UNUSED;
2047 int size ATTRIBUTE_UNUSED;
2052 /* Restore function stack, frame, and registers. */
2055 ix86_expand_epilogue ()
2061 ix86_epilogue (do_rtl)
2068 int pic_reg_used = PIC_REG_USED;
2069 int sp_valid = !frame_pointer_needed || current_function_sp_is_unchanging;
2070 HOST_WIDE_INT offset;
2071 HOST_WIDE_INT tsize = ix86_compute_frame_size (get_frame_size (), &nregs);
2073 /* sp is often unreliable so we may have to go off the frame pointer. */
2075 offset = -(tsize + nregs * UNITS_PER_WORD);
2077 xops[2] = stack_pointer_rtx;
2079 /* When -fpic, we must emit a scheduling barrier, so that the instruction
2080 that restores %ebx (which is PIC_OFFSET_TABLE_REGNUM), does not get
2081 moved before any instruction which implicitly uses the got. This
2082 includes any instruction which uses a SYMBOL_REF or a LABEL_REF.
2084 Alternatively, this could be fixed by making the dependence on the
2085 PIC_OFFSET_TABLE_REGNUM explicit in the RTL. */
2087 if (flag_pic || profile_flag || profile_block_flag)
2088 emit_insn (gen_blockage ());
2090 #ifdef FUNCTION_PROFILER_EPILOGUE
2091 FUNCTION_PROFILER_EPILOGUE (asm_out_file, do_rtl);
2094 /* If we're only restoring one register and sp is not valid then
2095 using a move instruction to restore the register since it's
2096 less work than reloading sp and popping the register. Otherwise,
2097 restore sp (if necessary) and pop the registers. */
2099 limit = frame_pointer_needed
2100 ? FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM;
2102 if (nregs > 1 || sp_valid)
2106 xops[0] = adj_offsettable_operand (AT_BP (QImode), offset);
2108 emit_insn (gen_movsi_lea (xops[2], XEXP (xops[0], 0)));
2110 output_asm_insn (AS2 (lea%L2,%0,%2), xops);
2113 for (regno = 0; regno < limit; regno++)
2114 if ((regs_ever_live[regno] && ! call_used_regs[regno])
2115 || (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used))
2117 xops[0] = gen_rtx_REG (SImode, regno);
2120 emit_insn (gen_pop (xops[0]));
2122 output_asm_insn ("pop%L0 %0", xops);
2127 for (regno = 0; regno < limit; regno++)
2128 if ((regs_ever_live[regno] && ! call_used_regs[regno])
2129 || (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used))
2131 xops[0] = gen_rtx_REG (SImode, regno);
2132 xops[1] = adj_offsettable_operand (AT_BP (Pmode), offset);
2135 emit_move_insn (xops[0], xops[1]);
2137 output_asm_insn (AS2 (mov%L0,%1,%0), xops);
2142 if (frame_pointer_needed)
2144 /* If not an i386, mov & pop is faster than "leave". */
2146 if (TARGET_USE_LEAVE)
2149 emit_insn (gen_leave());
2151 output_asm_insn ("leave", xops);
2155 xops[0] = frame_pointer_rtx;
2156 xops[1] = stack_pointer_rtx;
2160 emit_insn (gen_epilogue_set_stack_ptr());
2161 emit_insn (gen_pop (xops[0]));
2165 output_asm_insn (AS2 (mov%L2,%0,%2), xops);
2166 output_asm_insn ("pop%L0 %0", xops);
2173 /* Intel's docs say that for 4 or 8 bytes of stack frame one should
2174 use `pop' and not `add'. */
2175 int use_pop = tsize == 4;
2177 /* Use two pops only for the Pentium processors. */
2178 if (tsize == 8 && !TARGET_386 && !TARGET_486)
2180 rtx retval = current_function_return_rtx;
2182 xops[1] = gen_rtx_REG (SImode, 1); /* %edx */
2184 /* This case is a bit more complex. Since we cannot pop into
2185 %ecx twice we need a second register. But this is only
2186 available if the return value is not of DImode in which
2187 case the %edx register is not available. */
2188 use_pop = (retval == NULL
2189 || ! reg_overlap_mentioned_p (xops[1], retval));
2194 xops[0] = gen_rtx_REG (SImode, 2); /* %ecx */
2198 /* We have to prevent the two pops here from being scheduled.
2199 GCC otherwise would try in some situation to put other
2200 instructions in between them which has a bad effect. */
2201 emit_insn (gen_blockage ());
2202 emit_insn (gen_pop (xops[0]));
2204 emit_insn (gen_pop (xops[1]));
2208 output_asm_insn ("pop%L0 %0", xops);
2210 output_asm_insn ("pop%L1 %1", xops);
2215 /* If there is no frame pointer, we must still release the frame. */
2216 xops[0] = GEN_INT (tsize);
2219 emit_insn (gen_rtx (SET, VOIDmode, xops[2],
2220 gen_rtx (PLUS, SImode, xops[2], xops[0])));
2222 output_asm_insn (AS2 (add%L2,%0,%2), xops);
2226 #ifdef FUNCTION_BLOCK_PROFILER_EXIT
2227 if (profile_block_flag == 2)
2229 /* XXX this is hosed like FUNCTION_PROFILER_EPILOGUE () was. */
2230 FUNCTION_BLOCK_PROFILER_EXIT(file);
2234 if (current_function_pops_args && current_function_args_size)
2236 xops[1] = GEN_INT (current_function_pops_args);
2238 /* i386 can only pop 32K bytes (maybe 64K? Is it signed?). If
2239 asked to pop more, pop return address, do explicit add, and jump
2240 indirectly to the caller. */
2242 if (current_function_pops_args >= 32768)
2244 /* ??? Which register to use here? */
2245 xops[0] = gen_rtx_REG (SImode, 2);
2249 emit_insn (gen_pop (xops[0]));
2250 emit_insn (gen_rtx (SET, VOIDmode, xops[2],
2251 gen_rtx (PLUS, SImode, xops[1], xops[2])));
2252 emit_jump_insn (xops[0]);
2256 output_asm_insn ("pop%L0 %0", xops);
2257 output_asm_insn (AS2 (add%L2,%1,%2), xops);
2258 output_asm_insn ("jmp %*%0", xops);
2264 emit_jump_insn (gen_return_pop_internal (xops[1]));
2266 output_asm_insn ("ret %1", xops);
2272 emit_jump_insn (gen_return_internal ());
2274 output_asm_insn ("ret", xops);
2278 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
2279 that is a valid memory address for an instruction.
2280 The MODE argument is the machine mode for the MEM expression
2281 that wants to use this address.
2283 On x86, legitimate addresses are:
2284 base movl (base),reg
2285 displacement movl disp,reg
2286 base + displacement movl disp(base),reg
2287 index + base movl (base,index),reg
2288 (index + base) + displacement movl disp(base,index),reg
2289 index*scale movl (,index,scale),reg
2290 index*scale + disp movl disp(,index,scale),reg
2291 index*scale + base movl (base,index,scale),reg
2292 (index*scale + base) + disp movl disp(base,index,scale),reg
2294 In each case, scale can be 1, 2, 4, 8. */
2296 /* This is exactly the same as print_operand_addr, except that
2297 it recognizes addresses instead of printing them.
2299 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
2300 convert common non-canonical forms to canonical form so that they will
2303 #define ADDR_INVALID(msg,insn) \
2305 if (TARGET_DEBUG_ADDR) \
2307 fprintf (stderr, msg); \
2313 legitimate_pic_address_disp_p (disp)
2316 if (GET_CODE (disp) != CONST)
2318 disp = XEXP (disp, 0);
2320 if (GET_CODE (disp) == PLUS)
2322 if (GET_CODE (XEXP (disp, 1)) != CONST_INT)
2324 disp = XEXP (disp, 0);
2327 if (GET_CODE (disp) != UNSPEC
2328 || XVECLEN (disp, 0) != 1)
2331 /* Must be @GOT or @GOTOFF. */
2332 if (XINT (disp, 1) != 6
2333 && XINT (disp, 1) != 7)
2336 if (GET_CODE (XVECEXP (disp, 0, 0)) != SYMBOL_REF
2337 && GET_CODE (XVECEXP (disp, 0, 0)) != LABEL_REF)
2344 legitimate_address_p (mode, addr, strict)
2345 enum machine_mode mode;
2349 rtx base = NULL_RTX;
2350 rtx indx = NULL_RTX;
2351 rtx scale = NULL_RTX;
2352 rtx disp = NULL_RTX;
2354 if (TARGET_DEBUG_ADDR)
2357 "\n======\nGO_IF_LEGITIMATE_ADDRESS, mode = %s, strict = %d\n",
2358 GET_MODE_NAME (mode), strict);
2363 if (GET_CODE (addr) == REG || GET_CODE (addr) == SUBREG)
2366 else if (GET_CODE (addr) == PLUS)
2368 rtx op0 = XEXP (addr, 0);
2369 rtx op1 = XEXP (addr, 1);
2370 enum rtx_code code0 = GET_CODE (op0);
2371 enum rtx_code code1 = GET_CODE (op1);
2373 if (code0 == REG || code0 == SUBREG)
2375 if (code1 == REG || code1 == SUBREG)
2377 indx = op0; /* index + base */
2383 base = op0; /* base + displacement */
2388 else if (code0 == MULT)
2390 indx = XEXP (op0, 0);
2391 scale = XEXP (op0, 1);
2393 if (code1 == REG || code1 == SUBREG)
2394 base = op1; /* index*scale + base */
2397 disp = op1; /* index*scale + disp */
2400 else if (code0 == PLUS && GET_CODE (XEXP (op0, 0)) == MULT)
2402 indx = XEXP (XEXP (op0, 0), 0); /* index*scale + base + disp */
2403 scale = XEXP (XEXP (op0, 0), 1);
2404 base = XEXP (op0, 1);
2408 else if (code0 == PLUS)
2410 indx = XEXP (op0, 0); /* index + base + disp */
2411 base = XEXP (op0, 1);
2417 ADDR_INVALID ("PLUS subcode is not valid.\n", op0);
2422 else if (GET_CODE (addr) == MULT)
2424 indx = XEXP (addr, 0); /* index*scale */
2425 scale = XEXP (addr, 1);
2429 disp = addr; /* displacement */
2431 /* Allow arg pointer and stack pointer as index if there is not scaling */
2432 if (base && indx && !scale
2433 && (indx == arg_pointer_rtx || indx == stack_pointer_rtx))
2440 /* Validate base register:
2442 Don't allow SUBREG's here, it can lead to spill failures when the base
2443 is one word out of a two word structure, which is represented internally
2448 if (GET_CODE (base) != REG)
2450 ADDR_INVALID ("Base is not a register.\n", base);
2454 if (GET_MODE (base) != Pmode)
2456 ADDR_INVALID ("Base is not in Pmode.\n", base);
2460 if ((strict && ! REG_OK_FOR_BASE_STRICT_P (base))
2461 || (! strict && ! REG_OK_FOR_BASE_NONSTRICT_P (base)))
2463 ADDR_INVALID ("Base is not valid.\n", base);
2468 /* Validate index register:
2470 Don't allow SUBREG's here, it can lead to spill failures when the index
2471 is one word out of a two word structure, which is represented internally
2475 if (GET_CODE (indx) != REG)
2477 ADDR_INVALID ("Index is not a register.\n", indx);
2481 if (GET_MODE (indx) != Pmode)
2483 ADDR_INVALID ("Index is not in Pmode.\n", indx);
2487 if ((strict && ! REG_OK_FOR_INDEX_STRICT_P (indx))
2488 || (! strict && ! REG_OK_FOR_INDEX_NONSTRICT_P (indx)))
2490 ADDR_INVALID ("Index is not valid.\n", indx);
2495 abort (); /* scale w/o index invalid */
2497 /* Validate scale factor: */
2500 HOST_WIDE_INT value;
2502 if (GET_CODE (scale) != CONST_INT)
2504 ADDR_INVALID ("Scale is not valid.\n", scale);
2508 value = INTVAL (scale);
2509 if (value != 1 && value != 2 && value != 4 && value != 8)
2511 ADDR_INVALID ("Scale is not a good multiplier.\n", scale);
2516 /* Validate displacement. */
2519 if (!CONSTANT_ADDRESS_P (disp))
2521 ADDR_INVALID ("Displacement is not valid.\n", disp);
2525 else if (GET_CODE (disp) == CONST_DOUBLE)
2527 ADDR_INVALID ("Displacement is a const_double.\n", disp);
2531 if (flag_pic && SYMBOLIC_CONST (disp))
2533 if (! legitimate_pic_address_disp_p (disp))
2535 ADDR_INVALID ("Displacement is an invalid PIC construct.\n",
2540 if (base != pic_offset_table_rtx
2541 && (indx != pic_offset_table_rtx || scale != NULL_RTX))
2543 ADDR_INVALID ("PIC displacement against invalid base.\n", disp);
2548 else if (HALF_PIC_P ())
2550 if (! HALF_PIC_ADDRESS_P (disp)
2551 || (base != NULL_RTX || indx != NULL_RTX))
2553 ADDR_INVALID ("Displacement is an invalid half-pic reference.\n",
2560 if (TARGET_DEBUG_ADDR)
2561 fprintf (stderr, "Address is valid.\n");
2563 /* Everything looks valid, return true */
2567 /* Return a legitimate reference for ORIG (an address) using the
2568 register REG. If REG is 0, a new pseudo is generated.
2570 There are two types of references that must be handled:
2572 1. Global data references must load the address from the GOT, via
2573 the PIC reg. An insn is emitted to do this load, and the reg is
2576 2. Static data references, constant pool addresses, and code labels
2577 compute the address as an offset from the GOT, whose base is in
2578 the PIC reg. Static data objects have SYMBOL_REF_FLAG set to
2579 differentiate them from global data objects. The returned
2580 address is the PIC reg + an unspec constant.
2582 GO_IF_LEGITIMATE_ADDRESS rejects symbolic references unless the PIC
2583 reg also appears in the address. */
2586 legitimize_pic_address (orig, reg)
2594 if (GET_CODE (addr) == LABEL_REF
2595 || (GET_CODE (addr) == SYMBOL_REF
2596 && (CONSTANT_POOL_ADDRESS_P (addr)
2597 || SYMBOL_REF_FLAG (addr))))
2599 /* This symbol may be referenced via a displacement from the PIC
2600 base address (@GOTOFF). */
2602 current_function_uses_pic_offset_table = 1;
2603 new = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, addr), 7);
2604 new = gen_rtx_CONST (VOIDmode, new);
2605 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new);
2609 emit_move_insn (reg, new);
2613 else if (GET_CODE (addr) == SYMBOL_REF)
2615 /* This symbol must be referenced via a load from the
2616 Global Offset Table (@GOT). */
2618 current_function_uses_pic_offset_table = 1;
2619 new = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, addr), 6);
2620 new = gen_rtx_CONST (VOIDmode, new);
2621 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new);
2622 new = gen_rtx_MEM (Pmode, new);
2623 RTX_UNCHANGING_P (new) = 1;
2626 reg = gen_reg_rtx (Pmode);
2627 emit_move_insn (reg, new);
2632 if (GET_CODE (addr) == CONST)
2634 addr = XEXP (addr, 0);
2635 if (GET_CODE (addr) == UNSPEC)
2637 /* Check that the unspec is one of the ones we generate? */
2639 else if (GET_CODE (addr) != PLUS)
2642 if (GET_CODE (addr) == PLUS)
2644 rtx op0 = XEXP (addr, 0), op1 = XEXP (addr, 1);
2646 /* Check first to see if this is a constant offset from a @GOTOFF
2647 symbol reference. */
2648 if ((GET_CODE (op0) == LABEL_REF
2649 || (GET_CODE (op0) == SYMBOL_REF
2650 && (CONSTANT_POOL_ADDRESS_P (op0)
2651 || SYMBOL_REF_FLAG (op0))))
2652 && GET_CODE (op1) == CONST_INT)
2654 current_function_uses_pic_offset_table = 1;
2655 new = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, op0), 7);
2656 new = gen_rtx_PLUS (VOIDmode, new, op1);
2657 new = gen_rtx_CONST (VOIDmode, new);
2658 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new);
2662 emit_move_insn (reg, new);
2668 base = legitimize_pic_address (XEXP (addr, 0), reg);
2669 new = legitimize_pic_address (XEXP (addr, 1),
2670 base == reg ? NULL_RTX : reg);
2672 if (GET_CODE (new) == CONST_INT)
2673 new = plus_constant (base, INTVAL (new));
2676 if (GET_CODE (new) == PLUS && CONSTANT_P (XEXP (new, 1)))
2678 base = gen_rtx_PLUS (Pmode, base, XEXP (new, 0));
2679 new = XEXP (new, 1);
2681 new = gen_rtx_PLUS (Pmode, base, new);
2689 /* Emit insns to move operands[1] into operands[0]. */
2692 emit_pic_move (operands, mode)
2694 enum machine_mode mode ATTRIBUTE_UNUSED;
2696 rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode);
2698 if (GET_CODE (operands[0]) == MEM && SYMBOLIC_CONST (operands[1]))
2699 operands[1] = force_reg (Pmode, operands[1]);
2701 operands[1] = legitimize_pic_address (operands[1], temp);
2704 /* Try machine-dependent ways of modifying an illegitimate address
2705 to be legitimate. If we find one, return the new, valid address.
2706 This macro is used in only one place: `memory_address' in explow.c.
2708 OLDX is the address as it was before break_out_memory_refs was called.
2709 In some cases it is useful to look at this to decide what needs to be done.
2711 MODE and WIN are passed so that this macro can use
2712 GO_IF_LEGITIMATE_ADDRESS.
2714 It is always safe for this macro to do nothing. It exists to recognize
2715 opportunities to optimize the output.
2717 For the 80386, we handle X+REG by loading X into a register R and
2718 using R+REG. R will go in a general reg and indexing will be used.
2719 However, if REG is a broken-out memory address or multiplication,
2720 nothing needs to be done because REG can certainly go in a general reg.
2722 When -fpic is used, special handling is needed for symbolic references.
2723 See comments by legitimize_pic_address in i386.c for details. */
2726 legitimize_address (x, oldx, mode)
2728 register rtx oldx ATTRIBUTE_UNUSED;
2729 enum machine_mode mode;
2734 if (TARGET_DEBUG_ADDR)
2736 fprintf (stderr, "\n==========\nLEGITIMIZE_ADDRESS, mode = %s\n",
2737 GET_MODE_NAME (mode));
2741 if (flag_pic && SYMBOLIC_CONST (x))
2742 return legitimize_pic_address (x, 0);
2744 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
2745 if (GET_CODE (x) == ASHIFT
2746 && GET_CODE (XEXP (x, 1)) == CONST_INT
2747 && (log = (unsigned)exact_log2 (INTVAL (XEXP (x, 1)))) < 4)
2750 x = gen_rtx_MULT (Pmode, force_reg (Pmode, XEXP (x, 0)),
2751 GEN_INT (1 << log));
2754 if (GET_CODE (x) == PLUS)
2756 /* Canonicalize shifts by 0, 1, 2, 3 into multiply. */
2758 if (GET_CODE (XEXP (x, 0)) == ASHIFT
2759 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2760 && (log = (unsigned)exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) < 4)
2763 XEXP (x, 0) = gen_rtx (MULT, Pmode,
2764 force_reg (Pmode, XEXP (XEXP (x, 0), 0)),
2765 GEN_INT (1 << log));
2768 if (GET_CODE (XEXP (x, 1)) == ASHIFT
2769 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
2770 && (log = (unsigned)exact_log2 (INTVAL (XEXP (XEXP (x, 1), 1)))) < 4)
2773 XEXP (x, 1) = gen_rtx (MULT, Pmode,
2774 force_reg (Pmode, XEXP (XEXP (x, 1), 0)),
2775 GEN_INT (1 << log));
2778 /* Put multiply first if it isn't already. */
2779 if (GET_CODE (XEXP (x, 1)) == MULT)
2781 rtx tmp = XEXP (x, 0);
2782 XEXP (x, 0) = XEXP (x, 1);
2787 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
2788 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
2789 created by virtual register instantiation, register elimination, and
2790 similar optimizations. */
2791 if (GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == PLUS)
2794 x = gen_rtx (PLUS, Pmode,
2795 gen_rtx (PLUS, Pmode, XEXP (x, 0),
2796 XEXP (XEXP (x, 1), 0)),
2797 XEXP (XEXP (x, 1), 1));
2801 (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
2802 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
2803 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS
2804 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
2805 && GET_CODE (XEXP (XEXP (x, 0), 1)) == PLUS
2806 && CONSTANT_P (XEXP (x, 1)))
2809 rtx other = NULL_RTX;
2811 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
2813 constant = XEXP (x, 1);
2814 other = XEXP (XEXP (XEXP (x, 0), 1), 1);
2816 else if (GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 1)) == CONST_INT)
2818 constant = XEXP (XEXP (XEXP (x, 0), 1), 1);
2819 other = XEXP (x, 1);
2827 x = gen_rtx (PLUS, Pmode,
2828 gen_rtx (PLUS, Pmode, XEXP (XEXP (x, 0), 0),
2829 XEXP (XEXP (XEXP (x, 0), 1), 0)),
2830 plus_constant (other, INTVAL (constant)));
2834 if (changed && legitimate_address_p (mode, x, FALSE))
2837 if (GET_CODE (XEXP (x, 0)) == MULT)
2840 XEXP (x, 0) = force_operand (XEXP (x, 0), 0);
2843 if (GET_CODE (XEXP (x, 1)) == MULT)
2846 XEXP (x, 1) = force_operand (XEXP (x, 1), 0);
2850 && GET_CODE (XEXP (x, 1)) == REG
2851 && GET_CODE (XEXP (x, 0)) == REG)
2854 if (flag_pic && SYMBOLIC_CONST (XEXP (x, 1)))
2857 x = legitimize_pic_address (x, 0);
2860 if (changed && legitimate_address_p (mode, x, FALSE))
2863 if (GET_CODE (XEXP (x, 0)) == REG)
2865 register rtx temp = gen_reg_rtx (Pmode);
2866 register rtx val = force_operand (XEXP (x, 1), temp);
2868 emit_move_insn (temp, val);
2874 else if (GET_CODE (XEXP (x, 1)) == REG)
2876 register rtx temp = gen_reg_rtx (Pmode);
2877 register rtx val = force_operand (XEXP (x, 0), temp);
2879 emit_move_insn (temp, val);
2889 /* Print an integer constant expression in assembler syntax. Addition
2890 and subtraction are the only arithmetic that may appear in these
2891 expressions. FILE is the stdio stream to write to, X is the rtx, and
2892 CODE is the operand print code from the output string. */
2895 output_pic_addr_const (file, x, code)
2902 switch (GET_CODE (x))
2912 assemble_name (file, XSTR (x, 0));
2913 #ifdef ASM_HACK_SYMBOLREF_CODE
2914 ASM_HACK_SYMBOLREF_CODE (XSTR (x, 0), code);
2916 if (code == 'P' && ! SYMBOL_REF_FLAG (x))
2917 fputs ("@PLT", file);
2924 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (x));
2925 assemble_name (asm_out_file, buf);
2929 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
2933 /* This used to output parentheses around the expression,
2934 but that does not work on the 386 (either ATT or BSD assembler). */
2935 output_pic_addr_const (file, XEXP (x, 0), code);
2939 if (GET_MODE (x) == VOIDmode)
2941 /* We can use %d if the number is <32 bits and positive. */
2942 if (CONST_DOUBLE_HIGH (x) || CONST_DOUBLE_LOW (x) < 0)
2943 fprintf (file, "0x%lx%08lx",
2944 (unsigned long) CONST_DOUBLE_HIGH (x),
2945 (unsigned long) CONST_DOUBLE_LOW (x));
2947 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x));
2950 /* We can't handle floating point constants;
2951 PRINT_OPERAND must handle them. */
2952 output_operand_lossage ("floating constant misused");
2956 /* Some assemblers need integer constants to appear first. */
2957 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
2959 output_pic_addr_const (file, XEXP (x, 0), code);
2960 fprintf (file, "+");
2961 output_pic_addr_const (file, XEXP (x, 1), code);
2963 else if (GET_CODE (XEXP (x, 1)) == CONST_INT)
2965 output_pic_addr_const (file, XEXP (x, 1), code);
2966 fprintf (file, "+");
2967 output_pic_addr_const (file, XEXP (x, 0), code);
2974 output_pic_addr_const (file, XEXP (x, 0), code);
2975 fprintf (file, "-");
2976 output_pic_addr_const (file, XEXP (x, 1), code);
2980 if (XVECLEN (x, 0) != 1)
2982 output_pic_addr_const (file, XVECEXP (x, 0, 0), code);
2983 switch (XINT (x, 1))
2986 fputs ("@GOT", file);
2989 fputs ("@GOTOFF", file);
2992 fputs ("@PLT", file);
2995 output_operand_lossage ("invalid UNSPEC as operand");
3001 output_operand_lossage ("invalid expression as operand");
3006 put_jump_code (code, reverse, file)
3011 int flags = cc_prev_status.flags;
3012 int ieee = (TARGET_IEEE_FP && (flags & CC_IN_80387)
3013 && !(cc_prev_status.flags & CC_FCOMI));
3016 if (flags & CC_Z_IN_NOT_C)
3020 fputs (reverse ? "c" : "nc", file);
3024 fputs (reverse ? "nc" : "c", file);
3035 suffix = reverse ? "ae" : "b";
3040 suffix = reverse ? "ne" : "e";
3043 suffix = reverse ? "ne" : "e";
3046 suffix = reverse ? "e" : "ne";
3051 fputs (suffix, file);
3054 if (flags & CC_TEST_AX)
3056 if ((flags & CC_NO_OVERFLOW) && (code == LE || code == GT))
3059 code = reverse_condition (code);
3071 suffix = flags & CC_IN_80387 ? "a" : "g";
3079 if (flags & CC_NO_OVERFLOW)
3082 suffix = flags & CC_IN_80387 ? "b" : "l";
3090 if (flags & CC_NO_OVERFLOW)
3093 suffix = flags & CC_IN_80387 ? "ae" : "ge";
3101 suffix = flags & CC_IN_80387 ? "be" : "le";
3111 fputs (suffix, file);
3114 /* Append the correct conditional move suffix which corresponds to CODE. */
3117 put_condition_code (code, reverse_cc, mode, file)
3120 enum mode_class mode;
3123 int ieee = (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387)
3124 && ! (cc_prev_status.flags & CC_FCOMI));
3125 if (reverse_cc && ! ieee)
3126 code = reverse_condition (code);
3128 if (mode == MODE_INT)
3132 if (cc_prev_status.flags & CC_Z_IN_NOT_C)
3139 if (cc_prev_status.flags & CC_Z_IN_NOT_C)
3146 if (cc_prev_status.flags & CC_NO_OVERFLOW)
3161 if (cc_prev_status.flags & CC_NO_OVERFLOW)
3184 output_operand_lossage ("Invalid %%C operand");
3187 else if (mode == MODE_FLOAT)
3191 fputs (ieee ? (reverse_cc ? "ne" : "e") : "ne", file);
3194 fputs (ieee ? (reverse_cc ? "ne" : "e") : "e", file);
3197 fputs (ieee ? (reverse_cc ? "ne" : "e") : "nb", file);
3200 fputs (ieee ? (reverse_cc ? "ne" : "e") : "nbe", file);
3203 fputs (ieee ? (reverse_cc ? "nb" : "b") : "be", file);
3206 fputs (ieee ? (reverse_cc ? "ne" : "e") : "b", file);
3209 fputs (ieee ? (reverse_cc ? "ne" : "e") : "nb", file);
3212 fputs (ieee ? (reverse_cc ? "ne" : "e") : "nbe", file);
3215 fputs (ieee ? (reverse_cc ? "nb" : "b") : "be", file);
3218 fputs (ieee ? (reverse_cc ? "ne" : "e") : "b", file);
3221 output_operand_lossage ("Invalid %%C operand");
3226 L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
3227 C -- print opcode suffix for set/cmov insn.
3228 c -- like C, but print reversed condition
3229 F -- print opcode suffix for fcmov insn.
3230 f -- like F, but print reversed condition
3231 D -- print the opcode suffix for a jump
3232 d -- like D, but print reversed condition
3233 R -- print the prefix for register names.
3234 z -- print the opcode suffix for the size of the current operand.
3235 * -- print a star (in certain assembler syntax)
3236 w -- print the operand as if it's a "word" (HImode) even if it isn't.
3237 J -- print the appropriate jump operand.
3238 s -- print a shift double count, followed by the assemblers argument
3240 b -- print the QImode name of the register for the indicated operand.
3241 %b0 would print %al if operands[0] is reg 0.
3242 w -- likewise, print the HImode name of the register.
3243 k -- likewise, print the SImode name of the register.
3244 h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
3245 y -- print "st(0)" instead of "st" as a register.
3246 P -- print as a PIC constant
3247 _ -- output "_" if YES_UNDERSCORES */
3250 print_operand (file, x, code)
3265 #ifdef YES_UNDERSCORES
3271 PUT_OP_SIZE (code, 'l', file);
3275 PUT_OP_SIZE (code, 'w', file);
3279 PUT_OP_SIZE (code, 'b', file);
3283 PUT_OP_SIZE (code, 'l', file);
3287 PUT_OP_SIZE (code, 's', file);
3291 PUT_OP_SIZE (code, 't', file);
3295 /* 387 opcodes don't get size suffixes if the operands are
3298 if (STACK_REG_P (x))
3301 /* this is the size of op from size of operand */
3302 switch (GET_MODE_SIZE (GET_MODE (x)))
3305 #ifdef HAVE_GAS_FILDS_FISTS
3306 PUT_OP_SIZE ('W', 's', file);
3311 if (GET_MODE (x) == SFmode)
3313 PUT_OP_SIZE ('S', 's', file);
3317 PUT_OP_SIZE ('L', 'l', file);
3321 PUT_OP_SIZE ('T', 't', file);
3325 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_INT)
3327 #ifdef GAS_MNEMONICS
3328 PUT_OP_SIZE ('Q', 'q', file);
3331 PUT_OP_SIZE ('Q', 'l', file); /* Fall through */
3335 PUT_OP_SIZE ('Q', 'l', file);
3352 switch (GET_CODE (x))
3354 /* These conditions are appropriate for testing the result
3355 of an arithmetic operation, not for a compare operation.
3356 Cases GE, LT assume CC_NO_OVERFLOW true. All cases assume
3357 CC_Z_IN_NOT_C false and not floating point. */
3358 case NE: fputs ("jne", file); return;
3359 case EQ: fputs ("je", file); return;
3360 case GE: fputs ("jns", file); return;
3361 case LT: fputs ("js", file); return;
3362 case GEU: fputs ("jmp", file); return;
3363 case GTU: fputs ("jne", file); return;
3364 case LEU: fputs ("je", file); return;
3365 case LTU: fputs ("#branch never", file); return;
3367 /* no matching branches for GT nor LE */
3374 if (GET_CODE (x) == CONST_INT || ! SHIFT_DOUBLE_OMITS_COUNT)
3376 PRINT_OPERAND (file, x, 0);
3377 fputs (AS2C (,) + 1, file);
3383 put_jump_code (GET_CODE (x), 0, file);
3387 put_jump_code (GET_CODE (x), 1, file);
3390 /* This is used by the conditional move instructions. */
3392 put_condition_code (GET_CODE (x), 0, MODE_INT, file);
3395 /* Like above, but reverse condition */
3397 put_condition_code (GET_CODE (x), 1, MODE_INT, file); return;
3400 put_condition_code (GET_CODE (x), 0, MODE_FLOAT, file);
3403 /* Like above, but reverse condition */
3405 put_condition_code (GET_CODE (x), 1, MODE_FLOAT, file);
3412 sprintf (str, "invalid operand code `%c'", code);
3413 output_operand_lossage (str);
3418 if (GET_CODE (x) == REG)
3420 PRINT_REG (x, code, file);
3423 else if (GET_CODE (x) == MEM)
3425 PRINT_PTR (x, file);
3426 if (CONSTANT_ADDRESS_P (XEXP (x, 0)))
3429 output_pic_addr_const (file, XEXP (x, 0), code);
3431 output_addr_const (file, XEXP (x, 0));
3434 output_address (XEXP (x, 0));
3437 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode)
3442 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
3443 REAL_VALUE_TO_TARGET_SINGLE (r, l);
3444 PRINT_IMMED_PREFIX (file);
3445 fprintf (file, "0x%lx", l);
3448 /* These float cases don't actually occur as immediate operands. */
3449 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode)
3454 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
3455 REAL_VALUE_TO_DECIMAL (r, "%.22e", dstr);
3456 fprintf (file, "%s", dstr);
3459 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == XFmode)
3464 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
3465 REAL_VALUE_TO_DECIMAL (r, "%.22e", dstr);
3466 fprintf (file, "%s", dstr);
3472 if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)
3473 PRINT_IMMED_PREFIX (file);
3474 else if (GET_CODE (x) == CONST || GET_CODE (x) == SYMBOL_REF
3475 || GET_CODE (x) == LABEL_REF)
3476 PRINT_OFFSET_PREFIX (file);
3479 output_pic_addr_const (file, x, code);
3481 output_addr_const (file, x);
3485 /* Print a memory operand whose address is ADDR. */
3488 print_operand_address (file, addr)
3492 register rtx reg1, reg2, breg, ireg;
3495 switch (GET_CODE (addr))
3498 /* ESI addressing makes instruction vector decoded on the K6. We can
3499 avoid this by ESI+0 addressing. */
3500 if (REGNO_REG_CLASS (REGNO (addr)) == SIREG
3501 && ix86_cpu == PROCESSOR_K6 && !optimize_size)
3502 output_addr_const (file, const0_rtx);
3504 fprintf (file, "%se", RP);
3505 fputs (hi_reg_name[REGNO (addr)], file);
3515 if (CONSTANT_ADDRESS_P (XEXP (addr, 0)))
3517 offset = XEXP (addr, 0);
3518 addr = XEXP (addr, 1);
3520 else if (CONSTANT_ADDRESS_P (XEXP (addr, 1)))
3522 offset = XEXP (addr, 1);
3523 addr = XEXP (addr, 0);
3526 if (GET_CODE (addr) != PLUS)
3528 else if (GET_CODE (XEXP (addr, 0)) == MULT)
3529 reg1 = XEXP (addr, 0), addr = XEXP (addr, 1);
3530 else if (GET_CODE (XEXP (addr, 1)) == MULT)
3531 reg1 = XEXP (addr, 1), addr = XEXP (addr, 0);
3532 else if (GET_CODE (XEXP (addr, 0)) == REG)
3533 reg1 = XEXP (addr, 0), addr = XEXP (addr, 1);
3534 else if (GET_CODE (XEXP (addr, 1)) == REG)
3535 reg1 = XEXP (addr, 1), addr = XEXP (addr, 0);
3537 if (GET_CODE (addr) == REG || GET_CODE (addr) == MULT)
3554 if ((reg1 && GET_CODE (reg1) == MULT)
3555 || (reg2 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg2))))
3560 else if (reg1 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg1)))
3566 if (ireg != 0 || breg != 0)
3573 output_pic_addr_const (file, addr, 0);
3574 else if (GET_CODE (addr) == LABEL_REF)
3575 output_asm_label (addr);
3577 output_addr_const (file, addr);
3580 if (ireg != 0 && GET_CODE (ireg) == MULT)
3582 scale = INTVAL (XEXP (ireg, 1));
3583 ireg = XEXP (ireg, 0);
3586 /* The stack pointer can only appear as a base register,
3587 never an index register, so exchange the regs if it is wrong. */
3589 if (scale == 1 && ireg && REGNO (ireg) == STACK_POINTER_REGNUM)
3598 /* output breg+ireg*scale */
3599 PRINT_B_I_S (breg, ireg, scale, file);
3607 if (GET_CODE (XEXP (addr, 0)) == CONST_INT)
3609 scale = INTVAL (XEXP (addr, 0));
3610 ireg = XEXP (addr, 1);
3614 scale = INTVAL (XEXP (addr, 1));
3615 ireg = XEXP (addr, 0);
3618 /* (reg,reg,) is shorter than (,reg,2). */
3621 PRINT_B_I_S (ireg, ireg, 1, file);
3625 output_addr_const (file, const0_rtx);
3626 PRINT_B_I_S (NULL_RTX, ireg, scale, file);
3632 if (GET_CODE (addr) == CONST_INT
3633 && INTVAL (addr) < 0x8000
3634 && INTVAL (addr) >= -0x8000)
3635 fprintf (file, "%d", (int) INTVAL (addr));
3639 output_pic_addr_const (file, addr, 0);
3641 output_addr_const (file, addr);
3646 /* Set the cc_status for the results of an insn whose pattern is EXP.
3647 On the 80386, we assume that only test and compare insns, as well
3648 as SI, HI, & DI mode ADD, SUB, NEG, AND, IOR, XOR, BSF, ASHIFT,
3649 ASHIFTRT, and LSHIFTRT instructions set the condition codes usefully.
3650 Also, we assume that jumps, moves and sCOND don't affect the condition
3651 codes. All else clobbers the condition codes, by assumption.
3653 We assume that ALL integer add, minus, etc. instructions effect the
3654 condition codes. This MUST be consistent with i386.md.
3656 We don't record any float test or compare - the redundant test &
3657 compare check in final.c does not handle stack-like regs correctly. */
3660 notice_update_cc (exp)
3663 if (GET_CODE (exp) == SET)
3665 /* Jumps do not alter the cc's. */
3666 if (SET_DEST (exp) == pc_rtx)
3669 /* Moving register or memory into a register:
3670 it doesn't alter the cc's, but it might invalidate
3671 the RTX's which we remember the cc's came from.
3672 (Note that moving a constant 0 or 1 MAY set the cc's). */
3673 if (REG_P (SET_DEST (exp))
3674 && (REG_P (SET_SRC (exp)) || GET_CODE (SET_SRC (exp)) == MEM
3675 || GET_RTX_CLASS (GET_CODE (SET_SRC (exp))) == '<'
3676 || GET_CODE (SET_SRC (exp)) == IF_THEN_ELSE))
3678 if (cc_status.value1
3679 && reg_overlap_mentioned_p (SET_DEST (exp), cc_status.value1))
3680 cc_status.value1 = 0;
3682 if (cc_status.value2
3683 && reg_overlap_mentioned_p (SET_DEST (exp), cc_status.value2))
3684 cc_status.value2 = 0;
3689 /* Moving register into memory doesn't alter the cc's.
3690 It may invalidate the RTX's which we remember the cc's came from. */
3691 if (GET_CODE (SET_DEST (exp)) == MEM
3692 && (REG_P (SET_SRC (exp))
3693 || GET_RTX_CLASS (GET_CODE (SET_SRC (exp))) == '<'))
3695 if (cc_status.value1
3696 && reg_overlap_mentioned_p (SET_DEST (exp), cc_status.value1))
3697 cc_status.value1 = 0;
3698 if (cc_status.value2
3699 && reg_overlap_mentioned_p (SET_DEST (exp), cc_status.value2))
3700 cc_status.value2 = 0;
3705 /* Function calls clobber the cc's. */
3706 else if (GET_CODE (SET_SRC (exp)) == CALL)
3712 /* Tests and compares set the cc's in predictable ways. */
3713 else if (SET_DEST (exp) == cc0_rtx)
3716 cc_status.value1 = SET_SRC (exp);
3720 /* Certain instructions effect the condition codes. */
3721 else if (GET_MODE (SET_SRC (exp)) == SImode
3722 || GET_MODE (SET_SRC (exp)) == HImode
3723 || GET_MODE (SET_SRC (exp)) == QImode)
3724 switch (GET_CODE (SET_SRC (exp)))
3726 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
3727 /* Shifts on the 386 don't set the condition codes if the
3728 shift count is zero. */
3729 if (GET_CODE (XEXP (SET_SRC (exp), 1)) != CONST_INT)
3735 /* We assume that the CONST_INT is non-zero (this rtx would
3736 have been deleted if it were zero. */
3738 case PLUS: case MINUS: case NEG:
3739 case AND: case IOR: case XOR:
3740 cc_status.flags = CC_NO_OVERFLOW;
3741 cc_status.value1 = SET_SRC (exp);
3742 cc_status.value2 = SET_DEST (exp);
3745 /* This is the bsf pattern used by ffs. */
3747 if (XINT (SET_SRC (exp), 1) == 5)
3749 /* Only the Z flag is defined after bsf. */
3751 = CC_NOT_POSITIVE | CC_NOT_NEGATIVE | CC_NO_OVERFLOW;
3752 cc_status.value1 = XVECEXP (SET_SRC (exp), 0, 0);
3753 cc_status.value2 = 0;
3766 else if (GET_CODE (exp) == PARALLEL
3767 && GET_CODE (XVECEXP (exp, 0, 0)) == SET)
3769 if (SET_DEST (XVECEXP (exp, 0, 0)) == pc_rtx)
3771 if (SET_DEST (XVECEXP (exp, 0, 0)) == cc0_rtx)
3775 if (stack_regs_mentioned_p (SET_SRC (XVECEXP (exp, 0, 0))))
3777 cc_status.flags |= CC_IN_80387;
3778 if (TARGET_CMOVE && stack_regs_mentioned_p
3779 (XEXP (SET_SRC (XVECEXP (exp, 0, 0)), 1)))
3780 cc_status.flags |= CC_FCOMI;
3783 cc_status.value1 = SET_SRC (XVECEXP (exp, 0, 0));
3795 /* Split one or more DImode RTL references into pairs of SImode
3796 references. The RTL can be REG, offsettable MEM, integer constant, or
3797 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
3798 split and "num" is its length. lo_half and hi_half are output arrays
3799 that parallel "operands". */
3802 split_di (operands, num, lo_half, hi_half)
3805 rtx lo_half[], hi_half[];
3809 rtx op = operands[num];
3810 if (! reload_completed)
3812 lo_half[num] = gen_lowpart (SImode, op);
3813 hi_half[num] = gen_highpart (SImode, op);
3815 else if (GET_CODE (op) == REG)
3817 lo_half[num] = gen_rtx_REG (SImode, REGNO (op));
3818 hi_half[num] = gen_rtx_REG (SImode, REGNO (op) + 1);
3820 else if (CONSTANT_P (op))
3821 split_double (op, &lo_half[num], &hi_half[num]);
3822 else if (offsettable_memref_p (op))
3824 rtx lo_addr = XEXP (op, 0);
3825 rtx hi_addr = XEXP (adj_offsettable_operand (op, 4), 0);
3826 lo_half[num] = change_address (op, SImode, lo_addr);
3827 hi_half[num] = change_address (op, SImode, hi_addr);
3834 /* Return 1 if this is a valid binary operation on a 387.
3835 OP is the expression matched, and MODE is its mode. */
3838 binary_387_op (op, mode)
3840 enum machine_mode mode;
3842 if (mode != VOIDmode && mode != GET_MODE (op))
3845 switch (GET_CODE (op))
3851 return GET_MODE_CLASS (GET_MODE (op)) == MODE_FLOAT;
3858 /* Return 1 if this is a valid shift or rotate operation on a 386.
3859 OP is the expression matched, and MODE is its mode. */
3864 enum machine_mode mode;
3866 rtx operand = XEXP (op, 0);
3868 if (mode != VOIDmode && mode != GET_MODE (op))
3871 if (GET_MODE (operand) != GET_MODE (op)
3872 || GET_MODE_CLASS (GET_MODE (op)) != MODE_INT)
3875 return (GET_CODE (op) == ASHIFT
3876 || GET_CODE (op) == ASHIFTRT
3877 || GET_CODE (op) == LSHIFTRT
3878 || GET_CODE (op) == ROTATE
3879 || GET_CODE (op) == ROTATERT);
3882 /* Return 1 if OP is COMPARE rtx with mode VOIDmode.
3883 MODE is not used. */
3886 VOIDmode_compare_op (op, mode)
3888 enum machine_mode mode ATTRIBUTE_UNUSED;
3890 return GET_CODE (op) == COMPARE && GET_MODE (op) == VOIDmode;
3893 /* Output code to perform a 387 binary operation in INSN, one of PLUS,
3894 MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3]
3895 is the expression of the binary operation. The output may either be
3896 emitted here, or returned to the caller, like all output_* functions.
3898 There is no guarantee that the operands are the same mode, as they
3899 might be within FLOAT or FLOAT_EXTEND expressions. */
3902 output_387_binary_op (insn, operands)
3908 static char buf[100];
3910 switch (GET_CODE (operands[3]))
3932 strcpy (buf, base_op);
3934 switch (GET_CODE (operands[3]))
3938 if (REG_P (operands[2]) && REGNO (operands[0]) == REGNO (operands[2]))
3941 operands[2] = operands[1];
3945 if (GET_CODE (operands[2]) == MEM)
3946 return strcat (buf, AS1 (%z2,%2));
3948 if (! STACK_REG_P (operands[1]) || ! STACK_REG_P (operands[2]))
3951 if (find_regno_note (insn, REG_DEAD, REGNO (operands[2])))
3953 if (STACK_TOP_P (operands[0]))
3954 return strcat (buf, AS2 (p,%0,%2));
3956 return strcat (buf, AS2 (p,%2,%0));
3959 if (STACK_TOP_P (operands[0]))
3960 return strcat (buf, AS2C (%y2,%0));
3962 return strcat (buf, AS2C (%2,%0));
3966 if (GET_CODE (operands[1]) == MEM)
3967 return strcat (buf, AS1 (r%z1,%1));
3969 if (GET_CODE (operands[2]) == MEM)
3970 return strcat (buf, AS1 (%z2,%2));
3972 if (! STACK_REG_P (operands[1]) || ! STACK_REG_P (operands[2]))
3975 if (find_regno_note (insn, REG_DEAD, REGNO (operands[2])))
3977 if (STACK_TOP_P (operands[0]))
3978 return strcat (buf, AS2 (p,%0,%2));
3980 return strcat (buf, AS2 (rp,%2,%0));
3983 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3985 if (STACK_TOP_P (operands[0]))
3986 return strcat (buf, AS2 (rp,%0,%1));
3988 return strcat (buf, AS2 (p,%1,%0));
3991 if (STACK_TOP_P (operands[0]))
3993 if (STACK_TOP_P (operands[1]))
3994 return strcat (buf, AS2C (%y2,%0));
3996 return strcat (buf, AS2 (r,%y1,%0));
3998 else if (STACK_TOP_P (operands[1]))
3999 return strcat (buf, AS2C (%1,%0));
4001 return strcat (buf, AS2 (r,%2,%0));
4008 /* Output code for INSN to convert a float to a signed int. OPERANDS
4009 are the insn operands. The input may be SFmode, DFmode, or XFmode
4010 and the output operand may be SImode or DImode. As a special case,
4011 make sure that the 387 stack top dies if the output mode is DImode,
4012 because the hardware requires this. */
4015 output_fix_trunc (insn, operands)
4019 int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
4022 if (! STACK_TOP_P (operands[1]))
4025 if (GET_MODE (operands[0]) == DImode && ! stack_top_dies)
4028 xops[0] = GEN_INT (0x0c00);
4029 xops[1] = operands[5];
4031 output_asm_insn (AS1 (fnstc%W2,%2), operands);
4032 output_asm_insn (AS2 (mov%W5,%2,%w5), operands);
4033 output_asm_insn (AS2 (or%W1,%0,%w1), xops);
4034 output_asm_insn (AS2 (mov%W3,%w5,%3), operands);
4035 output_asm_insn (AS1 (fldc%W3,%3), operands);
4037 xops[0] = NON_STACK_REG_P (operands[0]) ? operands[4] : operands[0];
4040 output_asm_insn (AS1 (fistp%z0,%y0), xops);
4042 output_asm_insn (AS1 (fist%z0,%y0), xops);
4044 if (NON_STACK_REG_P (operands[0]))
4046 if (GET_MODE (operands[0]) == SImode)
4047 output_asm_insn (AS2 (mov%L0,%4,%0), operands);
4050 xops[0] = operands[0];
4051 xops[1] = operands[4];
4052 output_asm_insn (output_move_double (xops), xops);
4056 return AS1 (fldc%W2,%2);
4059 /* Output code for INSN to extend a float. OPERANDS are the insn
4060 operands. The output may be DFmode or XFmode and the input operand
4061 may be SFmode or DFmode. Operands 2 and 3 are scratch memory and
4062 are only necessary if operands 0 or 1 are non-stack registers. */
4065 output_float_extend (insn, operands)
4069 int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
4072 if (! STACK_TOP_P (operands[0]) && ! STACK_TOP_P (operands[1]))
4075 if (STACK_TOP_P (operands[0]) && STACK_TOP_P (operands[1]) && stack_top_dies)
4078 if (STACK_TOP_P (operands[0]) )
4080 if (NON_STACK_REG_P (operands[1]))
4082 if (GET_MODE (operands[1]) == SFmode)
4083 output_asm_insn (AS2 (mov%L0,%1,%2), operands);
4086 xops[0] = operands[2];
4087 xops[1] = operands[1];
4088 output_asm_insn (output_move_double (xops), xops);
4092 xops[0] = NON_STACK_REG_P (operands[1]) ? operands[2] : operands[1];
4094 output_asm_insn (AS1 (fld%z0,%y0), xops);
4098 xops[0] = NON_STACK_REG_P (operands[0]) ? operands[3] : operands[0];
4101 || (GET_CODE (xops[0]) == MEM && GET_MODE (xops[0]) == XFmode))
4103 output_asm_insn (AS1 (fstp%z0,%y0), xops);
4104 if (! stack_top_dies)
4105 output_asm_insn (AS1 (fld%z0,%y0), xops);
4108 output_asm_insn (AS1 (fst%z0,%y0), xops);
4110 if (NON_STACK_REG_P (operands[0]))
4112 xops[0] = operands[0];
4113 xops[1] = operands[3];
4114 output_asm_insn (output_move_double (xops), xops);
4119 /* Output code for INSN to compare OPERANDS. The two operands might
4120 not have the same mode: one might be within a FLOAT or FLOAT_EXTEND
4121 expression. If the compare is in mode CCFPEQmode, use an opcode that
4122 will not fault if a qNaN is present. */
4125 output_float_compare (insn, operands)
4130 rtx body = XVECEXP (PATTERN (insn), 0, 0);
4131 int unordered_compare = GET_MODE (SET_SRC (body)) == CCFPEQmode;
4136 if (TARGET_CMOVE && STACK_REG_P (operands[1])
4137 && STACK_REG_P (operands[0]))
4139 cc_status.flags |= CC_FCOMI;
4140 cc_prev_status.flags &= ~CC_TEST_AX;
4143 if (! STACK_TOP_P (operands[0]))
4146 operands[0] = operands[1];
4148 cc_status.flags |= CC_REVERSED;
4151 if (! STACK_TOP_P (operands[0]))
4154 stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
4156 if (STACK_REG_P (operands[1])
4158 && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
4159 && REGNO (operands[1]) == FIRST_STACK_REG + 1)
4161 /* If both the top of the 387 stack dies, and the other operand
4162 is also a stack register that dies, then this must be a
4163 `fcompp' float compare */
4165 if (unordered_compare)
4167 if (cc_status.flags & CC_FCOMI)
4169 output_asm_insn (AS2 (fucomip,%y1,%0), operands);
4170 output_asm_insn (AS1 (fstp, %y0), operands);
4171 if (!TARGET_IEEE_FP)
4175 output_asm_insn ("fucompp", operands);
4179 if (cc_status.flags & CC_FCOMI)
4181 output_asm_insn (AS2 (fcomip, %y1,%0), operands);
4182 output_asm_insn (AS1 (fstp, %y0), operands);
4183 if (!TARGET_IEEE_FP)
4187 output_asm_insn ("fcompp", operands);
4192 static char buf[100];
4194 /* Decide if this is a float compare or an unordered float compare. */
4196 if (unordered_compare)
4197 strcpy (buf, (cc_status.flags & CC_FCOMI) ? "fucomi" : "fucom");
4199 strcpy (buf, (cc_status.flags & CC_FCOMI) ? "fcomi" : "fcom");
4201 /* Modify the opcode if the 387 stack is to be popped. */
4206 if (cc_status.flags & CC_FCOMI)
4208 output_asm_insn (strcat (buf, AS2 (%z1,%y1,%0)), operands);
4209 if (!TARGET_IEEE_FP)
4213 output_asm_insn (strcat (buf, AS1 (%z1,%y1)), operands);
4216 /* Now retrieve the condition code. */
4219 char *r = output_fp_cc0_set (insn);
4220 if (r[0]) output_asm_insn (r, operands);
4224 /* We emit fstp instruction after integer comparsions to improve
4226 for (i = 0; i < 2 ; i++)
4228 if (STACK_REG_P (operands[i])
4229 && find_regno_note (insn, REG_DEAD, REGNO (operands[i]))
4230 && REGNO (operands[i]) != FIRST_STACK_REG
4231 && (!stack_top_dies || REGNO (operands[i]) != FIRST_STACK_REG + 1))
4234 xexp[0] = gen_rtx_REG (DFmode,
4235 REGNO (operands[i]) - (stack_top_dies != 0));
4236 output_asm_insn (AS1 (fstp, %y0), xexp);
4245 /* Output opcodes to transfer the results of FP compare or test INSN
4246 from the FPU to the CPU flags. If TARGET_IEEE_FP, ensure that if the
4247 result of the compare or test is unordered, no comparison operator
4248 succeeds except NE. Return an output template, if any. */
4251 output_fp_cc0_set (insn)
4258 if (!(cc_status.flags & CC_FCOMI))
4260 xops[0] = gen_rtx_REG (HImode, 0);
4261 output_asm_insn (AS1 (fnsts%W0,%0), xops);
4264 if (! TARGET_IEEE_FP)
4266 if (!(cc_status.flags & CC_REVERSED))
4268 next = next_cc0_user (insn);
4270 if (GET_CODE (PATTERN (next)) == SET
4271 && SET_DEST (PATTERN (next)) == pc_rtx
4272 && GET_CODE (SET_SRC (PATTERN (next))) == IF_THEN_ELSE)
4273 code = GET_CODE (XEXP (SET_SRC (PATTERN (next)), 0));
4274 else if (GET_CODE (PATTERN (next)) == SET)
4275 code = GET_CODE (SET_SRC (PATTERN (next)));
4279 if (code == GT || code == LT || code == EQ || code == NE
4280 || code == LE || code == GE)
4282 /* We will test eax directly. */
4283 cc_status.flags |= CC_TEST_AX;
4291 next = next_cc0_user (insn);
4292 if (next == NULL_RTX)
4295 if (GET_CODE (PATTERN (next)) == SET
4296 && SET_DEST (PATTERN (next)) == pc_rtx
4297 && GET_CODE (SET_SRC (PATTERN (next))) == IF_THEN_ELSE)
4298 code = GET_CODE (XEXP (SET_SRC (PATTERN (next)), 0));
4299 else if (GET_CODE (PATTERN (next)) == SET)
4301 if (GET_CODE (SET_SRC (PATTERN (next))) == IF_THEN_ELSE)
4302 code = GET_CODE (XEXP (SET_SRC (PATTERN (next)), 0));
4304 code = GET_CODE (SET_SRC (PATTERN (next)));
4307 else if (GET_CODE (PATTERN (next)) == PARALLEL
4308 && GET_CODE (XVECEXP (PATTERN (next), 0, 0)) == SET)
4310 if (GET_CODE (SET_SRC (XVECEXP (PATTERN (next), 0, 0))) == IF_THEN_ELSE)
4311 code = GET_CODE (XEXP (SET_SRC (XVECEXP (PATTERN (next), 0, 0)), 0));
4313 code = GET_CODE (SET_SRC (XVECEXP (PATTERN (next), 0, 0)));
4318 if (cc_status.flags & CC_FCOMI)
4320 /* It is very tricky. We have to do it right. */
4322 xops [0] = gen_rtx_REG (QImode, 0);
4331 output_asm_insn (AS1 (setb,%b0), xops);
4332 output_asm_insn (AS1 (setp,%h0), xops);
4333 output_asm_insn (AS2 (cmp%B0,%b0,%h0), xops);
4337 output_asm_insn (AS1 (setbe,%b0), xops);
4338 output_asm_insn (AS1 (setnp,%h0), xops);
4339 output_asm_insn (AS2 (xor%B0,%b0,%h0), xops);
4344 output_asm_insn (AS1 (setne,%b0), xops);
4345 output_asm_insn (AS1 (setp,%h0), xops);
4346 output_asm_insn (AS2 (or%B0,%b0,%h0), xops);
4359 xops[0] = gen_rtx_REG (QImode, 0);
4364 xops[1] = GEN_INT (0x45);
4365 output_asm_insn (AS2 (and%B0,%1,%h0), xops);
4370 xops[1] = GEN_INT (0x45);
4371 xops[2] = GEN_INT (0x01);
4372 output_asm_insn (AS2 (and%B0,%1,%h0), xops);
4373 output_asm_insn (AS2 (cmp%B0,%2,%h0), xops);
4378 xops[1] = GEN_INT (0x05);
4379 output_asm_insn (AS2 (and%B0,%1,%h0), xops);
4384 xops[1] = GEN_INT (0x45);
4385 xops[2] = GEN_INT (0x40);
4386 output_asm_insn (AS2 (and%B0,%1,%h0), xops);
4387 output_asm_insn (AS1 (dec%B0,%h0), xops);
4388 output_asm_insn (AS2 (cmp%B0,%2,%h0), xops);
4393 xops[1] = GEN_INT (0x45);
4394 xops[2] = GEN_INT (0x40);
4395 output_asm_insn (AS2 (and%B0,%1,%h0), xops);
4396 output_asm_insn (AS2 (cmp%B0,%2,%h0), xops);
4401 xops[1] = GEN_INT (0x44);
4402 xops[2] = GEN_INT (0x40);
4403 output_asm_insn (AS2 (and%B0,%1,%h0), xops);
4404 output_asm_insn (AS2 (xor%B0,%2,%h0), xops);
4420 #define MAX_386_STACK_LOCALS 2
4422 static rtx i386_stack_locals[(int) MAX_MACHINE_MODE][MAX_386_STACK_LOCALS];
4424 /* Define the structure for the machine field in struct function. */
4425 struct machine_function
4427 rtx i386_stack_locals[(int) MAX_MACHINE_MODE][MAX_386_STACK_LOCALS];
4429 char pic_label_name[256];
4432 /* Functions to save and restore i386_stack_locals.
4433 These will be called, via pointer variables,
4434 from push_function_context and pop_function_context. */
4437 save_386_machine_status (p)
4441 = (struct machine_function *) xmalloc (sizeof (struct machine_function));
4442 bcopy ((char *) i386_stack_locals, (char *) p->machine->i386_stack_locals,
4443 sizeof i386_stack_locals);
4444 p->machine->pic_label_rtx = pic_label_rtx;
4445 bcopy (pic_label_name, p->machine->pic_label_name, 256);
4449 restore_386_machine_status (p)
4452 bcopy ((char *) p->machine->i386_stack_locals, (char *) i386_stack_locals,
4453 sizeof i386_stack_locals);
4454 pic_label_rtx = p->machine->pic_label_rtx;
4455 bcopy (p->machine->pic_label_name, pic_label_name, 256);
4460 /* Clear stack slot assignments remembered from previous functions.
4461 This is called from INIT_EXPANDERS once before RTL is emitted for each
4465 clear_386_stack_locals ()
4467 enum machine_mode mode;
4470 for (mode = VOIDmode; (int) mode < (int) MAX_MACHINE_MODE;
4471 mode = (enum machine_mode) ((int) mode + 1))
4472 for (n = 0; n < MAX_386_STACK_LOCALS; n++)
4473 i386_stack_locals[(int) mode][n] = NULL_RTX;
4475 pic_label_rtx = NULL_RTX;
4476 bzero (pic_label_name, 256);
4477 /* Arrange to save and restore i386_stack_locals around nested functions. */
4478 save_machine_status = save_386_machine_status;
4479 restore_machine_status = restore_386_machine_status;
4482 /* Return a MEM corresponding to a stack slot with mode MODE.
4483 Allocate a new slot if necessary.
4485 The RTL for a function can have several slots available: N is
4486 which slot to use. */
4489 assign_386_stack_local (mode, n)
4490 enum machine_mode mode;
4493 if (n < 0 || n >= MAX_386_STACK_LOCALS)
4496 if (i386_stack_locals[(int) mode][n] == NULL_RTX)
4497 i386_stack_locals[(int) mode][n]
4498 = assign_stack_local (mode, GET_MODE_SIZE (mode), 0);
4500 return i386_stack_locals[(int) mode][n];
4505 enum machine_mode mode ATTRIBUTE_UNUSED;
4507 return (GET_CODE (op) == MULT);
4512 enum machine_mode mode ATTRIBUTE_UNUSED;
4514 return (GET_CODE (op) == DIV);
4518 /* Create a new copy of an rtx.
4519 Recursively copies the operands of the rtx,
4520 except for those few rtx codes that are sharable.
4521 Doesn't share CONST */
4529 register RTX_CODE code;
4530 register char *format_ptr;
4532 code = GET_CODE (orig);
4545 /* SCRATCH must be shared because they represent distinct values. */
4550 /* CONST can be shared if it contains a SYMBOL_REF. If it contains
4551 a LABEL_REF, it isn't sharable. */
4552 if (GET_CODE (XEXP (orig, 0)) == PLUS
4553 && GET_CODE (XEXP (XEXP (orig, 0), 0)) == SYMBOL_REF
4554 && GET_CODE (XEXP (XEXP (orig, 0), 1)) == CONST_INT)
4558 /* A MEM with a constant address is not sharable. The problem is that
4559 the constant address may need to be reloaded. If the mem is shared,
4560 then reloading one copy of this mem will cause all copies to appear
4561 to have been reloaded. */
4564 copy = rtx_alloc (code);
4565 PUT_MODE (copy, GET_MODE (orig));
4566 copy->in_struct = orig->in_struct;
4567 copy->volatil = orig->volatil;
4568 copy->unchanging = orig->unchanging;
4569 copy->integrated = orig->integrated;
4571 copy->is_spill_rtx = orig->is_spill_rtx;
4573 format_ptr = GET_RTX_FORMAT (GET_CODE (copy));
4575 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (copy)); i++)
4577 switch (*format_ptr++)
4580 XEXP (copy, i) = XEXP (orig, i);
4581 if (XEXP (orig, i) != NULL)
4582 XEXP (copy, i) = copy_rtx (XEXP (orig, i));
4587 XEXP (copy, i) = XEXP (orig, i);
4592 XVEC (copy, i) = XVEC (orig, i);
4593 if (XVEC (orig, i) != NULL)
4595 XVEC (copy, i) = rtvec_alloc (XVECLEN (orig, i));
4596 for (j = 0; j < XVECLEN (copy, i); j++)
4597 XVECEXP (copy, i, j) = copy_rtx (XVECEXP (orig, i, j));
4602 XWINT (copy, i) = XWINT (orig, i);
4606 XINT (copy, i) = XINT (orig, i);
4611 XSTR (copy, i) = XSTR (orig, i);
4622 /* Try to rewrite a memory address to make it valid */
4625 rewrite_address (mem_rtx)
4628 rtx index_rtx, base_rtx, offset_rtx, scale_rtx, ret_rtx;
4630 int offset_adjust = 0;
4631 int was_only_offset = 0;
4632 rtx mem_addr = XEXP (mem_rtx, 0);
4633 char *storage = oballoc (0);
4635 int is_spill_rtx = 0;
4637 in_struct = MEM_IN_STRUCT_P (mem_rtx);
4638 is_spill_rtx = RTX_IS_SPILL_P (mem_rtx);
4640 if (GET_CODE (mem_addr) == PLUS
4641 && GET_CODE (XEXP (mem_addr, 1)) == PLUS
4642 && GET_CODE (XEXP (XEXP (mem_addr, 1), 0)) == REG)
4644 /* This part is utilized by the combiner. */
4646 = gen_rtx (PLUS, GET_MODE (mem_addr),
4647 gen_rtx (PLUS, GET_MODE (XEXP (mem_addr, 1)),
4648 XEXP (mem_addr, 0), XEXP (XEXP (mem_addr, 1), 0)),
4649 XEXP (XEXP (mem_addr, 1), 1));
4651 if (memory_address_p (GET_MODE (mem_rtx), ret_rtx))
4653 XEXP (mem_rtx, 0) = ret_rtx;
4654 RTX_IS_SPILL_P (ret_rtx) = is_spill_rtx;
4661 /* This part is utilized by loop.c.
4662 If the address contains PLUS (reg,const) and this pattern is invalid
4663 in this case - try to rewrite the address to make it valid. */
4664 storage = oballoc (0);
4665 index_rtx = base_rtx = offset_rtx = NULL;
4667 /* Find the base index and offset elements of the memory address. */
4668 if (GET_CODE (mem_addr) == PLUS)
4670 if (GET_CODE (XEXP (mem_addr, 0)) == REG)
4672 if (GET_CODE (XEXP (mem_addr, 1)) == REG)
4673 base_rtx = XEXP (mem_addr, 1), index_rtx = XEXP (mem_addr, 0);
4675 base_rtx = XEXP (mem_addr, 0), offset_rtx = XEXP (mem_addr, 1);
4678 else if (GET_CODE (XEXP (mem_addr, 0)) == MULT)
4680 index_rtx = XEXP (mem_addr, 0);
4681 if (GET_CODE (XEXP (mem_addr, 1)) == REG)
4682 base_rtx = XEXP (mem_addr, 1);
4684 offset_rtx = XEXP (mem_addr, 1);
4687 else if (GET_CODE (XEXP (mem_addr, 0)) == PLUS)
4689 if (GET_CODE (XEXP (XEXP (mem_addr, 0), 0)) == PLUS
4690 && GET_CODE (XEXP (XEXP (XEXP (mem_addr, 0), 0), 0)) == MULT
4691 && (GET_CODE (XEXP (XEXP (XEXP (XEXP (mem_addr, 0), 0), 0), 0))
4693 && (GET_CODE (XEXP (XEXP (XEXP (XEXP (mem_addr, 0), 0), 0), 1))
4695 && (GET_CODE (XEXP (XEXP (XEXP (mem_addr, 0), 0), 1))
4697 && GET_CODE (XEXP (XEXP (mem_addr, 0), 1)) == REG
4698 && GET_CODE (XEXP (mem_addr, 1)) == SYMBOL_REF)
4700 index_rtx = XEXP (XEXP (XEXP (mem_addr, 0), 0), 0);
4701 offset_rtx = XEXP (mem_addr, 1);
4702 base_rtx = XEXP (XEXP (mem_addr, 0), 1);
4703 offset_adjust = INTVAL (XEXP (XEXP (XEXP (mem_addr, 0), 0), 1));
4707 offset_rtx = XEXP (mem_addr, 1);
4708 index_rtx = XEXP (XEXP (mem_addr, 0), 0);
4709 base_rtx = XEXP (XEXP (mem_addr, 0), 1);
4713 else if (GET_CODE (XEXP (mem_addr, 0)) == CONST_INT)
4715 was_only_offset = 1;
4718 offset_rtx = XEXP (mem_addr, 1);
4719 offset_adjust = INTVAL (XEXP (mem_addr, 0));
4720 if (offset_adjust == 0)
4722 XEXP (mem_rtx, 0) = offset_rtx;
4723 RTX_IS_SPILL_P (XEXP (mem_rtx, 0)) = is_spill_rtx;
4733 else if (GET_CODE (mem_addr) == MULT)
4734 index_rtx = mem_addr;
4741 if (index_rtx != 0 && GET_CODE (index_rtx) == MULT)
4743 if (GET_CODE (XEXP (index_rtx, 1)) != CONST_INT)
4749 scale_rtx = XEXP (index_rtx, 1);
4750 scale = INTVAL (scale_rtx);
4751 index_rtx = copy_all_rtx (XEXP (index_rtx, 0));
4754 /* Now find which of the elements are invalid and try to fix them. */
4755 if (index_rtx && GET_CODE (index_rtx) == CONST_INT && base_rtx == NULL)
4757 offset_adjust = INTVAL (index_rtx) * scale;
4759 if (offset_rtx != 0 && CONSTANT_P (offset_rtx))
4760 offset_rtx = plus_constant (offset_rtx, offset_adjust);
4761 else if (offset_rtx == 0)
4762 offset_rtx = const0_rtx;
4764 RTX_IS_SPILL_P (XEXP (mem_rtx, 0)) = is_spill_rtx;
4765 XEXP (mem_rtx, 0) = offset_rtx;
4769 if (base_rtx && GET_CODE (base_rtx) == PLUS
4770 && GET_CODE (XEXP (base_rtx, 0)) == REG
4771 && GET_CODE (XEXP (base_rtx, 1)) == CONST_INT)
4773 offset_adjust += INTVAL (XEXP (base_rtx, 1));
4774 base_rtx = copy_all_rtx (XEXP (base_rtx, 0));
4777 else if (base_rtx && GET_CODE (base_rtx) == CONST_INT)
4779 offset_adjust += INTVAL (base_rtx);
4783 if (index_rtx && GET_CODE (index_rtx) == PLUS
4784 && GET_CODE (XEXP (index_rtx, 0)) == REG
4785 && GET_CODE (XEXP (index_rtx, 1)) == CONST_INT)
4787 offset_adjust += INTVAL (XEXP (index_rtx, 1)) * scale;
4788 index_rtx = copy_all_rtx (XEXP (index_rtx, 0));
4793 if (! LEGITIMATE_INDEX_P (index_rtx)
4794 && ! (index_rtx == stack_pointer_rtx && scale == 1
4795 && base_rtx == NULL))
4804 if (! LEGITIMATE_INDEX_P (base_rtx) && GET_CODE (base_rtx) != REG)
4811 if (offset_adjust != 0)
4813 if (offset_rtx != 0 && CONSTANT_P (offset_rtx))
4814 offset_rtx = plus_constant (offset_rtx, offset_adjust);
4816 offset_rtx = const0_rtx;
4824 ret_rtx = gen_rtx (PLUS, GET_MODE (base_rtx),
4825 gen_rtx (MULT, GET_MODE (index_rtx),
4826 index_rtx, scale_rtx),
4829 if (GET_CODE (offset_rtx) != CONST_INT
4830 || INTVAL (offset_rtx) != 0)
4831 ret_rtx = gen_rtx (PLUS, GET_MODE (ret_rtx),
4832 ret_rtx, offset_rtx);
4836 ret_rtx = gen_rtx (PLUS, GET_MODE (index_rtx),
4837 index_rtx, base_rtx);
4839 if (GET_CODE (offset_rtx) != CONST_INT
4840 || INTVAL (offset_rtx) != 0)
4841 ret_rtx = gen_rtx (PLUS, GET_MODE (ret_rtx),
4842 ret_rtx, offset_rtx);
4849 ret_rtx = gen_rtx (MULT, GET_MODE (index_rtx),
4850 index_rtx, scale_rtx);
4852 if (GET_CODE (offset_rtx) != CONST_INT
4853 || INTVAL (offset_rtx) != 0)
4854 ret_rtx = gen_rtx (PLUS, GET_MODE (ret_rtx),
4855 ret_rtx, offset_rtx);
4859 if (GET_CODE (offset_rtx) == CONST_INT
4860 && INTVAL (offset_rtx) == 0)
4861 ret_rtx = index_rtx;
4863 ret_rtx = gen_rtx (PLUS, GET_MODE (index_rtx),
4864 index_rtx, offset_rtx);
4872 if (GET_CODE (offset_rtx) == CONST_INT
4873 && INTVAL (offset_rtx) == 0)
4876 ret_rtx = gen_rtx (PLUS, GET_MODE (base_rtx), base_rtx,
4879 else if (was_only_offset)
4880 ret_rtx = offset_rtx;
4888 XEXP (mem_rtx, 0) = ret_rtx;
4889 RTX_IS_SPILL_P (XEXP (mem_rtx, 0)) = is_spill_rtx;
4900 /* Return 1 if the first insn to set cc before INSN also sets the register
4901 REG_RTX; otherwise return 0. */
4903 last_to_set_cc (reg_rtx, insn)
4906 rtx prev_insn = PREV_INSN (insn);
4910 if (GET_CODE (prev_insn) == NOTE)
4913 else if (GET_CODE (prev_insn) == INSN)
4915 if (GET_CODE (PATTERN (prev_insn)) != SET)
4918 if (rtx_equal_p (SET_DEST (PATTERN (prev_insn)), reg_rtx))
4920 if (sets_condition_code (SET_SRC (PATTERN (prev_insn))))
4926 else if (! doesnt_set_condition_code (SET_SRC (PATTERN (prev_insn))))
4933 prev_insn = PREV_INSN (prev_insn);
4940 doesnt_set_condition_code (pat)
4943 switch (GET_CODE (pat))
4956 sets_condition_code (pat)
4959 switch (GET_CODE (pat))
4981 str_immediate_operand (op, mode)
4983 enum machine_mode mode ATTRIBUTE_UNUSED;
4985 if (GET_CODE (op) == CONST_INT && INTVAL (op) <= 32 && INTVAL (op) >= 0)
4995 if (GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SET
4996 && (GET_MODE (SET_DEST (PATTERN (insn))) == DFmode
4997 || GET_MODE (SET_DEST (PATTERN (insn))) == SFmode
4998 || GET_MODE (SET_DEST (PATTERN (insn))) == XFmode))
5004 /* Return 1 if the mode of the SET_DEST of insn is floating point
5005 and it is not an fld or a move from memory to memory.
5006 Otherwise return 0 */
5012 if (GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SET
5013 && (GET_MODE (SET_DEST (PATTERN (insn))) == DFmode
5014 || GET_MODE (SET_DEST (PATTERN (insn))) == SFmode
5015 || GET_MODE (SET_DEST (PATTERN (insn))) == XFmode)
5016 && GET_CODE (SET_DEST (PATTERN (insn))) == REG
5017 && REGNO (SET_DEST (PATTERN (insn))) >= FIRST_FLOAT_REG
5018 && GET_CODE (SET_SRC (PATTERN (insn))) != MEM)
5024 /* Return 1 if the mode of the SET_DEST of INSN is floating point and is
5025 memory and the source is a register. */
5031 if (GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SET
5032 && (GET_MODE (SET_DEST (PATTERN (insn))) == DFmode
5033 || GET_MODE (SET_DEST (PATTERN (insn))) == SFmode
5034 || GET_MODE (SET_DEST (PATTERN (insn))) == XFmode)
5035 && GET_CODE (SET_DEST (PATTERN (insn))) == MEM
5036 && GET_CODE (SET_SRC (PATTERN (insn))) == REG)
5042 /* Return 1 if DEP_INSN sets a register which INSN uses as a base
5043 or index to reference memory.
5044 otherwise return 0 */
5047 agi_dependent (insn, dep_insn)
5050 int push = 0, push_dep = 0;
5051 if (GET_CODE (dep_insn) == INSN
5052 && GET_CODE (PATTERN (dep_insn)) == SET
5053 && GET_CODE (SET_DEST (PATTERN (dep_insn))) == REG
5054 && reg_mentioned_in_mem (SET_DEST (PATTERN (dep_insn)), insn))
5057 if (GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SET
5058 && GET_CODE (SET_DEST (PATTERN (insn))) == MEM
5059 && push_operand (SET_DEST (PATTERN (insn)),
5060 GET_MODE (SET_DEST (PATTERN (insn)))))
5063 if (GET_CODE (dep_insn) == INSN && GET_CODE (PATTERN (dep_insn)) == SET
5064 && GET_CODE (SET_DEST (PATTERN (dep_insn))) == MEM
5065 && push_operand (SET_DEST (PATTERN (dep_insn)),
5066 GET_MODE (SET_DEST (PATTERN (dep_insn)))))
5069 /* CPUs contain special hardware to allow two pushes. */
5070 if (push && push_dep)
5073 /* Push operation implicitly change stack pointer causing AGI stalls. */
5074 if (push_dep && reg_mentioned_in_mem (stack_pointer_rtx, insn))
5077 /* Push also implicitly read stack pointer. */
5078 if (push && modified_in_p (stack_pointer_rtx, dep_insn))
5084 /* Return 1 if reg is used in rtl as a base or index for a memory ref
5085 otherwise return 0. */
5088 reg_mentioned_in_mem (reg, rtl)
5093 register enum rtx_code code;
5098 code = GET_CODE (rtl);
5116 if (code == MEM && reg_mentioned_p (reg, rtl))
5119 fmt = GET_RTX_FORMAT (code);
5120 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
5124 for (j = XVECLEN (rtl, i) - 1; j >= 0; j--)
5125 if (reg_mentioned_in_mem (reg, XVECEXP (rtl, i, j)))
5129 else if (fmt[i] == 'e' && reg_mentioned_in_mem (reg, XEXP (rtl, i)))
5136 /* Output the appropriate insns for doing strlen if not just doing repnz; scasb
5138 operands[0] = result, initialized with the startaddress
5139 operands[1] = alignment of the address.
5140 operands[2] = scratch register, initialized with the startaddress when
5141 not aligned, otherwise undefined
5143 This is just the body. It needs the initialisations mentioned above and
5144 some address computing at the end. These things are done in i386.md. */
5147 output_strlen_unroll (operands)
5152 xops[0] = operands[0]; /* Result */
5153 /* operands[1]; * Alignment */
5154 xops[1] = operands[2]; /* Scratch */
5155 xops[2] = GEN_INT (0);
5156 xops[3] = GEN_INT (2);
5157 xops[4] = GEN_INT (3);
5158 xops[5] = GEN_INT (4);
5159 /* xops[6] = gen_label_rtx (); * label when aligned to 3-byte */
5160 /* xops[7] = gen_label_rtx (); * label when aligned to 2-byte */
5161 xops[8] = gen_label_rtx (); /* label of main loop */
5163 if (TARGET_USE_Q_REG && QI_REG_P (xops[1]))
5164 xops[9] = gen_label_rtx (); /* pentium optimisation */
5166 xops[10] = gen_label_rtx (); /* end label 2 */
5167 xops[11] = gen_label_rtx (); /* end label 1 */
5168 xops[12] = gen_label_rtx (); /* end label */
5169 /* xops[13] * Temporary used */
5170 xops[14] = GEN_INT (0xff);
5171 xops[15] = GEN_INT (0xff00);
5172 xops[16] = GEN_INT (0xff0000);
5173 xops[17] = GEN_INT (0xff000000);
5175 /* Loop to check 1..3 bytes for null to get an aligned pointer. */
5177 /* Is there a known alignment and is it less than 4? */
5178 if (GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) < 4)
5180 /* Is there a known alignment and is it not 2? */
5181 if (GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 2)
5183 xops[6] = gen_label_rtx (); /* Label when aligned to 3-byte */
5184 xops[7] = gen_label_rtx (); /* Label when aligned to 2-byte */
5186 /* Leave just the 3 lower bits.
5187 If this is a q-register, then the high part is used later
5188 therefore use andl rather than andb. */
5189 output_asm_insn (AS2 (and%L1,%4,%1), xops);
5191 /* Is aligned to 4-byte address when zero */
5192 output_asm_insn (AS1 (je,%l8), xops);
5194 /* Side-effect even Parity when %eax == 3 */
5195 output_asm_insn (AS1 (jp,%6), xops);
5197 /* Is it aligned to 2 bytes ? */
5198 if (QI_REG_P (xops[1]))
5199 output_asm_insn (AS2 (cmp%L1,%3,%1), xops);
5201 output_asm_insn (AS2 (cmp%L1,%3,%1), xops);
5203 output_asm_insn (AS1 (je,%7), xops);
5207 /* Since the alignment is 2, we have to check 2 or 0 bytes;
5208 check if is aligned to 4 - byte. */
5209 output_asm_insn (AS2 (and%L1,%3,%1), xops);
5211 /* Is aligned to 4-byte address when zero */
5212 output_asm_insn (AS1 (je,%l8), xops);
5215 xops[13] = gen_rtx_MEM (QImode, xops[0]);
5217 /* Now compare the bytes; compare with the high part of a q-reg
5218 gives shorter code. */
5219 if (QI_REG_P (xops[1]))
5221 /* Compare the first n unaligned byte on a byte per byte basis. */
5222 output_asm_insn (AS2 (cmp%B1,%h1,%13), xops);
5224 /* When zero we reached the end. */
5225 output_asm_insn (AS1 (je,%l12), xops);
5227 /* Increment the address. */
5228 output_asm_insn (AS1 (inc%L0,%0), xops);
5230 /* Not needed with an alignment of 2 */
5231 if (GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 2)
5233 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
5234 CODE_LABEL_NUMBER (xops[7]));
5235 output_asm_insn (AS2 (cmp%B1,%h1,%13), xops);
5236 output_asm_insn (AS1 (je,%l12), xops);
5237 output_asm_insn (AS1 (inc%L0,%0), xops);
5239 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
5240 CODE_LABEL_NUMBER (xops[6]));
5243 output_asm_insn (AS2 (cmp%B1,%h1,%13), xops);
5247 output_asm_insn (AS2 (cmp%B13,%2,%13), xops);
5248 output_asm_insn (AS1 (je,%l12), xops);
5249 output_asm_insn (AS1 (inc%L0,%0), xops);
5251 /* Not needed with an alignment of 2 */
5252 if (GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 2)
5254 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
5255 CODE_LABEL_NUMBER (xops[7]));
5256 output_asm_insn (AS2 (cmp%B13,%2,%13), xops);
5257 output_asm_insn (AS1 (je,%l12), xops);
5258 output_asm_insn (AS1 (inc%L0,%0), xops);
5260 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
5261 CODE_LABEL_NUMBER (xops[6]));
5264 output_asm_insn (AS2 (cmp%B13,%2,%13), xops);
5267 output_asm_insn (AS1 (je,%l12), xops);
5268 output_asm_insn (AS1 (inc%L0,%0), xops);
5271 /* Generate loop to check 4 bytes at a time. It is not a good idea to
5272 align this loop. It gives only huge programs, but does not help to
5274 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (xops[8]));
5276 xops[13] = gen_rtx_MEM (SImode, xops[0]);
5277 output_asm_insn (AS2 (mov%L1,%13,%1), xops);
5279 if (QI_REG_P (xops[1]))
5281 /* On i586 it is faster to combine the hi- and lo- part as
5282 a kind of lookahead. If anding both yields zero, then one
5283 of both *could* be zero, otherwise none of both is zero;
5284 this saves one instruction, on i486 this is slower
5285 tested with P-90, i486DX2-66, AMD486DX2-66 */
5288 output_asm_insn (AS2 (test%B1,%h1,%b1), xops);
5289 output_asm_insn (AS1 (jne,%l9), xops);
5292 /* Check first byte. */
5293 output_asm_insn (AS2 (test%B1,%b1,%b1), xops);
5294 output_asm_insn (AS1 (je,%l12), xops);
5296 /* Check second byte. */
5297 output_asm_insn (AS2 (test%B1,%h1,%h1), xops);
5298 output_asm_insn (AS1 (je,%l11), xops);
5301 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
5302 CODE_LABEL_NUMBER (xops[9]));
5307 /* Check first byte. */
5308 output_asm_insn (AS2 (test%L1,%14,%1), xops);
5309 output_asm_insn (AS1 (je,%l12), xops);
5311 /* Check second byte. */
5312 output_asm_insn (AS2 (test%L1,%15,%1), xops);
5313 output_asm_insn (AS1 (je,%l11), xops);
5316 /* Check third byte. */
5317 output_asm_insn (AS2 (test%L1,%16,%1), xops);
5318 output_asm_insn (AS1 (je,%l10), xops);
5320 /* Check fourth byte and increment address. */
5321 output_asm_insn (AS2 (add%L0,%5,%0), xops);
5322 output_asm_insn (AS2 (test%L1,%17,%1), xops);
5323 output_asm_insn (AS1 (jne,%l8), xops);
5325 /* Now generate fixups when the compare stops within a 4-byte word. */
5326 output_asm_insn (AS2 (sub%L0,%4,%0), xops);
5328 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (xops[10]));
5329 output_asm_insn (AS1 (inc%L0,%0), xops);
5331 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (xops[11]));
5332 output_asm_insn (AS1 (inc%L0,%0), xops);
5334 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (xops[12]));
5340 output_fp_conditional_move (which_alternative, operands)
5341 int which_alternative;
5344 enum rtx_code code = GET_CODE (operands[1]);
5346 /* This should never happen. */
5347 if (!(cc_prev_status.flags & CC_IN_80387)
5348 && (code == GT || code == LE || code == GE || code == LT))
5351 switch (which_alternative)
5354 /* r <- cond ? arg : r */
5355 output_asm_insn (AS2 (fcmov%F1,%2,%0), operands);
5359 /* r <- cond ? r : arg */
5360 output_asm_insn (AS2 (fcmov%f1,%3,%0), operands);
5371 output_int_conditional_move (which_alternative, operands)
5372 int which_alternative;
5375 enum rtx_code code = GET_CODE (operands[1]);
5377 /* This is very tricky. We have to do it right. For a code segement
5386 final_scan_insn () may delete the insn which sets CC. We have to
5387 tell final_scan_insn () if it should be reinserted. When CODE is
5388 GT or LE, we have to check the CC_NO_OVERFLOW bit and return
5389 NULL_PTR to tell final to reinsert the test insn because the
5390 conditional move cannot be handled properly without it. */
5391 if ((code == GT || code == LE)
5392 && (cc_prev_status.flags & CC_NO_OVERFLOW))
5395 switch (which_alternative)
5398 /* r <- cond ? arg : r */
5399 output_asm_insn (AS2 (cmov%C1,%2,%0), operands);
5403 /* r <- cond ? r : arg */
5404 output_asm_insn (AS2 (cmov%c1,%3,%0), operands);
5415 x86_adjust_cost (insn, link, dep_insn, cost)
5416 rtx insn, link, dep_insn;
5421 if (GET_CODE (dep_insn) == CALL_INSN || GET_CODE (insn) == JUMP_INSN)
5424 if (GET_CODE (dep_insn) == INSN
5425 && GET_CODE (PATTERN (dep_insn)) == SET
5426 && GET_CODE (SET_DEST (PATTERN (dep_insn))) == REG
5427 && GET_CODE (insn) == INSN
5428 && GET_CODE (PATTERN (insn)) == SET
5429 && !reg_overlap_mentioned_p (SET_DEST (PATTERN (dep_insn)),
5430 SET_SRC (PATTERN (insn))))
5436 case PROCESSOR_PENTIUM:
5437 if (cost != 0 && is_fp_insn (insn) && is_fp_insn (dep_insn)
5438 && !is_fp_dest (dep_insn))
5441 if (agi_dependent (insn, dep_insn))
5442 return cost ? cost + 1 : 2;
5444 if (GET_CODE (insn) == INSN
5445 && GET_CODE (PATTERN (insn)) == SET
5446 && SET_DEST (PATTERN (insn)) == cc0_rtx
5447 && (next_inst = next_nonnote_insn (insn))
5448 && GET_CODE (next_inst) == JUMP_INSN)
5449 /* compare probably paired with jump */
5452 /* Stores stalls one cycle longer than other insns. */
5453 if (is_fp_insn (insn) && cost && is_fp_store (dep_insn))
5458 if (!is_fp_dest (dep_insn))
5460 if(!agi_dependent (insn, dep_insn))
5466 if (is_fp_store (insn) && is_fp_insn (dep_insn)
5467 && NEXT_INSN (insn) && NEXT_INSN (NEXT_INSN (insn))
5468 && NEXT_INSN (NEXT_INSN (NEXT_INSN (insn)))
5469 && (GET_CODE (NEXT_INSN (insn)) == INSN)
5470 && (GET_CODE (NEXT_INSN (NEXT_INSN (insn))) == JUMP_INSN)
5471 && (GET_CODE (NEXT_INSN (NEXT_INSN (NEXT_INSN (insn)))) == NOTE)
5472 && (NOTE_LINE_NUMBER (NEXT_INSN (NEXT_INSN (NEXT_INSN (insn))))
5473 == NOTE_INSN_LOOP_END))
5481 /* Output assembly code for a left shift.
5483 Always use "sal" when shifting a memory operand or for a non constant
5486 When optimizing for size, we know that src == dest, and we should always
5487 use "sal". If src != dest, then copy src to dest and use "sal".
5489 Pentium and PPro (speed):
5491 When src == dest, use "add" for a shift counts of one, else use
5492 "sal". If we modeled Pentium AGI stalls and U/V pipelining better we
5493 would want to generate lea for some shifts on the Pentium.
5495 When src != dest, use "lea" for small shift counts. Otherwise,
5496 copy src to dest and use the normal shifting code. Exception for
5497 TARGET_DOUBLE_WITH_ADD. */
5500 output_ashl (insn, operands)
5501 rtx insn, *operands;
5503 /* Handle case where srcreg != dstreg. */
5504 if (REG_P (operands[0]) && REGNO (operands[0]) != REGNO (operands[1]))
5506 if (TARGET_DOUBLE_WITH_ADD && INTVAL (operands[2]) == 1)
5507 switch (GET_MODE (operands[0]))
5510 output_asm_insn (AS2 (mov%L0,%1,%0), operands);
5511 return AS2 (add%L0,%1,%0);
5513 output_asm_insn (AS2 (mov%L0,%k1,%k0), operands);
5514 if (i386_cc_probably_useless_p (insn))
5517 return AS2 (add%L0,%k1,%k0);
5519 return AS2 (add%W0,%k1,%k0);
5521 output_asm_insn (AS2 (mov%B0,%1,%0), operands);
5522 return AS2 (add%B0,%1,%0);
5530 /* This should be extremely rare (impossible?). We can not encode a
5531 shift of the stack pointer using an lea instruction. So copy the
5532 stack pointer into the destination register and use an lea. */
5533 if (operands[1] == stack_pointer_rtx)
5535 output_asm_insn (AS2 (mov%L0,%k1,%k0), operands);
5536 operands[1] = operands[0];
5539 /* For shifts up to and including 3 bits, use lea. */
5540 operands[1] = gen_rtx_MULT (SImode,
5541 gen_rtx_REG (SImode, REGNO (operands[1])),
5542 GEN_INT (1 << INTVAL (operands[2])));
5543 return AS2 (lea%L0,%a1,%k0);
5547 /* Source and destination match. */
5549 /* Handle variable shift. */
5550 if (REG_P (operands[2]))
5551 switch (GET_MODE (operands[0]))
5554 return AS2 (sal%L0,%b2,%0);
5556 if (REG_P (operands[0]) && i386_cc_probably_useless_p (insn))
5559 return AS2 (sal%L0,%b2,%k0);
5562 return AS2 (sal%W0,%b2,%0);
5564 return AS2 (sal%B0,%b2,%0);
5569 /* Always perform shift by 1 using an add instruction. */
5570 if (REG_P (operands[0]) && operands[2] == const1_rtx)
5571 switch (GET_MODE (operands[0]))
5574 return AS2 (add%L0,%0,%0);
5576 if (REG_P (operands[0]) && i386_cc_probably_useless_p (insn))
5579 return AS2 (add%L0,%k0,%k0);
5582 return AS2 (add%W0,%0,%0);
5584 return AS2 (add%B0,%0,%0);
5590 /* ??? Currently disabled. Because our model of Pentium is far from being
5591 exact, this change will need some benchmarking. */
5592 /* Shift reg by 2 or 3 use an lea instruction for Pentium if this is
5593 insn is expected to issue into the V pipe (the insn's mode will be
5594 TImode for a U pipe, and !TImode for a V pipe instruction). */
5596 && REG_P (operands[0])
5597 && GET_CODE (operands[2]) == CONST_INT
5598 && INTVAL (operands[2]) <= 3
5599 && (int)ix86_cpu == (int)PROCESSOR_PENTIUM
5600 && GET_MODE (insn) != TImode)
5603 operands[1] = gen_rtx_MULT (SImode, gen_rtx_REG (SImode, REGNO (operands[1])),
5604 GEN_INT (1 << INTVAL (operands[2])));
5605 return AS2 (lea%L0,%a1,%0);
5609 /* Otherwise use a shift instruction. */
5610 switch (GET_MODE (operands[0]))
5613 return AS2 (sal%L0,%2,%0);
5615 if (REG_P (operands[0]) && i386_cc_probably_useless_p (insn))
5618 return AS2 (sal%L0,%2,%k0);
5621 return AS2 (sal%W0,%2,%0);
5623 return AS2 (sal%B0,%2,%0);
5629 /* Given the memory address ADDR, calculate the length of the address or
5630 the length of just the displacement (controlled by DISP_LENGTH).
5632 The length returned does not include the one-byte modrm, opcode,
5636 memory_address_info (addr, disp_length)
5640 rtx base, index, disp, scale;
5644 if (GET_CODE (addr) == PRE_DEC
5645 || GET_CODE (addr) == POST_INC)
5648 /* Register Indirect. */
5649 if (register_operand (addr, Pmode))
5651 /* Special cases: ebp and esp need the two-byte modrm form.
5653 We change [ESI] to [ESI+0] on the K6 when not optimizing
5655 if (addr == stack_pointer_rtx
5656 || addr == arg_pointer_rtx
5657 || addr == frame_pointer_rtx
5658 || (REGNO_REG_CLASS (REGNO (addr)) == SIREG
5659 && ix86_cpu == PROCESSOR_K6 && !optimize_size))
5665 /* Direct Addressing. */
5666 if (CONSTANT_P (addr))
5669 index = base = disp = scale = NULL_RTX;
5670 op0 = XEXP (addr, 0);
5671 op1 = XEXP (addr, 1);
5673 if (GET_CODE (addr) == PLUS)
5675 if (register_operand (op0, Pmode))
5677 if (register_operand (op1, Pmode))
5678 index = op0, base = op1;
5680 base = op0, disp = op1;
5682 else if (GET_CODE (op0) == MULT)
5684 index = XEXP (op0, 0);
5685 scale = XEXP (op0, 1);
5686 if (register_operand (op1, Pmode))
5691 else if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 0)) == MULT)
5693 index = XEXP (XEXP (op0, 0), 0);
5694 scale = XEXP (XEXP (op0, 0), 1);
5695 base = XEXP (op0, 1);
5698 else if (GET_CODE (op0) == PLUS)
5700 index = XEXP (op0, 0);
5701 base = XEXP (op0, 1);
5707 else if (GET_CODE (addr) == MULT
5708 /* We're called for lea too, which implements ashift on occasion. */
5709 || GET_CODE (addr) == ASHIFT)
5711 index = XEXP (addr, 0);
5712 scale = XEXP (addr, 1);
5717 /* Allow arg pointer and stack pointer as index if there is not scaling */
5718 if (base && index && !scale
5719 && (index == stack_pointer_rtx
5720 || index == arg_pointer_rtx
5721 || index == frame_pointer_rtx))
5728 /* Special case: ebp cannot be encoded as a base without a displacement. */
5729 if (base == frame_pointer_rtx && !disp)
5732 /* Scaling can not be encoded without base or displacement.
5733 Except for scale == 1 where we can encode reg + reg instead of reg * 2. */
5735 && (!scale || GET_CODE (scale) != CONST_INT || (INTVAL (scale) != 1)))
5738 /* Find the length of the displacement constant. */
5742 if (GET_CODE (disp) == CONST_INT
5743 && CONST_OK_FOR_LETTER_P (INTVAL (disp), 'K'))
5749 /* An index requires the two-byte modrm form. Not important
5750 if we are computing just length of the displacement. */
5751 if (index && ! disp_length)