sys/dev/netif/ig_hal/e1000_82571.c

   1 /******************************************************************************
   2
   3   Copyright (c) 2001-2009, Intel Corporation
   4   All rights reserved.
   5
   6   Redistribution and use in source and binary forms, with or without
   7   modification, are permitted provided that the following conditions are met:
   8
   9    1. Redistributions of source code must retain the above copyright notice,
  10       this list of conditions and the following disclaimer.
  11
  12    2. Redistributions in binary form must reproduce the above copyright
  13       notice, this list of conditions and the following disclaimer in the
  14       documentation and/or other materials provided with the distribution.
  15
  16    3. Neither the name of the Intel Corporation nor the names of its
  17       contributors may be used to endorse or promote products derived from
  18       this software without specific prior written permission.
  19
  20   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30   POSSIBILITY OF SUCH DAMAGE.
  31
  32 ******************************************************************************/
  33 /*$FreeBSD: $*/
  34
  35 /*
  36  * 82571EB Gigabit Ethernet Controller
  37  * 82571EB Gigabit Ethernet Controller (Copper)
  38  * 82571EB Gigabit Ethernet Controller (Fiber)
  39  * 82571EB Dual Port Gigabit Mezzanine Adapter
  40  * 82571EB Quad Port Gigabit Mezzanine Adapter
  41  * 82571PT Gigabit PT Quad Port Server ExpressModule
  42  * 82572EI Gigabit Ethernet Controller (Copper)
  43  * 82572EI Gigabit Ethernet Controller (Fiber)
  44  * 82572EI Gigabit Ethernet Controller
  45  * 82573V Gigabit Ethernet Controller (Copper)
  46  * 82573E Gigabit Ethernet Controller (Copper)
  47  * 82573L Gigabit Ethernet Controller
  48  * 82574L Gigabit Network Connection
  49  * 82583V Gigabit Network Connection
  50  */
  51
  52 #include "e1000_api.h"
  53
  54 static s32  e1000_init_phy_params_82571(struct e1000_hw *hw);
  55 static s32  e1000_init_nvm_params_82571(struct e1000_hw *hw);
  56 static s32  e1000_init_mac_params_82571(struct e1000_hw *hw);
  57 static s32  e1000_acquire_nvm_82571(struct e1000_hw *hw);
  58 static void e1000_release_nvm_82571(struct e1000_hw *hw);
  59 static s32  e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset,
  60                                   u16 words, u16 *data);
  61 static s32  e1000_update_nvm_checksum_82571(struct e1000_hw *hw);
  62 static s32  e1000_validate_nvm_checksum_82571(struct e1000_hw *hw);
  63 static s32  e1000_get_cfg_done_82571(struct e1000_hw *hw);
  64 static s32  e1000_set_d0_lplu_state_82571(struct e1000_hw *hw,
  65                                           bool active);
  66 static s32  e1000_reset_hw_82571(struct e1000_hw *hw);
  67 static s32  e1000_init_hw_82571(struct e1000_hw *hw);
  68 static void e1000_clear_vfta_82571(struct e1000_hw *hw);
  69 static bool e1000_check_mng_mode_82574(struct e1000_hw *hw);
  70 static s32 e1000_led_on_82574(struct e1000_hw *hw);
  71 static s32  e1000_setup_link_82571(struct e1000_hw *hw);
  72 static s32  e1000_setup_copper_link_82571(struct e1000_hw *hw);
  73 static s32  e1000_check_for_serdes_link_82571(struct e1000_hw *hw);
  74 static s32  e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw);
  75 static s32  e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data);
  76 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw);
  77 static s32  e1000_get_hw_semaphore_82571(struct e1000_hw *hw);
  78 static s32  e1000_fix_nvm_checksum_82571(struct e1000_hw *hw);
  79 static s32  e1000_get_phy_id_82571(struct e1000_hw *hw);
  80 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw);
  81 static s32  e1000_get_hw_semaphore_82573(struct e1000_hw *hw);
  82 static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw);
  83 static s32  e1000_get_hw_semaphore_82574(struct e1000_hw *hw);
  84 static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw);
  85 static s32  e1000_set_d0_lplu_state_82574(struct e1000_hw *hw,
  86                                           bool active);
  87 static s32  e1000_set_d3_lplu_state_82574(struct e1000_hw *hw,
  88                                           bool active);
  89 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw);
  90 static s32  e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
  91                                        u16 words, u16 *data);
  92 static s32  e1000_read_mac_addr_82571(struct e1000_hw *hw);
  93 static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw);
  94
  95 /**
  96  *  e1000_init_phy_params_82571 - Init PHY func ptrs.
  97  *  @hw: pointer to the HW structure
  98  **/
  99 static s32 e1000_init_phy_params_82571(struct e1000_hw *hw)
 100 {
 101         struct e1000_phy_info *phy = &hw->phy;
 102         s32 ret_val = E1000_SUCCESS;
 103
 104         DEBUGFUNC("e1000_init_phy_params_82571");
 105
 106         if (hw->phy.media_type != e1000_media_type_copper) {
 107                 phy->type = e1000_phy_none;
 108                 goto out;
 109         }
 110
 111         phy->addr                        = 1;
 112         phy->autoneg_mask                = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 113         phy->reset_delay_us              = 100;
 114
 115         phy->ops.check_reset_block       = e1000_check_reset_block_generic;
 116         phy->ops.reset                   = e1000_phy_hw_reset_generic;
 117         phy->ops.set_d0_lplu_state       = e1000_set_d0_lplu_state_82571;
 118         phy->ops.set_d3_lplu_state       = e1000_set_d3_lplu_state_generic;
 119         phy->ops.power_up                = e1000_power_up_phy_copper;
 120         phy->ops.power_down              = e1000_power_down_phy_copper_82571;
 121
 122         switch (hw->mac.type) {
 123         case e1000_82571:
 124         case e1000_82572:
 125                 phy->type                   = e1000_phy_igp_2;
 126                 phy->ops.get_cfg_done       = e1000_get_cfg_done_82571;
 127                 phy->ops.get_info           = e1000_get_phy_info_igp;
 128                 phy->ops.check_polarity     = e1000_check_polarity_igp;
 129                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
 130                 phy->ops.get_cable_length   = e1000_get_cable_length_igp_2;
 131                 phy->ops.read_reg           = e1000_read_phy_reg_igp;
 132                 phy->ops.write_reg          = e1000_write_phy_reg_igp;
 133                 phy->ops.acquire            = e1000_get_hw_semaphore_82571;
 134                 phy->ops.release            = e1000_put_hw_semaphore_82571;
 135                 break;
 136         case e1000_82573:
 137                 phy->type                   = e1000_phy_m88;
 138                 phy->ops.get_cfg_done       = e1000_get_cfg_done_generic;
 139                 phy->ops.get_info           = e1000_get_phy_info_m88;
 140                 phy->ops.check_polarity     = e1000_check_polarity_m88;
 141                 phy->ops.commit             = e1000_phy_sw_reset_generic;
 142                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
 143                 phy->ops.get_cable_length   = e1000_get_cable_length_m88;
 144                 phy->ops.read_reg           = e1000_read_phy_reg_m88;
 145                 phy->ops.write_reg          = e1000_write_phy_reg_m88;
 146                 phy->ops.acquire            = e1000_get_hw_semaphore_82571;
 147                 phy->ops.release            = e1000_put_hw_semaphore_82571;
 148                 break;
 149         case e1000_82574:
 150         case e1000_82583:
 151                 phy->type                   = e1000_phy_bm;
 152                 phy->ops.get_cfg_done       = e1000_get_cfg_done_generic;
 153                 phy->ops.get_info           = e1000_get_phy_info_m88;
 154                 phy->ops.check_polarity     = e1000_check_polarity_m88;
 155                 phy->ops.commit             = e1000_phy_sw_reset_generic;
 156                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
 157                 phy->ops.get_cable_length   = e1000_get_cable_length_m88;
 158                 phy->ops.read_reg           = e1000_read_phy_reg_bm2;
 159                 phy->ops.write_reg          = e1000_write_phy_reg_bm2;
 160                 phy->ops.acquire            = e1000_get_hw_semaphore_82574;
 161                 phy->ops.release            = e1000_put_hw_semaphore_82574;
 162                 phy->ops.set_d0_lplu_state  = e1000_set_d0_lplu_state_82574;
 163                 phy->ops.set_d3_lplu_state  = e1000_set_d3_lplu_state_82574;
 164                 break;
 165         default:
 166                 ret_val = -E1000_ERR_PHY;
 167                 goto out;
 168                 break;
 169         }
 170
 171         /* This can only be done after all function pointers are setup. */
 172         ret_val = e1000_get_phy_id_82571(hw);
 173         if (ret_val) {
 174                 DEBUGOUT("Error getting PHY ID\n");
 175                 goto out;
 176         }
 177
 178         /* Verify phy id */
 179         switch (hw->mac.type) {
 180         case e1000_82571:
 181         case e1000_82572:
 182                 if (phy->id != IGP01E1000_I_PHY_ID)
 183                         ret_val = -E1000_ERR_PHY;
 184                 break;
 185         case e1000_82573:
 186                 if (phy->id != M88E1111_I_PHY_ID)
 187                         ret_val = -E1000_ERR_PHY;
 188                 break;
 189         case e1000_82574:
 190         case e1000_82583:
 191                 if (phy->id != BME1000_E_PHY_ID_R2)
 192                         ret_val = -E1000_ERR_PHY;
 193                 break;
 194         default:
 195                 ret_val = -E1000_ERR_PHY;
 196                 break;
 197         }
 198
 199         if (ret_val)
 200                 DEBUGOUT1("PHY ID unknown: type = 0x%08x\n", phy->id);
 201
 202 out:
 203         return ret_val;
 204 }
 205
 206 /**
 207  *  e1000_init_nvm_params_82571 - Init NVM func ptrs.
 208  *  @hw: pointer to the HW structure
 209  **/
 210 static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw)
 211 {
 212         struct e1000_nvm_info *nvm = &hw->nvm;
 213         u32 eecd = E1000_READ_REG(hw, E1000_EECD);
 214         u16 size;
 215
 216         DEBUGFUNC("e1000_init_nvm_params_82571");
 217
 218         nvm->opcode_bits = 8;
 219         nvm->delay_usec = 1;
 220         switch (nvm->override) {
 221         case e1000_nvm_override_spi_large:
 222                 nvm->page_size = 32;
 223                 nvm->address_bits = 16;
 224                 break;
 225         case e1000_nvm_override_spi_small:
 226                 nvm->page_size = 8;
 227                 nvm->address_bits = 8;
 228                 break;
 229         default:
 230                 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
 231                 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
 232                 break;
 233         }
 234
 235         switch (hw->mac.type) {
 236         case e1000_82573:
 237         case e1000_82574:
 238         case e1000_82583:
 239                 if (((eecd >> 15) & 0x3) == 0x3) {
 240                         nvm->type = e1000_nvm_flash_hw;
 241                         nvm->word_size = 2048;
 242                         /*
 243                          * Autonomous Flash update bit must be cleared due
 244                          * to Flash update issue.
 245                          */
 246                         eecd &= ~E1000_EECD_AUPDEN;
 247                         E1000_WRITE_REG(hw, E1000_EECD, eecd);
 248                         break;
 249                 }
 250                 /* Fall Through */
 251         default:
 252                 nvm->type = e1000_nvm_eeprom_spi;
 253                 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
 254                                   E1000_EECD_SIZE_EX_SHIFT);
 255                 /*
 256                  * Added to a constant, "size" becomes the left-shift value
 257                  * for setting word_size.
 258                  */
 259                 size += NVM_WORD_SIZE_BASE_SHIFT;
 260
 261                 /* EEPROM access above 16k is unsupported */
 262                 if (size > 14)
 263                         size = 14;
 264                 nvm->word_size  = 1 << size;
 265                 break;
 266         }
 267
 268         /* Function Pointers */
 269         switch (hw->mac.type) {
 270         case e1000_82574:
 271         case e1000_82583:
 272                 nvm->ops.acquire = e1000_get_hw_semaphore_82574;
 273                 nvm->ops.release = e1000_put_hw_semaphore_82574;
 274                 break;
 275         default:
 276                 nvm->ops.acquire = e1000_acquire_nvm_82571;
 277                 nvm->ops.release = e1000_release_nvm_82571;
 278                 break;
 279         }
 280         nvm->ops.read          = e1000_read_nvm_eerd;
 281         nvm->ops.update        = e1000_update_nvm_checksum_82571;
 282         nvm->ops.validate      = e1000_validate_nvm_checksum_82571;
 283         nvm->ops.valid_led_default = e1000_valid_led_default_82571;
 284         nvm->ops.write         = e1000_write_nvm_82571;
 285
 286         return E1000_SUCCESS;
 287 }
 288
 289 /**
 290  *  e1000_init_mac_params_82571 - Init MAC func ptrs.
 291  *  @hw: pointer to the HW structure
 292  **/
 293 static s32 e1000_init_mac_params_82571(struct e1000_hw *hw)
 294 {
 295         struct e1000_mac_info *mac = &hw->mac;
 296         u32 swsm = 0;
 297         u32 swsm2 = 0;
 298         bool force_clear_smbi = FALSE;
 299
 300         DEBUGFUNC("e1000_init_mac_params_82571");
 301
 302         /* Set media type and media-dependent function pointers */
 303         switch (hw->device_id) {
 304         case E1000_DEV_ID_82571EB_FIBER:
 305         case E1000_DEV_ID_82572EI_FIBER:
 306         case E1000_DEV_ID_82571EB_QUAD_FIBER:
 307                 hw->phy.media_type = e1000_media_type_fiber;
 308                 mac->ops.setup_physical_interface =
 309                         e1000_setup_fiber_serdes_link_82571;
 310                 mac->ops.check_for_link = e1000_check_for_fiber_link_generic;
 311                 mac->ops.get_link_up_info =
 312                         e1000_get_speed_and_duplex_fiber_serdes_generic;
 313                 break;
 314         case E1000_DEV_ID_82571EB_SERDES:
 315         case E1000_DEV_ID_82571EB_SERDES_DUAL:
 316         case E1000_DEV_ID_82571EB_SERDES_QUAD:
 317         case E1000_DEV_ID_82572EI_SERDES:
 318                 hw->phy.media_type = e1000_media_type_internal_serdes;
 319                 mac->ops.setup_physical_interface =
 320                         e1000_setup_fiber_serdes_link_82571;
 321                 mac->ops.check_for_link = e1000_check_for_serdes_link_82571;
 322                 mac->ops.get_link_up_info =
 323                         e1000_get_speed_and_duplex_fiber_serdes_generic;
 324                 break;
 325         default:
 326                 hw->phy.media_type = e1000_media_type_copper;
 327                 mac->ops.setup_physical_interface =
 328                         e1000_setup_copper_link_82571;
 329                 mac->ops.check_for_link = e1000_check_for_copper_link_generic;
 330                 mac->ops.get_link_up_info =
 331                         e1000_get_speed_and_duplex_copper_generic;
 332                 break;
 333         }
 334
 335         /* Set mta register count */
 336         mac->mta_reg_count = 128;
 337         /* Set rar entry count */
 338         mac->rar_entry_count = E1000_RAR_ENTRIES;
 339         /* Set if part includes ASF firmware */
 340         mac->asf_firmware_present = TRUE;
 341         /* Adaptive IFS supported */
 342         mac->adaptive_ifs = TRUE;
 343
 344         /* Function pointers */
 345
 346         /* bus type/speed/width */
 347         mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic;
 348         /* reset */
 349         mac->ops.reset_hw = e1000_reset_hw_82571;
 350         /* hw initialization */
 351         mac->ops.init_hw = e1000_init_hw_82571;
 352         /* link setup */
 353         mac->ops.setup_link = e1000_setup_link_82571;
 354         /* multicast address update */
 355         mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
 356         /* writing VFTA */
 357         mac->ops.write_vfta = e1000_write_vfta_generic;
 358         /* clearing VFTA */
 359         mac->ops.clear_vfta = e1000_clear_vfta_82571;
 360         /* read mac address */
 361         mac->ops.read_mac_addr = e1000_read_mac_addr_82571;
 362         /* ID LED init */
 363         mac->ops.id_led_init = e1000_id_led_init_generic;
 364         /* setup LED */
 365         mac->ops.setup_led = e1000_setup_led_generic;
 366         /* cleanup LED */
 367         mac->ops.cleanup_led = e1000_cleanup_led_generic;
 368         /* turn off LED */
 369         mac->ops.led_off = e1000_led_off_generic;
 370         /* clear hardware counters */
 371         mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82571;
 372
 373         /* MAC-specific function pointers */
 374         switch (hw->mac.type) {
 375         case e1000_82573:
 376                 mac->ops.set_lan_id = e1000_set_lan_id_single_port;
 377                 mac->ops.check_mng_mode = e1000_check_mng_mode_generic;
 378                 mac->ops.led_on = e1000_led_on_generic;
 379                 mac->ops.blink_led = e1000_blink_led_generic;
 380
 381                 /* FWSM register */
 382                 mac->has_fwsm = TRUE;
 383                 /*
 384                  * ARC supported; valid only if manageability features are
 385                  * enabled.
 386                  */
 387                 mac->arc_subsystem_valid =
 388                         (E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK)
 389                         ? TRUE : FALSE;
 390                 break;
 391         case e1000_82574:
 392         case e1000_82583:
 393                 mac->ops.set_lan_id = e1000_set_lan_id_single_port;
 394                 mac->ops.check_mng_mode = e1000_check_mng_mode_82574;
 395                 mac->ops.led_on = e1000_led_on_82574;
 396                 break;
 397         default:
 398                 mac->ops.check_mng_mode = e1000_check_mng_mode_generic;
 399                 mac->ops.led_on = e1000_led_on_generic;
 400                 mac->ops.blink_led = e1000_blink_led_generic;
 401
 402                 /* FWSM register */
 403                 mac->has_fwsm = TRUE;
 404                 break;
 405         }
 406
 407         /*
 408          * Ensure that the inter-port SWSM.SMBI lock bit is clear before
 409          * first NVM or PHY acess. This should be done for single-port
 410          * devices, and for one port only on dual-port devices so that
 411          * for those devices we can still use the SMBI lock to synchronize
 412          * inter-port accesses to the PHY & NVM.
 413          */
 414         switch (hw->mac.type) {
 415         case e1000_82571:
 416         case e1000_82572:
 417                 swsm2 = E1000_READ_REG(hw, E1000_SWSM2);
 418
 419                 if (!(swsm2 & E1000_SWSM2_LOCK)) {
 420                         /* Only do this for the first interface on this card */
 421                         E1000_WRITE_REG(hw, E1000_SWSM2,
 422                             swsm2 | E1000_SWSM2_LOCK);
 423                         force_clear_smbi = TRUE;
 424                 } else
 425                         force_clear_smbi = FALSE;
 426                 break;
 427         default:
 428                 force_clear_smbi = TRUE;
 429                 break;
 430         }
 431
 432         if (force_clear_smbi) {
 433                 /* Make sure SWSM.SMBI is clear */
 434                 swsm = E1000_READ_REG(hw, E1000_SWSM);
 435                 if (swsm & E1000_SWSM_SMBI) {
 436                         /* This bit should not be set on a first interface, and
 437                          * indicates that the bootagent or EFI code has
 438                          * improperly left this bit enabled
 439                          */
 440                         DEBUGOUT("Please update your 82571 Bootagent\n");
 441                 }
 442                 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_SMBI);
 443         }
 444
 445         /*
 446          * Initialze device specific counter of SMBI acquisition
 447          * timeouts.
 448          */
 449          hw->dev_spec._82571.smb_counter = 0;
 450
 451         return E1000_SUCCESS;
 452 }
 453
 454 /**
 455  *  e1000_init_function_pointers_82571 - Init func ptrs.
 456  *  @hw: pointer to the HW structure
 457  *
 458  *  Called to initialize all function pointers and parameters.
 459  **/
 460 void e1000_init_function_pointers_82571(struct e1000_hw *hw)
 461 {
 462         DEBUGFUNC("e1000_init_function_pointers_82571");
 463
 464         hw->mac.ops.init_params = e1000_init_mac_params_82571;
 465         hw->nvm.ops.init_params = e1000_init_nvm_params_82571;
 466         hw->phy.ops.init_params = e1000_init_phy_params_82571;
 467 }
 468
 469 /**
 470  *  e1000_get_phy_id_82571 - Retrieve the PHY ID and revision
 471  *  @hw: pointer to the HW structure
 472  *
 473  *  Reads the PHY registers and stores the PHY ID and possibly the PHY
 474  *  revision in the hardware structure.
 475  **/
 476 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw)
 477 {
 478         struct e1000_phy_info *phy = &hw->phy;
 479         s32 ret_val = E1000_SUCCESS;
 480         u16 phy_id = 0;
 481
 482         DEBUGFUNC("e1000_get_phy_id_82571");
 483
 484         switch (hw->mac.type) {
 485         case e1000_82571:
 486         case e1000_82572:
 487                 /*
 488                  * The 82571 firmware may still be configuring the PHY.
 489                  * In this case, we cannot access the PHY until the
 490                  * configuration is done.  So we explicitly set the
 491                  * PHY ID.
 492                  */
 493                 phy->id = IGP01E1000_I_PHY_ID;
 494                 break;
 495         case e1000_82573:
 496                 ret_val = e1000_get_phy_id(hw);
 497                 break;
 498         case e1000_82574:
 499         case e1000_82583:
 500                 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
 501                 if (ret_val)
 502                         goto out;
 503
 504                 phy->id = (u32)(phy_id << 16);
 505                 usec_delay(20);
 506                 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);
 507                 if (ret_val)
 508                         goto out;
 509
 510                 phy->id |= (u32)(phy_id);
 511                 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
 512                 break;
 513         default:
 514                 ret_val = -E1000_ERR_PHY;
 515                 break;
 516         }
 517 out:
 518         return ret_val;
 519 }
 520
 521 /**
 522  *  e1000_get_hw_semaphore_82571 - Acquire hardware semaphore
 523  *  @hw: pointer to the HW structure
 524  *
 525  *  Acquire the HW semaphore to access the PHY or NVM
 526  **/
 527 static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw)
 528 {
 529         u32 swsm;
 530         s32 ret_val = E1000_SUCCESS;
 531         s32 sw_timeout = hw->nvm.word_size + 1;
 532         s32 fw_timeout = hw->nvm.word_size + 1;
 533         s32 i = 0;
 534
 535         DEBUGFUNC("e1000_get_hw_semaphore_82571");
 536
 537         /*
 538          * If we have timedout 3 times on trying to acquire
 539          * the inter-port SMBI semaphore, there is old code
 540          * operating on the other port, and it is not
 541          * releasing SMBI. Modify the number of times that
 542          * we try for the semaphore to interwork with this
 543          * older code.
 544          */
 545         if (hw->dev_spec._82571.smb_counter > 2)
 546                 sw_timeout = 1;
 547
 548         /* Get the SW semaphore */
 549         while (i < sw_timeout) {
 550                 swsm = E1000_READ_REG(hw, E1000_SWSM);
 551                 if (!(swsm & E1000_SWSM_SMBI))
 552                         break;
 553
 554                 usec_delay(50);
 555                 i++;
 556         }
 557
 558         if (i == sw_timeout) {
 559                 DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
 560                 hw->dev_spec._82571.smb_counter++;
 561         }
 562         /* Get the FW semaphore. */
 563         for (i = 0; i < fw_timeout; i++) {
 564                 swsm = E1000_READ_REG(hw, E1000_SWSM);
 565                 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI);
 566
 567                 /* Semaphore acquired if bit latched */
 568                 if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI)
 569                         break;
 570
 571                 usec_delay(50);
 572         }
 573
 574         if (i == fw_timeout) {
 575                 /* Release semaphores */
 576                 e1000_put_hw_semaphore_82571(hw);
 577                 DEBUGOUT("Driver can't access the NVM\n");
 578                 ret_val = -E1000_ERR_NVM;
 579                 goto out;
 580         }
 581
 582 out:
 583         return ret_val;
 584 }
 585
 586 /**
 587  *  e1000_put_hw_semaphore_82571 - Release hardware semaphore
 588  *  @hw: pointer to the HW structure
 589  *
 590  *  Release hardware semaphore used to access the PHY or NVM
 591  **/
 592 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw)
 593 {
 594         u32 swsm;
 595
 596         DEBUGFUNC("e1000_put_hw_semaphore_generic");
 597
 598         swsm = E1000_READ_REG(hw, E1000_SWSM);
 599
 600         swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
 601
 602         E1000_WRITE_REG(hw, E1000_SWSM, swsm);
 603 }
 604
 605 /**
 606  *  e1000_get_hw_semaphore_82573 - Acquire hardware semaphore
 607  *  @hw: pointer to the HW structure
 608  *
 609  *  Acquire the HW semaphore during reset.
 610  *
 611  **/
 612 static s32 e1000_get_hw_semaphore_82573(struct e1000_hw *hw)
 613 {
 614         u32 extcnf_ctrl;
 615         s32 ret_val = E1000_SUCCESS;
 616         s32 i = 0;
 617
 618         DEBUGFUNC("e1000_get_hw_semaphore_82573");
 619
 620         extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
 621         extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
 622         do {
 623                 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
 624                 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
 625
 626                 if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
 627                         break;
 628
 629                 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
 630
 631                 msec_delay(2);
 632                 i++;
 633         } while (i < MDIO_OWNERSHIP_TIMEOUT);
 634
 635         if (i == MDIO_OWNERSHIP_TIMEOUT) {
 636                 /* Release semaphores */
 637                 e1000_put_hw_semaphore_82573(hw);
 638                 DEBUGOUT("Driver can't access the PHY\n");
 639                 ret_val = -E1000_ERR_PHY;
 640                 goto out;
 641         }
 642
 643 out:
 644         return ret_val;
 645 }
 646
 647 /**
 648  *  e1000_put_hw_semaphore_82573 - Release hardware semaphore
 649  *  @hw: pointer to the HW structure
 650  *
 651  *  Release hardware semaphore used during reset.
 652  *
 653  **/
 654 static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw)
 655 {
 656         u32 extcnf_ctrl;
 657
 658         DEBUGFUNC("e1000_put_hw_semaphore_82573");
 659
 660         extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
 661         extcnf_ctrl &= ~E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
 662         E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
 663 }
 664
 665 /**
 666  *  e1000_get_hw_semaphore_82574 - Acquire hardware semaphore
 667  *  @hw: pointer to the HW structure
 668  *
 669  *  Acquire the HW semaphore to access the PHY or NVM.
 670  *
 671  **/
 672 static s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw)
 673 {
 674         s32 ret_val;
 675
 676         DEBUGFUNC("e1000_get_hw_semaphore_82574");
 677
 678         ret_val = e1000_get_hw_semaphore_82573(hw);
 679         return ret_val;
 680 }
 681
 682 /**
 683  *  e1000_put_hw_semaphore_82574 - Release hardware semaphore
 684  *  @hw: pointer to the HW structure
 685  *
 686  *  Release hardware semaphore used to access the PHY or NVM
 687  *
 688  **/
 689 static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw)
 690 {
 691         DEBUGFUNC("e1000_put_hw_semaphore_82574");
 692
 693         e1000_put_hw_semaphore_82573(hw);
 694 }
 695
 696 /**
 697  *  e1000_set_d0_lplu_state_82574 - Set Low Power Linkup D0 state
 698  *  @hw: pointer to the HW structure
 699  *  @active: TRUE to enable LPLU, FALSE to disable
 700  *
 701  *  Sets the LPLU D0 state according to the active flag.
 702  *  LPLU will not be activated unless the
 703  *  device autonegotiation advertisement meets standards of
 704  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
 705  *  This is a function pointer entry point only called by
 706  *  PHY setup routines.
 707  **/
 708 static s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw, bool active)
 709 {
 710         u16 data = E1000_READ_REG(hw, E1000_POEMB);
 711
 712         DEBUGFUNC("e1000_set_d0_lplu_state_82574");
 713
 714         if (active)
 715                 data |= E1000_PHY_CTRL_D0A_LPLU;
 716         else
 717                 data &= ~E1000_PHY_CTRL_D0A_LPLU;
 718
 719         E1000_WRITE_REG(hw, E1000_POEMB, data);
 720         return E1000_SUCCESS;
 721 }
 722
 723 /**
 724  *  e1000_set_d3_lplu_state_82574 - Sets low power link up state for D3
 725  *  @hw: pointer to the HW structure
 726  *  @active: boolean used to enable/disable lplu
 727  *
 728  *  The low power link up (lplu) state is set to the power management level D3
 729  *  when active is TRUE, else clear lplu for D3. LPLU
 730  *  is used during Dx states where the power conservation is most important.
 731  *  During driver activity, SmartSpeed should be enabled so performance is
 732  *  maintained.
 733  **/
 734 static s32 e1000_set_d3_lplu_state_82574(struct e1000_hw *hw, bool active)
 735 {
 736         u16 data = E1000_READ_REG(hw, E1000_POEMB);
 737
 738         DEBUGFUNC("e1000_set_d3_lplu_state_82574");
 739
 740         if (!active) {
 741                 data &= ~E1000_PHY_CTRL_NOND0A_LPLU;
 742         } else if ((hw->phy.autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
 743                    (hw->phy.autoneg_advertised == E1000_ALL_NOT_GIG) ||
 744                    (hw->phy.autoneg_advertised == E1000_ALL_10_SPEED)) {
 745                 data |= E1000_PHY_CTRL_NOND0A_LPLU;
 746         }
 747
 748         E1000_WRITE_REG(hw, E1000_POEMB, data);
 749         return E1000_SUCCESS;
 750 }
 751
 752 /**
 753  *  e1000_acquire_nvm_82571 - Request for access to the EEPROM
 754  *  @hw: pointer to the HW structure
 755  *
 756  *  To gain access to the EEPROM, first we must obtain a hardware semaphore.
 757  *  Then for non-82573 hardware, set the EEPROM access request bit and wait
 758  *  for EEPROM access grant bit.  If the access grant bit is not set, release
 759  *  hardware semaphore.
 760  **/
 761 static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw)
 762 {
 763         s32 ret_val;
 764
 765         DEBUGFUNC("e1000_acquire_nvm_82571");
 766
 767         ret_val = e1000_get_hw_semaphore_82571(hw);
 768         if (ret_val)
 769                 goto out;
 770
 771         switch (hw->mac.type) {
 772         case e1000_82573:
 773                 break;
 774         default:
 775                 ret_val = e1000_acquire_nvm_generic(hw);
 776                 break;
 777         }
 778
 779         if (ret_val)
 780                 e1000_put_hw_semaphore_82571(hw);
 781
 782 out:
 783         return ret_val;
 784 }
 785
 786 /**
 787  *  e1000_release_nvm_82571 - Release exclusive access to EEPROM
 788  *  @hw: pointer to the HW structure
 789  *
 790  *  Stop any current commands to the EEPROM and clear the EEPROM request bit.
 791  **/
 792 static void e1000_release_nvm_82571(struct e1000_hw *hw)
 793 {
 794         DEBUGFUNC("e1000_release_nvm_82571");
 795
 796         e1000_release_nvm_generic(hw);
 797         e1000_put_hw_semaphore_82571(hw);
 798 }
 799
 800 /**
 801  *  e1000_write_nvm_82571 - Write to EEPROM using appropriate interface
 802  *  @hw: pointer to the HW structure
 803  *  @offset: offset within the EEPROM to be written to
 804  *  @words: number of words to write
 805  *  @data: 16 bit word(s) to be written to the EEPROM
 806  *
 807  *  For non-82573 silicon, write data to EEPROM at offset using SPI interface.
 808  *
 809  *  If e1000_update_nvm_checksum is not called after this function, the
 810  *  EEPROM will most likely contain an invalid checksum.
 811  **/
 812 static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words,
 813                                  u16 *data)
 814 {
 815         s32 ret_val = E1000_SUCCESS;
 816
 817         DEBUGFUNC("e1000_write_nvm_82571");
 818
 819         switch (hw->mac.type) {
 820         case e1000_82573:
 821         case e1000_82574:
 822         case e1000_82583:
 823                 ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data);
 824                 break;
 825         case e1000_82571:
 826         case e1000_82572:
 827                 ret_val = e1000_write_nvm_spi(hw, offset, words, data);
 828                 break;
 829         default:
 830                 ret_val = -E1000_ERR_NVM;
 831                 break;
 832         }
 833
 834         return ret_val;
 835 }
 836
 837 /**
 838  *  e1000_update_nvm_checksum_82571 - Update EEPROM checksum
 839  *  @hw: pointer to the HW structure
 840  *
 841  *  Updates the EEPROM checksum by reading/adding each word of the EEPROM
 842  *  up to the checksum.  Then calculates the EEPROM checksum and writes the
 843  *  value to the EEPROM.
 844  **/
 845 static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw)
 846 {
 847         u32 eecd;
 848         s32 ret_val;
 849         u16 i;
 850
 851         DEBUGFUNC("e1000_update_nvm_checksum_82571");
 852
 853         ret_val = e1000_update_nvm_checksum_generic(hw);
 854         if (ret_val)
 855                 goto out;
 856
 857         /*
 858          * If our nvm is an EEPROM, then we're done
 859          * otherwise, commit the checksum to the flash NVM.
 860          */
 861         if (hw->nvm.type != e1000_nvm_flash_hw)
 862                 goto out;
 863
 864         /* Check for pending operations. */
 865         for (i = 0; i < E1000_FLASH_UPDATES; i++) {
 866                 msec_delay(1);
 867                 if ((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD) == 0)
 868                         break;
 869         }
 870
 871         if (i == E1000_FLASH_UPDATES) {
 872                 ret_val = -E1000_ERR_NVM;
 873                 goto out;
 874         }
 875
 876         /* Reset the firmware if using STM opcode. */
 877         if ((E1000_READ_REG(hw, E1000_FLOP) & 0xFF00) == E1000_STM_OPCODE) {
 878                 /*
 879                  * The enabling of and the actual reset must be done
 880                  * in two write cycles.
 881                  */
 882                 E1000_WRITE_REG(hw, E1000_HICR, E1000_HICR_FW_RESET_ENABLE);
 883                 E1000_WRITE_FLUSH(hw);
 884                 E1000_WRITE_REG(hw, E1000_HICR, E1000_HICR_FW_RESET);
 885         }
 886
 887         /* Commit the write to flash */
 888         eecd = E1000_READ_REG(hw, E1000_EECD) | E1000_EECD_FLUPD;
 889         E1000_WRITE_REG(hw, E1000_EECD, eecd);
 890
 891         for (i = 0; i < E1000_FLASH_UPDATES; i++) {
 892                 msec_delay(1);
 893                 if ((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD) == 0)
 894                         break;
 895         }
 896
 897         if (i == E1000_FLASH_UPDATES) {
 898                 ret_val = -E1000_ERR_NVM;
 899                 goto out;
 900         }
 901
 902 out:
 903         return ret_val;
 904 }
 905
 906 /**
 907  *  e1000_validate_nvm_checksum_82571 - Validate EEPROM checksum
 908  *  @hw: pointer to the HW structure
 909  *
 910  *  Calculates the EEPROM checksum by reading/adding each word of the EEPROM
 911  *  and then verifies that the sum of the EEPROM is equal to 0xBABA.
 912  **/
 913 static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw)
 914 {
 915         DEBUGFUNC("e1000_validate_nvm_checksum_82571");
 916
 917         if (hw->nvm.type == e1000_nvm_flash_hw)
 918                 e1000_fix_nvm_checksum_82571(hw);
 919
 920         return e1000_validate_nvm_checksum_generic(hw);
 921 }
 922
 923 /**
 924  *  e1000_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon
 925  *  @hw: pointer to the HW structure
 926  *  @offset: offset within the EEPROM to be written to
 927  *  @words: number of words to write
 928  *  @data: 16 bit word(s) to be written to the EEPROM
 929  *
 930  *  After checking for invalid values, poll the EEPROM to ensure the previous
 931  *  command has completed before trying to write the next word.  After write
 932  *  poll for completion.
 933  *
 934  *  If e1000_update_nvm_checksum is not called after this function, the
 935  *  EEPROM will most likely contain an invalid checksum.
 936  **/
 937 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
 938                                       u16 words, u16 *data)
 939 {
 940         struct e1000_nvm_info *nvm = &hw->nvm;
 941         u32 i, eewr = 0;
 942         s32 ret_val = 0;
 943
 944         DEBUGFUNC("e1000_write_nvm_eewr_82571");
 945
 946         /*
 947          * A check for invalid values:  offset too large, too many words,
 948          * and not enough words.
 949          */
 950         if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
 951             (words == 0)) {
 952                 DEBUGOUT("nvm parameter(s) out of bounds\n");
 953                 ret_val = -E1000_ERR_NVM;
 954                 goto out;
 955         }
 956
 957         for (i = 0; i < words; i++) {
 958                 eewr = (data[i] << E1000_NVM_RW_REG_DATA) |
 959                        ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) |
 960                        E1000_NVM_RW_REG_START;
 961
 962                 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
 963                 if (ret_val)
 964                         break;
 965
 966                 E1000_WRITE_REG(hw, E1000_EEWR, eewr);
 967
 968                 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
 969                 if (ret_val)
 970                         break;
 971         }
 972
 973 out:
 974         return ret_val;
 975 }
 976
 977 /**
 978  *  e1000_get_cfg_done_82571 - Poll for configuration done
 979  *  @hw: pointer to the HW structure
 980  *
 981  *  Reads the management control register for the config done bit to be set.
 982  **/
 983 static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw)
 984 {
 985         s32 timeout = PHY_CFG_TIMEOUT;
 986         s32 ret_val = E1000_SUCCESS;
 987
 988         DEBUGFUNC("e1000_get_cfg_done_82571");
 989
 990         while (timeout) {
 991                 if (E1000_READ_REG(hw, E1000_EEMNGCTL) &
 992                     E1000_NVM_CFG_DONE_PORT_0)
 993                         break;
 994                 msec_delay(1);
 995                 timeout--;
 996         }
 997         if (!timeout) {
 998                 DEBUGOUT("MNG configuration cycle has not completed.\n");
 999                 ret_val = -E1000_ERR_RESET;
1000                 goto out;
1001         }
1002
1003 out:
1004         return ret_val;
1005 }
1006
1007 /**
1008  *  e1000_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state
1009  *  @hw: pointer to the HW structure
1010  *  @active: TRUE to enable LPLU, FALSE to disable
1011  *
1012  *  Sets the LPLU D0 state according to the active flag.  When activating LPLU
1013  *  this function also disables smart speed and vice versa.  LPLU will not be
1014  *  activated unless the device autonegotiation advertisement meets standards
1015  *  of either 10 or 10/100 or 10/100/1000 at all duplexes.  This is a function
1016  *  pointer entry point only called by PHY setup routines.
1017  **/
1018 static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active)
1019 {
1020         struct e1000_phy_info *phy = &hw->phy;
1021         s32 ret_val = E1000_SUCCESS;
1022         u16 data;
1023
1024         DEBUGFUNC("e1000_set_d0_lplu_state_82571");
1025
1026         if (!(phy->ops.read_reg))
1027                 goto out;
1028
1029         ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
1030         if (ret_val)
1031                 goto out;
1032
1033         if (active) {
1034                 data |= IGP02E1000_PM_D0_LPLU;
1035                 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
1036                                              data);
1037                 if (ret_val)
1038                         goto out;
1039
1040                 /* When LPLU is enabled, we should disable SmartSpeed */
1041                 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1042                                             &data);
1043                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1044                 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1045                                              data);
1046                 if (ret_val)
1047                         goto out;
1048         } else {
1049                 data &= ~IGP02E1000_PM_D0_LPLU;
1050                 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
1051                                              data);
1052                 /*
1053                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
1054                  * during Dx states where the power conservation is most
1055                  * important.  During driver activity we should enable
1056                  * SmartSpeed, so performance is maintained.
1057                  */
1058                 if (phy->smart_speed == e1000_smart_speed_on) {
1059                         ret_val = phy->ops.read_reg(hw,
1060                                                     IGP01E1000_PHY_PORT_CONFIG,
1061                                                     &data);
1062                         if (ret_val)
1063                                 goto out;
1064
1065                         data |= IGP01E1000_PSCFR_SMART_SPEED;
1066                         ret_val = phy->ops.write_reg(hw,
1067                                                      IGP01E1000_PHY_PORT_CONFIG,
1068                                                      data);
1069                         if (ret_val)
1070                                 goto out;
1071                 } else if (phy->smart_speed == e1000_smart_speed_off) {
1072                         ret_val = phy->ops.read_reg(hw,
1073                                                     IGP01E1000_PHY_PORT_CONFIG,
1074                                                     &data);
1075                         if (ret_val)
1076                                 goto out;
1077
1078                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1079                         ret_val = phy->ops.write_reg(hw,
1080                                                      IGP01E1000_PHY_PORT_CONFIG,
1081                                                      data);
1082                         if (ret_val)
1083                                 goto out;
1084                 }
1085         }
1086
1087 out:
1088         return ret_val;
1089 }
1090
1091 /**
1092  *  e1000_reset_hw_82571 - Reset hardware
1093  *  @hw: pointer to the HW structure
1094  *
1095  *  This resets the hardware into a known state.
1096  **/
1097 static s32 e1000_reset_hw_82571(struct e1000_hw *hw)
1098 {
1099         u32 ctrl, ctrl_ext;
1100         s32 ret_val;
1101
1102         DEBUGFUNC("e1000_reset_hw_82571");
1103
1104         /*
1105          * Prevent the PCI-E bus from sticking if there is no TLP connection
1106          * on the last TLP read/write transaction when MAC is reset.
1107          */
1108         ret_val = e1000_disable_pcie_master_generic(hw);
1109         if (ret_val)
1110                 DEBUGOUT("PCI-E Master disable polling has failed.\n");
1111
1112         DEBUGOUT("Masking off all interrupts\n");
1113         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1114
1115         E1000_WRITE_REG(hw, E1000_RCTL, 0);
1116         E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
1117         E1000_WRITE_FLUSH(hw);
1118
1119         msec_delay(10);
1120
1121         /*
1122          * Must acquire the MDIO ownership before MAC reset.
1123          * Ownership defaults to firmware after a reset.
1124          */
1125         switch (hw->mac.type) {
1126         case e1000_82573:
1127                 ret_val = e1000_get_hw_semaphore_82573(hw);
1128                 break;
1129         case e1000_82574:
1130         case e1000_82583:
1131                 ret_val = e1000_get_hw_semaphore_82574(hw);
1132                 break;
1133         default:
1134                 break;
1135         }
1136         if (ret_val)
1137                 DEBUGOUT("Cannot acquire MDIO ownership\n");
1138
1139         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1140
1141         DEBUGOUT("Issuing a global reset to MAC\n");
1142         E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
1143
1144         /* Must release MDIO ownership and mutex after MAC reset. */
1145         switch (hw->mac.type) {
1146         case e1000_82574:
1147         case e1000_82583:
1148                 e1000_put_hw_semaphore_82574(hw);
1149                 break;
1150         default:
1151                 break;
1152         }
1153
1154         if (hw->nvm.type == e1000_nvm_flash_hw) {
1155                 usec_delay(10);
1156                 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1157                 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
1158                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1159                 E1000_WRITE_FLUSH(hw);
1160         }
1161
1162         ret_val = e1000_get_auto_rd_done_generic(hw);
1163         if (ret_val)
1164                 /* We don't want to continue accessing MAC registers. */
1165                 goto out;
1166
1167         /*
1168          * Phy configuration from NVM just starts after EECD_AUTO_RD is set.
1169          * Need to wait for Phy configuration completion before accessing
1170          * NVM and Phy.
1171          */
1172
1173         switch (hw->mac.type) {
1174         case e1000_82573:
1175         case e1000_82574:
1176         case e1000_82583:
1177                 msec_delay(25);
1178                 break;
1179         default:
1180                 break;
1181         }
1182
1183         /* Clear any pending interrupt events. */
1184         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1185         E1000_READ_REG(hw, E1000_ICR);
1186
1187         if (hw->mac.type == e1000_82571) {
1188                 /* Install any alternate MAC address into RAR0 */
1189                 ret_val = e1000_check_alt_mac_addr_generic(hw);
1190                 if (ret_val)
1191                         goto out;
1192
1193                 e1000_set_laa_state_82571(hw, TRUE);
1194         }
1195
1196         /* Reinitialize the 82571 serdes link state machine */
1197         if (hw->phy.media_type == e1000_media_type_internal_serdes)
1198                 hw->mac.serdes_link_state = e1000_serdes_link_down;
1199
1200 out:
1201         return ret_val;
1202 }
1203
1204 /**
1205  *  e1000_init_hw_82571 - Initialize hardware
1206  *  @hw: pointer to the HW structure
1207  *
1208  *  This inits the hardware readying it for operation.
1209  **/
1210 static s32 e1000_init_hw_82571(struct e1000_hw *hw)
1211 {
1212         struct e1000_mac_info *mac = &hw->mac;
1213         u32 reg_data;
1214         s32 ret_val;
1215         u16 i, rar_count = mac->rar_entry_count;
1216
1217         DEBUGFUNC("e1000_init_hw_82571");
1218
1219         e1000_initialize_hw_bits_82571(hw);
1220
1221         /* Initialize identification LED */
1222         ret_val = mac->ops.id_led_init(hw);
1223         if (ret_val)
1224                 DEBUGOUT("Error initializing identification LED\n");
1225                 /* This is not fatal and we should not stop init due to this */
1226
1227         /* Disabling VLAN filtering */
1228         DEBUGOUT("Initializing the IEEE VLAN\n");
1229         mac->ops.clear_vfta(hw);
1230
1231         /* Setup the receive address. */
1232         /*
1233          * If, however, a locally administered address was assigned to the
1234          * 82571, we must reserve a RAR for it to work around an issue where
1235          * resetting one port will reload the MAC on the other port.
1236          */
1237         if (e1000_get_laa_state_82571(hw))
1238                 rar_count--;
1239         e1000_init_rx_addrs_generic(hw, rar_count);
1240
1241         /* Zero out the Multicast HASH table */
1242         DEBUGOUT("Zeroing the MTA\n");
1243         for (i = 0; i < mac->mta_reg_count; i++)
1244                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
1245
1246         /* Setup link and flow control */
1247         ret_val = mac->ops.setup_link(hw);
1248
1249         /* Set the transmit descriptor write-back policy */
1250         reg_data = E1000_READ_REG(hw, E1000_TXDCTL(0));
1251         reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
1252                    E1000_TXDCTL_FULL_TX_DESC_WB |
1253                    E1000_TXDCTL_COUNT_DESC;
1254         E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg_data);
1255
1256         /* ...for both queues. */
1257         switch (mac->type) {
1258         case e1000_82573:
1259                 e1000_enable_tx_pkt_filtering_generic(hw);
1260                 /* fall through */
1261         case e1000_82574:
1262         case e1000_82583:
1263                 reg_data = E1000_READ_REG(hw, E1000_GCR);
1264                 reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
1265                 E1000_WRITE_REG(hw, E1000_GCR, reg_data);
1266                 break;
1267         default:
1268                 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(1));
1269                 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
1270                            E1000_TXDCTL_FULL_TX_DESC_WB |
1271                            E1000_TXDCTL_COUNT_DESC;
1272                 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg_data);
1273                 break;
1274         }
1275
1276         /*
1277          * Clear all of the statistics registers (clear on read).  It is
1278          * important that we do this after we have tried to establish link
1279          * because the symbol error count will increment wildly if there
1280          * is no link.
1281          */
1282         e1000_clear_hw_cntrs_82571(hw);
1283
1284         return ret_val;
1285 }
1286
1287 /**
1288  *  e1000_initialize_hw_bits_82571 - Initialize hardware-dependent bits
1289  *  @hw: pointer to the HW structure
1290  *
1291  *  Initializes required hardware-dependent bits needed for normal operation.
1292  **/
1293 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw)
1294 {
1295         u32 reg;
1296
1297         DEBUGFUNC("e1000_initialize_hw_bits_82571");
1298
1299         /* Transmit Descriptor Control 0 */
1300         reg = E1000_READ_REG(hw, E1000_TXDCTL(0));
1301         reg |= (1 << 22);
1302         E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg);
1303
1304         /* Transmit Descriptor Control 1 */
1305         reg = E1000_READ_REG(hw, E1000_TXDCTL(1));
1306         reg |= (1 << 22);
1307         E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg);
1308
1309         /* Transmit Arbitration Control 0 */
1310         reg = E1000_READ_REG(hw, E1000_TARC(0));
1311         reg &= ~(0xF << 27); /* 30:27 */
1312         switch (hw->mac.type) {
1313         case e1000_82571:
1314         case e1000_82572:
1315                 reg |= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26);
1316                 break;
1317         default:
1318                 break;
1319         }
1320         E1000_WRITE_REG(hw, E1000_TARC(0), reg);
1321
1322         /* Transmit Arbitration Control 1 */
1323         reg = E1000_READ_REG(hw, E1000_TARC(1));
1324         switch (hw->mac.type) {
1325         case e1000_82571:
1326         case e1000_82572:
1327                 reg &= ~((1 << 29) | (1 << 30));
1328                 reg |= (1 << 22) | (1 << 24) | (1 << 25) | (1 << 26);
1329                 if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR)
1330                         reg &= ~(1 << 28);
1331                 else
1332                         reg |= (1 << 28);
1333                 E1000_WRITE_REG(hw, E1000_TARC(1), reg);
1334                 break;
1335         default:
1336                 break;
1337         }
1338
1339         /* Device Control */
1340         switch (hw->mac.type) {
1341         case e1000_82573:
1342         case e1000_82574:
1343         case e1000_82583:
1344                 reg = E1000_READ_REG(hw, E1000_CTRL);
1345                 reg &= ~(1 << 29);
1346                 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1347                 break;
1348         default:
1349                 break;
1350         }
1351
1352         /* Extended Device Control */
1353         switch (hw->mac.type) {
1354         case e1000_82573:
1355         case e1000_82574:
1356         case e1000_82583:
1357                 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1358                 reg &= ~(1 << 23);
1359                 reg |= (1 << 22);
1360                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1361                 break;
1362         default:
1363                 break;
1364         }
1365
1366         if (hw->mac.type == e1000_82571) {
1367                 reg = E1000_READ_REG(hw, E1000_PBA_ECC);
1368                 reg |= E1000_PBA_ECC_CORR_EN;
1369                 E1000_WRITE_REG(hw, E1000_PBA_ECC, reg);
1370         }
1371
1372         /*
1373          * Workaround for hardware errata.
1374          * Ensure that DMA Dynamic Clock gating is disabled on 82571 and 82572
1375          */
1376         if ((hw->mac.type == e1000_82571) ||
1377            (hw->mac.type == e1000_82572)) {
1378                 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1379                 reg &= ~E1000_CTRL_EXT_DMA_DYN_CLK_EN;
1380                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1381         }
1382
1383         /* PCI-Ex Control Registers */
1384         switch (hw->mac.type) {
1385         case e1000_82574:
1386         case e1000_82583:
1387                 reg = E1000_READ_REG(hw, E1000_GCR);
1388                 reg |= (1 << 22);
1389                 E1000_WRITE_REG(hw, E1000_GCR, reg);
1390
1391                 /*
1392                  * Workaround for hardware errata.
1393                  * apply workaround for hardware errata documented in errata
1394                  * docs Fixes issue where some error prone or unreliable PCIe
1395                  * completions are occurring, particularly with ASPM enabled.
1396                  * Without fix, issue can cause Tx timeouts.
1397                  */
1398                 reg = E1000_READ_REG(hw, E1000_GCR2);
1399                 reg |= 1;
1400                 E1000_WRITE_REG(hw, E1000_GCR2, reg);
1401                 break;
1402         default:
1403                 break;
1404         }
1405
1406         return;
1407 }
1408
1409 /**
1410  *  e1000_clear_vfta_82571 - Clear VLAN filter table
1411  *  @hw: pointer to the HW structure
1412  *
1413  *  Clears the register array which contains the VLAN filter table by
1414  *  setting all the values to 0.
1415  **/
1416 static void e1000_clear_vfta_82571(struct e1000_hw *hw)
1417 {
1418         u32 offset;
1419         u32 vfta_value = 0;
1420         u32 vfta_offset = 0;
1421         u32 vfta_bit_in_reg = 0;
1422
1423         DEBUGFUNC("e1000_clear_vfta_82571");
1424
1425         switch (hw->mac.type) {
1426         case e1000_82573:
1427         case e1000_82574:
1428         case e1000_82583:
1429                 if (hw->mng_cookie.vlan_id != 0) {
1430                         /*
1431                          * The VFTA is a 4096b bit-field, each identifying
1432                          * a single VLAN ID.  The following operations
1433                          * determine which 32b entry (i.e. offset) into the
1434                          * array we want to set the VLAN ID (i.e. bit) of
1435                          * the manageability unit.
1436                          */
1437                         vfta_offset = (hw->mng_cookie.vlan_id >>
1438                                 E1000_VFTA_ENTRY_SHIFT) & E1000_VFTA_ENTRY_MASK;
1439                         vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id &
1440                                 E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
1441                 }
1442                 break;
1443         default:
1444                 break;
1445         }
1446         for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
1447                 /*
1448                  * If the offset we want to clear is the same offset of the
1449                  * manageability VLAN ID, then clear all bits except that of
1450                  * the manageability unit.
1451                  */
1452                 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
1453                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, vfta_value);
1454                 E1000_WRITE_FLUSH(hw);
1455         }
1456 }
1457
1458 /**
1459  *  e1000_check_mng_mode_82574 - Check manageability is enabled
1460  *  @hw: pointer to the HW structure
1461  *
1462  *  Reads the NVM Initialization Control Word 2 and returns TRUE
1463  *  (>0) if any manageability is enabled, else FALSE (0).
1464  **/
1465 static bool e1000_check_mng_mode_82574(struct e1000_hw *hw)
1466 {
1467         u16 data;
1468
1469         DEBUGFUNC("e1000_check_mng_mode_82574");
1470
1471         hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &data);
1472         return (data & E1000_NVM_INIT_CTRL2_MNGM) != 0;
1473 }
1474
1475 /**
1476  *  e1000_led_on_82574 - Turn LED on
1477  *  @hw: pointer to the HW structure
1478  *
1479  *  Turn LED on.
1480  **/
1481 static s32 e1000_led_on_82574(struct e1000_hw *hw)
1482 {
1483         u32 ctrl;
1484         u32 i;
1485
1486         DEBUGFUNC("e1000_led_on_82574");
1487
1488         ctrl = hw->mac.ledctl_mode2;
1489         if (!(E1000_STATUS_LU & E1000_READ_REG(hw, E1000_STATUS))) {
1490                 /*
1491                  * If no link, then turn LED on by setting the invert bit
1492                  * for each LED that's "on" (0x0E) in ledctl_mode2.
1493                  */
1494                 for (i = 0; i < 4; i++)
1495                         if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
1496                             E1000_LEDCTL_MODE_LED_ON)
1497                                 ctrl |= (E1000_LEDCTL_LED0_IVRT << (i * 8));
1498         }
1499         E1000_WRITE_REG(hw, E1000_LEDCTL, ctrl);
1500
1501         return E1000_SUCCESS;
1502 }
1503
1504 /**
1505  *  e1000_check_phy_82574 - check 82574 phy hung state
1506  *  @hw: pointer to the HW structure
1507  *
1508  *  Returns whether phy is hung or not
1509  **/
1510 bool e1000_check_phy_82574(struct e1000_hw *hw)
1511 {
1512         u16 status_1kbt = 0;
1513         u16 receive_errors = 0;
1514         bool phy_hung = FALSE;
1515         s32 ret_val = E1000_SUCCESS;
1516
1517         DEBUGFUNC("e1000_check_phy_82574");
1518
1519         /*
1520          * Read PHY Receive Error counter first, if its is max - all F's then
1521          * read the Base1000T status register If both are max then PHY is hung.
1522          */
1523         ret_val = hw->phy.ops.read_reg(hw, E1000_RECEIVE_ERROR_COUNTER,
1524                                        &receive_errors);
1525         if (ret_val)
1526                 goto out;
1527         if (receive_errors == E1000_RECEIVE_ERROR_MAX) {
1528                 ret_val = hw->phy.ops.read_reg(hw, E1000_BASE1000T_STATUS,
1529                                                &status_1kbt);
1530                 if (ret_val)
1531                         goto out;
1532                 if ((status_1kbt & E1000_IDLE_ERROR_COUNT_MASK) ==
1533                     E1000_IDLE_ERROR_COUNT_MASK)
1534                         phy_hung = TRUE;
1535         }
1536 out:
1537         return phy_hung;
1538 }
1539
1540
1541 /**
1542  *  e1000_setup_link_82571 - Setup flow control and link settings
1543  *  @hw: pointer to the HW structure
1544  *
1545  *  Determines which flow control settings to use, then configures flow
1546  *  control.  Calls the appropriate media-specific link configuration
1547  *  function.  Assuming the adapter has a valid link partner, a valid link
1548  *  should be established.  Assumes the hardware has previously been reset
1549  *  and the transmitter and receiver are not enabled.
1550  **/
1551 static s32 e1000_setup_link_82571(struct e1000_hw *hw)
1552 {
1553         DEBUGFUNC("e1000_setup_link_82571");
1554
1555         /*
1556          * 82573 does not have a word in the NVM to determine
1557          * the default flow control setting, so we explicitly
1558          * set it to full.
1559          */
1560         switch (hw->mac.type) {
1561         case e1000_82573:
1562         case e1000_82574:
1563         case e1000_82583:
1564                 if (hw->fc.requested_mode == e1000_fc_default)
1565                         hw->fc.requested_mode = e1000_fc_full;
1566                 break;
1567         default:
1568                 break;
1569         }
1570
1571         return e1000_setup_link_generic(hw);
1572 }
1573
1574 /**
1575  *  e1000_setup_copper_link_82571 - Configure copper link settings
1576  *  @hw: pointer to the HW structure
1577  *
1578  *  Configures the link for auto-neg or forced speed and duplex.  Then we check
1579  *  for link, once link is established calls to configure collision distance
1580  *  and flow control are called.
1581  **/
1582 static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw)
1583 {
1584         u32 ctrl;
1585         s32 ret_val;
1586
1587         DEBUGFUNC("e1000_setup_copper_link_82571");
1588
1589         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1590         ctrl |= E1000_CTRL_SLU;
1591         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1592         E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1593
1594         switch (hw->phy.type) {
1595         case e1000_phy_m88:
1596         case e1000_phy_bm:
1597                 ret_val = e1000_copper_link_setup_m88(hw);
1598                 break;
1599         case e1000_phy_igp_2:
1600                 ret_val = e1000_copper_link_setup_igp(hw);
1601                 break;
1602         default:
1603                 ret_val = -E1000_ERR_PHY;
1604                 break;
1605         }
1606
1607         if (ret_val)
1608                 goto out;
1609
1610         ret_val = e1000_setup_copper_link_generic(hw);
1611
1612 out:
1613         return ret_val;
1614 }
1615
1616 /**
1617  *  e1000_setup_fiber_serdes_link_82571 - Setup link for fiber/serdes
1618  *  @hw: pointer to the HW structure
1619  *
1620  *  Configures collision distance and flow control for fiber and serdes links.
1621  *  Upon successful setup, poll for link.
1622  **/
1623 static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw)
1624 {
1625         DEBUGFUNC("e1000_setup_fiber_serdes_link_82571");
1626
1627         switch (hw->mac.type) {
1628         case e1000_82571:
1629         case e1000_82572:
1630                 /*
1631                  * If SerDes loopback mode is entered, there is no form
1632                  * of reset to take the adapter out of that mode.  So we
1633                  * have to explicitly take the adapter out of loopback
1634                  * mode.  This prevents drivers from twiddling their thumbs
1635                  * if another tool failed to take it out of loopback mode.
1636                  */
1637                 E1000_WRITE_REG(hw, E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1638                 break;
1639         default:
1640                 break;
1641         }
1642
1643         return e1000_setup_fiber_serdes_link_generic(hw);
1644 }
1645
1646 /**
1647  *  e1000_check_for_serdes_link_82571 - Check for link (Serdes)
1648  *  @hw: pointer to the HW structure
1649  *
1650  *  Reports the link state as up or down.
1651  *
1652  *  If autonegotiation is supported by the link partner, the link state is
1653  *  determined by the result of autonegotiation. This is the most likely case.
1654  *  If autonegotiation is not supported by the link partner, and the link
1655  *  has a valid signal, force the link up.
1656  *
1657  *  The link state is represented internally here by 4 states:
1658  *
1659  *  1) down
1660  *  2) autoneg_progress
1661  *  3) autoneg_complete (the link sucessfully autonegotiated)
1662  *  4) forced_up (the link has been forced up, it did not autonegotiate)
1663  *
1664  **/
1665 static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw)
1666 {
1667         struct e1000_mac_info *mac = &hw->mac;
1668         u32 rxcw;
1669         u32 ctrl;
1670         u32 status;
1671         u32 txcw;
1672         u32 i;
1673         s32 ret_val = E1000_SUCCESS;
1674
1675         DEBUGFUNC("e1000_check_for_serdes_link_82571");
1676
1677         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1678         status = E1000_READ_REG(hw, E1000_STATUS);
1679         rxcw = E1000_READ_REG(hw, E1000_RXCW);
1680
1681         if ((rxcw & E1000_RXCW_SYNCH) && !(rxcw & E1000_RXCW_IV)) {
1682
1683                 /* Receiver is synchronized with no invalid bits.  */
1684                 switch (mac->serdes_link_state) {
1685                 case e1000_serdes_link_autoneg_complete:
1686                         if (!(status & E1000_STATUS_LU)) {
1687                                 /*
1688                                  * We have lost link, retry autoneg before
1689                                  * reporting link failure
1690                                  */
1691                                 mac->serdes_link_state =
1692                                     e1000_serdes_link_autoneg_progress;
1693                                 mac->serdes_has_link = FALSE;
1694                                 DEBUGOUT("AN_UP     -> AN_PROG\n");
1695                         } else {
1696                                 mac->serdes_has_link = TRUE;
1697                         }
1698                         break;
1699
1700                 case e1000_serdes_link_forced_up:
1701                         /*
1702                          * If we are receiving /C/ ordered sets, re-enable
1703                          * auto-negotiation in the TXCW register and disable
1704                          * forced link in the Device Control register in an
1705                          * attempt to auto-negotiate with our link partner.
1706                          * If the partner code word is null, stop forcing
1707                          * and restart auto negotiation.
1708                          */
1709                         if ((rxcw & E1000_RXCW_C) || !(rxcw & E1000_RXCW_CW))  {
1710                                 /* Enable autoneg, and unforce link up */
1711                                 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
1712                                 E1000_WRITE_REG(hw, E1000_CTRL,
1713                                     (ctrl & ~E1000_CTRL_SLU));
1714                                 mac->serdes_link_state =
1715                                     e1000_serdes_link_autoneg_progress;
1716                                 mac->serdes_has_link = FALSE;
1717                                 DEBUGOUT("FORCED_UP -> AN_PROG\n");
1718                         } else {
1719                                 mac->serdes_has_link = TRUE;
1720                         }
1721                         break;
1722
1723                 case e1000_serdes_link_autoneg_progress:
1724                         if (rxcw & E1000_RXCW_C) {
1725                                 /*
1726                                  * We received /C/ ordered sets, meaning the
1727                                  * link partner has autonegotiated, and we can
1728                                  * trust the Link Up (LU) status bit.
1729                                  */
1730                                 if (status & E1000_STATUS_LU) {
1731                                         mac->serdes_link_state =
1732                                             e1000_serdes_link_autoneg_complete;
1733                                         DEBUGOUT("AN_PROG   -> AN_UP\n");
1734                                         mac->serdes_has_link = TRUE;
1735                                 } else {
1736                                         /* Autoneg completed, but failed. */
1737                                         mac->serdes_link_state =
1738                                             e1000_serdes_link_down;
1739                                         DEBUGOUT("AN_PROG   -> DOWN\n");
1740                                 }
1741                         } else {
1742                                 /*
1743                                  * The link partner did not autoneg.
1744                                  * Force link up and full duplex, and change
1745                                  * state to forced.
1746                                  */
1747                                 E1000_WRITE_REG(hw, E1000_TXCW,
1748                                 (mac->txcw & ~E1000_TXCW_ANE));
1749                                 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
1750                                 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1751
1752                                 /* Configure Flow Control after link up. */
1753                                 ret_val =
1754                                     e1000_config_fc_after_link_up_generic(hw);
1755                                 if (ret_val) {
1756                                         DEBUGOUT("Error config flow control\n");
1757                                         break;
1758                                 }
1759                                 mac->serdes_link_state =
1760                                 e1000_serdes_link_forced_up;
1761                                 mac->serdes_has_link = TRUE;
1762                                 DEBUGOUT("AN_PROG   -> FORCED_UP\n");
1763                         }
1764                         break;
1765
1766                 case e1000_serdes_link_down:
1767                 default:
1768                         /*
1769                          * The link was down but the receiver has now gained
1770                          * valid sync, so lets see if we can bring the link
1771                          * up.
1772                          */
1773                         E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
1774                         E1000_WRITE_REG(hw, E1000_CTRL,
1775                             (ctrl & ~E1000_CTRL_SLU));
1776                         mac->serdes_link_state =
1777                             e1000_serdes_link_autoneg_progress;
1778                         mac->serdes_has_link = FALSE;
1779                         DEBUGOUT("DOWN      -> AN_PROG\n");
1780                         break;
1781                 }
1782         } else {
1783                 if (!(rxcw & E1000_RXCW_SYNCH)) {
1784                         mac->serdes_has_link = FALSE;
1785                         mac->serdes_link_state = e1000_serdes_link_down;
1786                         DEBUGOUT("ANYSTATE  -> DOWN\n");
1787                 } else {
1788                         /*
1789                          * Check several times, if Sync and Config
1790                          * both are consistently 1 then simply ignore
1791                          * the Invalid bit and restart Autoneg
1792                          */
1793                         for (i = 0; i < AN_RETRY_COUNT; i++) {
1794                                 usec_delay(10);
1795                                 rxcw = E1000_READ_REG(hw, E1000_RXCW);
1796                                 if ((rxcw & E1000_RXCW_IV) &&
1797                                     !((rxcw & E1000_RXCW_SYNCH) &&
1798                                       (rxcw & E1000_RXCW_C))) {
1799                                         mac->serdes_has_link = FALSE;
1800                                         mac->serdes_link_state =
1801                                             e1000_serdes_link_down;
1802                                         DEBUGOUT("ANYSTATE  -> DOWN\n");
1803                                         break;
1804                                 }
1805                         }
1806
1807                         if (i == AN_RETRY_COUNT) {
1808                                 txcw = E1000_READ_REG(hw, E1000_TXCW);
1809                                 txcw |= E1000_TXCW_ANE;
1810                                 E1000_WRITE_REG(hw, E1000_TXCW, txcw);
1811                                 mac->serdes_link_state =
1812                                     e1000_serdes_link_autoneg_progress;
1813                                 mac->serdes_has_link = FALSE;
1814                                 DEBUGOUT("ANYSTATE  -> AN_PROG\n");
1815                         }
1816                 }
1817         }
1818
1819         return ret_val;
1820 }
1821
1822 /**
1823  *  e1000_valid_led_default_82571 - Verify a valid default LED config
1824  *  @hw: pointer to the HW structure
1825  *  @data: pointer to the NVM (EEPROM)
1826  *
1827  *  Read the EEPROM for the current default LED configuration.  If the
1828  *  LED configuration is not valid, set to a valid LED configuration.
1829  **/
1830 static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data)
1831 {
1832         s32 ret_val;
1833
1834         DEBUGFUNC("e1000_valid_led_default_82571");
1835
1836         ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1837         if (ret_val) {
1838                 DEBUGOUT("NVM Read Error\n");
1839                 goto out;
1840         }
1841
1842         switch (hw->mac.type) {
1843         case e1000_82573:
1844         case e1000_82574:
1845         case e1000_82583:
1846                 if (*data == ID_LED_RESERVED_F746)
1847                         *data = ID_LED_DEFAULT_82573;
1848                 break;
1849         default:
1850                 if (*data == ID_LED_RESERVED_0000 ||
1851                     *data == ID_LED_RESERVED_FFFF)
1852                         *data = ID_LED_DEFAULT;
1853                 break;
1854         }
1855
1856 out:
1857         return ret_val;
1858 }
1859
1860 /**
1861  *  e1000_get_laa_state_82571 - Get locally administered address state
1862  *  @hw: pointer to the HW structure
1863  *
1864  *  Retrieve and return the current locally administered address state.
1865  **/
1866 bool e1000_get_laa_state_82571(struct e1000_hw *hw)
1867 {
1868         DEBUGFUNC("e1000_get_laa_state_82571");
1869
1870         if (hw->mac.type != e1000_82571)
1871                 return FALSE;
1872
1873         return hw->dev_spec._82571.laa_is_present;
1874 }
1875
1876 /**
1877  *  e1000_set_laa_state_82571 - Set locally administered address state
1878  *  @hw: pointer to the HW structure
1879  *  @state: enable/disable locally administered address
1880  *
1881  *  Enable/Disable the current locally administered address state.
1882  **/
1883 void e1000_set_laa_state_82571(struct e1000_hw *hw, bool state)
1884 {
1885         DEBUGFUNC("e1000_set_laa_state_82571");
1886
1887         if (hw->mac.type != e1000_82571)
1888                 return;
1889
1890         hw->dev_spec._82571.laa_is_present = state;
1891
1892         /* If workaround is activated... */
1893         if (state)
1894                 /*
1895                  * Hold a copy of the LAA in RAR[14] This is done so that
1896                  * between the time RAR[0] gets clobbered and the time it
1897                  * gets fixed, the actual LAA is in one of the RARs and no
1898                  * incoming packets directed to this port are dropped.
1899                  * Eventually the LAA will be in RAR[0] and RAR[14].
1900                  */
1901                 e1000_rar_set_generic(hw, hw->mac.addr,
1902                                       hw->mac.rar_entry_count - 1);
1903         return;
1904 }
1905
1906 /**
1907  *  e1000_fix_nvm_checksum_82571 - Fix EEPROM checksum
1908  *  @hw: pointer to the HW structure
1909  *
1910  *  Verifies that the EEPROM has completed the update.  After updating the
1911  *  EEPROM, we need to check bit 15 in work 0x23 for the checksum fix.  If
1912  *  the checksum fix is not implemented, we need to set the bit and update
1913  *  the checksum.  Otherwise, if bit 15 is set and the checksum is incorrect,
1914  *  we need to return bad checksum.
1915  **/
1916 static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw)
1917 {
1918         struct e1000_nvm_info *nvm = &hw->nvm;
1919         s32 ret_val = E1000_SUCCESS;
1920         u16 data;
1921
1922         DEBUGFUNC("e1000_fix_nvm_checksum_82571");
1923
1924         if (nvm->type != e1000_nvm_flash_hw)
1925                 goto out;
1926
1927         /*
1928          * Check bit 4 of word 10h.  If it is 0, firmware is done updating
1929          * 10h-12h.  Checksum may need to be fixed.
1930          */
1931         ret_val = nvm->ops.read(hw, 0x10, 1, &data);
1932         if (ret_val)
1933                 goto out;
1934
1935         if (!(data & 0x10)) {
1936                 /*
1937                  * Read 0x23 and check bit 15.  This bit is a 1
1938                  * when the checksum has already been fixed.  If
1939                  * the checksum is still wrong and this bit is a
1940                  * 1, we need to return bad checksum.  Otherwise,
1941                  * we need to set this bit to a 1 and update the
1942                  * checksum.
1943                  */
1944                 ret_val = nvm->ops.read(hw, 0x23, 1, &data);
1945                 if (ret_val)
1946                         goto out;
1947
1948                 if (!(data & 0x8000)) {
1949                         data |= 0x8000;
1950                         ret_val = nvm->ops.write(hw, 0x23, 1, &data);
1951                         if (ret_val)
1952                                 goto out;
1953                         ret_val = nvm->ops.update(hw);
1954                 }
1955         }
1956
1957 out:
1958         return ret_val;
1959 }
1960
1961
1962 /**
1963  *  e1000_read_mac_addr_82571 - Read device MAC address
1964  *  @hw: pointer to the HW structure
1965  **/
1966 static s32 e1000_read_mac_addr_82571(struct e1000_hw *hw)
1967 {
1968         s32 ret_val = E1000_SUCCESS;
1969
1970         DEBUGFUNC("e1000_read_mac_addr_82571");
1971
1972         if (hw->mac.type == e1000_82571) {
1973                 /*
1974                  * If there's an alternate MAC address place it in RAR0
1975                  * so that it will override the Si installed default perm
1976                  * address.
1977                  */
1978                 ret_val = e1000_check_alt_mac_addr_generic(hw);
1979                 if (ret_val)
1980                         goto out;
1981         }
1982
1983         ret_val = e1000_read_mac_addr_generic(hw);
1984
1985 out:
1986         return ret_val;
1987 }
1988
1989 /**
1990  * e1000_power_down_phy_copper_82571 - Remove link during PHY power down
1991  * @hw: pointer to the HW structure
1992  *
1993  * In the case of a PHY power down to save power, or to turn off link during a
1994  * driver unload, or wake on lan is not enabled, remove the link.
1995  **/
1996 static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw)
1997 {
1998         struct e1000_phy_info *phy = &hw->phy;
1999         struct e1000_mac_info *mac = &hw->mac;
2000
2001         if (!(phy->ops.check_reset_block))
2002                 return;
2003
2004         /* If the management interface is not enabled, then power down */
2005         if (!(mac->ops.check_mng_mode(hw) || phy->ops.check_reset_block(hw)))
2006                 e1000_power_down_phy_copper(hw);
2007
2008         return;
2009 }
2010
2011 /**
2012  *  e1000_clear_hw_cntrs_82571 - Clear device specific hardware counters
2013  *  @hw: pointer to the HW structure
2014  *
2015  *  Clears the hardware counters by reading the counter registers.
2016  **/
2017 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw)
2018 {
2019         DEBUGFUNC("e1000_clear_hw_cntrs_82571");
2020
2021         e1000_clear_hw_cntrs_base_generic(hw);
2022
2023         E1000_READ_REG(hw, E1000_PRC64);
2024         E1000_READ_REG(hw, E1000_PRC127);
2025         E1000_READ_REG(hw, E1000_PRC255);
2026         E1000_READ_REG(hw, E1000_PRC511);
2027         E1000_READ_REG(hw, E1000_PRC1023);
2028         E1000_READ_REG(hw, E1000_PRC1522);
2029         E1000_READ_REG(hw, E1000_PTC64);
2030         E1000_READ_REG(hw, E1000_PTC127);
2031         E1000_READ_REG(hw, E1000_PTC255);
2032         E1000_READ_REG(hw, E1000_PTC511);
2033         E1000_READ_REG(hw, E1000_PTC1023);
2034         E1000_READ_REG(hw, E1000_PTC1522);
2035
2036         E1000_READ_REG(hw, E1000_ALGNERRC);
2037         E1000_READ_REG(hw, E1000_RXERRC);
2038         E1000_READ_REG(hw, E1000_TNCRS);
2039         E1000_READ_REG(hw, E1000_CEXTERR);
2040         E1000_READ_REG(hw, E1000_TSCTC);
2041         E1000_READ_REG(hw, E1000_TSCTFC);
2042
2043         E1000_READ_REG(hw, E1000_MGTPRC);
2044         E1000_READ_REG(hw, E1000_MGTPDC);
2045         E1000_READ_REG(hw, E1000_MGTPTC);
2046
2047         E1000_READ_REG(hw, E1000_IAC);
2048         E1000_READ_REG(hw, E1000_ICRXOC);
2049
2050         E1000_READ_REG(hw, E1000_ICRXPTC);
2051         E1000_READ_REG(hw, E1000_ICRXATC);
2052         E1000_READ_REG(hw, E1000_ICTXPTC);
2053         E1000_READ_REG(hw, E1000_ICTXATC);
2054         E1000_READ_REG(hw, E1000_ICTXQEC);
2055         E1000_READ_REG(hw, E1000_ICTXQMTC);
2056         E1000_READ_REG(hw, E1000_ICRXDMTC);
2057 }