1 /******************************************************************************
3 Copyright (c) 2001-2009, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
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13 notice, this list of conditions and the following disclaimer in the
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32 ******************************************************************************/
35 #include "e1000_api.h"
37 static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg);
38 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
39 u16 *data, bool read, bool page_set);
40 static u32 e1000_get_phy_addr_for_hv_page(u32 page);
41 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
42 u16 *data, bool read);
44 /* Cable length tables */
45 static const u16 e1000_m88_cable_length_table[] = {
46 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED };
47 #define M88E1000_CABLE_LENGTH_TABLE_SIZE \
48 (sizeof(e1000_m88_cable_length_table) / \
49 sizeof(e1000_m88_cable_length_table[0]))
51 static const u16 e1000_igp_2_cable_length_table[] = {
52 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3,
53 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22,
54 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 21, 26, 31, 35, 40,
55 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 40, 45, 51, 56, 61,
56 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 60, 66, 72, 77, 82,
57 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 83, 89, 95,
58 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121,
60 #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \
61 (sizeof(e1000_igp_2_cable_length_table) / \
62 sizeof(e1000_igp_2_cable_length_table[0]))
65 * e1000_init_phy_ops_generic - Initialize PHY function pointers
66 * @hw: pointer to the HW structure
68 * Setups up the function pointers to no-op functions
70 void e1000_init_phy_ops_generic(struct e1000_hw *hw)
72 struct e1000_phy_info *phy = &hw->phy;
73 DEBUGFUNC("e1000_init_phy_ops_generic");
75 /* Initialize function pointers */
76 phy->ops.init_params = e1000_null_ops_generic;
77 phy->ops.acquire = e1000_null_ops_generic;
78 phy->ops.check_polarity = e1000_null_ops_generic;
79 phy->ops.check_reset_block = e1000_null_ops_generic;
80 phy->ops.commit = e1000_null_ops_generic;
81 phy->ops.force_speed_duplex = e1000_null_ops_generic;
82 phy->ops.get_cfg_done = e1000_null_ops_generic;
83 phy->ops.get_cable_length = e1000_null_ops_generic;
84 phy->ops.get_info = e1000_null_ops_generic;
85 phy->ops.set_page = e1000_null_set_page;
86 phy->ops.read_reg = e1000_null_read_reg;
87 phy->ops.read_reg_locked = e1000_null_read_reg;
88 phy->ops.read_reg_page = e1000_null_read_reg;
89 phy->ops.release = e1000_null_phy_generic;
90 phy->ops.reset = e1000_null_ops_generic;
91 phy->ops.set_d0_lplu_state = e1000_null_lplu_state;
92 phy->ops.set_d3_lplu_state = e1000_null_lplu_state;
93 phy->ops.write_reg = e1000_null_write_reg;
94 phy->ops.write_reg_locked = e1000_null_write_reg;
95 phy->ops.write_reg_page = e1000_null_write_reg;
96 phy->ops.power_up = e1000_null_phy_generic;
97 phy->ops.power_down = e1000_null_phy_generic;
98 phy->ops.cfg_on_link_up = e1000_null_ops_generic;
102 * e1000_null_set_page - No-op function, return 0
103 * @hw: pointer to the HW structure
105 s32 e1000_null_set_page(struct e1000_hw *hw, u16 data)
107 DEBUGFUNC("e1000_null_set_page");
108 return E1000_SUCCESS;
112 * e1000_null_read_reg - No-op function, return 0
113 * @hw: pointer to the HW structure
115 s32 e1000_null_read_reg(struct e1000_hw *hw, u32 offset, u16 *data)
117 DEBUGFUNC("e1000_null_read_reg");
118 return E1000_SUCCESS;
122 * e1000_null_phy_generic - No-op function, return void
123 * @hw: pointer to the HW structure
125 void e1000_null_phy_generic(struct e1000_hw *hw)
127 DEBUGFUNC("e1000_null_phy_generic");
132 * e1000_null_lplu_state - No-op function, return 0
133 * @hw: pointer to the HW structure
135 s32 e1000_null_lplu_state(struct e1000_hw *hw, bool active)
137 DEBUGFUNC("e1000_null_lplu_state");
138 return E1000_SUCCESS;
142 * e1000_null_write_reg - No-op function, return 0
143 * @hw: pointer to the HW structure
145 s32 e1000_null_write_reg(struct e1000_hw *hw, u32 offset, u16 data)
147 DEBUGFUNC("e1000_null_write_reg");
148 return E1000_SUCCESS;
152 * e1000_check_reset_block_generic - Check if PHY reset is blocked
153 * @hw: pointer to the HW structure
155 * Read the PHY management control register and check whether a PHY reset
156 * is blocked. If a reset is not blocked return E1000_SUCCESS, otherwise
157 * return E1000_BLK_PHY_RESET (12).
159 s32 e1000_check_reset_block_generic(struct e1000_hw *hw)
163 DEBUGFUNC("e1000_check_reset_block");
165 manc = E1000_READ_REG(hw, E1000_MANC);
167 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
168 E1000_BLK_PHY_RESET : E1000_SUCCESS;
172 * e1000_get_phy_id - Retrieve the PHY ID and revision
173 * @hw: pointer to the HW structure
175 * Reads the PHY registers and stores the PHY ID and possibly the PHY
176 * revision in the hardware structure.
178 s32 e1000_get_phy_id(struct e1000_hw *hw)
180 struct e1000_phy_info *phy = &hw->phy;
181 s32 ret_val = E1000_SUCCESS;
185 DEBUGFUNC("e1000_get_phy_id");
187 if (!(phy->ops.read_reg))
190 while (retry_count < 2) {
191 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
195 phy->id = (u32)(phy_id << 16);
197 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);
201 phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
202 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
204 if (phy->id != 0 && phy->id != PHY_REVISION_MASK)
214 * e1000_phy_reset_dsp_generic - Reset PHY DSP
215 * @hw: pointer to the HW structure
217 * Reset the digital signal processor.
219 s32 e1000_phy_reset_dsp_generic(struct e1000_hw *hw)
221 s32 ret_val = E1000_SUCCESS;
223 DEBUGFUNC("e1000_phy_reset_dsp_generic");
225 if (!(hw->phy.ops.write_reg))
228 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);
232 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0);
239 * e1000_read_phy_reg_mdic - Read MDI control register
240 * @hw: pointer to the HW structure
241 * @offset: register offset to be read
242 * @data: pointer to the read data
244 * Reads the MDI control register in the PHY at offset and stores the
245 * information read to data.
247 s32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
249 struct e1000_phy_info *phy = &hw->phy;
251 s32 ret_val = E1000_SUCCESS;
253 DEBUGFUNC("e1000_read_phy_reg_mdic");
255 if (offset > MAX_PHY_REG_ADDRESS) {
256 DEBUGOUT1("PHY Address %d is out of range\n", offset);
257 return -E1000_ERR_PARAM;
261 * Set up Op-code, Phy Address, and register offset in the MDI
262 * Control register. The MAC will take care of interfacing with the
263 * PHY to retrieve the desired data.
265 mdic = ((offset << E1000_MDIC_REG_SHIFT) |
266 (phy->addr << E1000_MDIC_PHY_SHIFT) |
267 (E1000_MDIC_OP_READ));
269 E1000_WRITE_REG(hw, E1000_MDIC, mdic);
272 * Poll the ready bit to see if the MDI read completed
273 * Increasing the time out as testing showed failures with
276 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
278 mdic = E1000_READ_REG(hw, E1000_MDIC);
279 if (mdic & E1000_MDIC_READY)
282 if (!(mdic & E1000_MDIC_READY)) {
283 DEBUGOUT("MDI Read did not complete\n");
284 ret_val = -E1000_ERR_PHY;
287 if (mdic & E1000_MDIC_ERROR) {
288 DEBUGOUT("MDI Error\n");
289 ret_val = -E1000_ERR_PHY;
295 * Allow some time after each MDIC transaction to avoid
296 * reading duplicate data in the next MDIC transaction.
298 if (hw->mac.type == e1000_pch2lan)
306 * e1000_write_phy_reg_mdic - Write MDI control register
307 * @hw: pointer to the HW structure
308 * @offset: register offset to write to
309 * @data: data to write to register at offset
311 * Writes data to MDI control register in the PHY at offset.
313 s32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
315 struct e1000_phy_info *phy = &hw->phy;
317 s32 ret_val = E1000_SUCCESS;
319 DEBUGFUNC("e1000_write_phy_reg_mdic");
321 if (offset > MAX_PHY_REG_ADDRESS) {
322 DEBUGOUT1("PHY Address %d is out of range\n", offset);
323 return -E1000_ERR_PARAM;
327 * Set up Op-code, Phy Address, and register offset in the MDI
328 * Control register. The MAC will take care of interfacing with the
329 * PHY to retrieve the desired data.
331 mdic = (((u32)data) |
332 (offset << E1000_MDIC_REG_SHIFT) |
333 (phy->addr << E1000_MDIC_PHY_SHIFT) |
334 (E1000_MDIC_OP_WRITE));
336 E1000_WRITE_REG(hw, E1000_MDIC, mdic);
339 * Poll the ready bit to see if the MDI read completed
340 * Increasing the time out as testing showed failures with
343 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
345 mdic = E1000_READ_REG(hw, E1000_MDIC);
346 if (mdic & E1000_MDIC_READY)
349 if (!(mdic & E1000_MDIC_READY)) {
350 DEBUGOUT("MDI Write did not complete\n");
351 ret_val = -E1000_ERR_PHY;
354 if (mdic & E1000_MDIC_ERROR) {
355 DEBUGOUT("MDI Error\n");
356 ret_val = -E1000_ERR_PHY;
361 * Allow some time after each MDIC transaction to avoid
362 * reading duplicate data in the next MDIC transaction.
364 if (hw->mac.type == e1000_pch2lan)
372 * e1000_read_phy_reg_m88 - Read m88 PHY register
373 * @hw: pointer to the HW structure
374 * @offset: register offset to be read
375 * @data: pointer to the read data
377 * Acquires semaphore, if necessary, then reads the PHY register at offset
378 * and storing the retrieved information in data. Release any acquired
379 * semaphores before exiting.
381 s32 e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data)
383 s32 ret_val = E1000_SUCCESS;
385 DEBUGFUNC("e1000_read_phy_reg_m88");
387 if (!(hw->phy.ops.acquire))
390 ret_val = hw->phy.ops.acquire(hw);
394 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
397 hw->phy.ops.release(hw);
404 * e1000_write_phy_reg_m88 - Write m88 PHY register
405 * @hw: pointer to the HW structure
406 * @offset: register offset to write to
407 * @data: data to write at register offset
409 * Acquires semaphore, if necessary, then writes the data to PHY register
410 * at the offset. Release any acquired semaphores before exiting.
412 s32 e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data)
414 s32 ret_val = E1000_SUCCESS;
416 DEBUGFUNC("e1000_write_phy_reg_m88");
418 if (!(hw->phy.ops.acquire))
421 ret_val = hw->phy.ops.acquire(hw);
425 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
428 hw->phy.ops.release(hw);
435 * e1000_set_page_igp - Set page as on IGP-like PHY(s)
436 * @hw: pointer to the HW structure
437 * @page: page to set (shifted left when necessary)
439 * Sets PHY page required for PHY register access. Assumes semaphore is
440 * already acquired. Note, this function sets phy.addr to 1 so the caller
441 * must set it appropriately (if necessary) after this function returns.
443 s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page)
445 DEBUGFUNC("e1000_set_page_igp");
447 DEBUGOUT1("Setting page 0x%x\n", page);
451 return e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, page);
455 * __e1000_read_phy_reg_igp - Read igp PHY register
456 * @hw: pointer to the HW structure
457 * @offset: register offset to be read
458 * @data: pointer to the read data
459 * @locked: semaphore has already been acquired or not
461 * Acquires semaphore, if necessary, then reads the PHY register at offset
462 * and stores the retrieved information in data. Release any acquired
463 * semaphores before exiting.
465 static s32 __e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data,
468 s32 ret_val = E1000_SUCCESS;
470 DEBUGFUNC("__e1000_read_phy_reg_igp");
473 if (!(hw->phy.ops.acquire))
476 ret_val = hw->phy.ops.acquire(hw);
481 if (offset > MAX_PHY_MULTI_PAGE_REG) {
482 ret_val = e1000_write_phy_reg_mdic(hw,
483 IGP01E1000_PHY_PAGE_SELECT,
489 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
494 hw->phy.ops.release(hw);
500 * e1000_read_phy_reg_igp - Read igp PHY register
501 * @hw: pointer to the HW structure
502 * @offset: register offset to be read
503 * @data: pointer to the read data
505 * Acquires semaphore then reads the PHY register at offset and stores the
506 * retrieved information in data.
507 * Release the acquired semaphore before exiting.
509 s32 e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)
511 return __e1000_read_phy_reg_igp(hw, offset, data, FALSE);
515 * e1000_read_phy_reg_igp_locked - Read igp PHY register
516 * @hw: pointer to the HW structure
517 * @offset: register offset to be read
518 * @data: pointer to the read data
520 * Reads the PHY register at offset and stores the retrieved information
521 * in data. Assumes semaphore already acquired.
523 s32 e1000_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data)
525 return __e1000_read_phy_reg_igp(hw, offset, data, TRUE);
529 * e1000_write_phy_reg_igp - Write igp PHY register
530 * @hw: pointer to the HW structure
531 * @offset: register offset to write to
532 * @data: data to write at register offset
533 * @locked: semaphore has already been acquired or not
535 * Acquires semaphore, if necessary, then writes the data to PHY register
536 * at the offset. Release any acquired semaphores before exiting.
538 static s32 __e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data,
541 s32 ret_val = E1000_SUCCESS;
543 DEBUGFUNC("e1000_write_phy_reg_igp");
546 if (!(hw->phy.ops.acquire))
549 ret_val = hw->phy.ops.acquire(hw);
554 if (offset > MAX_PHY_MULTI_PAGE_REG) {
555 ret_val = e1000_write_phy_reg_mdic(hw,
556 IGP01E1000_PHY_PAGE_SELECT,
562 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
567 hw->phy.ops.release(hw);
574 * e1000_write_phy_reg_igp - Write igp PHY register
575 * @hw: pointer to the HW structure
576 * @offset: register offset to write to
577 * @data: data to write at register offset
579 * Acquires semaphore then writes the data to PHY register
580 * at the offset. Release any acquired semaphores before exiting.
582 s32 e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)
584 return __e1000_write_phy_reg_igp(hw, offset, data, FALSE);
588 * e1000_write_phy_reg_igp_locked - Write igp PHY register
589 * @hw: pointer to the HW structure
590 * @offset: register offset to write to
591 * @data: data to write at register offset
593 * Writes the data to PHY register at the offset.
594 * Assumes semaphore already acquired.
596 s32 e1000_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data)
598 return __e1000_write_phy_reg_igp(hw, offset, data, TRUE);
602 * __e1000_read_kmrn_reg - Read kumeran register
603 * @hw: pointer to the HW structure
604 * @offset: register offset to be read
605 * @data: pointer to the read data
606 * @locked: semaphore has already been acquired or not
608 * Acquires semaphore, if necessary. Then reads the PHY register at offset
609 * using the kumeran interface. The information retrieved is stored in data.
610 * Release any acquired semaphores before exiting.
612 static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data,
616 s32 ret_val = E1000_SUCCESS;
618 DEBUGFUNC("__e1000_read_kmrn_reg");
621 if (!(hw->phy.ops.acquire))
624 ret_val = hw->phy.ops.acquire(hw);
629 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
630 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
631 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
635 kmrnctrlsta = E1000_READ_REG(hw, E1000_KMRNCTRLSTA);
636 *data = (u16)kmrnctrlsta;
639 hw->phy.ops.release(hw);
646 * e1000_read_kmrn_reg_generic - Read kumeran register
647 * @hw: pointer to the HW structure
648 * @offset: register offset to be read
649 * @data: pointer to the read data
651 * Acquires semaphore then reads the PHY register at offset using the
652 * kumeran interface. The information retrieved is stored in data.
653 * Release the acquired semaphore before exiting.
655 s32 e1000_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data)
657 return __e1000_read_kmrn_reg(hw, offset, data, FALSE);
661 * e1000_read_kmrn_reg_locked - Read kumeran register
662 * @hw: pointer to the HW structure
663 * @offset: register offset to be read
664 * @data: pointer to the read data
666 * Reads the PHY register at offset using the kumeran interface. The
667 * information retrieved is stored in data.
668 * Assumes semaphore already acquired.
670 s32 e1000_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data)
672 return __e1000_read_kmrn_reg(hw, offset, data, TRUE);
676 * __e1000_write_kmrn_reg - Write kumeran register
677 * @hw: pointer to the HW structure
678 * @offset: register offset to write to
679 * @data: data to write at register offset
680 * @locked: semaphore has already been acquired or not
682 * Acquires semaphore, if necessary. Then write the data to PHY register
683 * at the offset using the kumeran interface. Release any acquired semaphores
686 static s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data,
690 s32 ret_val = E1000_SUCCESS;
692 DEBUGFUNC("e1000_write_kmrn_reg_generic");
695 if (!(hw->phy.ops.acquire))
698 ret_val = hw->phy.ops.acquire(hw);
703 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
704 E1000_KMRNCTRLSTA_OFFSET) | data;
705 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
710 hw->phy.ops.release(hw);
717 * e1000_write_kmrn_reg_generic - Write kumeran register
718 * @hw: pointer to the HW structure
719 * @offset: register offset to write to
720 * @data: data to write at register offset
722 * Acquires semaphore then writes the data to the PHY register at the offset
723 * using the kumeran interface. Release the acquired semaphore before exiting.
725 s32 e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data)
727 return __e1000_write_kmrn_reg(hw, offset, data, FALSE);
731 * e1000_write_kmrn_reg_locked - Write kumeran register
732 * @hw: pointer to the HW structure
733 * @offset: register offset to write to
734 * @data: data to write at register offset
736 * Write the data to PHY register at the offset using the kumeran interface.
737 * Assumes semaphore already acquired.
739 s32 e1000_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data)
741 return __e1000_write_kmrn_reg(hw, offset, data, TRUE);
745 * e1000_copper_link_setup_82577 - Setup 82577 PHY for copper link
746 * @hw: pointer to the HW structure
748 * Sets up Carrier-sense on Transmit and downshift values.
750 s32 e1000_copper_link_setup_82577(struct e1000_hw *hw)
755 DEBUGFUNC("e1000_copper_link_setup_82577");
757 if (hw->phy.reset_disable) {
758 ret_val = E1000_SUCCESS;
762 if (hw->phy.type == e1000_phy_82580) {
763 ret_val = hw->phy.ops.reset(hw);
765 DEBUGOUT("Error resetting the PHY.\n");
770 /* Enable CRS on Tx. This must be set for half-duplex operation. */
771 ret_val = hw->phy.ops.read_reg(hw, I82577_CFG_REG, &phy_data);
775 phy_data |= I82577_CFG_ASSERT_CRS_ON_TX;
777 /* Enable downshift */
778 phy_data |= I82577_CFG_ENABLE_DOWNSHIFT;
780 ret_val = hw->phy.ops.write_reg(hw, I82577_CFG_REG, phy_data);
787 * e1000_copper_link_setup_m88 - Setup m88 PHY's for copper link
788 * @hw: pointer to the HW structure
790 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock
791 * and downshift values are set also.
793 s32 e1000_copper_link_setup_m88(struct e1000_hw *hw)
795 struct e1000_phy_info *phy = &hw->phy;
799 DEBUGFUNC("e1000_copper_link_setup_m88");
801 if (phy->reset_disable) {
802 ret_val = E1000_SUCCESS;
806 /* Enable CRS on Tx. This must be set for half-duplex operation. */
807 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
811 /* For BM PHY this bit is downshift enable */
812 if (phy->type != e1000_phy_bm)
813 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
817 * MDI/MDI-X = 0 (default)
818 * 0 - Auto for all speeds
821 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
823 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
827 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
830 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
833 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
837 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
843 * disable_polarity_correction = 0 (default)
844 * Automatic Correction for Reversed Cable Polarity
848 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
849 if (phy->disable_polarity_correction == 1)
850 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
852 /* Enable downshift on BM (disabled by default) */
853 if (phy->type == e1000_phy_bm)
854 phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT;
856 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
860 if ((phy->type == e1000_phy_m88) &&
861 (phy->revision < E1000_REVISION_4) &&
862 (phy->id != BME1000_E_PHY_ID_R2)) {
864 * Force TX_CLK in the Extended PHY Specific Control Register
867 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
872 phy_data |= M88E1000_EPSCR_TX_CLK_25;
874 if ((phy->revision == E1000_REVISION_2) &&
875 (phy->id == M88E1111_I_PHY_ID)) {
876 /* 82573L PHY - set the downshift counter to 5x. */
877 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK;
878 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
880 /* Configure Master and Slave downshift values */
881 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
882 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
883 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
884 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
886 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
892 if ((phy->type == e1000_phy_bm) && (phy->id == BME1000_E_PHY_ID_R2)) {
893 /* Set PHY page 0, register 29 to 0x0003 */
894 ret_val = phy->ops.write_reg(hw, 29, 0x0003);
898 /* Set PHY page 0, register 30 to 0x0000 */
899 ret_val = phy->ops.write_reg(hw, 30, 0x0000);
904 /* Commit the changes. */
905 ret_val = phy->ops.commit(hw);
907 DEBUGOUT("Error committing the PHY changes\n");
911 if (phy->type == e1000_phy_82578) {
912 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
917 /* 82578 PHY - set the downshift count to 1x. */
918 phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE;
919 phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK;
920 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
931 * e1000_copper_link_setup_igp - Setup igp PHY's for copper link
932 * @hw: pointer to the HW structure
934 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
937 s32 e1000_copper_link_setup_igp(struct e1000_hw *hw)
939 struct e1000_phy_info *phy = &hw->phy;
943 DEBUGFUNC("e1000_copper_link_setup_igp");
945 if (phy->reset_disable) {
946 ret_val = E1000_SUCCESS;
950 ret_val = hw->phy.ops.reset(hw);
952 DEBUGOUT("Error resetting the PHY.\n");
957 * Wait 100ms for MAC to configure PHY from NVM settings, to avoid
958 * timeout issues when LFS is enabled.
963 * The NVM settings will configure LPLU in D3 for
966 if (phy->type == e1000_phy_igp) {
967 /* disable lplu d3 during driver init */
968 ret_val = hw->phy.ops.set_d3_lplu_state(hw, FALSE);
970 DEBUGOUT("Error Disabling LPLU D3\n");
975 /* disable lplu d0 during driver init */
976 if (hw->phy.ops.set_d0_lplu_state) {
977 ret_val = hw->phy.ops.set_d0_lplu_state(hw, FALSE);
979 DEBUGOUT("Error Disabling LPLU D0\n");
983 /* Configure mdi-mdix settings */
984 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data);
988 data &= ~IGP01E1000_PSCR_AUTO_MDIX;
992 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
995 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
999 data |= IGP01E1000_PSCR_AUTO_MDIX;
1002 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, data);
1006 /* set auto-master slave resolution settings */
1007 if (hw->mac.autoneg) {
1009 * when autonegotiation advertisement is only 1000Mbps then we
1010 * should disable SmartSpeed and enable Auto MasterSlave
1011 * resolution as hardware default.
1013 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
1014 /* Disable SmartSpeed */
1015 ret_val = phy->ops.read_reg(hw,
1016 IGP01E1000_PHY_PORT_CONFIG,
1021 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1022 ret_val = phy->ops.write_reg(hw,
1023 IGP01E1000_PHY_PORT_CONFIG,
1028 /* Set auto Master/Slave resolution process */
1029 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data);
1033 data &= ~CR_1000T_MS_ENABLE;
1034 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data);
1039 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data);
1043 /* load defaults for future use */
1044 phy->original_ms_type = (data & CR_1000T_MS_ENABLE) ?
1045 ((data & CR_1000T_MS_VALUE) ?
1046 e1000_ms_force_master :
1047 e1000_ms_force_slave) :
1050 switch (phy->ms_type) {
1051 case e1000_ms_force_master:
1052 data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
1054 case e1000_ms_force_slave:
1055 data |= CR_1000T_MS_ENABLE;
1056 data &= ~(CR_1000T_MS_VALUE);
1059 data &= ~CR_1000T_MS_ENABLE;
1063 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data);
1073 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link
1074 * @hw: pointer to the HW structure
1076 * Performs initial bounds checking on autoneg advertisement parameter, then
1077 * configure to advertise the full capability. Setup the PHY to autoneg
1078 * and restart the negotiation process between the link partner. If
1079 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting.
1081 s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
1083 struct e1000_phy_info *phy = &hw->phy;
1087 DEBUGFUNC("e1000_copper_link_autoneg");
1090 * Perform some bounds checking on the autoneg advertisement
1093 phy->autoneg_advertised &= phy->autoneg_mask;
1096 * If autoneg_advertised is zero, we assume it was not defaulted
1097 * by the calling code so we set to advertise full capability.
1099 if (phy->autoneg_advertised == 0)
1100 phy->autoneg_advertised = phy->autoneg_mask;
1102 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
1103 ret_val = e1000_phy_setup_autoneg(hw);
1105 DEBUGOUT("Error Setting up Auto-Negotiation\n");
1108 DEBUGOUT("Restarting Auto-Neg\n");
1111 * Restart auto-negotiation by setting the Auto Neg Enable bit and
1112 * the Auto Neg Restart bit in the PHY control register.
1114 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
1118 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
1119 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
1124 * Does the user want to wait for Auto-Neg to complete here, or
1125 * check at a later time (for example, callback routine).
1127 if (phy->autoneg_wait_to_complete) {
1128 ret_val = hw->mac.ops.wait_autoneg(hw);
1130 DEBUGOUT("Error while waiting for "
1131 "autoneg to complete\n");
1136 hw->mac.get_link_status = TRUE;
1143 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation
1144 * @hw: pointer to the HW structure
1146 * Reads the MII auto-neg advertisement register and/or the 1000T control
1147 * register and if the PHY is already setup for auto-negotiation, then
1148 * return successful. Otherwise, setup advertisement and flow control to
1149 * the appropriate values for the wanted auto-negotiation.
1151 s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
1153 struct e1000_phy_info *phy = &hw->phy;
1155 u16 mii_autoneg_adv_reg;
1156 u16 mii_1000t_ctrl_reg = 0;
1158 DEBUGFUNC("e1000_phy_setup_autoneg");
1160 phy->autoneg_advertised &= phy->autoneg_mask;
1162 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
1163 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
1167 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
1168 /* Read the MII 1000Base-T Control Register (Address 9). */
1169 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL,
1170 &mii_1000t_ctrl_reg);
1176 * Need to parse both autoneg_advertised and fc and set up
1177 * the appropriate PHY registers. First we will parse for
1178 * autoneg_advertised software override. Since we can advertise
1179 * a plethora of combinations, we need to check each bit
1184 * First we clear all the 10/100 mb speed bits in the Auto-Neg
1185 * Advertisement Register (Address 4) and the 1000 mb speed bits in
1186 * the 1000Base-T Control Register (Address 9).
1188 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS |
1189 NWAY_AR_100TX_HD_CAPS |
1190 NWAY_AR_10T_FD_CAPS |
1191 NWAY_AR_10T_HD_CAPS);
1192 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS);
1194 DEBUGOUT1("autoneg_advertised %x\n", phy->autoneg_advertised);
1196 /* Do we want to advertise 10 Mb Half Duplex? */
1197 if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
1198 DEBUGOUT("Advertise 10mb Half duplex\n");
1199 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
1202 /* Do we want to advertise 10 Mb Full Duplex? */
1203 if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
1204 DEBUGOUT("Advertise 10mb Full duplex\n");
1205 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
1208 /* Do we want to advertise 100 Mb Half Duplex? */
1209 if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
1210 DEBUGOUT("Advertise 100mb Half duplex\n");
1211 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
1214 /* Do we want to advertise 100 Mb Full Duplex? */
1215 if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
1216 DEBUGOUT("Advertise 100mb Full duplex\n");
1217 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
1220 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
1221 if (phy->autoneg_advertised & ADVERTISE_1000_HALF)
1222 DEBUGOUT("Advertise 1000mb Half duplex request denied!\n");
1224 /* Do we want to advertise 1000 Mb Full Duplex? */
1225 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
1226 DEBUGOUT("Advertise 1000mb Full duplex\n");
1227 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
1231 * Check for a software override of the flow control settings, and
1232 * setup the PHY advertisement registers accordingly. If
1233 * auto-negotiation is enabled, then software will have to set the
1234 * "PAUSE" bits to the correct value in the Auto-Negotiation
1235 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-
1238 * The possible values of the "fc" parameter are:
1239 * 0: Flow control is completely disabled
1240 * 1: Rx flow control is enabled (we can receive pause frames
1241 * but not send pause frames).
1242 * 2: Tx flow control is enabled (we can send pause frames
1243 * but we do not support receiving pause frames).
1244 * 3: Both Rx and Tx flow control (symmetric) are enabled.
1245 * other: No software override. The flow control configuration
1246 * in the EEPROM is used.
1248 switch (hw->fc.current_mode) {
1251 * Flow control (Rx & Tx) is completely disabled by a
1252 * software over-ride.
1254 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1256 case e1000_fc_rx_pause:
1258 * Rx Flow control is enabled, and Tx Flow control is
1259 * disabled, by a software over-ride.
1261 * Since there really isn't a way to advertise that we are
1262 * capable of Rx Pause ONLY, we will advertise that we
1263 * support both symmetric and asymmetric Rx PAUSE. Later
1264 * (in e1000_config_fc_after_link_up) we will disable the
1265 * hw's ability to send PAUSE frames.
1267 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1269 case e1000_fc_tx_pause:
1271 * Tx Flow control is enabled, and Rx Flow control is
1272 * disabled, by a software over-ride.
1274 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
1275 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
1279 * Flow control (both Rx and Tx) is enabled by a software
1282 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1285 DEBUGOUT("Flow control param set incorrectly\n");
1286 ret_val = -E1000_ERR_CONFIG;
1290 ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
1294 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1296 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
1297 ret_val = phy->ops.write_reg(hw,
1299 mii_1000t_ctrl_reg);
1309 * e1000_setup_copper_link_generic - Configure copper link settings
1310 * @hw: pointer to the HW structure
1312 * Calls the appropriate function to configure the link for auto-neg or forced
1313 * speed and duplex. Then we check for link, once link is established calls
1314 * to configure collision distance and flow control are called. If link is
1315 * not established, we return -E1000_ERR_PHY (-2).
1317 s32 e1000_setup_copper_link_generic(struct e1000_hw *hw)
1322 DEBUGFUNC("e1000_setup_copper_link_generic");
1324 if (hw->mac.autoneg) {
1326 * Setup autoneg and flow control advertisement and perform
1329 ret_val = e1000_copper_link_autoneg(hw);
1334 * PHY will be set to 10H, 10F, 100H or 100F
1335 * depending on user settings.
1337 DEBUGOUT("Forcing Speed and Duplex\n");
1338 ret_val = hw->phy.ops.force_speed_duplex(hw);
1340 DEBUGOUT("Error Forcing Speed and Duplex\n");
1346 * Check link status. Wait up to 100 microseconds for link to become
1349 ret_val = e1000_phy_has_link_generic(hw,
1350 COPPER_LINK_UP_LIMIT,
1357 DEBUGOUT("Valid link established!!!\n");
1358 e1000_config_collision_dist_generic(hw);
1359 ret_val = e1000_config_fc_after_link_up_generic(hw);
1361 DEBUGOUT("Unable to establish link!!!\n");
1369 * e1000_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
1370 * @hw: pointer to the HW structure
1372 * Calls the PHY setup function to force speed and duplex. Clears the
1373 * auto-crossover to force MDI manually. Waits for link and returns
1374 * successful if link up is successful, else -E1000_ERR_PHY (-2).
1376 s32 e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw)
1378 struct e1000_phy_info *phy = &hw->phy;
1383 DEBUGFUNC("e1000_phy_force_speed_duplex_igp");
1385 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1389 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
1391 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1396 * Clear Auto-Crossover to force MDI manually. IGP requires MDI
1397 * forced whenever speed and duplex are forced.
1399 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1403 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1404 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1406 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1410 DEBUGOUT1("IGP PSCR: %X\n", phy_data);
1414 if (phy->autoneg_wait_to_complete) {
1415 DEBUGOUT("Waiting for forced speed/duplex link on IGP phy.\n");
1417 ret_val = e1000_phy_has_link_generic(hw,
1425 DEBUGOUT("Link taking longer than expected.\n");
1428 ret_val = e1000_phy_has_link_generic(hw,
1441 * e1000_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
1442 * @hw: pointer to the HW structure
1444 * Calls the PHY setup function to force speed and duplex. Clears the
1445 * auto-crossover to force MDI manually. Resets the PHY to commit the
1446 * changes. If time expires while waiting for link up, we reset the DSP.
1447 * After reset, TX_CLK and CRS on Tx must be set. Return successful upon
1448 * successful completion, else return corresponding error code.
1450 s32 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw)
1452 struct e1000_phy_info *phy = &hw->phy;
1457 DEBUGFUNC("e1000_phy_force_speed_duplex_m88");
1460 * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
1461 * forced whenever speed and duplex are forced.
1463 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1467 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1468 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1472 DEBUGOUT1("M88E1000 PSCR: %X\n", phy_data);
1474 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1478 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
1480 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1484 /* Reset the phy to commit changes. */
1485 ret_val = hw->phy.ops.commit(hw);
1489 if (phy->autoneg_wait_to_complete) {
1490 DEBUGOUT("Waiting for forced speed/duplex link on M88 phy.\n");
1492 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1498 if (hw->phy.type != e1000_phy_m88) {
1499 DEBUGOUT("Link taking longer than expected.\n");
1502 * We didn't get link.
1503 * Reset the DSP and cross our fingers.
1505 ret_val = phy->ops.write_reg(hw,
1506 M88E1000_PHY_PAGE_SELECT,
1510 ret_val = e1000_phy_reset_dsp_generic(hw);
1517 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1523 if (hw->phy.type != e1000_phy_m88)
1526 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1531 * Resetting the phy means we need to re-force TX_CLK in the
1532 * Extended PHY Specific Control Register to 25MHz clock from
1533 * the reset value of 2.5MHz.
1535 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1536 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1541 * In addition, we must re-enable CRS on Tx for both half and full
1544 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1548 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1549 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1556 * e1000_phy_force_speed_duplex_ife - Force PHY speed & duplex
1557 * @hw: pointer to the HW structure
1559 * Forces the speed and duplex settings of the PHY.
1560 * This is a function pointer entry point only called by
1561 * PHY setup routines.
1563 s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw)
1565 struct e1000_phy_info *phy = &hw->phy;
1570 DEBUGFUNC("e1000_phy_force_speed_duplex_ife");
1572 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &data);
1576 e1000_phy_force_speed_duplex_setup(hw, &data);
1578 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, data);
1582 /* Disable MDI-X support for 10/100 */
1583 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data);
1587 data &= ~IFE_PMC_AUTO_MDIX;
1588 data &= ~IFE_PMC_FORCE_MDIX;
1590 ret_val = phy->ops.write_reg(hw, IFE_PHY_MDIX_CONTROL, data);
1594 DEBUGOUT1("IFE PMC: %X\n", data);
1598 if (phy->autoneg_wait_to_complete) {
1599 DEBUGOUT("Waiting for forced speed/duplex link on IFE phy.\n");
1601 ret_val = e1000_phy_has_link_generic(hw,
1609 DEBUGOUT("Link taking longer than expected.\n");
1612 ret_val = e1000_phy_has_link_generic(hw,
1625 * e1000_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
1626 * @hw: pointer to the HW structure
1627 * @phy_ctrl: pointer to current value of PHY_CONTROL
1629 * Forces speed and duplex on the PHY by doing the following: disable flow
1630 * control, force speed/duplex on the MAC, disable auto speed detection,
1631 * disable auto-negotiation, configure duplex, configure speed, configure
1632 * the collision distance, write configuration to CTRL register. The
1633 * caller must write to the PHY_CONTROL register for these settings to
1636 void e1000_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl)
1638 struct e1000_mac_info *mac = &hw->mac;
1641 DEBUGFUNC("e1000_phy_force_speed_duplex_setup");
1643 /* Turn off flow control when forcing speed/duplex */
1644 hw->fc.current_mode = e1000_fc_none;
1646 /* Force speed/duplex on the mac */
1647 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1648 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1649 ctrl &= ~E1000_CTRL_SPD_SEL;
1651 /* Disable Auto Speed Detection */
1652 ctrl &= ~E1000_CTRL_ASDE;
1654 /* Disable autoneg on the phy */
1655 *phy_ctrl &= ~MII_CR_AUTO_NEG_EN;
1657 /* Forcing Full or Half Duplex? */
1658 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) {
1659 ctrl &= ~E1000_CTRL_FD;
1660 *phy_ctrl &= ~MII_CR_FULL_DUPLEX;
1661 DEBUGOUT("Half Duplex\n");
1663 ctrl |= E1000_CTRL_FD;
1664 *phy_ctrl |= MII_CR_FULL_DUPLEX;
1665 DEBUGOUT("Full Duplex\n");
1668 /* Forcing 10mb or 100mb? */
1669 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) {
1670 ctrl |= E1000_CTRL_SPD_100;
1671 *phy_ctrl |= MII_CR_SPEED_100;
1672 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
1673 DEBUGOUT("Forcing 100mb\n");
1675 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1676 *phy_ctrl |= MII_CR_SPEED_10;
1677 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
1678 DEBUGOUT("Forcing 10mb\n");
1681 e1000_config_collision_dist_generic(hw);
1683 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1687 * e1000_set_d3_lplu_state_generic - Sets low power link up state for D3
1688 * @hw: pointer to the HW structure
1689 * @active: boolean used to enable/disable lplu
1691 * Success returns 0, Failure returns 1
1693 * The low power link up (lplu) state is set to the power management level D3
1694 * and SmartSpeed is disabled when active is TRUE, else clear lplu for D3
1695 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
1696 * is used during Dx states where the power conservation is most important.
1697 * During driver activity, SmartSpeed should be enabled so performance is
1700 s32 e1000_set_d3_lplu_state_generic(struct e1000_hw *hw, bool active)
1702 struct e1000_phy_info *phy = &hw->phy;
1703 s32 ret_val = E1000_SUCCESS;
1706 DEBUGFUNC("e1000_set_d3_lplu_state_generic");
1708 if (!(hw->phy.ops.read_reg))
1711 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
1716 data &= ~IGP02E1000_PM_D3_LPLU;
1717 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
1722 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
1723 * during Dx states where the power conservation is most
1724 * important. During driver activity we should enable
1725 * SmartSpeed, so performance is maintained.
1727 if (phy->smart_speed == e1000_smart_speed_on) {
1728 ret_val = phy->ops.read_reg(hw,
1729 IGP01E1000_PHY_PORT_CONFIG,
1734 data |= IGP01E1000_PSCFR_SMART_SPEED;
1735 ret_val = phy->ops.write_reg(hw,
1736 IGP01E1000_PHY_PORT_CONFIG,
1740 } else if (phy->smart_speed == e1000_smart_speed_off) {
1741 ret_val = phy->ops.read_reg(hw,
1742 IGP01E1000_PHY_PORT_CONFIG,
1747 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1748 ret_val = phy->ops.write_reg(hw,
1749 IGP01E1000_PHY_PORT_CONFIG,
1754 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1755 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1756 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1757 data |= IGP02E1000_PM_D3_LPLU;
1758 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
1763 /* When LPLU is enabled, we should disable SmartSpeed */
1764 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1769 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1770 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1779 * e1000_check_downshift_generic - Checks whether a downshift in speed occurred
1780 * @hw: pointer to the HW structure
1782 * Success returns 0, Failure returns 1
1784 * A downshift is detected by querying the PHY link health.
1786 s32 e1000_check_downshift_generic(struct e1000_hw *hw)
1788 struct e1000_phy_info *phy = &hw->phy;
1790 u16 phy_data, offset, mask;
1792 DEBUGFUNC("e1000_check_downshift_generic");
1794 switch (phy->type) {
1796 case e1000_phy_gg82563:
1798 case e1000_phy_82578:
1799 offset = M88E1000_PHY_SPEC_STATUS;
1800 mask = M88E1000_PSSR_DOWNSHIFT;
1803 case e1000_phy_igp_2:
1804 case e1000_phy_igp_3:
1805 offset = IGP01E1000_PHY_LINK_HEALTH;
1806 mask = IGP01E1000_PLHR_SS_DOWNGRADE;
1809 /* speed downshift not supported */
1810 phy->speed_downgraded = FALSE;
1811 ret_val = E1000_SUCCESS;
1815 ret_val = phy->ops.read_reg(hw, offset, &phy_data);
1818 phy->speed_downgraded = (phy_data & mask) ? TRUE : FALSE;
1825 * e1000_check_polarity_m88 - Checks the polarity.
1826 * @hw: pointer to the HW structure
1828 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1830 * Polarity is determined based on the PHY specific status register.
1832 s32 e1000_check_polarity_m88(struct e1000_hw *hw)
1834 struct e1000_phy_info *phy = &hw->phy;
1838 DEBUGFUNC("e1000_check_polarity_m88");
1840 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &data);
1843 phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY)
1844 ? e1000_rev_polarity_reversed
1845 : e1000_rev_polarity_normal;
1851 * e1000_check_polarity_igp - Checks the polarity.
1852 * @hw: pointer to the HW structure
1854 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1856 * Polarity is determined based on the PHY port status register, and the
1857 * current speed (since there is no polarity at 100Mbps).
1859 s32 e1000_check_polarity_igp(struct e1000_hw *hw)
1861 struct e1000_phy_info *phy = &hw->phy;
1863 u16 data, offset, mask;
1865 DEBUGFUNC("e1000_check_polarity_igp");
1868 * Polarity is determined based on the speed of
1871 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
1875 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
1876 IGP01E1000_PSSR_SPEED_1000MBPS) {
1877 offset = IGP01E1000_PHY_PCS_INIT_REG;
1878 mask = IGP01E1000_PHY_POLARITY_MASK;
1881 * This really only applies to 10Mbps since
1882 * there is no polarity for 100Mbps (always 0).
1884 offset = IGP01E1000_PHY_PORT_STATUS;
1885 mask = IGP01E1000_PSSR_POLARITY_REVERSED;
1888 ret_val = phy->ops.read_reg(hw, offset, &data);
1891 phy->cable_polarity = (data & mask)
1892 ? e1000_rev_polarity_reversed
1893 : e1000_rev_polarity_normal;
1900 * e1000_check_polarity_ife - Check cable polarity for IFE PHY
1901 * @hw: pointer to the HW structure
1903 * Polarity is determined on the polarity reversal feature being enabled.
1905 s32 e1000_check_polarity_ife(struct e1000_hw *hw)
1907 struct e1000_phy_info *phy = &hw->phy;
1909 u16 phy_data, offset, mask;
1911 DEBUGFUNC("e1000_check_polarity_ife");
1914 * Polarity is determined based on the reversal feature being enabled.
1916 if (phy->polarity_correction) {
1917 offset = IFE_PHY_EXTENDED_STATUS_CONTROL;
1918 mask = IFE_PESC_POLARITY_REVERSED;
1920 offset = IFE_PHY_SPECIAL_CONTROL;
1921 mask = IFE_PSC_FORCE_POLARITY;
1924 ret_val = phy->ops.read_reg(hw, offset, &phy_data);
1927 phy->cable_polarity = (phy_data & mask)
1928 ? e1000_rev_polarity_reversed
1929 : e1000_rev_polarity_normal;
1935 * e1000_wait_autoneg_generic - Wait for auto-neg completion
1936 * @hw: pointer to the HW structure
1938 * Waits for auto-negotiation to complete or for the auto-negotiation time
1939 * limit to expire, which ever happens first.
1941 s32 e1000_wait_autoneg_generic(struct e1000_hw *hw)
1943 s32 ret_val = E1000_SUCCESS;
1946 DEBUGFUNC("e1000_wait_autoneg_generic");
1948 if (!(hw->phy.ops.read_reg))
1949 return E1000_SUCCESS;
1951 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
1952 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {
1953 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
1956 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
1959 if (phy_status & MII_SR_AUTONEG_COMPLETE)
1965 * PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
1972 * e1000_phy_has_link_generic - Polls PHY for link
1973 * @hw: pointer to the HW structure
1974 * @iterations: number of times to poll for link
1975 * @usec_interval: delay between polling attempts
1976 * @success: pointer to whether polling was successful or not
1978 * Polls the PHY status register for link, 'iterations' number of times.
1980 s32 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
1981 u32 usec_interval, bool *success)
1983 s32 ret_val = E1000_SUCCESS;
1986 DEBUGFUNC("e1000_phy_has_link_generic");
1988 if (!(hw->phy.ops.read_reg))
1989 return E1000_SUCCESS;
1991 for (i = 0; i < iterations; i++) {
1993 * Some PHYs require the PHY_STATUS register to be read
1994 * twice due to the link bit being sticky. No harm doing
1995 * it across the board.
1997 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2000 * If the first read fails, another entity may have
2001 * ownership of the resources, wait and try again to
2002 * see if they have relinquished the resources yet.
2004 usec_delay(usec_interval);
2005 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2008 if (phy_status & MII_SR_LINK_STATUS)
2010 if (usec_interval >= 1000)
2011 msec_delay_irq(usec_interval/1000);
2013 usec_delay(usec_interval);
2016 *success = (i < iterations) ? TRUE : FALSE;
2022 * e1000_get_cable_length_m88 - Determine cable length for m88 PHY
2023 * @hw: pointer to the HW structure
2025 * Reads the PHY specific status register to retrieve the cable length
2026 * information. The cable length is determined by averaging the minimum and
2027 * maximum values to get the "average" cable length. The m88 PHY has four
2028 * possible cable length values, which are:
2029 * Register Value Cable Length
2033 * 3 110 - 140 meters
2036 s32 e1000_get_cable_length_m88(struct e1000_hw *hw)
2038 struct e1000_phy_info *phy = &hw->phy;
2040 u16 phy_data, index;
2042 DEBUGFUNC("e1000_get_cable_length_m88");
2044 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
2048 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
2049 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
2050 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) {
2051 ret_val = -E1000_ERR_PHY;
2055 phy->min_cable_length = e1000_m88_cable_length_table[index];
2056 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
2058 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
2065 * e1000_get_cable_length_igp_2 - Determine cable length for igp2 PHY
2066 * @hw: pointer to the HW structure
2068 * The automatic gain control (agc) normalizes the amplitude of the
2069 * received signal, adjusting for the attenuation produced by the
2070 * cable. By reading the AGC registers, which represent the
2071 * combination of coarse and fine gain value, the value can be put
2072 * into a lookup table to obtain the approximate cable length
2075 s32 e1000_get_cable_length_igp_2(struct e1000_hw *hw)
2077 struct e1000_phy_info *phy = &hw->phy;
2078 s32 ret_val = E1000_SUCCESS;
2079 u16 phy_data, i, agc_value = 0;
2080 u16 cur_agc_index, max_agc_index = 0;
2081 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1;
2082 static const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = {
2083 IGP02E1000_PHY_AGC_A,
2084 IGP02E1000_PHY_AGC_B,
2085 IGP02E1000_PHY_AGC_C,
2086 IGP02E1000_PHY_AGC_D
2089 DEBUGFUNC("e1000_get_cable_length_igp_2");
2091 /* Read the AGC registers for all channels */
2092 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
2093 ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &phy_data);
2098 * Getting bits 15:9, which represent the combination of
2099 * coarse and fine gain values. The result is a number
2100 * that can be put into the lookup table to obtain the
2101 * approximate cable length.
2103 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
2104 IGP02E1000_AGC_LENGTH_MASK;
2106 /* Array index bound check. */
2107 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) ||
2108 (cur_agc_index == 0)) {
2109 ret_val = -E1000_ERR_PHY;
2113 /* Remove min & max AGC values from calculation. */
2114 if (e1000_igp_2_cable_length_table[min_agc_index] >
2115 e1000_igp_2_cable_length_table[cur_agc_index])
2116 min_agc_index = cur_agc_index;
2117 if (e1000_igp_2_cable_length_table[max_agc_index] <
2118 e1000_igp_2_cable_length_table[cur_agc_index])
2119 max_agc_index = cur_agc_index;
2121 agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
2124 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
2125 e1000_igp_2_cable_length_table[max_agc_index]);
2126 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
2128 /* Calculate cable length with the error range of +/- 10 meters. */
2129 phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
2130 (agc_value - IGP02E1000_AGC_RANGE) : 0;
2131 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE;
2133 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
2140 * e1000_get_phy_info_m88 - Retrieve PHY information
2141 * @hw: pointer to the HW structure
2143 * Valid for only copper links. Read the PHY status register (sticky read)
2144 * to verify that link is up. Read the PHY special control register to
2145 * determine the polarity and 10base-T extended distance. Read the PHY
2146 * special status register to determine MDI/MDIx and current speed. If
2147 * speed is 1000, then determine cable length, local and remote receiver.
2149 s32 e1000_get_phy_info_m88(struct e1000_hw *hw)
2151 struct e1000_phy_info *phy = &hw->phy;
2156 DEBUGFUNC("e1000_get_phy_info_m88");
2158 if (phy->media_type != e1000_media_type_copper) {
2159 DEBUGOUT("Phy info is only valid for copper media\n");
2160 ret_val = -E1000_ERR_CONFIG;
2164 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2169 DEBUGOUT("Phy info is only valid if link is up\n");
2170 ret_val = -E1000_ERR_CONFIG;
2174 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2178 phy->polarity_correction = (phy_data & M88E1000_PSCR_POLARITY_REVERSAL)
2181 ret_val = e1000_check_polarity_m88(hw);
2185 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
2189 phy->is_mdix = (phy_data & M88E1000_PSSR_MDIX) ? TRUE : FALSE;
2191 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
2192 ret_val = hw->phy.ops.get_cable_length(hw);
2196 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data);
2200 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS)
2201 ? e1000_1000t_rx_status_ok
2202 : e1000_1000t_rx_status_not_ok;
2204 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS)
2205 ? e1000_1000t_rx_status_ok
2206 : e1000_1000t_rx_status_not_ok;
2208 /* Set values to "undefined" */
2209 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2210 phy->local_rx = e1000_1000t_rx_status_undefined;
2211 phy->remote_rx = e1000_1000t_rx_status_undefined;
2219 * e1000_get_phy_info_igp - Retrieve igp PHY information
2220 * @hw: pointer to the HW structure
2222 * Read PHY status to determine if link is up. If link is up, then
2223 * set/determine 10base-T extended distance and polarity correction. Read
2224 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
2225 * determine on the cable length, local and remote receiver.
2227 s32 e1000_get_phy_info_igp(struct e1000_hw *hw)
2229 struct e1000_phy_info *phy = &hw->phy;
2234 DEBUGFUNC("e1000_get_phy_info_igp");
2236 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2241 DEBUGOUT("Phy info is only valid if link is up\n");
2242 ret_val = -E1000_ERR_CONFIG;
2246 phy->polarity_correction = TRUE;
2248 ret_val = e1000_check_polarity_igp(hw);
2252 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
2256 phy->is_mdix = (data & IGP01E1000_PSSR_MDIX) ? TRUE : FALSE;
2258 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
2259 IGP01E1000_PSSR_SPEED_1000MBPS) {
2260 ret_val = phy->ops.get_cable_length(hw);
2264 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
2268 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
2269 ? e1000_1000t_rx_status_ok
2270 : e1000_1000t_rx_status_not_ok;
2272 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
2273 ? e1000_1000t_rx_status_ok
2274 : e1000_1000t_rx_status_not_ok;
2276 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2277 phy->local_rx = e1000_1000t_rx_status_undefined;
2278 phy->remote_rx = e1000_1000t_rx_status_undefined;
2286 * e1000_get_phy_info_ife - Retrieves various IFE PHY states
2287 * @hw: pointer to the HW structure
2289 * Populates "phy" structure with various feature states.
2291 s32 e1000_get_phy_info_ife(struct e1000_hw *hw)
2293 struct e1000_phy_info *phy = &hw->phy;
2298 DEBUGFUNC("e1000_get_phy_info_ife");
2300 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2305 DEBUGOUT("Phy info is only valid if link is up\n");
2306 ret_val = -E1000_ERR_CONFIG;
2310 ret_val = phy->ops.read_reg(hw, IFE_PHY_SPECIAL_CONTROL, &data);
2313 phy->polarity_correction = (data & IFE_PSC_AUTO_POLARITY_DISABLE)
2316 if (phy->polarity_correction) {
2317 ret_val = e1000_check_polarity_ife(hw);
2321 /* Polarity is forced */
2322 phy->cable_polarity = (data & IFE_PSC_FORCE_POLARITY)
2323 ? e1000_rev_polarity_reversed
2324 : e1000_rev_polarity_normal;
2327 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data);
2331 phy->is_mdix = (data & IFE_PMC_MDIX_STATUS) ? TRUE : FALSE;
2333 /* The following parameters are undefined for 10/100 operation. */
2334 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2335 phy->local_rx = e1000_1000t_rx_status_undefined;
2336 phy->remote_rx = e1000_1000t_rx_status_undefined;
2343 * e1000_phy_sw_reset_generic - PHY software reset
2344 * @hw: pointer to the HW structure
2346 * Does a software reset of the PHY by reading the PHY control register and
2347 * setting/write the control register reset bit to the PHY.
2349 s32 e1000_phy_sw_reset_generic(struct e1000_hw *hw)
2351 s32 ret_val = E1000_SUCCESS;
2354 DEBUGFUNC("e1000_phy_sw_reset_generic");
2356 if (!(hw->phy.ops.read_reg))
2359 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
2363 phy_ctrl |= MII_CR_RESET;
2364 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
2375 * e1000_phy_hw_reset_generic - PHY hardware reset
2376 * @hw: pointer to the HW structure
2378 * Verify the reset block is not blocking us from resetting. Acquire
2379 * semaphore (if necessary) and read/set/write the device control reset
2380 * bit in the PHY. Wait the appropriate delay time for the device to
2381 * reset and release the semaphore (if necessary).
2383 s32 e1000_phy_hw_reset_generic(struct e1000_hw *hw)
2385 struct e1000_phy_info *phy = &hw->phy;
2386 s32 ret_val = E1000_SUCCESS;
2389 DEBUGFUNC("e1000_phy_hw_reset_generic");
2391 ret_val = phy->ops.check_reset_block(hw);
2393 ret_val = E1000_SUCCESS;
2397 ret_val = phy->ops.acquire(hw);
2401 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2402 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PHY_RST);
2403 E1000_WRITE_FLUSH(hw);
2405 usec_delay(phy->reset_delay_us);
2407 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2408 E1000_WRITE_FLUSH(hw);
2412 phy->ops.release(hw);
2414 ret_val = phy->ops.get_cfg_done(hw);
2421 * e1000_get_cfg_done_generic - Generic configuration done
2422 * @hw: pointer to the HW structure
2424 * Generic function to wait 10 milli-seconds for configuration to complete
2425 * and return success.
2427 s32 e1000_get_cfg_done_generic(struct e1000_hw *hw)
2429 DEBUGFUNC("e1000_get_cfg_done_generic");
2433 return E1000_SUCCESS;
2437 * e1000_phy_init_script_igp3 - Inits the IGP3 PHY
2438 * @hw: pointer to the HW structure
2440 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present.
2442 s32 e1000_phy_init_script_igp3(struct e1000_hw *hw)
2444 DEBUGOUT("Running IGP 3 PHY init script\n");
2446 /* PHY init IGP 3 */
2447 /* Enable rise/fall, 10-mode work in class-A */
2448 hw->phy.ops.write_reg(hw, 0x2F5B, 0x9018);
2449 /* Remove all caps from Replica path filter */
2450 hw->phy.ops.write_reg(hw, 0x2F52, 0x0000);
2451 /* Bias trimming for ADC, AFE and Driver (Default) */
2452 hw->phy.ops.write_reg(hw, 0x2FB1, 0x8B24);
2453 /* Increase Hybrid poly bias */
2454 hw->phy.ops.write_reg(hw, 0x2FB2, 0xF8F0);
2455 /* Add 4% to Tx amplitude in Gig mode */
2456 hw->phy.ops.write_reg(hw, 0x2010, 0x10B0);
2457 /* Disable trimming (TTT) */
2458 hw->phy.ops.write_reg(hw, 0x2011, 0x0000);
2459 /* Poly DC correction to 94.6% + 2% for all channels */
2460 hw->phy.ops.write_reg(hw, 0x20DD, 0x249A);
2461 /* ABS DC correction to 95.9% */
2462 hw->phy.ops.write_reg(hw, 0x20DE, 0x00D3);
2463 /* BG temp curve trim */
2464 hw->phy.ops.write_reg(hw, 0x28B4, 0x04CE);
2465 /* Increasing ADC OPAMP stage 1 currents to max */
2466 hw->phy.ops.write_reg(hw, 0x2F70, 0x29E4);
2467 /* Force 1000 ( required for enabling PHY regs configuration) */
2468 hw->phy.ops.write_reg(hw, 0x0000, 0x0140);
2469 /* Set upd_freq to 6 */
2470 hw->phy.ops.write_reg(hw, 0x1F30, 0x1606);
2472 hw->phy.ops.write_reg(hw, 0x1F31, 0xB814);
2473 /* Disable adaptive fixed FFE (Default) */
2474 hw->phy.ops.write_reg(hw, 0x1F35, 0x002A);
2475 /* Enable FFE hysteresis */
2476 hw->phy.ops.write_reg(hw, 0x1F3E, 0x0067);
2477 /* Fixed FFE for short cable lengths */
2478 hw->phy.ops.write_reg(hw, 0x1F54, 0x0065);
2479 /* Fixed FFE for medium cable lengths */
2480 hw->phy.ops.write_reg(hw, 0x1F55, 0x002A);
2481 /* Fixed FFE for long cable lengths */
2482 hw->phy.ops.write_reg(hw, 0x1F56, 0x002A);
2483 /* Enable Adaptive Clip Threshold */
2484 hw->phy.ops.write_reg(hw, 0x1F72, 0x3FB0);
2485 /* AHT reset limit to 1 */
2486 hw->phy.ops.write_reg(hw, 0x1F76, 0xC0FF);
2487 /* Set AHT master delay to 127 msec */
2488 hw->phy.ops.write_reg(hw, 0x1F77, 0x1DEC);
2489 /* Set scan bits for AHT */
2490 hw->phy.ops.write_reg(hw, 0x1F78, 0xF9EF);
2491 /* Set AHT Preset bits */
2492 hw->phy.ops.write_reg(hw, 0x1F79, 0x0210);
2493 /* Change integ_factor of channel A to 3 */
2494 hw->phy.ops.write_reg(hw, 0x1895, 0x0003);
2495 /* Change prop_factor of channels BCD to 8 */
2496 hw->phy.ops.write_reg(hw, 0x1796, 0x0008);
2497 /* Change cg_icount + enable integbp for channels BCD */
2498 hw->phy.ops.write_reg(hw, 0x1798, 0xD008);
2500 * Change cg_icount + enable integbp + change prop_factor_master
2501 * to 8 for channel A
2503 hw->phy.ops.write_reg(hw, 0x1898, 0xD918);
2504 /* Disable AHT in Slave mode on channel A */
2505 hw->phy.ops.write_reg(hw, 0x187A, 0x0800);
2507 * Enable LPLU and disable AN to 1000 in non-D0a states,
2510 hw->phy.ops.write_reg(hw, 0x0019, 0x008D);
2511 /* Enable restart AN on an1000_dis change */
2512 hw->phy.ops.write_reg(hw, 0x001B, 0x2080);
2513 /* Enable wh_fifo read clock in 10/100 modes */
2514 hw->phy.ops.write_reg(hw, 0x0014, 0x0045);
2515 /* Restart AN, Speed selection is 1000 */
2516 hw->phy.ops.write_reg(hw, 0x0000, 0x1340);
2518 return E1000_SUCCESS;
2522 * e1000_get_phy_type_from_id - Get PHY type from id
2523 * @phy_id: phy_id read from the phy
2525 * Returns the phy type from the id.
2527 enum e1000_phy_type e1000_get_phy_type_from_id(u32 phy_id)
2529 enum e1000_phy_type phy_type = e1000_phy_unknown;
2532 case M88E1000_I_PHY_ID:
2533 case M88E1000_E_PHY_ID:
2534 case M88E1111_I_PHY_ID:
2535 case M88E1011_I_PHY_ID:
2536 phy_type = e1000_phy_m88;
2538 case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */
2539 phy_type = e1000_phy_igp_2;
2541 case GG82563_E_PHY_ID:
2542 phy_type = e1000_phy_gg82563;
2544 case IGP03E1000_E_PHY_ID:
2545 phy_type = e1000_phy_igp_3;
2548 case IFE_PLUS_E_PHY_ID:
2549 case IFE_C_E_PHY_ID:
2550 phy_type = e1000_phy_ife;
2552 case BME1000_E_PHY_ID:
2553 case BME1000_E_PHY_ID_R2:
2554 phy_type = e1000_phy_bm;
2556 case I82578_E_PHY_ID:
2557 phy_type = e1000_phy_82578;
2559 case I82577_E_PHY_ID:
2560 phy_type = e1000_phy_82577;
2562 case I82579_E_PHY_ID:
2563 phy_type = e1000_phy_82579;
2565 case I82580_I_PHY_ID:
2566 phy_type = e1000_phy_82580;
2569 phy_type = e1000_phy_unknown;
2576 * e1000_determine_phy_address - Determines PHY address.
2577 * @hw: pointer to the HW structure
2579 * This uses a trial and error method to loop through possible PHY
2580 * addresses. It tests each by reading the PHY ID registers and
2581 * checking for a match.
2583 s32 e1000_determine_phy_address(struct e1000_hw *hw)
2585 s32 ret_val = -E1000_ERR_PHY_TYPE;
2588 enum e1000_phy_type phy_type = e1000_phy_unknown;
2590 hw->phy.id = phy_type;
2592 for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) {
2593 hw->phy.addr = phy_addr;
2597 e1000_get_phy_id(hw);
2598 phy_type = e1000_get_phy_type_from_id(hw->phy.id);
2601 * If phy_type is valid, break - we found our
2604 if (phy_type != e1000_phy_unknown) {
2605 ret_val = E1000_SUCCESS;
2618 * e1000_get_phy_addr_for_bm_page - Retrieve PHY page address
2619 * @page: page to access
2621 * Returns the phy address for the page requested.
2623 static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg)
2627 if ((page >= 768) || (page == 0 && reg == 25) || (reg == 31))
2634 * e1000_write_phy_reg_bm - Write BM PHY register
2635 * @hw: pointer to the HW structure
2636 * @offset: register offset to write to
2637 * @data: data to write at register offset
2639 * Acquires semaphore, if necessary, then writes the data to PHY register
2640 * at the offset. Release any acquired semaphores before exiting.
2642 s32 e1000_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data)
2645 u32 page = offset >> IGP_PAGE_SHIFT;
2647 DEBUGFUNC("e1000_write_phy_reg_bm");
2649 ret_val = hw->phy.ops.acquire(hw);
2653 /* Page 800 works differently than the rest so it has its own func */
2654 if (page == BM_WUC_PAGE) {
2655 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
2660 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
2662 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2663 u32 page_shift, page_select;
2666 * Page select is register 31 for phy address 1 and 22 for
2667 * phy address 2 and 3. Page select is shifted only for
2670 if (hw->phy.addr == 1) {
2671 page_shift = IGP_PAGE_SHIFT;
2672 page_select = IGP01E1000_PHY_PAGE_SELECT;
2675 page_select = BM_PHY_PAGE_SELECT;
2678 /* Page is shifted left, PHY expects (page x 32) */
2679 ret_val = e1000_write_phy_reg_mdic(hw, page_select,
2680 (page << page_shift));
2685 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2689 hw->phy.ops.release(hw);
2694 * e1000_read_phy_reg_bm - Read BM PHY register
2695 * @hw: pointer to the HW structure
2696 * @offset: register offset to be read
2697 * @data: pointer to the read data
2699 * Acquires semaphore, if necessary, then reads the PHY register at offset
2700 * and storing the retrieved information in data. Release any acquired
2701 * semaphores before exiting.
2703 s32 e1000_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data)
2706 u32 page = offset >> IGP_PAGE_SHIFT;
2708 DEBUGFUNC("e1000_read_phy_reg_bm");
2710 ret_val = hw->phy.ops.acquire(hw);
2714 /* Page 800 works differently than the rest so it has its own func */
2715 if (page == BM_WUC_PAGE) {
2716 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
2721 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
2723 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2724 u32 page_shift, page_select;
2727 * Page select is register 31 for phy address 1 and 22 for
2728 * phy address 2 and 3. Page select is shifted only for
2731 if (hw->phy.addr == 1) {
2732 page_shift = IGP_PAGE_SHIFT;
2733 page_select = IGP01E1000_PHY_PAGE_SELECT;
2736 page_select = BM_PHY_PAGE_SELECT;
2739 /* Page is shifted left, PHY expects (page x 32) */
2740 ret_val = e1000_write_phy_reg_mdic(hw, page_select,
2741 (page << page_shift));
2746 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2749 hw->phy.ops.release(hw);
2754 * e1000_read_phy_reg_bm2 - Read BM PHY register
2755 * @hw: pointer to the HW structure
2756 * @offset: register offset to be read
2757 * @data: pointer to the read data
2759 * Acquires semaphore, if necessary, then reads the PHY register at offset
2760 * and storing the retrieved information in data. Release any acquired
2761 * semaphores before exiting.
2763 s32 e1000_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data)
2766 u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
2768 DEBUGFUNC("e1000_read_phy_reg_bm2");
2770 ret_val = hw->phy.ops.acquire(hw);
2774 /* Page 800 works differently than the rest so it has its own func */
2775 if (page == BM_WUC_PAGE) {
2776 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
2783 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2785 /* Page is shifted left, PHY expects (page x 32) */
2786 ret_val = e1000_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
2793 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2796 hw->phy.ops.release(hw);
2801 * e1000_write_phy_reg_bm2 - Write BM PHY register
2802 * @hw: pointer to the HW structure
2803 * @offset: register offset to write to
2804 * @data: data to write at register offset
2806 * Acquires semaphore, if necessary, then writes the data to PHY register
2807 * at the offset. Release any acquired semaphores before exiting.
2809 s32 e1000_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data)
2812 u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
2814 DEBUGFUNC("e1000_write_phy_reg_bm2");
2816 ret_val = hw->phy.ops.acquire(hw);
2820 /* Page 800 works differently than the rest so it has its own func */
2821 if (page == BM_WUC_PAGE) {
2822 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
2829 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2830 /* Page is shifted left, PHY expects (page x 32) */
2831 ret_val = e1000_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
2838 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2842 hw->phy.ops.release(hw);
2847 * e1000_enable_phy_wakeup_reg_access_bm - enable access to BM wakeup registers
2848 * @hw: pointer to the HW structure
2849 * @phy_reg: pointer to store original contents of BM_WUC_ENABLE_REG
2851 * Assumes semaphore already acquired and phy_reg points to a valid memory
2852 * address to store contents of the BM_WUC_ENABLE_REG register.
2854 s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg)
2859 DEBUGFUNC("e1000_enable_phy_wakeup_reg_access_bm");
2862 ret_val = -E1000_ERR_PARAM;
2866 /* All page select, port ctrl and wakeup registers use phy address 1 */
2869 /* Select Port Control Registers page */
2870 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));
2872 DEBUGOUT("Could not set Port Control page\n");
2876 ret_val = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg);
2878 DEBUGOUT2("Could not read PHY register %d.%d\n",
2879 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
2884 * Enable both PHY wakeup mode and Wakeup register page writes.
2885 * Prevent a power state change by disabling ME and Host PHY wakeup.
2888 temp |= BM_WUC_ENABLE_BIT;
2889 temp &= ~(BM_WUC_ME_WU_BIT | BM_WUC_HOST_WU_BIT);
2891 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, temp);
2893 DEBUGOUT2("Could not write PHY register %d.%d\n",
2894 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
2898 /* Select Host Wakeup Registers page */
2899 ret_val = e1000_set_page_igp(hw, (BM_WUC_PAGE << IGP_PAGE_SHIFT));
2901 /* caller now able to write registers on the Wakeup registers page */
2907 * e1000_disable_phy_wakeup_reg_access_bm - disable access to BM wakeup regs
2908 * @hw: pointer to the HW structure
2909 * @phy_reg: pointer to original contents of BM_WUC_ENABLE_REG
2911 * Restore BM_WUC_ENABLE_REG to its original value.
2913 * Assumes semaphore already acquired and *phy_reg is the contents of the
2914 * BM_WUC_ENABLE_REG before register(s) on BM_WUC_PAGE were accessed by
2917 s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg)
2919 s32 ret_val = E1000_SUCCESS;
2921 DEBUGFUNC("e1000_disable_phy_wakeup_reg_access_bm");
2924 return -E1000_ERR_PARAM;
2926 /* Select Port Control Registers page */
2927 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));
2929 DEBUGOUT("Could not set Port Control page\n");
2933 /* Restore 769.17 to its original value */
2934 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, *phy_reg);
2936 DEBUGOUT2("Could not restore PHY register %d.%d\n",
2937 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
2943 * e1000_access_phy_wakeup_reg_bm - Read/write BM PHY wakeup register
2944 * @hw: pointer to the HW structure
2945 * @offset: register offset to be read or written
2946 * @data: pointer to the data to read or write
2947 * @read: determines if operation is read or write
2948 * @page_set: BM_WUC_PAGE already set and access enabled
2950 * Read the PHY register at offset and store the retrieved information in
2951 * data, or write data to PHY register at offset. Note the procedure to
2952 * access the PHY wakeup registers is different than reading the other PHY
2953 * registers. It works as such:
2954 * 1) Set 769.17.2 (page 769, register 17, bit 2) = 1
2955 * 2) Set page to 800 for host (801 if we were manageability)
2956 * 3) Write the address using the address opcode (0x11)
2957 * 4) Read or write the data using the data opcode (0x12)
2958 * 5) Restore 769.17.2 to its original value
2960 * Steps 1 and 2 are done by e1000_enable_phy_wakeup_reg_access_bm() and
2961 * step 5 is done by e1000_disable_phy_wakeup_reg_access_bm().
2963 * Assumes semaphore is already acquired. When page_set==TRUE, assumes
2964 * the PHY page is set to BM_WUC_PAGE (i.e. a function in the call stack
2965 * is responsible for calls to e1000_[enable|disable]_phy_wakeup_reg_bm()).
2967 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
2968 u16 *data, bool read, bool page_set)
2971 u16 reg = BM_PHY_REG_NUM(offset);
2974 DEBUGFUNC("e1000_access_phy_wakeup_reg_bm");
2976 /* Gig must be disabled for MDIO accesses to Host Wakeup reg page */
2977 if ((hw->mac.type == e1000_pchlan) &&
2978 (!(E1000_READ_REG(hw, E1000_PHY_CTRL) & E1000_PHY_CTRL_GBE_DISABLE)))
2979 DEBUGOUT1("Attempting to access page %d while gig enabled.\n",
2983 /* Enable access to PHY wakeup registers */
2984 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2986 DEBUGOUT("Could not enable PHY wakeup reg access\n");
2991 DEBUGOUT2("Accessing PHY page %d reg 0x%x\n", page, reg);
2993 /* Write the Wakeup register page offset value using opcode 0x11 */
2994 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg);
2996 DEBUGOUT1("Could not write address opcode to page %d\n", page);
3001 /* Read the Wakeup register page value using opcode 0x12 */
3002 ret_val = e1000_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
3005 /* Write the Wakeup register page value using opcode 0x12 */
3006 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
3011 DEBUGOUT2("Could not access PHY reg %d.%d\n", page, reg);
3016 ret_val = e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
3023 * e1000_power_up_phy_copper - Restore copper link in case of PHY power down
3024 * @hw: pointer to the HW structure
3026 * In the case of a PHY power down to save power, or to turn off link during a
3027 * driver unload, or wake on lan is not enabled, restore the link to previous
3030 void e1000_power_up_phy_copper(struct e1000_hw *hw)
3034 /* The PHY will retain its settings across a power down/up cycle */
3035 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
3036 mii_reg &= ~MII_CR_POWER_DOWN;
3037 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
3041 * e1000_power_down_phy_copper - Restore copper link in case of PHY power down
3042 * @hw: pointer to the HW structure
3044 * In the case of a PHY power down to save power, or to turn off link during a
3045 * driver unload, or wake on lan is not enabled, restore the link to previous
3048 void e1000_power_down_phy_copper(struct e1000_hw *hw)
3052 /* The PHY will retain its settings across a power down/up cycle */
3053 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
3054 mii_reg |= MII_CR_POWER_DOWN;
3055 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
3060 * __e1000_read_phy_reg_hv - Read HV PHY register
3061 * @hw: pointer to the HW structure
3062 * @offset: register offset to be read
3063 * @data: pointer to the read data
3064 * @locked: semaphore has already been acquired or not
3066 * Acquires semaphore, if necessary, then reads the PHY register at offset
3067 * and stores the retrieved information in data. Release any acquired
3068 * semaphore before exiting.
3070 static s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data,
3071 bool locked, bool page_set)
3074 u16 page = BM_PHY_REG_PAGE(offset);
3075 u16 reg = BM_PHY_REG_NUM(offset);
3076 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
3078 DEBUGFUNC("__e1000_read_phy_reg_hv");
3081 ret_val = hw->phy.ops.acquire(hw);
3086 /* Page 800 works differently than the rest so it has its own func */
3087 if (page == BM_WUC_PAGE) {
3088 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
3093 if (page > 0 && page < HV_INTC_FC_PAGE_START) {
3094 ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
3100 if (page == HV_INTC_FC_PAGE_START)
3103 if (reg > MAX_PHY_MULTI_PAGE_REG) {
3104 /* Page is shifted left, PHY expects (page x 32) */
3105 ret_val = e1000_set_page_igp(hw,
3106 (page << IGP_PAGE_SHIFT));
3108 hw->phy.addr = phy_addr;
3115 DEBUGOUT3("reading PHY page %d (or 0x%x shifted) reg 0x%x\n", page,
3116 page << IGP_PAGE_SHIFT, reg);
3118 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
3122 hw->phy.ops.release(hw);
3128 * e1000_read_phy_reg_hv - Read HV PHY register
3129 * @hw: pointer to the HW structure
3130 * @offset: register offset to be read
3131 * @data: pointer to the read data
3133 * Acquires semaphore then reads the PHY register at offset and stores
3134 * the retrieved information in data. Release the acquired semaphore
3137 s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data)
3139 return __e1000_read_phy_reg_hv(hw, offset, data, FALSE, FALSE);
3143 * e1000_read_phy_reg_hv_locked - Read HV PHY register
3144 * @hw: pointer to the HW structure
3145 * @offset: register offset to be read
3146 * @data: pointer to the read data
3148 * Reads the PHY register at offset and stores the retrieved information
3149 * in data. Assumes semaphore already acquired.
3151 s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data)
3153 return __e1000_read_phy_reg_hv(hw, offset, data, TRUE, FALSE);
3157 * e1000_read_phy_reg_page_hv - Read HV PHY register
3158 * @hw: pointer to the HW structure
3159 * @offset: register offset to write to
3160 * @data: data to write at register offset
3162 * Reads the PHY register at offset and stores the retrieved information
3163 * in data. Assumes semaphore already acquired and page already set.
3165 s32 e1000_read_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 *data)
3167 return __e1000_read_phy_reg_hv(hw, offset, data, TRUE, TRUE);
3171 * __e1000_write_phy_reg_hv - Write HV PHY register
3172 * @hw: pointer to the HW structure
3173 * @offset: register offset to write to
3174 * @data: data to write at register offset
3175 * @locked: semaphore has already been acquired or not
3177 * Acquires semaphore, if necessary, then writes the data to PHY register
3178 * at the offset. Release any acquired semaphores before exiting.
3180 static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data,
3181 bool locked, bool page_set)
3184 u16 page = BM_PHY_REG_PAGE(offset);
3185 u16 reg = BM_PHY_REG_NUM(offset);
3186 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
3188 DEBUGFUNC("__e1000_write_phy_reg_hv");
3191 ret_val = hw->phy.ops.acquire(hw);
3196 /* Page 800 works differently than the rest so it has its own func */
3197 if (page == BM_WUC_PAGE) {
3198 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
3203 if (page > 0 && page < HV_INTC_FC_PAGE_START) {
3204 ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
3210 if (page == HV_INTC_FC_PAGE_START)
3214 * Workaround MDIO accesses being disabled after entering IEEE
3215 * Power Down (when bit 11 of the PHY Control register is set)
3217 if ((hw->phy.type == e1000_phy_82578) &&
3218 (hw->phy.revision >= 1) &&
3219 (hw->phy.addr == 2) &&
3220 ((MAX_PHY_REG_ADDRESS & reg) == 0) &&
3221 (data & (1 << 11))) {
3223 ret_val = e1000_access_phy_debug_regs_hv(hw,
3230 if (reg > MAX_PHY_MULTI_PAGE_REG) {
3231 /* Page is shifted left, PHY expects (page x 32) */
3232 ret_val = e1000_set_page_igp(hw,
3233 (page << IGP_PAGE_SHIFT));
3235 hw->phy.addr = phy_addr;
3242 DEBUGOUT3("writing PHY page %d (or 0x%x shifted) reg 0x%x\n", page,
3243 page << IGP_PAGE_SHIFT, reg);
3245 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
3250 hw->phy.ops.release(hw);
3256 * e1000_write_phy_reg_hv - Write HV PHY register
3257 * @hw: pointer to the HW structure
3258 * @offset: register offset to write to
3259 * @data: data to write at register offset
3261 * Acquires semaphore then writes the data to PHY register at the offset.
3262 * Release the acquired semaphores before exiting.
3264 s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data)
3266 return __e1000_write_phy_reg_hv(hw, offset, data, FALSE, FALSE);
3270 * e1000_write_phy_reg_hv_locked - Write HV PHY register
3271 * @hw: pointer to the HW structure
3272 * @offset: register offset to write to
3273 * @data: data to write at register offset
3275 * Writes the data to PHY register at the offset. Assumes semaphore
3278 s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data)
3280 return __e1000_write_phy_reg_hv(hw, offset, data, TRUE, FALSE);
3284 * e1000_write_phy_reg_page_hv - Write HV PHY register
3285 * @hw: pointer to the HW structure
3286 * @offset: register offset to write to
3287 * @data: data to write at register offset
3289 * Writes the data to PHY register at the offset. Assumes semaphore
3290 * already acquired and page already set.
3292 s32 e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 data)
3294 return __e1000_write_phy_reg_hv(hw, offset, data, TRUE, TRUE);
3298 * e1000_get_phy_addr_for_hv_page - Get PHY adrress based on page
3299 * @page: page to be accessed
3301 static u32 e1000_get_phy_addr_for_hv_page(u32 page)
3305 if (page >= HV_INTC_FC_PAGE_START)
3312 * e1000_access_phy_debug_regs_hv - Read HV PHY vendor specific high registers
3313 * @hw: pointer to the HW structure
3314 * @offset: register offset to be read or written
3315 * @data: pointer to the data to be read or written
3316 * @read: determines if operation is read or write
3318 * Reads the PHY register at offset and stores the retreived information
3319 * in data. Assumes semaphore already acquired. Note that the procedure
3320 * to access these regs uses the address port and data port to read/write.
3321 * These accesses done with PHY address 2 and without using pages.
3323 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
3324 u16 *data, bool read)
3330 DEBUGFUNC("e1000_access_phy_debug_regs_hv");
3332 /* This takes care of the difference with desktop vs mobile phy */
3333 addr_reg = (hw->phy.type == e1000_phy_82578) ?
3334 I82578_ADDR_REG : I82577_ADDR_REG;
3335 data_reg = addr_reg + 1;
3337 /* All operations in this function are phy address 2 */
3340 /* masking with 0x3F to remove the page from offset */
3341 ret_val = e1000_write_phy_reg_mdic(hw, addr_reg, (u16)offset & 0x3F);
3343 DEBUGOUT("Could not write the Address Offset port register\n");
3347 /* Read or write the data value next */
3349 ret_val = e1000_read_phy_reg_mdic(hw, data_reg, data);
3351 ret_val = e1000_write_phy_reg_mdic(hw, data_reg, *data);
3354 DEBUGOUT("Could not access the Data port register\n");
3363 * e1000_link_stall_workaround_hv - Si workaround
3364 * @hw: pointer to the HW structure
3366 * This function works around a Si bug where the link partner can get
3367 * a link up indication before the PHY does. If small packets are sent
3368 * by the link partner they can be placed in the packet buffer without
3369 * being properly accounted for by the PHY and will stall preventing
3370 * further packets from being received. The workaround is to clear the
3371 * packet buffer after the PHY detects link up.
3373 s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw)
3375 s32 ret_val = E1000_SUCCESS;
3378 DEBUGFUNC("e1000_link_stall_workaround_hv");
3380 if (hw->phy.type != e1000_phy_82578)
3383 /* Do not apply workaround if in PHY loopback bit 14 set */
3384 hw->phy.ops.read_reg(hw, PHY_CONTROL, &data);
3385 if (data & PHY_CONTROL_LB)
3388 /* check if link is up and at 1Gbps */
3389 ret_val = hw->phy.ops.read_reg(hw, BM_CS_STATUS, &data);
3393 data &= BM_CS_STATUS_LINK_UP |
3394 BM_CS_STATUS_RESOLVED |
3395 BM_CS_STATUS_SPEED_MASK;
3397 if (data != (BM_CS_STATUS_LINK_UP |
3398 BM_CS_STATUS_RESOLVED |
3399 BM_CS_STATUS_SPEED_1000))
3404 /* flush the packets in the fifo buffer */
3405 ret_val = hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL,
3406 HV_MUX_DATA_CTRL_GEN_TO_MAC |
3407 HV_MUX_DATA_CTRL_FORCE_SPEED);
3411 ret_val = hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL,
3412 HV_MUX_DATA_CTRL_GEN_TO_MAC);
3419 * e1000_check_polarity_82577 - Checks the polarity.
3420 * @hw: pointer to the HW structure
3422 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
3424 * Polarity is determined based on the PHY specific status register.
3426 s32 e1000_check_polarity_82577(struct e1000_hw *hw)
3428 struct e1000_phy_info *phy = &hw->phy;
3432 DEBUGFUNC("e1000_check_polarity_82577");
3434 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data);
3437 phy->cable_polarity = (data & I82577_PHY_STATUS2_REV_POLARITY)
3438 ? e1000_rev_polarity_reversed
3439 : e1000_rev_polarity_normal;
3445 * e1000_phy_force_speed_duplex_82577 - Force speed/duplex for I82577 PHY
3446 * @hw: pointer to the HW structure
3448 * Calls the PHY setup function to force speed and duplex.
3450 s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw)
3452 struct e1000_phy_info *phy = &hw->phy;
3457 DEBUGFUNC("e1000_phy_force_speed_duplex_82577");
3459 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
3463 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
3465 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
3471 if (phy->autoneg_wait_to_complete) {
3472 DEBUGOUT("Waiting for forced speed/duplex link on 82577 phy\n");
3474 ret_val = e1000_phy_has_link_generic(hw,
3482 DEBUGOUT("Link taking longer than expected.\n");
3485 ret_val = e1000_phy_has_link_generic(hw,
3498 * e1000_get_phy_info_82577 - Retrieve I82577 PHY information
3499 * @hw: pointer to the HW structure
3501 * Read PHY status to determine if link is up. If link is up, then
3502 * set/determine 10base-T extended distance and polarity correction. Read
3503 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
3504 * determine on the cable length, local and remote receiver.
3506 s32 e1000_get_phy_info_82577(struct e1000_hw *hw)
3508 struct e1000_phy_info *phy = &hw->phy;
3513 DEBUGFUNC("e1000_get_phy_info_82577");
3515 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
3520 DEBUGOUT("Phy info is only valid if link is up\n");
3521 ret_val = -E1000_ERR_CONFIG;
3525 phy->polarity_correction = TRUE;
3527 ret_val = e1000_check_polarity_82577(hw);
3531 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data);
3535 phy->is_mdix = (data & I82577_PHY_STATUS2_MDIX) ? TRUE : FALSE;
3537 if ((data & I82577_PHY_STATUS2_SPEED_MASK) ==
3538 I82577_PHY_STATUS2_SPEED_1000MBPS) {
3539 ret_val = hw->phy.ops.get_cable_length(hw);
3543 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
3547 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
3548 ? e1000_1000t_rx_status_ok
3549 : e1000_1000t_rx_status_not_ok;
3551 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
3552 ? e1000_1000t_rx_status_ok
3553 : e1000_1000t_rx_status_not_ok;
3555 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
3556 phy->local_rx = e1000_1000t_rx_status_undefined;
3557 phy->remote_rx = e1000_1000t_rx_status_undefined;
3565 * e1000_get_cable_length_82577 - Determine cable length for 82577 PHY
3566 * @hw: pointer to the HW structure
3568 * Reads the diagnostic status register and verifies result is valid before
3569 * placing it in the phy_cable_length field.
3571 s32 e1000_get_cable_length_82577(struct e1000_hw *hw)
3573 struct e1000_phy_info *phy = &hw->phy;
3575 u16 phy_data, length;
3577 DEBUGFUNC("e1000_get_cable_length_82577");
3579 ret_val = phy->ops.read_reg(hw, I82577_PHY_DIAG_STATUS, &phy_data);
3583 length = (phy_data & I82577_DSTATUS_CABLE_LENGTH) >>
3584 I82577_DSTATUS_CABLE_LENGTH_SHIFT;
3586 if (length == E1000_CABLE_LENGTH_UNDEFINED)
3587 ret_val = -E1000_ERR_PHY;
3589 phy->cable_length = length;