2 * Copyright (c) 1999,2000,2001 Jonathan Lemon
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. Neither the name of the author nor the names of any co-contributors
14 * may be used to endorse or promote products derived from this software
15 * without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * $FreeBSD: src/sys/dev/gx/if_gxvar.h,v 1.1.2.1 2001/11/15 03:09:23 jlemon Exp $
30 * $DragonFly: src/sys/dev/netif/gx/Attic/if_gxvar.h,v 1.5 2005/05/05 22:57:44 swildner Exp $
33 #if defined(__DragonFly__) || __FreeBSD_version < 500000
36 #define mtx_init(a, b, c)
37 #define mtx_destroy(a)
38 struct mtx { int filler; };
40 #define GX_LOCK(gx) mtx_lock(&(gx)->gx_mtx)
41 #define GX_UNLOCK(gx) mtx_unlock(&(gx)->gx_mtx)
44 #ifndef PCIM_CMD_MWIEN
45 #define PCIM_CMD_MWIEN 0x0010
50 /* CSR_WRITE_8 assumes the register is in low/high order */
51 #define CSR_WRITE_8(gx, reg, val) do { \
52 bus_space_write_4(gx->gx_btag, gx->gx_bhandle, reg, val & 0xffffffff); \
53 bus_space_write_4(gx->gx_btag, gx->gx_bhandle, reg + 4, val >> 32); \
55 #define CSR_WRITE_4(gx, reg, val) \
56 bus_space_write_4(gx->gx_btag, gx->gx_bhandle, reg, val)
57 #define CSR_WRITE_2(gx, reg, val) \
58 bus_space_write_2(gx->gx_btag, gx->gx_bhandle, reg, val)
59 #define CSR_WRITE_1(gx, reg, val) \
60 bus_space_write_1(gx->gx_btag, gx->gx_bhandle, reg, val)
62 #define CSR_READ_4(gx, reg) \
63 bus_space_read_4(gx->gx_btag, gx->gx_bhandle, reg)
64 #define CSR_READ_2(gx, reg) \
65 bus_space_read_2(gx->gx_btag, gx->gx_bhandle, reg)
66 #define CSR_READ_1(gx, reg) \
67 bus_space_read_1(gx->gx_btag, gx->gx_bhandle, reg)
69 #define GX_SETBIT(gx, reg, x) \
70 CSR_WRITE_4(gx, reg, (CSR_READ_4(gx, reg) | (x)))
71 #define GX_CLRBIT(gx, reg, x) \
72 CSR_WRITE_4(gx, reg, (CSR_READ_4(gx, reg) & ~(x)))
75 * In theory, these can go up to 64K each, but due to chip bugs,
76 * they are limited to 256 max. Descriptor counts should be a
79 #define GX_TX_RING_CNT 256
80 #define GX_RX_RING_CNT 256
82 #define GX_INC(x, y) (x) = (x + 1) % y
83 #define GX_PREV(x, y) (x == 0 ? y - 1 : x - 1)
85 #define GX_MAX_MTU (16 * 1024)
88 struct gx_rx_desc gx_rx_ring[GX_RX_RING_CNT];
89 struct gx_tx_desc gx_tx_ring[GX_TX_RING_CNT];
92 struct gx_chain_data {
93 struct mbuf *gx_rx_chain[GX_RX_RING_CNT];
94 struct mbuf *gx_tx_chain[GX_TX_RING_CNT];
114 struct arpcom arpcom; /* interface info */
115 struct ifmedia gx_media; /* media info */
116 bus_space_handle_t gx_bhandle; /* bus space handle */
117 bus_space_tag_t gx_btag; /* bus space tag */
118 void *gx_intrhand; /* irq handler handle */
119 struct resource *gx_irq; /* IRQ resource handle */
120 struct resource *gx_res; /* I/O or shared mem handle */
123 u_int8_t gx_unit; /* controller number */
124 u_int8_t gx_tbimode; /* transceiver flag */
125 int gx_vflags; /* version-specific flags */
126 u_int32_t gx_ipg; /* version-specific IPG */
127 struct gx_ring_data *gx_rdata;
128 struct gx_chain_data gx_cdata;
130 struct mbuf *gx_pkthdr;
131 struct mbuf **gx_pktnextp;
132 int gx_rx_tail_idx; /* receive ring tail index */
133 int gx_tx_tail_idx; /* transmit ring tail index */
134 int gx_tx_head_idx; /* transmit ring tail index */
136 int gx_txcontext; /* current TX context */
137 struct gx_regs gx_reg;
141 int gx_tx_intr_delay;
142 int gx_rx_intr_delay;
145 int gx_tx_interrupts;
146 int gx_rx_interrupts;
151 * flags to compensate for differing chip variants
153 #define GXF_FORCE_TBI 0x0001 /* force TBI mode on */
154 #define GXF_DMA 0x0002 /* has DMA control registers */
155 #define GXF_ENABLE_MWI 0x0004 /* supports MWI burst mode */
156 #define GXF_OLD_REGS 0x0008 /* use old register mapping */
157 #define GXF_CSUM 0x0010 /* hardware checksum offload */
160 * TX Context definitions.
162 #define GX_TXCONTEXT_NONE 0
163 #define GX_TXCONTEXT_TCPIP 1
164 #define GX_TXCONTEXT_UDPIP 2