2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
25 * Michel Thierry <michel.thierry@intel.com>
26 * Thomas Daniel <thomas.daniel@intel.com>
27 * Oscar Mateo <oscar.mateo@intel.com>
32 * DOC: Logical Rings, Logical Ring Contexts and Execlists
35 * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts".
36 * These expanded contexts enable a number of new abilities, especially
37 * "Execlists" (also implemented in this file).
39 * One of the main differences with the legacy HW contexts is that logical
40 * ring contexts incorporate many more things to the context's state, like
41 * PDPs or ringbuffer control registers:
43 * The reason why PDPs are included in the context is straightforward: as
44 * PPGTTs (per-process GTTs) are actually per-context, having the PDPs
45 * contained there mean you don't need to do a ppgtt->switch_mm yourself,
46 * instead, the GPU will do it for you on the context switch.
48 * But, what about the ringbuffer control registers (head, tail, etc..)?
49 * shouldn't we just need a set of those per engine command streamer? This is
50 * where the name "Logical Rings" starts to make sense: by virtualizing the
51 * rings, the engine cs shifts to a new "ring buffer" with every context
52 * switch. When you want to submit a workload to the GPU you: A) choose your
53 * context, B) find its appropriate virtualized ring, C) write commands to it
54 * and then, finally, D) tell the GPU to switch to that context.
56 * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch
57 * to a contexts is via a context execution list, ergo "Execlists".
60 * Regarding the creation of contexts, we have:
62 * - One global default context.
63 * - One local default context for each opened fd.
64 * - One local extra context for each context create ioctl call.
66 * Now that ringbuffers belong per-context (and not per-engine, like before)
67 * and that contexts are uniquely tied to a given engine (and not reusable,
68 * like before) we need:
70 * - One ringbuffer per-engine inside each context.
71 * - One backing object per-engine inside each context.
73 * The global default context starts its life with these new objects fully
74 * allocated and populated. The local default context for each opened fd is
75 * more complex, because we don't know at creation time which engine is going
76 * to use them. To handle this, we have implemented a deferred creation of LR
79 * The local context starts its life as a hollow or blank holder, that only
80 * gets populated for a given engine once we receive an execbuffer. If later
81 * on we receive another execbuffer ioctl for the same context but a different
82 * engine, we allocate/populate a new ringbuffer and context backing object and
85 * Finally, regarding local contexts created using the ioctl call: as they are
86 * only allowed with the render ring, we can allocate & populate them right
87 * away (no need to defer anything, at least for now).
89 * Execlists implementation:
90 * Execlists are the new method by which, on gen8+ hardware, workloads are
91 * submitted for execution (as opposed to the legacy, ringbuffer-based, method).
92 * This method works as follows:
94 * When a request is committed, its commands (the BB start and any leading or
95 * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer
96 * for the appropriate context. The tail pointer in the hardware context is not
97 * updated at this time, but instead, kept by the driver in the ringbuffer
98 * structure. A structure representing this request is added to a request queue
99 * for the appropriate engine: this structure contains a copy of the context's
100 * tail after the request was written to the ring buffer and a pointer to the
103 * If the engine's request queue was empty before the request was added, the
104 * queue is processed immediately. Otherwise the queue will be processed during
105 * a context switch interrupt. In any case, elements on the queue will get sent
106 * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a
107 * globally unique 20-bits submission ID.
109 * When execution of a request completes, the GPU updates the context status
110 * buffer with a context complete event and generates a context switch interrupt.
111 * During the interrupt handling, the driver examines the events in the buffer:
112 * for each context complete event, if the announced ID matches that on the head
113 * of the request queue, then that request is retired and removed from the queue.
115 * After processing, if any requests were retired and the queue is not empty
116 * then a new execution list can be submitted. The two requests at the front of
117 * the queue are next to be submitted but since a context may not occur twice in
118 * an execution list, if subsequent requests have the same ID as the first then
119 * the two requests must be combined. This is done simply by discarding requests
120 * at the head of the queue until either only one requests is left (in which case
121 * we use a NULL second context) or the first two requests have unique IDs.
123 * By always executing the first two requests in the queue the driver ensures
124 * that the GPU is kept as busy as possible. In the case where a single context
125 * completes but a second context is still executing, the request for this second
126 * context will be at the head of the queue when we remove the first one. This
127 * request will then be resubmitted along with a new request for a different context,
128 * which will cause the hardware to continue executing the second request and queue
129 * the new request (the GPU detects the condition of a context getting preempted
130 * with the same context and optimizes the context switch flow by not doing
131 * preemption, but just sampling the new tail pointer).
135 #include <drm/drmP.h>
136 #include <drm/i915_drm.h>
137 #include "i915_drv.h"
138 #include "intel_drv.h"
139 #include "intel_mocs.h"
141 #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE)
142 #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE)
143 #define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE)
145 #define RING_EXECLIST_QFULL (1 << 0x2)
146 #define RING_EXECLIST1_VALID (1 << 0x3)
147 #define RING_EXECLIST0_VALID (1 << 0x4)
148 #define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE)
149 #define RING_EXECLIST1_ACTIVE (1 << 0x11)
150 #define RING_EXECLIST0_ACTIVE (1 << 0x12)
152 #define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0)
153 #define GEN8_CTX_STATUS_PREEMPTED (1 << 1)
154 #define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2)
155 #define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3)
156 #define GEN8_CTX_STATUS_COMPLETE (1 << 4)
157 #define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15)
159 #define CTX_LRI_HEADER_0 0x01
160 #define CTX_CONTEXT_CONTROL 0x02
161 #define CTX_RING_HEAD 0x04
162 #define CTX_RING_TAIL 0x06
163 #define CTX_RING_BUFFER_START 0x08
164 #define CTX_RING_BUFFER_CONTROL 0x0a
165 #define CTX_BB_HEAD_U 0x0c
166 #define CTX_BB_HEAD_L 0x0e
167 #define CTX_BB_STATE 0x10
168 #define CTX_SECOND_BB_HEAD_U 0x12
169 #define CTX_SECOND_BB_HEAD_L 0x14
170 #define CTX_SECOND_BB_STATE 0x16
171 #define CTX_BB_PER_CTX_PTR 0x18
172 #define CTX_RCS_INDIRECT_CTX 0x1a
173 #define CTX_RCS_INDIRECT_CTX_OFFSET 0x1c
174 #define CTX_LRI_HEADER_1 0x21
175 #define CTX_CTX_TIMESTAMP 0x22
176 #define CTX_PDP3_UDW 0x24
177 #define CTX_PDP3_LDW 0x26
178 #define CTX_PDP2_UDW 0x28
179 #define CTX_PDP2_LDW 0x2a
180 #define CTX_PDP1_UDW 0x2c
181 #define CTX_PDP1_LDW 0x2e
182 #define CTX_PDP0_UDW 0x30
183 #define CTX_PDP0_LDW 0x32
184 #define CTX_LRI_HEADER_2 0x41
185 #define CTX_R_PWR_CLK_STATE 0x42
186 #define CTX_GPGPU_CSR_BASE_ADDRESS 0x44
188 #define GEN8_CTX_VALID (1<<0)
189 #define GEN8_CTX_FORCE_PD_RESTORE (1<<1)
190 #define GEN8_CTX_FORCE_RESTORE (1<<2)
191 #define GEN8_CTX_L3LLC_COHERENT (1<<5)
192 #define GEN8_CTX_PRIVILEGE (1<<8)
194 #define ASSIGN_CTX_PDP(ppgtt, reg_state, n) { \
195 const u64 _addr = i915_page_dir_dma_addr((ppgtt), (n)); \
196 reg_state[CTX_PDP ## n ## _UDW+1] = upper_32_bits(_addr); \
197 reg_state[CTX_PDP ## n ## _LDW+1] = lower_32_bits(_addr); \
200 #define ASSIGN_CTX_PML4(ppgtt, reg_state) { \
201 reg_state[CTX_PDP0_UDW + 1] = upper_32_bits(px_dma(&ppgtt->pml4)); \
202 reg_state[CTX_PDP0_LDW + 1] = lower_32_bits(px_dma(&ppgtt->pml4)); \
206 ADVANCED_CONTEXT = 0,
211 #define GEN8_CTX_ADDRESSING_MODE_SHIFT 3
212 #define GEN8_CTX_ADDRESSING_MODE(dev) (USES_FULL_48BIT_PPGTT(dev) ?\
213 LEGACY_64B_CONTEXT :\
217 FAULT_AND_HALT, /* Debug only */
219 FAULT_AND_CONTINUE /* Unsupported */
221 #define GEN8_CTX_ID_SHIFT 32
222 #define CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x17
224 static int intel_lr_context_pin(struct drm_i915_gem_request *rq);
225 static void lrc_setup_hardware_status_page(struct intel_engine_cs *ring,
226 struct drm_i915_gem_object *default_ctx_obj);
230 * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists
232 * @enable_execlists: value of i915.enable_execlists module parameter.
234 * Only certain platforms support Execlists (the prerequisites being
235 * support for Logical Ring Contexts and Aliasing PPGTT or better).
237 * Return: 1 if Execlists is supported and has to be enabled.
239 int intel_sanitize_enable_execlists(struct drm_device *dev, int enable_execlists)
241 WARN_ON(i915.enable_ppgtt == -1);
243 /* On platforms with execlist available, vGPU will only
244 * support execlist mode, no ring buffer mode.
246 if (HAS_LOGICAL_RING_CONTEXTS(dev) && intel_vgpu_active(dev))
249 if (INTEL_INFO(dev)->gen >= 9)
252 if (enable_execlists == 0)
255 if (HAS_LOGICAL_RING_CONTEXTS(dev) && USES_PPGTT(dev) &&
256 i915.use_mmio_flip >= 0)
263 * intel_execlists_ctx_id() - get the Execlists Context ID
264 * @ctx_obj: Logical Ring Context backing object.
266 * Do not confuse with ctx->id! Unfortunately we have a name overload
267 * here: the old context ID we pass to userspace as a handler so that
268 * they can refer to a context, and the new context ID we pass to the
269 * ELSP so that the GPU can inform us of the context status via
272 * Return: 20-bits globally unique context ID.
274 u32 intel_execlists_ctx_id(struct drm_i915_gem_object *ctx_obj)
276 u32 lrca = i915_gem_obj_ggtt_offset(ctx_obj) +
277 LRC_PPHWSP_PN * PAGE_SIZE;
279 /* LRCA is required to be 4K aligned so the more significant 20 bits
280 * are globally unique */
284 static bool disable_lite_restore_wa(struct intel_engine_cs *ring)
286 struct drm_device *dev = ring->dev;
288 return ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0) ||
289 (IS_BROXTON(dev) && INTEL_REVID(dev) == BXT_REVID_A0)) &&
290 (ring->id == VCS || ring->id == VCS2);
293 uint64_t intel_lr_context_descriptor(struct intel_context *ctx,
294 struct intel_engine_cs *ring)
296 struct drm_i915_gem_object *ctx_obj = ctx->engine[ring->id].state;
298 uint64_t lrca = i915_gem_obj_ggtt_offset(ctx_obj) +
299 LRC_PPHWSP_PN * PAGE_SIZE;
301 WARN_ON(lrca & 0xFFFFFFFF00000FFFULL);
303 desc = GEN8_CTX_VALID;
304 desc |= GEN8_CTX_ADDRESSING_MODE(dev) << GEN8_CTX_ADDRESSING_MODE_SHIFT;
305 if (IS_GEN8(ctx_obj->base.dev))
306 desc |= GEN8_CTX_L3LLC_COHERENT;
307 desc |= GEN8_CTX_PRIVILEGE;
309 desc |= (u64)intel_execlists_ctx_id(ctx_obj) << GEN8_CTX_ID_SHIFT;
311 /* TODO: WaDisableLiteRestore when we start using semaphore
312 * signalling between Command Streamers */
313 /* desc |= GEN8_CTX_FORCE_RESTORE; */
315 /* WaEnableForceRestoreInCtxtDescForVCS:skl */
316 /* WaEnableForceRestoreInCtxtDescForVCS:bxt */
317 if (disable_lite_restore_wa(ring))
318 desc |= GEN8_CTX_FORCE_RESTORE;
323 static void execlists_elsp_write(struct drm_i915_gem_request *rq0,
324 struct drm_i915_gem_request *rq1)
327 struct intel_engine_cs *ring = rq0->ring;
328 struct drm_device *dev = ring->dev;
329 struct drm_i915_private *dev_priv = dev->dev_private;
333 desc[1] = intel_lr_context_descriptor(rq1->ctx, rq1->ring);
334 rq1->elsp_submitted++;
339 desc[0] = intel_lr_context_descriptor(rq0->ctx, rq0->ring);
340 rq0->elsp_submitted++;
342 /* You must always write both descriptors in the order below. */
343 lockmgr(&dev_priv->uncore.lock, LK_EXCLUSIVE);
344 intel_uncore_forcewake_get__locked(dev_priv, FORCEWAKE_ALL);
345 I915_WRITE_FW(RING_ELSP(ring), upper_32_bits(desc[1]));
346 I915_WRITE_FW(RING_ELSP(ring), lower_32_bits(desc[1]));
348 I915_WRITE_FW(RING_ELSP(ring), upper_32_bits(desc[0]));
349 /* The context is automatically loaded after the following */
350 I915_WRITE_FW(RING_ELSP(ring), lower_32_bits(desc[0]));
352 /* ELSP is a wo register, use another nearby reg for posting */
353 POSTING_READ_FW(RING_EXECLIST_STATUS_LO(ring));
354 intel_uncore_forcewake_put__locked(dev_priv, FORCEWAKE_ALL);
355 lockmgr(&dev_priv->uncore.lock, LK_RELEASE);
358 static int execlists_update_context(struct drm_i915_gem_request *rq)
360 struct intel_engine_cs *ring = rq->ring;
361 struct i915_hw_ppgtt *ppgtt = rq->ctx->ppgtt;
362 struct drm_i915_gem_object *ctx_obj = rq->ctx->engine[ring->id].state;
363 struct drm_i915_gem_object *rb_obj = rq->ringbuf->obj;
364 struct vm_page *page;
368 WARN_ON(!i915_gem_obj_is_pinned(ctx_obj));
369 WARN_ON(!i915_gem_obj_is_pinned(rb_obj));
371 page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
372 reg_state = kmap_atomic(page);
374 reg_state[CTX_RING_TAIL+1] = rq->tail;
375 reg_state[CTX_RING_BUFFER_START+1] = i915_gem_obj_ggtt_offset(rb_obj);
377 if (ppgtt && !USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) {
378 /* True 32b PPGTT with dynamic page allocation: update PDP
379 * registers and point the unallocated PDPs to scratch page.
380 * PML4 is allocated during ppgtt init, so this is not needed
383 ASSIGN_CTX_PDP(ppgtt, reg_state, 3);
384 ASSIGN_CTX_PDP(ppgtt, reg_state, 2);
385 ASSIGN_CTX_PDP(ppgtt, reg_state, 1);
386 ASSIGN_CTX_PDP(ppgtt, reg_state, 0);
389 kunmap_atomic(reg_state);
394 static void execlists_submit_requests(struct drm_i915_gem_request *rq0,
395 struct drm_i915_gem_request *rq1)
397 execlists_update_context(rq0);
400 execlists_update_context(rq1);
402 execlists_elsp_write(rq0, rq1);
405 static void execlists_context_unqueue(struct intel_engine_cs *ring)
407 struct drm_i915_gem_request *req0 = NULL, *req1 = NULL;
408 struct drm_i915_gem_request *cursor = NULL, *tmp = NULL;
410 assert_spin_locked(&ring->execlist_lock);
413 * If irqs are not active generate a warning as batches that finish
414 * without the irqs may get lost and a GPU Hang may occur.
416 WARN_ON(!intel_irqs_enabled(ring->dev->dev_private));
418 if (list_empty(&ring->execlist_queue))
421 /* Try to read in pairs */
422 list_for_each_entry_safe(cursor, tmp, &ring->execlist_queue,
426 } else if (req0->ctx == cursor->ctx) {
427 /* Same ctx: ignore first request, as second request
428 * will update tail past first request's workload */
429 cursor->elsp_submitted = req0->elsp_submitted;
430 list_del(&req0->execlist_link);
431 list_add_tail(&req0->execlist_link,
432 &ring->execlist_retired_req_list);
440 if (IS_GEN8(ring->dev) || IS_GEN9(ring->dev)) {
442 * WaIdleLiteRestore: make sure we never cause a lite
443 * restore with HEAD==TAIL
445 if (req0->elsp_submitted) {
447 * Apply the wa NOOPS to prevent ring:HEAD == req:TAIL
448 * as we resubmit the request. See gen8_emit_request()
449 * for where we prepare the padding after the end of the
452 struct intel_ringbuffer *ringbuf;
454 ringbuf = req0->ctx->engine[ring->id].ringbuf;
456 req0->tail &= ringbuf->size - 1;
460 WARN_ON(req1 && req1->elsp_submitted);
462 execlists_submit_requests(req0, req1);
465 static bool execlists_check_remove_request(struct intel_engine_cs *ring,
468 struct drm_i915_gem_request *head_req;
470 assert_spin_locked(&ring->execlist_lock);
472 head_req = list_first_entry_or_null(&ring->execlist_queue,
473 struct drm_i915_gem_request,
476 if (head_req != NULL) {
477 struct drm_i915_gem_object *ctx_obj =
478 head_req->ctx->engine[ring->id].state;
479 if (intel_execlists_ctx_id(ctx_obj) == request_id) {
480 WARN(head_req->elsp_submitted == 0,
481 "Never submitted head request\n");
483 if (--head_req->elsp_submitted <= 0) {
484 list_del(&head_req->execlist_link);
485 list_add_tail(&head_req->execlist_link,
486 &ring->execlist_retired_req_list);
496 * intel_lrc_irq_handler() - handle Context Switch interrupts
497 * @ring: Engine Command Streamer to handle.
499 * Check the unread Context Status Buffers and manage the submission of new
500 * contexts to the ELSP accordingly.
502 void intel_lrc_irq_handler(struct intel_engine_cs *ring)
504 struct drm_i915_private *dev_priv = ring->dev->dev_private;
510 u32 submit_contexts = 0;
512 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring));
514 read_pointer = ring->next_context_status_buffer;
515 write_pointer = status_pointer & GEN8_CSB_PTR_MASK;
516 if (read_pointer > write_pointer)
517 write_pointer += GEN8_CSB_ENTRIES;
519 lockmgr(&ring->execlist_lock, LK_EXCLUSIVE);
521 while (read_pointer < write_pointer) {
523 status = I915_READ(RING_CONTEXT_STATUS_BUF_LO(ring, read_pointer % GEN8_CSB_ENTRIES));
524 status_id = I915_READ(RING_CONTEXT_STATUS_BUF_HI(ring, read_pointer % GEN8_CSB_ENTRIES));
526 if (status & GEN8_CTX_STATUS_IDLE_ACTIVE)
529 if (status & GEN8_CTX_STATUS_PREEMPTED) {
530 if (status & GEN8_CTX_STATUS_LITE_RESTORE) {
531 if (execlists_check_remove_request(ring, status_id))
532 WARN(1, "Lite Restored request removed from queue\n");
534 WARN(1, "Preemption without Lite Restore\n");
537 if ((status & GEN8_CTX_STATUS_ACTIVE_IDLE) ||
538 (status & GEN8_CTX_STATUS_ELEMENT_SWITCH)) {
539 if (execlists_check_remove_request(ring, status_id))
544 if (disable_lite_restore_wa(ring)) {
545 /* Prevent a ctx to preempt itself */
546 if ((status & GEN8_CTX_STATUS_ACTIVE_IDLE) &&
547 (submit_contexts != 0))
548 execlists_context_unqueue(ring);
549 } else if (submit_contexts != 0) {
550 execlists_context_unqueue(ring);
553 lockmgr(&ring->execlist_lock, LK_RELEASE);
555 WARN(submit_contexts > 2, "More than two context complete events?\n");
556 ring->next_context_status_buffer = write_pointer % GEN8_CSB_ENTRIES;
558 I915_WRITE(RING_CONTEXT_STATUS_PTR(ring),
559 _MASKED_FIELD(GEN8_CSB_PTR_MASK << 8,
560 ((u32)ring->next_context_status_buffer &
561 GEN8_CSB_PTR_MASK) << 8));
564 static int execlists_context_queue(struct drm_i915_gem_request *request)
566 struct intel_engine_cs *ring = request->ring;
567 struct drm_i915_gem_request *cursor;
568 int num_elements = 0;
570 if (request->ctx != ring->default_context)
571 intel_lr_context_pin(request);
573 i915_gem_request_reference(request);
575 spin_lock_irq(&ring->execlist_lock);
577 list_for_each_entry(cursor, &ring->execlist_queue, execlist_link)
578 if (++num_elements > 2)
581 if (num_elements > 2) {
582 struct drm_i915_gem_request *tail_req;
584 tail_req = list_last_entry(&ring->execlist_queue,
585 struct drm_i915_gem_request,
588 if (request->ctx == tail_req->ctx) {
589 WARN(tail_req->elsp_submitted != 0,
590 "More than 2 already-submitted reqs queued\n");
591 list_del(&tail_req->execlist_link);
592 list_add_tail(&tail_req->execlist_link,
593 &ring->execlist_retired_req_list);
597 list_add_tail(&request->execlist_link, &ring->execlist_queue);
598 if (num_elements == 0)
599 execlists_context_unqueue(ring);
601 spin_unlock_irq(&ring->execlist_lock);
606 static int logical_ring_invalidate_all_caches(struct drm_i915_gem_request *req)
608 struct intel_engine_cs *ring = req->ring;
609 uint32_t flush_domains;
613 if (ring->gpu_caches_dirty)
614 flush_domains = I915_GEM_GPU_DOMAINS;
616 ret = ring->emit_flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
620 ring->gpu_caches_dirty = false;
624 static int execlists_move_to_gpu(struct drm_i915_gem_request *req,
625 struct list_head *vmas)
627 const unsigned other_rings = ~intel_ring_flag(req->ring);
628 struct i915_vma *vma;
629 uint32_t flush_domains = 0;
630 bool flush_chipset = false;
633 list_for_each_entry(vma, vmas, exec_list) {
634 struct drm_i915_gem_object *obj = vma->obj;
636 if (obj->active & other_rings) {
637 ret = i915_gem_object_sync(obj, req->ring, &req);
642 if (obj->base.write_domain & I915_GEM_DOMAIN_CPU)
643 flush_chipset |= i915_gem_clflush_object(obj, false);
645 flush_domains |= obj->base.write_domain;
648 if (flush_domains & I915_GEM_DOMAIN_GTT)
651 /* Unconditionally invalidate gpu caches and ensure that we do flush
652 * any residual writes from the previous batch.
654 return logical_ring_invalidate_all_caches(req);
657 int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request)
661 request->ringbuf = request->ctx->engine[request->ring->id].ringbuf;
663 if (request->ctx != request->ring->default_context) {
664 ret = intel_lr_context_pin(request);
672 static int logical_ring_wait_for_space(struct drm_i915_gem_request *req,
675 struct intel_ringbuffer *ringbuf = req->ringbuf;
676 struct intel_engine_cs *ring = req->ring;
677 struct drm_i915_gem_request *target;
681 if (intel_ring_space(ringbuf) >= bytes)
684 /* The whole point of reserving space is to not wait! */
685 WARN_ON(ringbuf->reserved_in_use);
687 list_for_each_entry(target, &ring->request_list, list) {
689 * The request queue is per-engine, so can contain requests
690 * from multiple ringbuffers. Here, we must ignore any that
691 * aren't from the ringbuffer we're considering.
693 if (target->ringbuf != ringbuf)
696 /* Would completion of this request free enough space? */
697 space = __intel_ring_space(target->postfix, ringbuf->tail,
703 if (WARN_ON(&target->list == &ring->request_list))
706 ret = i915_wait_request(target);
710 ringbuf->space = space;
715 * intel_logical_ring_advance_and_submit() - advance the tail and submit the workload
716 * @request: Request to advance the logical ringbuffer of.
718 * The tail is updated in our logical ringbuffer struct, not in the actual context. What
719 * really happens during submission is that the context and current tail will be placed
720 * on a queue waiting for the ELSP to be ready to accept a new context submission. At that
721 * point, the tail *inside* the context is updated and the ELSP written to.
724 intel_logical_ring_advance_and_submit(struct drm_i915_gem_request *request)
726 struct intel_engine_cs *ring = request->ring;
727 struct drm_i915_private *dev_priv = request->i915;
729 intel_logical_ring_advance(request->ringbuf);
731 request->tail = request->ringbuf->tail;
733 if (intel_ring_stopped(ring))
736 if (dev_priv->guc.execbuf_client)
737 i915_guc_submit(dev_priv->guc.execbuf_client, request);
739 execlists_context_queue(request);
742 static void __wrap_ring_buffer(struct intel_ringbuffer *ringbuf)
744 uint32_t __iomem *virt;
745 int rem = ringbuf->size - ringbuf->tail;
747 virt = (uint32_t *)(ringbuf->virtual_start + ringbuf->tail);
750 iowrite32(MI_NOOP, virt++);
753 intel_ring_update_space(ringbuf);
756 static int logical_ring_prepare(struct drm_i915_gem_request *req, int bytes)
758 struct intel_ringbuffer *ringbuf = req->ringbuf;
759 int remain_usable = ringbuf->effective_size - ringbuf->tail;
760 int remain_actual = ringbuf->size - ringbuf->tail;
761 int ret, total_bytes, wait_bytes = 0;
762 bool need_wrap = false;
764 if (ringbuf->reserved_in_use)
767 total_bytes = bytes + ringbuf->reserved_size;
769 if (unlikely(bytes > remain_usable)) {
771 * Not enough space for the basic request. So need to flush
772 * out the remainder and then wait for base + reserved.
774 wait_bytes = remain_actual + total_bytes;
777 if (unlikely(total_bytes > remain_usable)) {
779 * The base request will fit but the reserved space
780 * falls off the end. So only need to to wait for the
781 * reserved size after flushing out the remainder.
783 wait_bytes = remain_actual + ringbuf->reserved_size;
785 } else if (total_bytes > ringbuf->space) {
786 /* No wrapping required, just waiting. */
787 wait_bytes = total_bytes;
792 ret = logical_ring_wait_for_space(req, wait_bytes);
797 __wrap_ring_buffer(ringbuf);
804 * intel_logical_ring_begin() - prepare the logical ringbuffer to accept some commands
806 * @req: The request to start some new work for
807 * @num_dwords: number of DWORDs that we plan to write to the ringbuffer.
809 * The ringbuffer might not be ready to accept the commands right away (maybe it needs to
810 * be wrapped, or wait a bit for the tail to be updated). This function takes care of that
811 * and also preallocates a request (every workload submission is still mediated through
812 * requests, same as it did with legacy ringbuffer submission).
814 * Return: non-zero if the ringbuffer is not ready to be written to.
816 int intel_logical_ring_begin(struct drm_i915_gem_request *req, int num_dwords)
818 struct drm_i915_private *dev_priv;
821 WARN_ON(req == NULL);
822 dev_priv = req->ring->dev->dev_private;
824 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
825 dev_priv->mm.interruptible);
829 ret = logical_ring_prepare(req, num_dwords * sizeof(uint32_t));
833 req->ringbuf->space -= num_dwords * sizeof(uint32_t);
837 int intel_logical_ring_reserve_space(struct drm_i915_gem_request *request)
840 * The first call merely notes the reserve request and is common for
841 * all back ends. The subsequent localised _begin() call actually
842 * ensures that the reservation is available. Without the begin, if
843 * the request creator immediately submitted the request without
844 * adding any commands to it then there might not actually be
845 * sufficient room for the submission commands.
847 intel_ring_reserved_space_reserve(request->ringbuf, MIN_SPACE_FOR_ADD_REQUEST);
849 return intel_logical_ring_begin(request, 0);
853 * execlists_submission() - submit a batchbuffer for execution, Execlists style
856 * @ring: Engine Command Streamer to submit to.
857 * @ctx: Context to employ for this submission.
858 * @args: execbuffer call arguments.
859 * @vmas: list of vmas.
860 * @batch_obj: the batchbuffer to submit.
861 * @exec_start: batchbuffer start virtual address pointer.
862 * @dispatch_flags: translated execbuffer call flags.
864 * This is the evil twin version of i915_gem_ringbuffer_submission. It abstracts
865 * away the submission details of the execbuffer ioctl call.
867 * Return: non-zero if the submission fails.
869 int intel_execlists_submission(struct i915_execbuffer_params *params,
870 struct drm_i915_gem_execbuffer2 *args,
871 struct list_head *vmas)
873 struct drm_device *dev = params->dev;
874 struct intel_engine_cs *ring = params->ring;
875 struct drm_i915_private *dev_priv = dev->dev_private;
876 struct intel_ringbuffer *ringbuf = params->ctx->engine[ring->id].ringbuf;
882 instp_mode = args->flags & I915_EXEC_CONSTANTS_MASK;
883 instp_mask = I915_EXEC_CONSTANTS_MASK;
884 switch (instp_mode) {
885 case I915_EXEC_CONSTANTS_REL_GENERAL:
886 case I915_EXEC_CONSTANTS_ABSOLUTE:
887 case I915_EXEC_CONSTANTS_REL_SURFACE:
888 if (instp_mode != 0 && ring != &dev_priv->ring[RCS]) {
889 DRM_DEBUG("non-0 rel constants mode on non-RCS\n");
893 if (instp_mode != dev_priv->relative_constants_mode) {
894 if (instp_mode == I915_EXEC_CONSTANTS_REL_SURFACE) {
895 DRM_DEBUG("rel surface constants mode invalid on gen5+\n");
899 /* The HW changed the meaning on this bit on gen6 */
900 instp_mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE;
904 DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode);
908 if (args->flags & I915_EXEC_GEN7_SOL_RESET) {
909 DRM_DEBUG("sol reset is gen7 only\n");
913 ret = execlists_move_to_gpu(params->request, vmas);
917 if (ring == &dev_priv->ring[RCS] &&
918 instp_mode != dev_priv->relative_constants_mode) {
919 ret = intel_logical_ring_begin(params->request, 4);
923 intel_logical_ring_emit(ringbuf, MI_NOOP);
924 intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(1));
925 intel_logical_ring_emit(ringbuf, INSTPM);
926 intel_logical_ring_emit(ringbuf, instp_mask << 16 | instp_mode);
927 intel_logical_ring_advance(ringbuf);
929 dev_priv->relative_constants_mode = instp_mode;
932 exec_start = params->batch_obj_vm_offset +
933 args->batch_start_offset;
935 ret = ring->emit_bb_start(params->request, exec_start, params->dispatch_flags);
939 trace_i915_gem_ring_dispatch(params->request, params->dispatch_flags);
941 i915_gem_execbuffer_move_to_active(vmas, params->request);
942 i915_gem_execbuffer_retire_commands(params);
947 void intel_execlists_retire_requests(struct intel_engine_cs *ring)
949 struct drm_i915_gem_request *req, *tmp;
950 struct list_head retired_list;
952 WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex));
953 if (list_empty(&ring->execlist_retired_req_list))
956 INIT_LIST_HEAD(&retired_list);
957 spin_lock_irq(&ring->execlist_lock);
958 list_replace_init(&ring->execlist_retired_req_list, &retired_list);
959 spin_unlock_irq(&ring->execlist_lock);
961 list_for_each_entry_safe(req, tmp, &retired_list, execlist_link) {
962 struct intel_context *ctx = req->ctx;
963 struct drm_i915_gem_object *ctx_obj =
964 ctx->engine[ring->id].state;
966 if (ctx_obj && (ctx != ring->default_context))
967 intel_lr_context_unpin(req);
968 list_del(&req->execlist_link);
969 i915_gem_request_unreference(req);
973 void intel_logical_ring_stop(struct intel_engine_cs *ring)
975 struct drm_i915_private *dev_priv = ring->dev->dev_private;
978 if (!intel_ring_initialized(ring))
981 ret = intel_ring_idle(ring);
982 if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error))
983 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
986 /* TODO: Is this correct with Execlists enabled? */
987 I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING));
988 if (wait_for_atomic((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) {
989 DRM_ERROR("%s :timed out trying to stop ring\n", ring->name);
992 I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING));
995 int logical_ring_flush_all_caches(struct drm_i915_gem_request *req)
997 struct intel_engine_cs *ring = req->ring;
1000 if (!ring->gpu_caches_dirty)
1003 ret = ring->emit_flush(req, 0, I915_GEM_GPU_DOMAINS);
1007 ring->gpu_caches_dirty = false;
1011 static int intel_lr_context_do_pin(struct intel_engine_cs *ring,
1012 struct drm_i915_gem_object *ctx_obj,
1013 struct intel_ringbuffer *ringbuf)
1015 struct drm_device *dev = ring->dev;
1016 struct drm_i915_private *dev_priv = dev->dev_private;
1019 WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex));
1020 ret = i915_gem_obj_ggtt_pin(ctx_obj, GEN8_LR_CONTEXT_ALIGN,
1021 PIN_OFFSET_BIAS | GUC_WOPCM_TOP);
1025 ret = intel_pin_and_map_ringbuffer_obj(ring->dev, ringbuf);
1029 ctx_obj->dirty = true;
1031 /* Invalidate GuC TLB. */
1032 if (i915.enable_guc_submission)
1033 I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
1038 i915_gem_object_ggtt_unpin(ctx_obj);
1043 static int intel_lr_context_pin(struct drm_i915_gem_request *rq)
1046 struct intel_engine_cs *ring = rq->ring;
1047 struct drm_i915_gem_object *ctx_obj = rq->ctx->engine[ring->id].state;
1048 struct intel_ringbuffer *ringbuf = rq->ringbuf;
1050 if (rq->ctx->engine[ring->id].pin_count++ == 0) {
1051 ret = intel_lr_context_do_pin(ring, ctx_obj, ringbuf);
1053 goto reset_pin_count;
1058 rq->ctx->engine[ring->id].pin_count = 0;
1062 void intel_lr_context_unpin(struct drm_i915_gem_request *rq)
1064 struct intel_engine_cs *ring = rq->ring;
1065 struct drm_i915_gem_object *ctx_obj = rq->ctx->engine[ring->id].state;
1066 struct intel_ringbuffer *ringbuf = rq->ringbuf;
1069 WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex));
1070 if (--rq->ctx->engine[ring->id].pin_count == 0) {
1071 intel_unpin_ringbuffer_obj(ringbuf);
1072 i915_gem_object_ggtt_unpin(ctx_obj);
1077 static int intel_logical_ring_workarounds_emit(struct drm_i915_gem_request *req)
1080 struct intel_engine_cs *ring = req->ring;
1081 struct intel_ringbuffer *ringbuf = req->ringbuf;
1082 struct drm_device *dev = ring->dev;
1083 struct drm_i915_private *dev_priv = dev->dev_private;
1084 struct i915_workarounds *w = &dev_priv->workarounds;
1086 if (WARN_ON_ONCE(w->count == 0))
1089 ring->gpu_caches_dirty = true;
1090 ret = logical_ring_flush_all_caches(req);
1094 ret = intel_logical_ring_begin(req, w->count * 2 + 2);
1098 intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(w->count));
1099 for (i = 0; i < w->count; i++) {
1100 intel_logical_ring_emit(ringbuf, w->reg[i].addr);
1101 intel_logical_ring_emit(ringbuf, w->reg[i].value);
1103 intel_logical_ring_emit(ringbuf, MI_NOOP);
1105 intel_logical_ring_advance(ringbuf);
1107 ring->gpu_caches_dirty = true;
1108 ret = logical_ring_flush_all_caches(req);
1115 #define wa_ctx_emit(batch, index, cmd) \
1117 int __index = (index)++; \
1118 if (WARN_ON(__index >= (PAGE_SIZE / sizeof(uint32_t)))) { \
1121 batch[__index] = (cmd); \
1126 * In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after
1127 * PIPE_CONTROL instruction. This is required for the flush to happen correctly
1128 * but there is a slight complication as this is applied in WA batch where the
1129 * values are only initialized once so we cannot take register value at the
1130 * beginning and reuse it further; hence we save its value to memory, upload a
1131 * constant value with bit21 set and then we restore it back with the saved value.
1132 * To simplify the WA, a constant value is formed by using the default value
1133 * of this register. This shouldn't be a problem because we are only modifying
1134 * it for a short period and this batch in non-premptible. We can ofcourse
1135 * use additional instructions that read the actual value of the register
1136 * at that time and set our bit of interest but it makes the WA complicated.
1138 * This WA is also required for Gen9 so extracting as a function avoids
1141 static inline int gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *ring,
1142 uint32_t *const batch,
1145 uint32_t l3sqc4_flush = (0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES);
1148 * WaDisableLSQCROPERFforOCL:skl
1149 * This WA is implemented in skl_init_clock_gating() but since
1150 * this batch updates GEN8_L3SQCREG4 with default value we need to
1151 * set this bit here to retain the WA during flush.
1153 if (IS_SKYLAKE(ring->dev) && INTEL_REVID(ring->dev) <= SKL_REVID_E0)
1154 l3sqc4_flush |= GEN8_LQSC_RO_PERF_DIS;
1156 wa_ctx_emit(batch, index, (MI_STORE_REGISTER_MEM_GEN8 |
1157 MI_SRM_LRM_GLOBAL_GTT));
1158 wa_ctx_emit(batch, index, GEN8_L3SQCREG4);
1159 wa_ctx_emit(batch, index, ring->scratch.gtt_offset + 256);
1160 wa_ctx_emit(batch, index, 0);
1162 wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1));
1163 wa_ctx_emit(batch, index, GEN8_L3SQCREG4);
1164 wa_ctx_emit(batch, index, l3sqc4_flush);
1166 wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6));
1167 wa_ctx_emit(batch, index, (PIPE_CONTROL_CS_STALL |
1168 PIPE_CONTROL_DC_FLUSH_ENABLE));
1169 wa_ctx_emit(batch, index, 0);
1170 wa_ctx_emit(batch, index, 0);
1171 wa_ctx_emit(batch, index, 0);
1172 wa_ctx_emit(batch, index, 0);
1174 wa_ctx_emit(batch, index, (MI_LOAD_REGISTER_MEM_GEN8 |
1175 MI_SRM_LRM_GLOBAL_GTT));
1176 wa_ctx_emit(batch, index, GEN8_L3SQCREG4);
1177 wa_ctx_emit(batch, index, ring->scratch.gtt_offset + 256);
1178 wa_ctx_emit(batch, index, 0);
1183 static inline uint32_t wa_ctx_start(struct i915_wa_ctx_bb *wa_ctx,
1185 uint32_t start_alignment)
1187 return wa_ctx->offset = ALIGN(offset, start_alignment);
1190 static inline int wa_ctx_end(struct i915_wa_ctx_bb *wa_ctx,
1192 uint32_t size_alignment)
1194 wa_ctx->size = offset - wa_ctx->offset;
1196 WARN(wa_ctx->size % size_alignment,
1197 "wa_ctx_bb failed sanity checks: size %d is not aligned to %d\n",
1198 wa_ctx->size, size_alignment);
1203 * gen8_init_indirectctx_bb() - initialize indirect ctx batch with WA
1205 * @ring: only applicable for RCS
1206 * @wa_ctx: structure representing wa_ctx
1207 * offset: specifies start of the batch, should be cache-aligned. This is updated
1208 * with the offset value received as input.
1209 * size: size of the batch in DWORDS but HW expects in terms of cachelines
1210 * @batch: page in which WA are loaded
1211 * @offset: This field specifies the start of the batch, it should be
1212 * cache-aligned otherwise it is adjusted accordingly.
1213 * Typically we only have one indirect_ctx and per_ctx batch buffer which are
1214 * initialized at the beginning and shared across all contexts but this field
1215 * helps us to have multiple batches at different offsets and select them based
1216 * on a criteria. At the moment this batch always start at the beginning of the page
1217 * and at this point we don't have multiple wa_ctx batch buffers.
1219 * The number of WA applied are not known at the beginning; we use this field
1220 * to return the no of DWORDS written.
1222 * It is to be noted that this batch does not contain MI_BATCH_BUFFER_END
1223 * so it adds NOOPs as padding to make it cacheline aligned.
1224 * MI_BATCH_BUFFER_END will be added to perctx batch and both of them together
1225 * makes a complete batch buffer.
1227 * Return: non-zero if we exceed the PAGE_SIZE limit.
1230 static int gen8_init_indirectctx_bb(struct intel_engine_cs *ring,
1231 struct i915_wa_ctx_bb *wa_ctx,
1232 uint32_t *const batch,
1235 uint32_t scratch_addr;
1236 uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
1238 /* WaDisableCtxRestoreArbitration:bdw,chv */
1239 wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE);
1241 /* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */
1242 if (IS_BROADWELL(ring->dev)) {
1243 int rc = gen8_emit_flush_coherentl3_wa(ring, batch, index);
1249 /* WaClearSlmSpaceAtContextSwitch:bdw,chv */
1250 /* Actual scratch location is at 128 bytes offset */
1251 scratch_addr = ring->scratch.gtt_offset + 2*CACHELINE_BYTES;
1253 wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6));
1254 wa_ctx_emit(batch, index, (PIPE_CONTROL_FLUSH_L3 |
1255 PIPE_CONTROL_GLOBAL_GTT_IVB |
1256 PIPE_CONTROL_CS_STALL |
1257 PIPE_CONTROL_QW_WRITE));
1258 wa_ctx_emit(batch, index, scratch_addr);
1259 wa_ctx_emit(batch, index, 0);
1260 wa_ctx_emit(batch, index, 0);
1261 wa_ctx_emit(batch, index, 0);
1263 /* Pad to end of cacheline */
1264 while (index % CACHELINE_DWORDS)
1265 wa_ctx_emit(batch, index, MI_NOOP);
1268 * MI_BATCH_BUFFER_END is not required in Indirect ctx BB because
1269 * execution depends on the length specified in terms of cache lines
1270 * in the register CTX_RCS_INDIRECT_CTX
1273 return wa_ctx_end(wa_ctx, *offset = index, CACHELINE_DWORDS);
1277 * gen8_init_perctx_bb() - initialize per ctx batch with WA
1279 * @ring: only applicable for RCS
1280 * @wa_ctx: structure representing wa_ctx
1281 * offset: specifies start of the batch, should be cache-aligned.
1282 * size: size of the batch in DWORDS but HW expects in terms of cachelines
1283 * @batch: page in which WA are loaded
1284 * @offset: This field specifies the start of this batch.
1285 * This batch is started immediately after indirect_ctx batch. Since we ensure
1286 * that indirect_ctx ends on a cacheline this batch is aligned automatically.
1288 * The number of DWORDS written are returned using this field.
1290 * This batch is terminated with MI_BATCH_BUFFER_END and so we need not add padding
1291 * to align it with cacheline as padding after MI_BATCH_BUFFER_END is redundant.
1293 static int gen8_init_perctx_bb(struct intel_engine_cs *ring,
1294 struct i915_wa_ctx_bb *wa_ctx,
1295 uint32_t *const batch,
1298 uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
1300 /* WaDisableCtxRestoreArbitration:bdw,chv */
1301 wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_ENABLE);
1303 wa_ctx_emit(batch, index, MI_BATCH_BUFFER_END);
1305 return wa_ctx_end(wa_ctx, *offset = index, 1);
1308 static int gen9_init_indirectctx_bb(struct intel_engine_cs *ring,
1309 struct i915_wa_ctx_bb *wa_ctx,
1310 uint32_t *const batch,
1314 struct drm_device *dev = ring->dev;
1315 uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
1317 /* WaDisableCtxRestoreArbitration:skl,bxt */
1318 if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) <= SKL_REVID_D0)) ||
1319 (IS_BROXTON(dev) && (INTEL_REVID(dev) == BXT_REVID_A0)))
1320 wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE);
1322 /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt */
1323 ret = gen8_emit_flush_coherentl3_wa(ring, batch, index);
1328 /* Pad to end of cacheline */
1329 while (index % CACHELINE_DWORDS)
1330 wa_ctx_emit(batch, index, MI_NOOP);
1332 return wa_ctx_end(wa_ctx, *offset = index, CACHELINE_DWORDS);
1335 static int gen9_init_perctx_bb(struct intel_engine_cs *ring,
1336 struct i915_wa_ctx_bb *wa_ctx,
1337 uint32_t *const batch,
1340 struct drm_device *dev = ring->dev;
1341 uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
1343 /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
1344 if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) <= SKL_REVID_B0)) ||
1345 (IS_BROXTON(dev) && (INTEL_REVID(dev) == BXT_REVID_A0))) {
1346 wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1));
1347 wa_ctx_emit(batch, index, GEN9_SLICE_COMMON_ECO_CHICKEN0);
1348 wa_ctx_emit(batch, index,
1349 _MASKED_BIT_ENABLE(DISABLE_PIXEL_MASK_CAMMING));
1350 wa_ctx_emit(batch, index, MI_NOOP);
1353 /* WaDisableCtxRestoreArbitration:skl,bxt */
1354 if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) <= SKL_REVID_D0)) ||
1355 (IS_BROXTON(dev) && (INTEL_REVID(dev) == BXT_REVID_A0)))
1356 wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_ENABLE);
1358 wa_ctx_emit(batch, index, MI_BATCH_BUFFER_END);
1360 return wa_ctx_end(wa_ctx, *offset = index, 1);
1363 static int lrc_setup_wa_ctx_obj(struct intel_engine_cs *ring, u32 size)
1367 ring->wa_ctx.obj = i915_gem_alloc_object(ring->dev, PAGE_ALIGN(size));
1368 if (!ring->wa_ctx.obj) {
1369 DRM_DEBUG_DRIVER("alloc LRC WA ctx backing obj failed.\n");
1373 ret = i915_gem_obj_ggtt_pin(ring->wa_ctx.obj, PAGE_SIZE, 0);
1375 DRM_DEBUG_DRIVER("pin LRC WA ctx backing obj failed: %d\n",
1377 drm_gem_object_unreference(&ring->wa_ctx.obj->base);
1384 static void lrc_destroy_wa_ctx_obj(struct intel_engine_cs *ring)
1386 if (ring->wa_ctx.obj) {
1387 i915_gem_object_ggtt_unpin(ring->wa_ctx.obj);
1388 drm_gem_object_unreference(&ring->wa_ctx.obj->base);
1389 ring->wa_ctx.obj = NULL;
1393 static int intel_init_workaround_bb(struct intel_engine_cs *ring)
1398 struct vm_page *page;
1399 struct i915_ctx_workarounds *wa_ctx = &ring->wa_ctx;
1401 WARN_ON(ring->id != RCS);
1403 /* update this when WA for higher Gen are added */
1404 if (INTEL_INFO(ring->dev)->gen > 9) {
1405 DRM_ERROR("WA batch buffer is not initialized for Gen%d\n",
1406 INTEL_INFO(ring->dev)->gen);
1410 /* some WA perform writes to scratch page, ensure it is valid */
1411 if (ring->scratch.obj == NULL) {
1412 DRM_ERROR("scratch page not allocated for %s\n", ring->name);
1416 ret = lrc_setup_wa_ctx_obj(ring, PAGE_SIZE);
1418 DRM_DEBUG_DRIVER("Failed to setup context WA page: %d\n", ret);
1422 page = i915_gem_object_get_page(wa_ctx->obj, 0);
1423 batch = kmap_atomic(page);
1426 if (INTEL_INFO(ring->dev)->gen == 8) {
1427 ret = gen8_init_indirectctx_bb(ring,
1428 &wa_ctx->indirect_ctx,
1434 ret = gen8_init_perctx_bb(ring,
1440 } else if (INTEL_INFO(ring->dev)->gen == 9) {
1441 ret = gen9_init_indirectctx_bb(ring,
1442 &wa_ctx->indirect_ctx,
1448 ret = gen9_init_perctx_bb(ring,
1457 kunmap_atomic(batch);
1459 lrc_destroy_wa_ctx_obj(ring);
1464 static int gen8_init_common_ring(struct intel_engine_cs *ring)
1466 struct drm_device *dev = ring->dev;
1467 struct drm_i915_private *dev_priv = dev->dev_private;
1468 u8 next_context_status_buffer_hw;
1470 lrc_setup_hardware_status_page(ring,
1471 ring->default_context->engine[ring->id].state);
1473 I915_WRITE_IMR(ring, ~(ring->irq_enable_mask | ring->irq_keep_mask));
1474 I915_WRITE(RING_HWSTAM(ring->mmio_base), 0xffffffff);
1476 if (ring->status_page.obj) {
1477 I915_WRITE(RING_HWS_PGA(ring->mmio_base),
1478 (u32)ring->status_page.gfx_addr);
1479 POSTING_READ(RING_HWS_PGA(ring->mmio_base));
1482 I915_WRITE(RING_MODE_GEN7(ring),
1483 _MASKED_BIT_DISABLE(GFX_REPLAY_MODE) |
1484 _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE));
1485 POSTING_READ(RING_MODE_GEN7(ring));
1488 * Instead of resetting the Context Status Buffer (CSB) read pointer to
1489 * zero, we need to read the write pointer from hardware and use its
1490 * value because "this register is power context save restored".
1491 * Effectively, these states have been observed:
1493 * | Suspend-to-idle (freeze) | Suspend-to-RAM (mem) |
1494 * BDW | CSB regs not reset | CSB regs reset |
1495 * CHT | CSB regs not reset | CSB regs not reset |
1497 next_context_status_buffer_hw = (I915_READ(RING_CONTEXT_STATUS_PTR(ring))
1498 & GEN8_CSB_PTR_MASK);
1501 * When the CSB registers are reset (also after power-up / gpu reset),
1502 * CSB write pointer is set to all 1's, which is not valid, use '5' in
1503 * this special case, so the first element read is CSB[0].
1505 if (next_context_status_buffer_hw == GEN8_CSB_PTR_MASK)
1506 next_context_status_buffer_hw = (GEN8_CSB_ENTRIES - 1);
1508 ring->next_context_status_buffer = next_context_status_buffer_hw;
1509 DRM_DEBUG_DRIVER("Execlists enabled for %s\n", ring->name);
1511 memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
1516 static int gen8_init_render_ring(struct intel_engine_cs *ring)
1518 struct drm_device *dev = ring->dev;
1519 struct drm_i915_private *dev_priv = dev->dev_private;
1522 ret = gen8_init_common_ring(ring);
1526 /* We need to disable the AsyncFlip performance optimisations in order
1527 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1528 * programmed to '1' on all products.
1530 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
1532 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1534 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
1536 return init_workarounds_ring(ring);
1539 static int gen9_init_render_ring(struct intel_engine_cs *ring)
1543 ret = gen8_init_common_ring(ring);
1547 return init_workarounds_ring(ring);
1550 static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request *req)
1552 struct i915_hw_ppgtt *ppgtt = req->ctx->ppgtt;
1553 struct intel_engine_cs *ring = req->ring;
1554 struct intel_ringbuffer *ringbuf = req->ringbuf;
1555 const int num_lri_cmds = GEN8_LEGACY_PDPES * 2;
1558 ret = intel_logical_ring_begin(req, num_lri_cmds * 2 + 2);
1562 intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(num_lri_cmds));
1563 for (i = GEN8_LEGACY_PDPES - 1; i >= 0; i--) {
1564 const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i);
1566 intel_logical_ring_emit(ringbuf, GEN8_RING_PDP_UDW(ring, i));
1567 intel_logical_ring_emit(ringbuf, upper_32_bits(pd_daddr));
1568 intel_logical_ring_emit(ringbuf, GEN8_RING_PDP_LDW(ring, i));
1569 intel_logical_ring_emit(ringbuf, lower_32_bits(pd_daddr));
1572 intel_logical_ring_emit(ringbuf, MI_NOOP);
1573 intel_logical_ring_advance(ringbuf);
1578 static int gen8_emit_bb_start(struct drm_i915_gem_request *req,
1579 u64 offset, unsigned dispatch_flags)
1581 struct intel_ringbuffer *ringbuf = req->ringbuf;
1582 bool ppgtt = !(dispatch_flags & I915_DISPATCH_SECURE);
1585 /* Don't rely in hw updating PDPs, specially in lite-restore.
1586 * Ideally, we should set Force PD Restore in ctx descriptor,
1587 * but we can't. Force Restore would be a second option, but
1588 * it is unsafe in case of lite-restore (because the ctx is
1589 * not idle). PML4 is allocated during ppgtt init so this is
1590 * not needed in 48-bit.*/
1591 if (req->ctx->ppgtt &&
1592 (intel_ring_flag(req->ring) & req->ctx->ppgtt->pd_dirty_rings)) {
1593 if (!USES_FULL_48BIT_PPGTT(req->i915) &&
1594 !intel_vgpu_active(req->i915->dev)) {
1595 ret = intel_logical_ring_emit_pdps(req);
1600 req->ctx->ppgtt->pd_dirty_rings &= ~intel_ring_flag(req->ring);
1603 ret = intel_logical_ring_begin(req, 4);
1607 /* FIXME(BDW): Address space and security selectors. */
1608 intel_logical_ring_emit(ringbuf, MI_BATCH_BUFFER_START_GEN8 |
1610 (dispatch_flags & I915_DISPATCH_RS ?
1611 MI_BATCH_RESOURCE_STREAMER : 0));
1612 intel_logical_ring_emit(ringbuf, lower_32_bits(offset));
1613 intel_logical_ring_emit(ringbuf, upper_32_bits(offset));
1614 intel_logical_ring_emit(ringbuf, MI_NOOP);
1615 intel_logical_ring_advance(ringbuf);
1620 static bool gen8_logical_ring_get_irq(struct intel_engine_cs *ring)
1622 struct drm_device *dev = ring->dev;
1623 struct drm_i915_private *dev_priv = dev->dev_private;
1624 unsigned long flags;
1626 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1629 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1630 if (ring->irq_refcount++ == 0) {
1631 I915_WRITE_IMR(ring, ~(ring->irq_enable_mask | ring->irq_keep_mask));
1632 POSTING_READ(RING_IMR(ring->mmio_base));
1634 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1639 static void gen8_logical_ring_put_irq(struct intel_engine_cs *ring)
1641 struct drm_device *dev = ring->dev;
1642 struct drm_i915_private *dev_priv = dev->dev_private;
1643 unsigned long flags;
1645 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1646 if (--ring->irq_refcount == 0) {
1647 I915_WRITE_IMR(ring, ~ring->irq_keep_mask);
1648 POSTING_READ(RING_IMR(ring->mmio_base));
1650 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1653 static int gen8_emit_flush(struct drm_i915_gem_request *request,
1654 u32 invalidate_domains,
1657 struct intel_ringbuffer *ringbuf = request->ringbuf;
1658 struct intel_engine_cs *ring = ringbuf->ring;
1659 struct drm_device *dev = ring->dev;
1660 struct drm_i915_private *dev_priv = dev->dev_private;
1664 ret = intel_logical_ring_begin(request, 4);
1668 cmd = MI_FLUSH_DW + 1;
1670 /* We always require a command barrier so that subsequent
1671 * commands, such as breadcrumb interrupts, are strictly ordered
1672 * wrt the contents of the write cache being flushed to memory
1673 * (and thus being coherent from the CPU).
1675 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
1677 if (invalidate_domains & I915_GEM_GPU_DOMAINS) {
1678 cmd |= MI_INVALIDATE_TLB;
1679 if (ring == &dev_priv->ring[VCS])
1680 cmd |= MI_INVALIDATE_BSD;
1683 intel_logical_ring_emit(ringbuf, cmd);
1684 intel_logical_ring_emit(ringbuf,
1685 I915_GEM_HWS_SCRATCH_ADDR |
1686 MI_FLUSH_DW_USE_GTT);
1687 intel_logical_ring_emit(ringbuf, 0); /* upper addr */
1688 intel_logical_ring_emit(ringbuf, 0); /* value */
1689 intel_logical_ring_advance(ringbuf);
1694 static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
1695 u32 invalidate_domains,
1698 struct intel_ringbuffer *ringbuf = request->ringbuf;
1699 struct intel_engine_cs *ring = ringbuf->ring;
1700 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
1705 flags |= PIPE_CONTROL_CS_STALL;
1707 if (flush_domains) {
1708 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
1709 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
1710 flags |= PIPE_CONTROL_FLUSH_ENABLE;
1713 if (invalidate_domains) {
1714 flags |= PIPE_CONTROL_TLB_INVALIDATE;
1715 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
1716 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
1717 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
1718 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
1719 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
1720 flags |= PIPE_CONTROL_QW_WRITE;
1721 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
1725 * On GEN9+ Before VF_CACHE_INVALIDATE we need to emit a NULL pipe
1728 vf_flush_wa = INTEL_INFO(ring->dev)->gen >= 9 &&
1729 flags & PIPE_CONTROL_VF_CACHE_INVALIDATE;
1731 ret = intel_logical_ring_begin(request, vf_flush_wa ? 12 : 6);
1736 intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
1737 intel_logical_ring_emit(ringbuf, 0);
1738 intel_logical_ring_emit(ringbuf, 0);
1739 intel_logical_ring_emit(ringbuf, 0);
1740 intel_logical_ring_emit(ringbuf, 0);
1741 intel_logical_ring_emit(ringbuf, 0);
1744 intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
1745 intel_logical_ring_emit(ringbuf, flags);
1746 intel_logical_ring_emit(ringbuf, scratch_addr);
1747 intel_logical_ring_emit(ringbuf, 0);
1748 intel_logical_ring_emit(ringbuf, 0);
1749 intel_logical_ring_emit(ringbuf, 0);
1750 intel_logical_ring_advance(ringbuf);
1755 static u32 gen8_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1757 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1760 static void gen8_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1762 intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
1765 static u32 bxt_a_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1769 * On BXT A steppings there is a HW coherency issue whereby the
1770 * MI_STORE_DATA_IMM storing the completed request's seqno
1771 * occasionally doesn't invalidate the CPU cache. Work around this by
1772 * clflushing the corresponding cacheline whenever the caller wants
1773 * the coherency to be guaranteed. Note that this cacheline is known
1774 * to be clean at this point, since we only write it in
1775 * bxt_a_set_seqno(), where we also do a clflush after the write. So
1776 * this clflush in practice becomes an invalidate operation.
1779 if (!lazy_coherency)
1780 intel_flush_status_page(ring, I915_GEM_HWS_INDEX);
1782 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1785 static void bxt_a_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1787 intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
1789 /* See bxt_a_get_seqno() explaining the reason for the clflush. */
1790 intel_flush_status_page(ring, I915_GEM_HWS_INDEX);
1793 static int gen8_emit_request(struct drm_i915_gem_request *request)
1795 struct intel_ringbuffer *ringbuf = request->ringbuf;
1796 struct intel_engine_cs *ring = ringbuf->ring;
1801 * Reserve space for 2 NOOPs at the end of each request to be
1802 * used as a workaround for not being allowed to do lite
1803 * restore with HEAD==TAIL (WaIdleLiteRestore).
1805 ret = intel_logical_ring_begin(request, 8);
1809 cmd = MI_STORE_DWORD_IMM_GEN4;
1810 cmd |= MI_GLOBAL_GTT;
1812 intel_logical_ring_emit(ringbuf, cmd);
1813 intel_logical_ring_emit(ringbuf,
1814 (ring->status_page.gfx_addr +
1815 (I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT)));
1816 intel_logical_ring_emit(ringbuf, 0);
1817 intel_logical_ring_emit(ringbuf, i915_gem_request_get_seqno(request));
1818 intel_logical_ring_emit(ringbuf, MI_USER_INTERRUPT);
1819 intel_logical_ring_emit(ringbuf, MI_NOOP);
1820 intel_logical_ring_advance_and_submit(request);
1823 * Here we add two extra NOOPs as padding to avoid
1824 * lite restore of a context with HEAD==TAIL.
1826 intel_logical_ring_emit(ringbuf, MI_NOOP);
1827 intel_logical_ring_emit(ringbuf, MI_NOOP);
1828 intel_logical_ring_advance(ringbuf);
1833 static int intel_lr_context_render_state_init(struct drm_i915_gem_request *req)
1835 struct render_state so;
1838 ret = i915_gem_render_state_prepare(req->ring, &so);
1842 if (so.rodata == NULL)
1845 ret = req->ring->emit_bb_start(req, so.ggtt_offset,
1846 I915_DISPATCH_SECURE);
1850 ret = req->ring->emit_bb_start(req,
1851 (so.ggtt_offset + so.aux_batch_offset),
1852 I915_DISPATCH_SECURE);
1856 i915_vma_move_to_active(i915_gem_obj_to_ggtt(so.obj), req);
1859 i915_gem_render_state_fini(&so);
1863 static int gen8_init_rcs_context(struct drm_i915_gem_request *req)
1867 ret = intel_logical_ring_workarounds_emit(req);
1871 ret = intel_rcs_context_init_mocs(req);
1873 * Failing to program the MOCS is non-fatal.The system will not
1874 * run at peak performance. So generate an error and carry on.
1877 DRM_ERROR("MOCS failed to program: expect performance issues.\n");
1879 return intel_lr_context_render_state_init(req);
1883 * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer
1885 * @ring: Engine Command Streamer.
1888 void intel_logical_ring_cleanup(struct intel_engine_cs *ring)
1890 struct drm_i915_private *dev_priv;
1892 if (!intel_ring_initialized(ring))
1895 dev_priv = ring->dev->dev_private;
1897 intel_logical_ring_stop(ring);
1898 WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
1901 ring->cleanup(ring);
1903 i915_cmd_parser_fini_ring(ring);
1904 i915_gem_batch_pool_fini(&ring->batch_pool);
1906 if (ring->status_page.obj) {
1907 kunmap(sg_page(ring->status_page.obj->pages->sgl));
1908 ring->status_page.obj = NULL;
1911 lrc_destroy_wa_ctx_obj(ring);
1914 static int logical_ring_init(struct drm_device *dev, struct intel_engine_cs *ring)
1918 /* Intentionally left blank. */
1919 ring->buffer = NULL;
1922 INIT_LIST_HEAD(&ring->active_list);
1923 INIT_LIST_HEAD(&ring->request_list);
1924 i915_gem_batch_pool_init(dev, &ring->batch_pool);
1925 init_waitqueue_head(&ring->irq_queue);
1927 INIT_LIST_HEAD(&ring->execlist_queue);
1928 INIT_LIST_HEAD(&ring->execlist_retired_req_list);
1929 lockinit(&ring->execlist_lock, "i915el", 0, LK_CANRECURSE);
1931 ret = i915_cmd_parser_init_ring(ring);
1935 ret = intel_lr_context_deferred_alloc(ring->default_context, ring);
1939 /* As this is the default context, always pin it */
1940 ret = intel_lr_context_do_pin(
1942 ring->default_context->engine[ring->id].state,
1943 ring->default_context->engine[ring->id].ringbuf);
1946 "Failed to pin and map ringbuffer %s: %d\n",
1954 static int logical_render_ring_init(struct drm_device *dev)
1956 struct drm_i915_private *dev_priv = dev->dev_private;
1957 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
1960 ring->name = "render ring";
1962 ring->mmio_base = RENDER_RING_BASE;
1963 ring->irq_enable_mask =
1964 GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT;
1965 ring->irq_keep_mask =
1966 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT;
1967 if (HAS_L3_DPF(dev))
1968 ring->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
1970 if (INTEL_INFO(dev)->gen >= 9)
1971 ring->init_hw = gen9_init_render_ring;
1973 ring->init_hw = gen8_init_render_ring;
1974 ring->init_context = gen8_init_rcs_context;
1975 ring->cleanup = intel_fini_pipe_control;
1976 if (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0) {
1977 ring->get_seqno = bxt_a_get_seqno;
1978 ring->set_seqno = bxt_a_set_seqno;
1980 ring->get_seqno = gen8_get_seqno;
1981 ring->set_seqno = gen8_set_seqno;
1983 ring->emit_request = gen8_emit_request;
1984 ring->emit_flush = gen8_emit_flush_render;
1985 ring->irq_get = gen8_logical_ring_get_irq;
1986 ring->irq_put = gen8_logical_ring_put_irq;
1987 ring->emit_bb_start = gen8_emit_bb_start;
1991 ret = intel_init_pipe_control(ring);
1995 ret = intel_init_workaround_bb(ring);
1998 * We continue even if we fail to initialize WA batch
1999 * because we only expect rare glitches but nothing
2000 * critical to prevent us from using GPU
2002 DRM_ERROR("WA batch buffer initialization failed: %d\n",
2006 ret = logical_ring_init(dev, ring);
2008 lrc_destroy_wa_ctx_obj(ring);
2014 static int logical_bsd_ring_init(struct drm_device *dev)
2016 struct drm_i915_private *dev_priv = dev->dev_private;
2017 struct intel_engine_cs *ring = &dev_priv->ring[VCS];
2019 ring->name = "bsd ring";
2021 ring->mmio_base = GEN6_BSD_RING_BASE;
2022 ring->irq_enable_mask =
2023 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
2024 ring->irq_keep_mask =
2025 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
2027 ring->init_hw = gen8_init_common_ring;
2028 if (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0) {
2029 ring->get_seqno = bxt_a_get_seqno;
2030 ring->set_seqno = bxt_a_set_seqno;
2032 ring->get_seqno = gen8_get_seqno;
2033 ring->set_seqno = gen8_set_seqno;
2035 ring->emit_request = gen8_emit_request;
2036 ring->emit_flush = gen8_emit_flush;
2037 ring->irq_get = gen8_logical_ring_get_irq;
2038 ring->irq_put = gen8_logical_ring_put_irq;
2039 ring->emit_bb_start = gen8_emit_bb_start;
2041 return logical_ring_init(dev, ring);
2044 static int logical_bsd2_ring_init(struct drm_device *dev)
2046 struct drm_i915_private *dev_priv = dev->dev_private;
2047 struct intel_engine_cs *ring = &dev_priv->ring[VCS2];
2049 ring->name = "bds2 ring";
2051 ring->mmio_base = GEN8_BSD2_RING_BASE;
2052 ring->irq_enable_mask =
2053 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
2054 ring->irq_keep_mask =
2055 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
2057 ring->init_hw = gen8_init_common_ring;
2058 ring->get_seqno = gen8_get_seqno;
2059 ring->set_seqno = gen8_set_seqno;
2060 ring->emit_request = gen8_emit_request;
2061 ring->emit_flush = gen8_emit_flush;
2062 ring->irq_get = gen8_logical_ring_get_irq;
2063 ring->irq_put = gen8_logical_ring_put_irq;
2064 ring->emit_bb_start = gen8_emit_bb_start;
2066 return logical_ring_init(dev, ring);
2069 static int logical_blt_ring_init(struct drm_device *dev)
2071 struct drm_i915_private *dev_priv = dev->dev_private;
2072 struct intel_engine_cs *ring = &dev_priv->ring[BCS];
2074 ring->name = "blitter ring";
2076 ring->mmio_base = BLT_RING_BASE;
2077 ring->irq_enable_mask =
2078 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
2079 ring->irq_keep_mask =
2080 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
2082 ring->init_hw = gen8_init_common_ring;
2083 if (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0) {
2084 ring->get_seqno = bxt_a_get_seqno;
2085 ring->set_seqno = bxt_a_set_seqno;
2087 ring->get_seqno = gen8_get_seqno;
2088 ring->set_seqno = gen8_set_seqno;
2090 ring->emit_request = gen8_emit_request;
2091 ring->emit_flush = gen8_emit_flush;
2092 ring->irq_get = gen8_logical_ring_get_irq;
2093 ring->irq_put = gen8_logical_ring_put_irq;
2094 ring->emit_bb_start = gen8_emit_bb_start;
2096 return logical_ring_init(dev, ring);
2099 static int logical_vebox_ring_init(struct drm_device *dev)
2101 struct drm_i915_private *dev_priv = dev->dev_private;
2102 struct intel_engine_cs *ring = &dev_priv->ring[VECS];
2104 ring->name = "video enhancement ring";
2106 ring->mmio_base = VEBOX_RING_BASE;
2107 ring->irq_enable_mask =
2108 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
2109 ring->irq_keep_mask =
2110 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
2112 ring->init_hw = gen8_init_common_ring;
2113 if (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0) {
2114 ring->get_seqno = bxt_a_get_seqno;
2115 ring->set_seqno = bxt_a_set_seqno;
2117 ring->get_seqno = gen8_get_seqno;
2118 ring->set_seqno = gen8_set_seqno;
2120 ring->emit_request = gen8_emit_request;
2121 ring->emit_flush = gen8_emit_flush;
2122 ring->irq_get = gen8_logical_ring_get_irq;
2123 ring->irq_put = gen8_logical_ring_put_irq;
2124 ring->emit_bb_start = gen8_emit_bb_start;
2126 return logical_ring_init(dev, ring);
2130 * intel_logical_rings_init() - allocate, populate and init the Engine Command Streamers
2133 * This function inits the engines for an Execlists submission style (the equivalent in the
2134 * legacy ringbuffer submission world would be i915_gem_init_rings). It does it only for
2135 * those engines that are present in the hardware.
2137 * Return: non-zero if the initialization failed.
2139 int intel_logical_rings_init(struct drm_device *dev)
2141 struct drm_i915_private *dev_priv = dev->dev_private;
2144 ret = logical_render_ring_init(dev);
2149 ret = logical_bsd_ring_init(dev);
2151 goto cleanup_render_ring;
2155 ret = logical_blt_ring_init(dev);
2157 goto cleanup_bsd_ring;
2160 if (HAS_VEBOX(dev)) {
2161 ret = logical_vebox_ring_init(dev);
2163 goto cleanup_blt_ring;
2166 if (HAS_BSD2(dev)) {
2167 ret = logical_bsd2_ring_init(dev);
2169 goto cleanup_vebox_ring;
2175 intel_logical_ring_cleanup(&dev_priv->ring[VECS]);
2177 intel_logical_ring_cleanup(&dev_priv->ring[BCS]);
2179 intel_logical_ring_cleanup(&dev_priv->ring[VCS]);
2180 cleanup_render_ring:
2181 intel_logical_ring_cleanup(&dev_priv->ring[RCS]);
2187 make_rpcs(struct drm_device *dev)
2192 * No explicit RPCS request is needed to ensure full
2193 * slice/subslice/EU enablement prior to Gen9.
2195 if (INTEL_INFO(dev)->gen < 9)
2199 * Starting in Gen9, render power gating can leave
2200 * slice/subslice/EU in a partially enabled state. We
2201 * must make an explicit request through RPCS for full
2204 if (INTEL_INFO(dev)->has_slice_pg) {
2205 rpcs |= GEN8_RPCS_S_CNT_ENABLE;
2206 rpcs |= INTEL_INFO(dev)->slice_total <<
2207 GEN8_RPCS_S_CNT_SHIFT;
2208 rpcs |= GEN8_RPCS_ENABLE;
2211 if (INTEL_INFO(dev)->has_subslice_pg) {
2212 rpcs |= GEN8_RPCS_SS_CNT_ENABLE;
2213 rpcs |= INTEL_INFO(dev)->subslice_per_slice <<
2214 GEN8_RPCS_SS_CNT_SHIFT;
2215 rpcs |= GEN8_RPCS_ENABLE;
2218 if (INTEL_INFO(dev)->has_eu_pg) {
2219 rpcs |= INTEL_INFO(dev)->eu_per_subslice <<
2220 GEN8_RPCS_EU_MIN_SHIFT;
2221 rpcs |= INTEL_INFO(dev)->eu_per_subslice <<
2222 GEN8_RPCS_EU_MAX_SHIFT;
2223 rpcs |= GEN8_RPCS_ENABLE;
2230 populate_lr_context(struct intel_context *ctx, struct drm_i915_gem_object *ctx_obj,
2231 struct intel_engine_cs *ring, struct intel_ringbuffer *ringbuf)
2233 struct drm_device *dev = ring->dev;
2234 struct drm_i915_private *dev_priv = dev->dev_private;
2235 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2236 struct vm_page *page;
2237 uint32_t *reg_state;
2241 ppgtt = dev_priv->mm.aliasing_ppgtt;
2243 ret = i915_gem_object_set_to_cpu_domain(ctx_obj, true);
2245 DRM_DEBUG_DRIVER("Could not set to CPU domain\n");
2249 ret = i915_gem_object_get_pages(ctx_obj);
2251 DRM_DEBUG_DRIVER("Could not get object pages\n");
2255 i915_gem_object_pin_pages(ctx_obj);
2257 /* The second page of the context object contains some fields which must
2258 * be set up prior to the first execution. */
2259 page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
2260 reg_state = kmap_atomic(page);
2262 /* A context is actually a big batch buffer with several MI_LOAD_REGISTER_IMM
2263 * commands followed by (reg, value) pairs. The values we are setting here are
2264 * only for the first context restore: on a subsequent save, the GPU will
2265 * recreate this batchbuffer with new values (including all the missing
2266 * MI_LOAD_REGISTER_IMM commands that we are not initializing here). */
2267 if (ring->id == RCS)
2268 reg_state[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(14);
2270 reg_state[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(11);
2271 reg_state[CTX_LRI_HEADER_0] |= MI_LRI_FORCE_POSTED;
2272 reg_state[CTX_CONTEXT_CONTROL] = RING_CONTEXT_CONTROL(ring);
2273 reg_state[CTX_CONTEXT_CONTROL+1] =
2274 _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH |
2275 CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT |
2276 CTX_CTRL_RS_CTX_ENABLE);
2277 reg_state[CTX_RING_HEAD] = RING_HEAD(ring->mmio_base);
2278 reg_state[CTX_RING_HEAD+1] = 0;
2279 reg_state[CTX_RING_TAIL] = RING_TAIL(ring->mmio_base);
2280 reg_state[CTX_RING_TAIL+1] = 0;
2281 reg_state[CTX_RING_BUFFER_START] = RING_START(ring->mmio_base);
2282 /* Ring buffer start address is not known until the buffer is pinned.
2283 * It is written to the context image in execlists_update_context()
2285 reg_state[CTX_RING_BUFFER_CONTROL] = RING_CTL(ring->mmio_base);
2286 reg_state[CTX_RING_BUFFER_CONTROL+1] =
2287 ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES) | RING_VALID;
2288 reg_state[CTX_BB_HEAD_U] = ring->mmio_base + 0x168;
2289 reg_state[CTX_BB_HEAD_U+1] = 0;
2290 reg_state[CTX_BB_HEAD_L] = ring->mmio_base + 0x140;
2291 reg_state[CTX_BB_HEAD_L+1] = 0;
2292 reg_state[CTX_BB_STATE] = ring->mmio_base + 0x110;
2293 reg_state[CTX_BB_STATE+1] = (1<<5);
2294 reg_state[CTX_SECOND_BB_HEAD_U] = ring->mmio_base + 0x11c;
2295 reg_state[CTX_SECOND_BB_HEAD_U+1] = 0;
2296 reg_state[CTX_SECOND_BB_HEAD_L] = ring->mmio_base + 0x114;
2297 reg_state[CTX_SECOND_BB_HEAD_L+1] = 0;
2298 reg_state[CTX_SECOND_BB_STATE] = ring->mmio_base + 0x118;
2299 reg_state[CTX_SECOND_BB_STATE+1] = 0;
2300 if (ring->id == RCS) {
2301 reg_state[CTX_BB_PER_CTX_PTR] = ring->mmio_base + 0x1c0;
2302 reg_state[CTX_BB_PER_CTX_PTR+1] = 0;
2303 reg_state[CTX_RCS_INDIRECT_CTX] = ring->mmio_base + 0x1c4;
2304 reg_state[CTX_RCS_INDIRECT_CTX+1] = 0;
2305 reg_state[CTX_RCS_INDIRECT_CTX_OFFSET] = ring->mmio_base + 0x1c8;
2306 reg_state[CTX_RCS_INDIRECT_CTX_OFFSET+1] = 0;
2307 if (ring->wa_ctx.obj) {
2308 struct i915_ctx_workarounds *wa_ctx = &ring->wa_ctx;
2309 uint32_t ggtt_offset = i915_gem_obj_ggtt_offset(wa_ctx->obj);
2311 reg_state[CTX_RCS_INDIRECT_CTX+1] =
2312 (ggtt_offset + wa_ctx->indirect_ctx.offset * sizeof(uint32_t)) |
2313 (wa_ctx->indirect_ctx.size / CACHELINE_DWORDS);
2315 reg_state[CTX_RCS_INDIRECT_CTX_OFFSET+1] =
2316 CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT << 6;
2318 reg_state[CTX_BB_PER_CTX_PTR+1] =
2319 (ggtt_offset + wa_ctx->per_ctx.offset * sizeof(uint32_t)) |
2323 reg_state[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9);
2324 reg_state[CTX_LRI_HEADER_1] |= MI_LRI_FORCE_POSTED;
2325 reg_state[CTX_CTX_TIMESTAMP] = ring->mmio_base + 0x3a8;
2326 reg_state[CTX_CTX_TIMESTAMP+1] = 0;
2327 reg_state[CTX_PDP3_UDW] = GEN8_RING_PDP_UDW(ring, 3);
2328 reg_state[CTX_PDP3_LDW] = GEN8_RING_PDP_LDW(ring, 3);
2329 reg_state[CTX_PDP2_UDW] = GEN8_RING_PDP_UDW(ring, 2);
2330 reg_state[CTX_PDP2_LDW] = GEN8_RING_PDP_LDW(ring, 2);
2331 reg_state[CTX_PDP1_UDW] = GEN8_RING_PDP_UDW(ring, 1);
2332 reg_state[CTX_PDP1_LDW] = GEN8_RING_PDP_LDW(ring, 1);
2333 reg_state[CTX_PDP0_UDW] = GEN8_RING_PDP_UDW(ring, 0);
2334 reg_state[CTX_PDP0_LDW] = GEN8_RING_PDP_LDW(ring, 0);
2336 if (USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) {
2337 /* 64b PPGTT (48bit canonical)
2338 * PDP0_DESCRIPTOR contains the base address to PML4 and
2339 * other PDP Descriptors are ignored.
2341 ASSIGN_CTX_PML4(ppgtt, reg_state);
2344 * PDP*_DESCRIPTOR contains the base address of space supported.
2345 * With dynamic page allocation, PDPs may not be allocated at
2346 * this point. Point the unallocated PDPs to the scratch page
2348 ASSIGN_CTX_PDP(ppgtt, reg_state, 3);
2349 ASSIGN_CTX_PDP(ppgtt, reg_state, 2);
2350 ASSIGN_CTX_PDP(ppgtt, reg_state, 1);
2351 ASSIGN_CTX_PDP(ppgtt, reg_state, 0);
2354 if (ring->id == RCS) {
2355 reg_state[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1);
2356 reg_state[CTX_R_PWR_CLK_STATE] = GEN8_R_PWR_CLK_STATE;
2357 reg_state[CTX_R_PWR_CLK_STATE+1] = make_rpcs(dev);
2360 kunmap_atomic(reg_state);
2363 set_page_dirty(page);
2364 i915_gem_object_unpin_pages(ctx_obj);
2370 * intel_lr_context_free() - free the LRC specific bits of a context
2371 * @ctx: the LR context to free.
2373 * The real context freeing is done in i915_gem_context_free: this only
2374 * takes care of the bits that are LRC related: the per-engine backing
2375 * objects and the logical ringbuffer.
2377 void intel_lr_context_free(struct intel_context *ctx)
2381 for (i = 0; i < I915_NUM_RINGS; i++) {
2382 struct drm_i915_gem_object *ctx_obj = ctx->engine[i].state;
2385 struct intel_ringbuffer *ringbuf =
2386 ctx->engine[i].ringbuf;
2387 struct intel_engine_cs *ring = ringbuf->ring;
2389 if (ctx == ring->default_context) {
2390 intel_unpin_ringbuffer_obj(ringbuf);
2391 i915_gem_object_ggtt_unpin(ctx_obj);
2393 WARN_ON(ctx->engine[ring->id].pin_count);
2394 intel_ringbuffer_free(ringbuf);
2395 drm_gem_object_unreference(&ctx_obj->base);
2400 static uint32_t get_lr_context_size(struct intel_engine_cs *ring)
2404 WARN_ON(INTEL_INFO(ring->dev)->gen < 8);
2408 if (INTEL_INFO(ring->dev)->gen >= 9)
2409 ret = GEN9_LR_CONTEXT_RENDER_SIZE;
2411 ret = GEN8_LR_CONTEXT_RENDER_SIZE;
2417 ret = GEN8_LR_CONTEXT_OTHER_SIZE;
2424 static void lrc_setup_hardware_status_page(struct intel_engine_cs *ring,
2425 struct drm_i915_gem_object *default_ctx_obj)
2427 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2428 struct vm_page *page;
2430 /* The HWSP is part of the default context object in LRC mode. */
2431 ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(default_ctx_obj)
2432 + LRC_PPHWSP_PN * PAGE_SIZE;
2433 page = i915_gem_object_get_page(default_ctx_obj, LRC_PPHWSP_PN);
2434 ring->status_page.page_addr = kmap(page);
2435 ring->status_page.obj = default_ctx_obj;
2437 I915_WRITE(RING_HWS_PGA(ring->mmio_base),
2438 (u32)ring->status_page.gfx_addr);
2439 POSTING_READ(RING_HWS_PGA(ring->mmio_base));
2443 * intel_lr_context_deferred_alloc() - create the LRC specific bits of a context
2444 * @ctx: LR context to create.
2445 * @ring: engine to be used with the context.
2447 * This function can be called more than once, with different engines, if we plan
2448 * to use the context with them. The context backing objects and the ringbuffers
2449 * (specially the ringbuffer backing objects) suck a lot of memory up, and that's why
2450 * the creation is a deferred call: it's better to make sure first that we need to use
2451 * a given ring with the context.
2453 * Return: non-zero on error.
2456 int intel_lr_context_deferred_alloc(struct intel_context *ctx,
2457 struct intel_engine_cs *ring)
2459 struct drm_device *dev = ring->dev;
2460 struct drm_i915_gem_object *ctx_obj;
2461 uint32_t context_size;
2462 struct intel_ringbuffer *ringbuf;
2465 WARN_ON(ctx->legacy_hw_ctx.rcs_state != NULL);
2466 WARN_ON(ctx->engine[ring->id].state);
2468 context_size = round_up(get_lr_context_size(ring), 4096);
2470 /* One extra page as the sharing data between driver and GuC */
2471 context_size += PAGE_SIZE * LRC_PPHWSP_PN;
2473 ctx_obj = i915_gem_alloc_object(dev, context_size);
2475 DRM_DEBUG_DRIVER("Alloc LRC backing obj failed.\n");
2479 ringbuf = intel_engine_create_ringbuffer(ring, 4 * PAGE_SIZE);
2480 if (IS_ERR(ringbuf)) {
2481 ret = PTR_ERR(ringbuf);
2482 goto error_deref_obj;
2485 ret = populate_lr_context(ctx, ctx_obj, ring, ringbuf);
2487 DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret);
2491 ctx->engine[ring->id].ringbuf = ringbuf;
2492 ctx->engine[ring->id].state = ctx_obj;
2494 if (ctx != ring->default_context && ring->init_context) {
2495 struct drm_i915_gem_request *req;
2497 ret = i915_gem_request_alloc(ring,
2500 DRM_ERROR("ring create req: %d\n",
2505 ret = ring->init_context(req);
2507 DRM_ERROR("ring init context: %d\n",
2509 i915_gem_request_cancel(req);
2512 i915_add_request_no_flush(req);
2517 intel_ringbuffer_free(ringbuf);
2519 drm_gem_object_unreference(&ctx_obj->base);
2520 ctx->engine[ring->id].ringbuf = NULL;
2521 ctx->engine[ring->id].state = NULL;
2525 void intel_lr_context_reset(struct drm_device *dev,
2526 struct intel_context *ctx)
2528 struct drm_i915_private *dev_priv = dev->dev_private;
2529 struct intel_engine_cs *ring;
2532 for_each_ring(ring, dev_priv, i) {
2533 struct drm_i915_gem_object *ctx_obj =
2534 ctx->engine[ring->id].state;
2535 struct intel_ringbuffer *ringbuf =
2536 ctx->engine[ring->id].ringbuf;
2537 uint32_t *reg_state;
2538 struct vm_page *page;
2543 if (i915_gem_object_get_pages(ctx_obj)) {
2544 WARN(1, "Failed get_pages for context obj\n");
2547 page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
2548 reg_state = kmap_atomic(page);
2550 reg_state[CTX_RING_HEAD+1] = 0;
2551 reg_state[CTX_RING_TAIL+1] = 0;
2553 kunmap_atomic(reg_state);