sys/dev/drm/i915kms/intel_iic.c

   1 /*
   2  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright © 2006-2008,2010 Intel Corporation
   4  *   Jesse Barnes <jesse.barnes@intel.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23  * DEALINGS IN THE SOFTWARE.
  24  *
  25  * Authors:
  26  *      Eric Anholt <eric@anholt.net>
  27  *      Chris Wilson <chris@chris-wilson.co.uk>
  28  *
  29  * Copyright (c) 2011 The FreeBSD Foundation
  30  * All rights reserved.
  31  *
  32  * This software was developed by Konstantin Belousov under sponsorship from
  33  * the FreeBSD Foundation.
  34  *
  35  * Redistribution and use in source and binary forms, with or without
  36  * modification, are permitted provided that the following conditions
  37  * are met:
  38  * 1. Redistributions of source code must retain the above copyright
  39  *    notice, this list of conditions and the following disclaimer.
  40  * 2. Redistributions in binary form must reproduce the above copyright
  41  *    notice, this list of conditions and the following disclaimer in the
  42  *    documentation and/or other materials provided with the distribution.
  43  *
  44  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  45  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  46  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  47  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  48  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  49  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  50  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  51  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  52  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  53  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  54  * SUCH DAMAGE.
  55  *
  56  * $FreeBSD: head/sys/dev/drm2/i915/intel_iic.c 249041 2013-04-03 08:27:35Z dumbbell $
  57  */
  58
  59 #include <sys/mplock2.h>
  60
  61 #include <dev/drm/drmP.h>
  62 #include <dev/drm/drm.h>
  63 #include "i915_drm.h"
  64 #include "i915_drv.h"
  65 #include "intel_drv.h"
  66 #include <bus/iicbus/iic.h>
  67 #include <bus/iicbus/iiconf.h>
  68 #include <bus/iicbus/iicbus.h>
  69 #include "iicbus_if.h"
  70 #include "iicbb_if.h"
  71
  72 static int intel_iic_quirk_xfer(device_t idev, struct iic_msg *msgs, int nmsgs);
  73 static void intel_teardown_gmbus_m(struct drm_device *dev, int m);
  74
  75 /* Intel GPIO access functions */
  76
  77 #define I2C_RISEFALL_TIME 10
  78
  79 struct intel_iic_softc {
  80         struct drm_device *drm_dev;
  81         device_t iic_dev;
  82         bool force_bit_dev;
  83         char name[32];
  84         uint32_t reg;
  85         uint32_t reg0;
  86 };
  87
  88 static void
  89 intel_iic_quirk_set(struct drm_i915_private *dev_priv, bool enable)
  90 {
  91         u32 val;
  92
  93         /* When using bit bashing for I2C, this bit needs to be set to 1 */
  94         if (!IS_PINEVIEW(dev_priv->dev))
  95                 return;
  96
  97         val = I915_READ(DSPCLK_GATE_D);
  98         if (enable)
  99                 val |= DPCUNIT_CLOCK_GATE_DISABLE;
 100         else
 101                 val &= ~DPCUNIT_CLOCK_GATE_DISABLE;
 102         I915_WRITE(DSPCLK_GATE_D, val);
 103 }
 104
 105 static u32
 106 intel_iic_get_reserved(device_t idev)
 107 {
 108         struct intel_iic_softc *sc;
 109         struct drm_device *dev;
 110         struct drm_i915_private *dev_priv;
 111         u32 reserved;
 112
 113         sc = device_get_softc(idev);
 114         dev = sc->drm_dev;
 115         dev_priv = dev->dev_private;
 116
 117         if (!IS_I830(dev) && !IS_845G(dev)) {
 118                 reserved = I915_READ_NOTRACE(sc->reg) &
 119                     (GPIO_DATA_PULLUP_DISABLE | GPIO_CLOCK_PULLUP_DISABLE);
 120         } else {
 121                 reserved = 0;
 122         }
 123
 124         return (reserved);
 125 }
 126
 127 void
 128 intel_iic_reset(struct drm_device *dev)
 129 {
 130         struct drm_i915_private *dev_priv;
 131
 132         dev_priv = dev->dev_private;
 133         if (HAS_PCH_SPLIT(dev))
 134                 I915_WRITE(PCH_GMBUS0, 0);
 135         else
 136                 I915_WRITE(GMBUS0, 0);
 137 }
 138
 139 static int
 140 intel_iicbus_reset(device_t idev, u_char speed, u_char addr, u_char *oldaddr)
 141 {
 142         struct intel_iic_softc *sc;
 143         struct drm_device *dev;
 144
 145         sc = device_get_softc(idev);
 146         dev = sc->drm_dev;
 147
 148         intel_iic_reset(dev);
 149         return (0);
 150 }
 151
 152 static void
 153 intel_iicbb_setsda(device_t idev, int val)
 154 {
 155         struct intel_iic_softc *sc;
 156         struct drm_i915_private *dev_priv;
 157         u32 reserved;
 158         u32 data_bits;
 159
 160         sc = device_get_softc(idev);
 161         dev_priv = sc->drm_dev->dev_private;
 162
 163         reserved = intel_iic_get_reserved(idev);
 164         if (val)
 165                 data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK;
 166         else
 167                 data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK |
 168                     GPIO_DATA_VAL_MASK;
 169
 170         I915_WRITE_NOTRACE(sc->reg, reserved | data_bits);
 171         POSTING_READ(sc->reg);
 172 }
 173
 174 static void
 175 intel_iicbb_setscl(device_t idev, int val)
 176 {
 177         struct intel_iic_softc *sc;
 178         struct drm_i915_private *dev_priv;
 179         u32 clock_bits, reserved;
 180
 181         sc = device_get_softc(idev);
 182         dev_priv = sc->drm_dev->dev_private;
 183
 184         reserved = intel_iic_get_reserved(idev);
 185         if (val)
 186                 clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK;
 187         else
 188                 clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK |
 189                     GPIO_CLOCK_VAL_MASK;
 190
 191         I915_WRITE_NOTRACE(sc->reg, reserved | clock_bits);
 192         POSTING_READ(sc->reg);
 193 }
 194
 195 static int
 196 intel_iicbb_getsda(device_t idev)
 197 {
 198         struct intel_iic_softc *sc;
 199         struct drm_i915_private *dev_priv;
 200         u32 reserved;
 201
 202         sc = device_get_softc(idev);
 203         dev_priv = sc->drm_dev->dev_private;
 204
 205         reserved = intel_iic_get_reserved(idev);
 206
 207         I915_WRITE_NOTRACE(sc->reg, reserved | GPIO_DATA_DIR_MASK);
 208         I915_WRITE_NOTRACE(sc->reg, reserved);
 209         return ((I915_READ_NOTRACE(sc->reg) & GPIO_DATA_VAL_IN) != 0);
 210 }
 211
 212 static int
 213 intel_iicbb_getscl(device_t idev)
 214 {
 215         struct intel_iic_softc *sc;
 216         struct drm_i915_private *dev_priv;
 217         u32 reserved;
 218
 219         sc = device_get_softc(idev);
 220         dev_priv = sc->drm_dev->dev_private;
 221
 222         reserved = intel_iic_get_reserved(idev);
 223
 224         I915_WRITE_NOTRACE(sc->reg, reserved | GPIO_CLOCK_DIR_MASK);
 225         I915_WRITE_NOTRACE(sc->reg, reserved);
 226         return ((I915_READ_NOTRACE(sc->reg) & GPIO_CLOCK_VAL_IN) != 0);
 227 }
 228
 229 static int
 230 intel_gmbus_transfer(device_t idev, struct iic_msg *msgs, uint32_t nmsgs)
 231 {
 232         struct intel_iic_softc *sc;
 233         struct drm_i915_private *dev_priv;
 234         u8 *buf;
 235         int error, i, reg_offset, unit;
 236         u32 val, loop;
 237         u16 len;
 238
 239         sc = device_get_softc(idev);
 240         dev_priv = sc->drm_dev->dev_private;
 241         unit = device_get_unit(idev);
 242
 243         lockmgr(&dev_priv->gmbus_lock, LK_EXCLUSIVE);
 244         if (sc->force_bit_dev) {
 245                 error = intel_iic_quirk_xfer(dev_priv->bbbus[unit], msgs, nmsgs);
 246                 goto out;
 247         }
 248
 249         reg_offset = HAS_PCH_SPLIT(dev_priv->dev) ? PCH_GMBUS0 - GMBUS0 : 0;
 250
 251         I915_WRITE(GMBUS0 + reg_offset, sc->reg0);
 252
 253         for (i = 0; i < nmsgs; i++) {
 254                 len = msgs[i].len;
 255                 buf = msgs[i].buf;
 256
 257                 if ((msgs[i].flags & IIC_M_RD) != 0) {
 258                         I915_WRITE(GMBUS1 + reg_offset, GMBUS_CYCLE_WAIT |
 259                             (i + 1 == nmsgs ? GMBUS_CYCLE_STOP : 0) |
 260                             (len << GMBUS_BYTE_COUNT_SHIFT) |
 261                             (msgs[i].slave << (GMBUS_SLAVE_ADDR_SHIFT - 1)) |
 262                             GMBUS_SLAVE_READ | GMBUS_SW_RDY);
 263                         POSTING_READ(GMBUS2 + reg_offset);
 264                         do {
 265                                 loop = 0;
 266
 267                                 if (_intel_wait_for(sc->drm_dev,
 268                                     (I915_READ(GMBUS2 + reg_offset) &
 269                                         (GMBUS_SATOER | GMBUS_HW_RDY)) != 0,
 270                                     50, 1, "915gbr"))
 271                                         goto timeout;
 272                                 if ((I915_READ(GMBUS2 + reg_offset) &
 273                                     GMBUS_SATOER) != 0)
 274                                         goto clear_err;
 275
 276                                 val = I915_READ(GMBUS3 + reg_offset);
 277                                 do {
 278                                         *buf++ = val & 0xff;
 279                                         val >>= 8;
 280                                 } while (--len != 0 && ++loop < 4);
 281                         } while (len != 0);
 282                 } else {
 283                         val = loop = 0;
 284                         do {
 285                                 val |= *buf++ << (8 * loop);
 286                         } while (--len != 0 && ++loop < 4);
 287
 288                         I915_WRITE(GMBUS3 + reg_offset, val);
 289                         I915_WRITE(GMBUS1 + reg_offset, GMBUS_CYCLE_WAIT |
 290                             (i + 1 == nmsgs ? GMBUS_CYCLE_STOP : 0) |
 291                             (msgs[i].len << GMBUS_BYTE_COUNT_SHIFT) |
 292                             (msgs[i].slave << (GMBUS_SLAVE_ADDR_SHIFT - 1)) |
 293                             GMBUS_SLAVE_WRITE | GMBUS_SW_RDY);
 294                         POSTING_READ(GMBUS2+reg_offset);
 295
 296                         while (len != 0) {
 297                                 if (_intel_wait_for(sc->drm_dev,
 298                                     (I915_READ(GMBUS2 + reg_offset) &
 299                                         (GMBUS_SATOER | GMBUS_HW_RDY)) != 0,
 300                                     50, 1, "915gbw"))
 301                                         goto timeout;
 302                                 if (I915_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
 303                                         goto clear_err;
 304
 305                                 val = loop = 0;
 306                                 do {
 307                                         val |= *buf++ << (8 * loop);
 308                                 } while (--len != 0 && ++loop < 4);
 309
 310                                 I915_WRITE(GMBUS3 + reg_offset, val);
 311                                 POSTING_READ(GMBUS2 + reg_offset);
 312                         }
 313                 }
 314
 315                 if (i + 1 < nmsgs && _intel_wait_for(sc->drm_dev,
 316                     (I915_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER |
 317                         GMBUS_HW_WAIT_PHASE)) != 0,
 318                     50, 1, "915gbh"))
 319                         goto timeout;
 320                 if ((I915_READ(GMBUS2 + reg_offset) & GMBUS_SATOER) != 0)
 321                         goto clear_err;
 322         }
 323
 324         error = 0;
 325 done:
 326         /* Mark the GMBUS interface as disabled after waiting for idle.
 327          * We will re-enable it at the start of the next xfer,
 328          * till then let it sleep.
 329          */
 330         if (_intel_wait_for(dev,
 331             (I915_READ(GMBUS2 + reg_offset) & GMBUS_ACTIVE) == 0,
 332             10, 1, "915gbu"))
 333                 DRM_INFO("GMBUS timed out waiting for idle\n");
 334         I915_WRITE(GMBUS0 + reg_offset, 0);
 335 out:
 336         lockmgr(&dev_priv->gmbus_lock, LK_RELEASE);
 337         return (error);
 338
 339 clear_err:
 340         /* Toggle the Software Clear Interrupt bit. This has the effect
 341          * of resetting the GMBUS controller and so clearing the
 342          * BUS_ERROR raised by the slave's NAK.
 343          */
 344         I915_WRITE(GMBUS1 + reg_offset, GMBUS_SW_CLR_INT);
 345         I915_WRITE(GMBUS1 + reg_offset, 0);
 346         error = EIO;
 347         goto done;
 348
 349 timeout:
 350         DRM_INFO("GMBUS timed out, falling back to bit banging on pin %d [%s]\n",
 351             sc->reg0 & 0xff, sc->name);
 352         I915_WRITE(GMBUS0 + reg_offset, 0);
 353
 354         /*
 355          * Hardware may not support GMBUS over these pins?
 356          * Try GPIO bitbanging instead.
 357          */
 358         sc->force_bit_dev = true;
 359
 360         error = intel_iic_quirk_xfer(dev_priv->bbbus[unit], msgs, nmsgs);
 361         goto out;
 362 }
 363
 364 void
 365 intel_gmbus_set_speed(device_t idev, int speed)
 366 {
 367         struct intel_iic_softc *sc;
 368
 369         sc = device_get_softc(device_get_parent(idev));
 370
 371         sc->reg0 = (sc->reg0 & ~(0x3 << 8)) | speed;
 372 }
 373
 374 void
 375 intel_gmbus_force_bit(device_t idev, bool force_bit)
 376 {
 377         struct intel_iic_softc *sc;
 378
 379         sc = device_get_softc(device_get_parent(idev));
 380         sc->force_bit_dev = force_bit;
 381 }
 382
 383 static int
 384 intel_iic_quirk_xfer(device_t idev, struct iic_msg *msgs, int nmsgs)
 385 {
 386         device_t bridge_dev;
 387         struct intel_iic_softc *sc;
 388         struct drm_i915_private *dev_priv;
 389         int ret;
 390         int i;
 391
 392         bridge_dev = device_get_parent(device_get_parent(idev));
 393         sc = device_get_softc(bridge_dev);
 394         dev_priv = sc->drm_dev->dev_private;
 395
 396         intel_iic_reset(sc->drm_dev);
 397         intel_iic_quirk_set(dev_priv, true);
 398         IICBB_SETSDA(bridge_dev, 1);
 399         IICBB_SETSCL(bridge_dev, 1);
 400         DELAY(I2C_RISEFALL_TIME);
 401
 402         for (i = 0; i < nmsgs - 1; i++) {
 403                 /* force use of repeated start instead of default stop+start */
 404                 msgs[i].flags |= IIC_M_NOSTOP;
 405         }
 406         ret = iicbus_transfer(idev, msgs, nmsgs);
 407         IICBB_SETSDA(bridge_dev, 1);
 408         IICBB_SETSCL(bridge_dev, 1);
 409         intel_iic_quirk_set(dev_priv, false);
 410
 411         return (ret);
 412 }
 413
 414 static const char *gpio_names[GMBUS_NUM_PORTS] = {
 415         "disabled",
 416         "ssc",
 417         "vga",
 418         "panel",
 419         "dpc",
 420         "dpb",
 421         "reserved",
 422         "dpd",
 423 };
 424
 425 static int
 426 intel_gmbus_probe(device_t dev)
 427 {
 428
 429         return (BUS_PROBE_SPECIFIC);
 430 }
 431
 432 static int
 433 intel_gmbus_attach(device_t idev)
 434 {
 435         struct drm_i915_private *dev_priv;
 436         struct intel_iic_softc *sc;
 437         int pin;
 438
 439         sc = device_get_softc(idev);
 440         sc->drm_dev = device_get_softc(device_get_parent(idev));
 441         dev_priv = sc->drm_dev->dev_private;
 442         pin = device_get_unit(idev);
 443
 444         ksnprintf(sc->name, sizeof(sc->name), "gmbus bus %s", gpio_names[pin]);
 445         device_set_desc(idev, sc->name);
 446
 447         /* By default use a conservative clock rate */
 448         sc->reg0 = pin | GMBUS_RATE_100KHZ;
 449
 450         /* XXX force bit banging until GMBUS is fully debugged */
 451         if (IS_GEN2(sc->drm_dev)) {
 452                 sc->force_bit_dev = true;
 453         }
 454
 455         /* add bus interface device */
 456         sc->iic_dev = device_add_child(idev, "iicbus", -1);
 457         if (sc->iic_dev == NULL)
 458                 return (ENXIO);
 459         device_quiet(sc->iic_dev);
 460         bus_generic_attach(idev);
 461
 462         return (0);
 463 }
 464
 465 static int
 466 intel_gmbus_detach(device_t idev)
 467 {
 468         struct intel_iic_softc *sc;
 469         struct drm_i915_private *dev_priv;
 470         device_t child;
 471         int u;
 472
 473         sc = device_get_softc(idev);
 474         u = device_get_unit(idev);
 475         dev_priv = sc->drm_dev->dev_private;
 476
 477         child = sc->iic_dev;
 478         bus_generic_detach(idev);
 479         if (child != NULL)
 480                 device_delete_child(idev, child);
 481
 482         return (0);
 483 }
 484
 485 static int
 486 intel_iicbb_probe(device_t dev)
 487 {
 488
 489         return (BUS_PROBE_DEFAULT);
 490 }
 491
 492 static int
 493 intel_iicbb_attach(device_t idev)
 494 {
 495         static const int map_pin_to_reg[] = {
 496                 0,
 497                 GPIOB,
 498                 GPIOA,
 499                 GPIOC,
 500                 GPIOD,
 501                 GPIOE,
 502                 0,
 503                 GPIOF
 504         };
 505
 506         struct intel_iic_softc *sc;
 507         struct drm_i915_private *dev_priv;
 508         int pin;
 509
 510         sc = device_get_softc(idev);
 511         sc->drm_dev = device_get_softc(device_get_parent(idev));
 512         dev_priv = sc->drm_dev->dev_private;
 513         pin = device_get_unit(idev);
 514
 515         ksnprintf(sc->name, sizeof(sc->name), "i915 iicbb %s", gpio_names[pin]);
 516         device_set_desc(idev, sc->name);
 517
 518         sc->reg0 = pin | GMBUS_RATE_100KHZ;
 519         sc->reg = map_pin_to_reg[pin];
 520         if (HAS_PCH_SPLIT(dev_priv->dev))
 521                 sc->reg += PCH_GPIOA - GPIOA;
 522
 523         /* add generic bit-banging code */
 524         sc->iic_dev = device_add_child(idev, "iicbb", -1);
 525         if (sc->iic_dev == NULL)
 526                 return (ENXIO);
 527         device_quiet(sc->iic_dev);
 528         bus_generic_attach(idev);
 529
 530         return (0);
 531 }
 532
 533 static int
 534 intel_iicbb_detach(device_t idev)
 535 {
 536         struct intel_iic_softc *sc;
 537         device_t child;
 538
 539         sc = device_get_softc(idev);
 540         child = sc->iic_dev;
 541         bus_generic_detach(idev);
 542         if (child)
 543                 device_delete_child(idev, child);
 544         return (0);
 545 }
 546
 547 static device_method_t intel_gmbus_methods[] = {
 548         DEVMETHOD(device_probe,         intel_gmbus_probe),
 549         DEVMETHOD(device_attach,        intel_gmbus_attach),
 550         DEVMETHOD(device_detach,        intel_gmbus_detach),
 551         DEVMETHOD(iicbus_reset,         intel_iicbus_reset),
 552         DEVMETHOD(iicbus_transfer,      intel_gmbus_transfer),
 553         DEVMETHOD_END
 554 };
 555 static driver_t intel_gmbus_driver = {
 556         "intel_gmbus",
 557         intel_gmbus_methods,
 558         sizeof(struct intel_iic_softc)
 559 };
 560 static devclass_t intel_gmbus_devclass;
 561 DRIVER_MODULE_ORDERED(intel_gmbus, drm, intel_gmbus_driver,
 562     intel_gmbus_devclass, 0, 0, SI_ORDER_FIRST);
 563 DRIVER_MODULE(iicbus, intel_gmbus, iicbus_driver, iicbus_devclass, 0, 0);
 564
 565 static device_method_t intel_iicbb_methods[] =  {
 566         DEVMETHOD(device_probe,         intel_iicbb_probe),
 567         DEVMETHOD(device_attach,        intel_iicbb_attach),
 568         DEVMETHOD(device_detach,        intel_iicbb_detach),
 569
 570         DEVMETHOD(bus_add_child,        bus_generic_add_child),
 571         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 572
 573         DEVMETHOD(iicbb_callback,       iicbus_null_callback),
 574         DEVMETHOD(iicbb_reset,          intel_iicbus_reset),
 575         DEVMETHOD(iicbb_setsda,         intel_iicbb_setsda),
 576         DEVMETHOD(iicbb_setscl,         intel_iicbb_setscl),
 577         DEVMETHOD(iicbb_getsda,         intel_iicbb_getsda),
 578         DEVMETHOD(iicbb_getscl,         intel_iicbb_getscl),
 579         DEVMETHOD_END
 580 };
 581 static driver_t intel_iicbb_driver = {
 582         "intel_iicbb",
 583         intel_iicbb_methods,
 584         sizeof(struct intel_iic_softc)
 585 };
 586 static devclass_t intel_iicbb_devclass;
 587 DRIVER_MODULE_ORDERED(intel_iicbb, drm, intel_iicbb_driver,
 588     intel_iicbb_devclass, 0, 0, SI_ORDER_FIRST);
 589 DRIVER_MODULE(iicbb, intel_iicbb, iicbb_driver, iicbb_devclass, 0, 0);
 590
 591 int
 592 intel_setup_gmbus(struct drm_device *dev)
 593 {
 594         struct drm_i915_private *dev_priv;
 595         device_t iic_dev;
 596         int i, ret;
 597
 598         dev_priv = dev->dev_private;
 599         lockinit(&dev_priv->gmbus_lock, "gmbus", 0, LK_CANRECURSE);
 600         dev_priv->gmbus_bridge = kmalloc(sizeof(device_t) * GMBUS_NUM_PORTS,
 601             DRM_MEM_DRIVER, M_WAITOK | M_ZERO);
 602         dev_priv->bbbus_bridge = kmalloc(sizeof(device_t) * GMBUS_NUM_PORTS,
 603             DRM_MEM_DRIVER, M_WAITOK | M_ZERO);
 604         dev_priv->gmbus = kmalloc(sizeof(device_t) * GMBUS_NUM_PORTS,
 605             DRM_MEM_DRIVER, M_WAITOK | M_ZERO);
 606         dev_priv->bbbus = kmalloc(sizeof(device_t) * GMBUS_NUM_PORTS,
 607             DRM_MEM_DRIVER, M_WAITOK | M_ZERO);
 608
 609         /*
 610          * The Giant there is recursed, most likely.  Normally, the
 611          * intel_setup_gmbus() is called from the attach method of the
 612          * driver.
 613          */
 614         get_mplock();
 615         for (i = 0; i < GMBUS_NUM_PORTS; i++) {
 616                 /*
 617                  * Initialized bbbus_bridge before gmbus_bridge, since
 618                  * gmbus may decide to force quirk transfer in the
 619                  * attachment code.
 620                  */
 621                 dev_priv->bbbus_bridge[i] = device_add_child(dev->device,
 622                     "intel_iicbb", i);
 623                 if (dev_priv->bbbus_bridge[i] == NULL) {
 624                         DRM_ERROR("bbbus bridge %d creation failed\n", i);
 625                         ret = ENXIO;
 626                         goto err;
 627                 }
 628                 device_quiet(dev_priv->bbbus_bridge[i]);
 629                 ret = device_probe_and_attach(dev_priv->bbbus_bridge[i]);
 630                 if (ret != 0) {
 631                         DRM_ERROR("bbbus bridge %d attach failed, %d\n", i,
 632                             ret);
 633                         goto err;
 634                 }
 635
 636                 iic_dev = device_find_child(dev_priv->bbbus_bridge[i], "iicbb",
 637                     -1);
 638                 if (iic_dev == NULL) {
 639                         DRM_ERROR("bbbus bridge doesn't have iicbb child\n");
 640                         goto err;
 641                 }
 642                 iic_dev = device_find_child(iic_dev, "iicbus", -1);
 643                 if (iic_dev == NULL) {
 644                         DRM_ERROR(
 645                 "bbbus bridge doesn't have iicbus grandchild\n");
 646                         goto err;
 647                 }
 648
 649                 dev_priv->bbbus[i] = iic_dev;
 650
 651                 dev_priv->gmbus_bridge[i] = device_add_child(dev->device,
 652                     "intel_gmbus", i);
 653                 if (dev_priv->gmbus_bridge[i] == NULL) {
 654                         DRM_ERROR("gmbus bridge %d creation failed\n", i);
 655                         ret = ENXIO;
 656                         goto err;
 657                 }
 658                 device_quiet(dev_priv->gmbus_bridge[i]);
 659                 ret = device_probe_and_attach(dev_priv->gmbus_bridge[i]);
 660                 if (ret != 0) {
 661                         DRM_ERROR("gmbus bridge %d attach failed, %d\n", i,
 662                             ret);
 663                         ret = ENXIO;
 664                         goto err;
 665                 }
 666
 667                 iic_dev = device_find_child(dev_priv->gmbus_bridge[i],
 668                     "iicbus", -1);
 669                 if (iic_dev == NULL) {
 670                         DRM_ERROR("gmbus bridge doesn't have iicbus child\n");
 671                         goto err;
 672                 }
 673                 dev_priv->gmbus[i] = iic_dev;
 674
 675                 intel_iic_reset(dev);
 676         }
 677
 678         rel_mplock();
 679         return (0);
 680
 681 err:
 682         intel_teardown_gmbus_m(dev, i);
 683         rel_mplock();
 684         return (ret);
 685 }
 686
 687 static void
 688 intel_teardown_gmbus_m(struct drm_device *dev, int m)
 689 {
 690         struct drm_i915_private *dev_priv;
 691
 692         dev_priv = dev->dev_private;
 693
 694         drm_free(dev_priv->gmbus, DRM_MEM_DRIVER);
 695         dev_priv->gmbus = NULL;
 696         drm_free(dev_priv->bbbus, DRM_MEM_DRIVER);
 697         dev_priv->bbbus = NULL;
 698         drm_free(dev_priv->gmbus_bridge, DRM_MEM_DRIVER);
 699         dev_priv->gmbus_bridge = NULL;
 700         drm_free(dev_priv->bbbus_bridge, DRM_MEM_DRIVER);
 701         dev_priv->bbbus_bridge = NULL;
 702         lockuninit(&dev_priv->gmbus_lock);
 703 }
 704
 705 void
 706 intel_teardown_gmbus(struct drm_device *dev)
 707 {
 708
 709         get_mplock();
 710         intel_teardown_gmbus_m(dev, GMBUS_NUM_PORTS);
 711         rel_mplock();
 712 }