sys/dev/drm/i915/intel_csr.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24 #include <linux/firmware.h>
  25 #include "i915_drv.h"
  26 #include "i915_reg.h"
  27 #include "intel_drv.h"
  28
  29 /**
  30  * DOC: csr support for dmc
  31  *
  32  * Display Context Save and Restore (CSR) firmware support added from gen9
  33  * onwards to drive newly added DMC (Display microcontroller) in display
  34  * engine to save and restore the state of display engine when it enter into
  35  * low-power state and comes back to normal.
  36  *
  37  * Firmware loading status will be one of the below states: FW_UNINITIALIZED,
  38  * FW_LOADED, FW_FAILED.
  39  *
  40  * Once the firmware is written into the registers status will be moved from
  41  * FW_UNINITIALIZED to FW_LOADED and for any erroneous condition status will
  42  * be moved to FW_FAILED.
  43  */
  44
  45 #define I915_CSR_SKL "i915/skl_dmc_ver1.bin"
  46 #define I915_CSR_BXT "i915/bxt_dmc_ver1.bin"
  47
  48 MODULE_FIRMWARE(I915_CSR_SKL);
  49 MODULE_FIRMWARE(I915_CSR_BXT);
  50
  51 /*
  52 * SKL CSR registers for DC5 and DC6
  53 */
  54 #define CSR_PROGRAM(i)                  (0x80000 + (i) * 4)
  55 #define CSR_SSP_BASE_ADDR_GEN9          0x00002FC0
  56 #define CSR_HTP_ADDR_SKL                0x00500034
  57 #define CSR_SSP_BASE                    0x8F074
  58 #define CSR_HTP_SKL                     0x8F004
  59 #define CSR_LAST_WRITE                  0x8F034
  60 #define CSR_LAST_WRITE_VALUE            0xc003b400
  61 /* MMIO address range for CSR program (0x80000 - 0x82FFF) */
  62 #define CSR_MAX_FW_SIZE                 0x2FFF
  63 #define CSR_DEFAULT_FW_OFFSET           0xFFFFFFFF
  64 #define CSR_MMIO_START_RANGE    0x80000
  65 #define CSR_MMIO_END_RANGE              0x8FFFF
  66
  67 struct intel_css_header {
  68         /* 0x09 for DMC */
  69         uint32_t module_type;
  70
  71         /* Includes the DMC specific header in dwords */
  72         uint32_t header_len;
  73
  74         /* always value would be 0x10000 */
  75         uint32_t header_ver;
  76
  77         /* Not used */
  78         uint32_t module_id;
  79
  80         /* Not used */
  81         uint32_t module_vendor;
  82
  83         /* in YYYYMMDD format */
  84         uint32_t date;
  85
  86         /* Size in dwords (CSS_Headerlen + PackageHeaderLen + dmc FWsLen)/4 */
  87         uint32_t size;
  88
  89         /* Not used */
  90         uint32_t key_size;
  91
  92         /* Not used */
  93         uint32_t modulus_size;
  94
  95         /* Not used */
  96         uint32_t exponent_size;
  97
  98         /* Not used */
  99         uint32_t reserved1[12];
 100
 101         /* Major Minor */
 102         uint32_t version;
 103
 104         /* Not used */
 105         uint32_t reserved2[8];
 106
 107         /* Not used */
 108         uint32_t kernel_header_info;
 109 } __packed;
 110
 111 struct intel_fw_info {
 112         uint16_t reserved1;
 113
 114         /* Stepping (A, B, C, ..., *). * is a wildcard */
 115         char stepping;
 116
 117         /* Sub-stepping (0, 1, ..., *). * is a wildcard */
 118         char substepping;
 119
 120         uint32_t offset;
 121         uint32_t reserved2;
 122 } __packed;
 123
 124 struct intel_package_header {
 125         /* DMC container header length in dwords */
 126         unsigned char header_len;
 127
 128         /* always value would be 0x01 */
 129         unsigned char header_ver;
 130
 131         unsigned char reserved[10];
 132
 133         /* Number of valid entries in the FWInfo array below */
 134         uint32_t num_entries;
 135
 136         struct intel_fw_info fw_info[20];
 137 } __packed;
 138
 139 struct intel_dmc_header {
 140         /* always value would be 0x40403E3E */
 141         uint32_t signature;
 142
 143         /* DMC binary header length */
 144         unsigned char header_len;
 145
 146         /* 0x01 */
 147         unsigned char header_ver;
 148
 149         /* Reserved */
 150         uint16_t dmcc_ver;
 151
 152         /* Major, Minor */
 153         uint32_t        project;
 154
 155         /* Firmware program size (excluding header) in dwords */
 156         uint32_t        fw_size;
 157
 158         /* Major Minor version */
 159         uint32_t fw_version;
 160
 161         /* Number of valid MMIO cycles present. */
 162         uint32_t mmio_count;
 163
 164         /* MMIO address */
 165         uint32_t mmioaddr[8];
 166
 167         /* MMIO data */
 168         uint32_t mmiodata[8];
 169
 170         /* FW filename  */
 171         unsigned char dfile[32];
 172
 173         uint32_t reserved1[2];
 174 } __packed;
 175
 176 struct stepping_info {
 177         char stepping;
 178         char substepping;
 179 };
 180
 181 static const struct stepping_info skl_stepping_info[] = {
 182                 {'A', '0'}, {'B', '0'}, {'C', '0'},
 183                 {'D', '0'}, {'E', '0'}, {'F', '0'},
 184                 {'G', '0'}, {'H', '0'}, {'I', '0'}
 185 };
 186
 187 #if 0
 188 static struct stepping_info bxt_stepping_info[] = {
 189         {'A', '0'}, {'A', '1'}, {'A', '2'},
 190         {'B', '0'}, {'B', '1'}, {'B', '2'}
 191 };
 192
 193 static char intel_get_stepping(struct drm_device *dev)
 194 {
 195         if (IS_SKYLAKE(dev) && (dev->pdev->revision <
 196                         ARRAY_SIZE(skl_stepping_info)))
 197                 return skl_stepping_info[dev->pdev->revision].stepping;
 198         else if (IS_BROXTON(dev) && (dev->pdev->revision <
 199                                 ARRAY_SIZE(bxt_stepping_info)))
 200                 return bxt_stepping_info[dev->pdev->revision].stepping;
 201         else
 202                 return -ENODATA;
 203 }
 204
 205 static char intel_get_substepping(struct drm_device *dev)
 206 {
 207         if (IS_SKYLAKE(dev) && (dev->pdev->revision <
 208                         ARRAY_SIZE(skl_stepping_info)))
 209                 return skl_stepping_info[dev->pdev->revision].substepping;
 210         else if (IS_BROXTON(dev) && (dev->pdev->revision <
 211                         ARRAY_SIZE(bxt_stepping_info)))
 212                 return bxt_stepping_info[dev->pdev->revision].substepping;
 213         else
 214                 return -ENODATA;
 215 }
 216 #endif
 217
 218 /**
 219  * intel_csr_load_status_get() - to get firmware loading status.
 220  * @dev_priv: i915 device.
 221  *
 222  * This function helps to get the firmware loading status.
 223  *
 224  * Return: Firmware loading status.
 225  */
 226 enum csr_state intel_csr_load_status_get(struct drm_i915_private *dev_priv)
 227 {
 228         enum csr_state state;
 229
 230         mutex_lock(&dev_priv->csr_lock);
 231         state = dev_priv->csr.state;
 232         mutex_unlock(&dev_priv->csr_lock);
 233
 234         return state;
 235 }
 236
 237 /**
 238  * intel_csr_load_status_set() - help to set firmware loading status.
 239  * @dev_priv: i915 device.
 240  * @state: enumeration of firmware loading status.
 241  *
 242  * Set the firmware loading status.
 243  */
 244 void intel_csr_load_status_set(struct drm_i915_private *dev_priv,
 245                         enum csr_state state)
 246 {
 247         mutex_lock(&dev_priv->csr_lock);
 248         dev_priv->csr.state = state;
 249         mutex_unlock(&dev_priv->csr_lock);
 250 }
 251
 252 /**
 253  * intel_csr_load_program() - write the firmware from memory to register.
 254  * @dev: drm device.
 255  *
 256  * CSR firmware is read from a .bin file and kept in internal memory one time.
 257  * Everytime display comes back from low power state this function is called to
 258  * copy the firmware from internal memory to registers.
 259  */
 260 void intel_csr_load_program(struct drm_device *dev)
 261 {
 262         struct drm_i915_private *dev_priv = dev->dev_private;
 263         u32 *payload = dev_priv->csr.dmc_payload;
 264         uint32_t i, fw_size;
 265
 266         if (!IS_GEN9(dev)) {
 267                 DRM_ERROR("No CSR support available for this platform\n");
 268                 return;
 269         }
 270
 271         /*
 272          * FIXME: Firmware gets lost on S3/S4, but not when entering system
 273          * standby or suspend-to-idle (which is just like forced runtime pm).
 274          * Unfortunately the ACPI subsystem doesn't yet give us a way to
 275          * differentiate this, hence figure it out with this hack.
 276          */
 277         if (I915_READ(CSR_PROGRAM(0)))
 278                 return;
 279
 280         mutex_lock(&dev_priv->csr_lock);
 281         fw_size = dev_priv->csr.dmc_fw_size;
 282         for (i = 0; i < fw_size; i++)
 283                 I915_WRITE(CSR_PROGRAM(i), payload[i]);
 284
 285         for (i = 0; i < dev_priv->csr.mmio_count; i++) {
 286                 I915_WRITE(dev_priv->csr.mmioaddr[i],
 287                         dev_priv->csr.mmiodata[i]);
 288         }
 289
 290         dev_priv->csr.state = FW_LOADED;
 291         mutex_unlock(&dev_priv->csr_lock);
 292 }
 293
 294 #if 0
 295 static void finish_csr_load(const struct firmware *fw, void *context)
 296 {
 297         struct drm_i915_private *dev_priv = context;
 298         struct drm_device *dev = dev_priv->dev;
 299         struct intel_css_header *css_header;
 300         struct intel_package_header *package_header;
 301         struct intel_dmc_header *dmc_header;
 302         struct intel_csr *csr = &dev_priv->csr;
 303         char stepping = intel_get_stepping(dev);
 304         char substepping = intel_get_substepping(dev);
 305         uint32_t dmc_offset = CSR_DEFAULT_FW_OFFSET, readcount = 0, nbytes;
 306         uint32_t i;
 307         uint32_t *dmc_payload;
 308         bool fw_loaded = false;
 309
 310         if (!fw) {
 311                 i915_firmware_load_error_print(csr->fw_path, 0);
 312                 goto out;
 313         }
 314
 315         if ((stepping == -ENODATA) || (substepping == -ENODATA)) {
 316                 DRM_ERROR("Unknown stepping info, firmware loading failed\n");
 317                 goto out;
 318         }
 319
 320         /* Extract CSS Header information*/
 321         css_header = (struct intel_css_header *)fw->data;
 322         if (sizeof(struct intel_css_header) !=
 323                 (css_header->header_len * 4)) {
 324                 DRM_ERROR("Firmware has wrong CSS header length %u bytes\n",
 325                         (css_header->header_len * 4));
 326                 goto out;
 327         }
 328         readcount += sizeof(struct intel_css_header);
 329
 330         /* Extract Package Header information*/
 331         package_header = (struct intel_package_header *)
 332                                         &fw->data[readcount];
 333         if (sizeof(struct intel_package_header) !=
 334                 (package_header->header_len * 4)) {
 335                 DRM_ERROR("Firmware has wrong package header length %u bytes\n",
 336                         (package_header->header_len * 4));
 337                 goto out;
 338         }
 339         readcount += sizeof(struct intel_package_header);
 340
 341         /* Search for dmc_offset to find firware binary. */
 342         for (i = 0; i < package_header->num_entries; i++) {
 343                 if (package_header->fw_info[i].substepping == '*' &&
 344                         stepping == package_header->fw_info[i].stepping) {
 345                         dmc_offset = package_header->fw_info[i].offset;
 346                         break;
 347                 } else if (stepping == package_header->fw_info[i].stepping &&
 348                         substepping == package_header->fw_info[i].substepping) {
 349                         dmc_offset = package_header->fw_info[i].offset;
 350                         break;
 351                 } else if (package_header->fw_info[i].stepping == '*' &&
 352                         package_header->fw_info[i].substepping == '*')
 353                         dmc_offset = package_header->fw_info[i].offset;
 354         }
 355         if (dmc_offset == CSR_DEFAULT_FW_OFFSET) {
 356                 DRM_ERROR("Firmware not supported for %c stepping\n", stepping);
 357                 goto out;
 358         }
 359         readcount += dmc_offset;
 360
 361         /* Extract dmc_header information. */
 362         dmc_header = (struct intel_dmc_header *)&fw->data[readcount];
 363         if (sizeof(struct intel_dmc_header) != (dmc_header->header_len)) {
 364                 DRM_ERROR("Firmware has wrong dmc header length %u bytes\n",
 365                                 (dmc_header->header_len));
 366                 goto out;
 367         }
 368         readcount += sizeof(struct intel_dmc_header);
 369
 370         /* Cache the dmc header info. */
 371         if (dmc_header->mmio_count > ARRAY_SIZE(csr->mmioaddr)) {
 372                 DRM_ERROR("Firmware has wrong mmio count %u\n",
 373                                                 dmc_header->mmio_count);
 374                 goto out;
 375         }
 376         csr->mmio_count = dmc_header->mmio_count;
 377         for (i = 0; i < dmc_header->mmio_count; i++) {
 378                 if (dmc_header->mmioaddr[i] < CSR_MMIO_START_RANGE ||
 379                         dmc_header->mmioaddr[i] > CSR_MMIO_END_RANGE) {
 380                         DRM_ERROR(" Firmware has wrong mmio address 0x%x\n",
 381                                                 dmc_header->mmioaddr[i]);
 382                         goto out;
 383                 }
 384                 csr->mmioaddr[i] = dmc_header->mmioaddr[i];
 385                 csr->mmiodata[i] = dmc_header->mmiodata[i];
 386         }
 387
 388         /* fw_size is in dwords, so multiplied by 4 to convert into bytes. */
 389         nbytes = dmc_header->fw_size * 4;
 390         if (nbytes > CSR_MAX_FW_SIZE) {
 391                 DRM_ERROR("CSR firmware too big (%u) bytes\n", nbytes);
 392                 goto out;
 393         }
 394         csr->dmc_fw_size = dmc_header->fw_size;
 395
 396         csr->dmc_payload = kmalloc(nbytes, M_DRM, M_WAITOK);
 397         if (!csr->dmc_payload) {
 398                 DRM_ERROR("Memory allocation failed for dmc payload\n");
 399                 goto out;
 400         }
 401
 402         dmc_payload = csr->dmc_payload;
 403         memcpy(dmc_payload, &fw->data[readcount], nbytes);
 404
 405         /* load csr program during system boot, as needed for DC states */
 406         intel_csr_load_program(dev);
 407         fw_loaded = true;
 408
 409         DRM_DEBUG_KMS("Finished loading %s\n", dev_priv->csr.fw_path);
 410 out:
 411         if (fw_loaded)
 412                 intel_runtime_pm_put(dev_priv);
 413         else
 414                 intel_csr_load_status_set(dev_priv, FW_FAILED);
 415
 416         release_firmware(fw);
 417 }
 418 #endif
 419
 420 /**
 421  * intel_csr_ucode_init() - initialize the firmware loading.
 422  * @dev: drm device.
 423  *
 424  * This function is called at the time of loading the display driver to read
 425  * firmware from a .bin file and copied into a internal memory.
 426  */
 427 void intel_csr_ucode_init(struct drm_device *dev)
 428 {
 429 #if 0
 430         struct drm_i915_private *dev_priv = dev->dev_private;
 431         struct intel_csr *csr = &dev_priv->csr;
 432         int ret;
 433
 434         if (!HAS_CSR(dev))
 435                 return;
 436
 437         if (IS_SKYLAKE(dev))
 438                 csr->fw_path = I915_CSR_SKL;
 439         else if (IS_BROXTON(dev_priv))
 440                 csr->fw_path = I915_CSR_BXT;
 441         else {
 442                 DRM_ERROR("Unexpected: no known CSR firmware for platform\n");
 443                 intel_csr_load_status_set(dev_priv, FW_FAILED);
 444                 return;
 445         }
 446
 447         DRM_DEBUG_KMS("Loading %s\n", csr->fw_path);
 448
 449         /*
 450          * Obtain a runtime pm reference, until CSR is loaded,
 451          * to avoid entering runtime-suspend.
 452          */
 453         intel_runtime_pm_get(dev_priv);
 454
 455         /* CSR supported for platform, load firmware */
 456         ret = request_firmware_nowait(THIS_MODULE, true, csr->fw_path,
 457                                 &dev_priv->dev->pdev->dev,
 458                                 GFP_KERNEL, dev_priv,
 459                                 finish_csr_load);
 460         if (ret) {
 461                 i915_firmware_load_error_print(csr->fw_path, ret);
 462                 intel_csr_load_status_set(dev_priv, FW_FAILED);
 463         }
 464 #endif
 465 }
 466
 467 /**
 468  * intel_csr_ucode_fini() - unload the CSR firmware.
 469  * @dev: drm device.
 470  *
 471  * Firmmware unloading includes freeing the internal momory and reset the
 472  * firmware loading status.
 473  */
 474 void intel_csr_ucode_fini(struct drm_device *dev)
 475 {
 476 #if 0
 477         struct drm_i915_private *dev_priv = dev->dev_private;
 478
 479         if (!HAS_CSR(dev))
 480                 return;
 481
 482         intel_csr_load_status_set(dev_priv, FW_FAILED);
 483         kfree(dev_priv->csr.dmc_payload);
 484 #endif
 485 }
 486
 487 void assert_csr_loaded(struct drm_i915_private *dev_priv)
 488 {
 489         WARN_ONCE(intel_csr_load_status_get(dev_priv) != FW_LOADED,
 490                   "CSR is not loaded.\n");
 491         WARN_ONCE(!I915_READ(CSR_PROGRAM(0)),
 492                   "CSR program storage start is NULL\n");
 493         WARN_ONCE(!I915_READ(CSR_SSP_BASE), "CSR SSP Base Not fine\n");
 494         WARN_ONCE(!I915_READ(CSR_HTP_SKL), "CSR HTP Not fine\n");
 495 }