sys/dev/disk/advansys/advansys.c

   1 /*
   2  * Generic driver for the Advanced Systems Inc. SCSI controllers
   3  * Product specific probe and attach routines can be found in:
   4  *
   5  * i386/isa/adv_isa.c   ABP5140, ABP542, ABP5150, ABP842, ABP852
   6  * i386/eisa/adv_eisa.c ABP742, ABP752
   7  * pci/adv_pci.c        ABP920, ABP930, ABP930U, ABP930UA, ABP940, ABP940U,
   8  *                      ABP940UA, ABP950, ABP960, ABP960U, ABP960UA,
   9  *                      ABP970, ABP970U
  10  *
  11  * Copyright (c) 1996-2000 Justin Gibbs.
  12  * All rights reserved.
  13  *
  14  * Redistribution and use in source and binary forms, with or without
  15  * modification, are permitted provided that the following conditions
  16  * are met:
  17  * 1. Redistributions of source code must retain the above copyright
  18  *    notice, this list of conditions, and the following disclaimer,
  19  *    without modification, immediately at the beginning of the file.
  20  * 2. The name of the author may not be used to endorse or promote products
  21  *    derived from this software without specific prior written permission.
  22  *
  23  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  24  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  25  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  26  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
  27  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  28  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  29  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  30  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  31  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  32  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  33  * SUCH DAMAGE.
  34  *
  35  * $FreeBSD: src/sys/dev/advansys/advansys.c,v 1.14.2.4 2002/01/06 21:21:42 dwmalone Exp $
  36  * $DragonFly: src/sys/dev/disk/advansys/advansys.c,v 1.5 2004/04/01 06:52:45 joerg Exp $
  37  */
  38 /*
  39  * Ported from:
  40  * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters
  41  *
  42  * Copyright (c) 1995-1997 Advanced System Products, Inc.
  43  * All Rights Reserved.
  44  *
  45  * Redistribution and use in source and binary forms, with or without
  46  * modification, are permitted provided that redistributions of source
  47  * code retain the above copyright notice and this comment without
  48  * modification.
  49  */
  50
  51 #include <sys/param.h>
  52 #include <sys/systm.h>
  53 #include <sys/malloc.h>
  54 #include <sys/kernel.h>
  55
  56 #include <machine/bus_pio.h>
  57 #include <machine/bus.h>
  58 #include <machine/resource.h>
  59 #include <sys/bus.h>
  60 #include <sys/rman.h>
  61
  62 #include <bus/cam/cam.h>
  63 #include <bus/cam/cam_ccb.h>
  64 #include <bus/cam/cam_sim.h>
  65 #include <bus/cam/cam_xpt_sim.h>
  66 #include <bus/cam/cam_xpt_periph.h>
  67 #include <bus/cam/cam_debug.h>
  68
  69 #include <bus/cam/scsi/scsi_all.h>
  70 #include <bus/cam/scsi/scsi_message.h>
  71
  72 #include <vm/vm.h>
  73 #include <vm/vm_param.h>
  74 #include <vm/pmap.h>
  75
  76 #include "advansys.h"
  77
  78 static void     adv_action(struct cam_sim *sim, union ccb *ccb);
  79 static void     adv_execute_ccb(void *arg, bus_dma_segment_t *dm_segs,
  80                                 int nsegments, int error);
  81 static void     adv_poll(struct cam_sim *sim);
  82 static void     adv_run_doneq(struct adv_softc *adv);
  83 static struct adv_ccb_info *
  84                 adv_alloc_ccb_info(struct adv_softc *adv);
  85 static void     adv_destroy_ccb_info(struct adv_softc *adv,
  86                                      struct adv_ccb_info *cinfo);
  87 static __inline struct adv_ccb_info *
  88                 adv_get_ccb_info(struct adv_softc *adv);
  89 static __inline void adv_free_ccb_info(struct adv_softc *adv,
  90                                        struct adv_ccb_info *cinfo);
  91 static __inline void adv_set_state(struct adv_softc *adv, adv_state state);
  92 static __inline void adv_clear_state(struct adv_softc *adv, union ccb* ccb);
  93 static void adv_clear_state_really(struct adv_softc *adv, union ccb* ccb);
  94
  95 static __inline struct adv_ccb_info *
  96 adv_get_ccb_info(struct adv_softc *adv)
  97 {
  98         struct adv_ccb_info *cinfo;
  99         int opri;
 100
 101         opri = splcam();
 102         if ((cinfo = SLIST_FIRST(&adv->free_ccb_infos)) != NULL) {
 103                 SLIST_REMOVE_HEAD(&adv->free_ccb_infos, links);
 104         } else {
 105                 cinfo = adv_alloc_ccb_info(adv);
 106         }
 107         splx(opri);
 108
 109         return (cinfo);
 110 }
 111
 112 static __inline void
 113 adv_free_ccb_info(struct adv_softc *adv, struct adv_ccb_info *cinfo)
 114 {
 115         int opri;
 116
 117         opri = splcam();
 118         cinfo->state = ACCB_FREE;
 119         SLIST_INSERT_HEAD(&adv->free_ccb_infos, cinfo, links);
 120         splx(opri);
 121 }
 122
 123 static __inline void
 124 adv_set_state(struct adv_softc *adv, adv_state state)
 125 {
 126         if (adv->state == 0)
 127                 xpt_freeze_simq(adv->sim, /*count*/1);
 128         adv->state |= state;
 129 }
 130
 131 static __inline void
 132 adv_clear_state(struct adv_softc *adv, union ccb* ccb)
 133 {
 134         if (adv->state != 0)
 135                 adv_clear_state_really(adv, ccb);
 136 }
 137
 138 static void
 139 adv_clear_state_really(struct adv_softc *adv, union ccb* ccb)
 140 {
 141         if ((adv->state & ADV_BUSDMA_BLOCK_CLEARED) != 0)
 142                 adv->state &= ~(ADV_BUSDMA_BLOCK_CLEARED|ADV_BUSDMA_BLOCK);
 143         if ((adv->state & ADV_RESOURCE_SHORTAGE) != 0) {
 144                 int openings;
 145
 146                 openings = adv->max_openings - adv->cur_active - ADV_MIN_FREE_Q;
 147                 if (openings >= adv->openings_needed) {
 148                         adv->state &= ~ADV_RESOURCE_SHORTAGE;
 149                         adv->openings_needed = 0;
 150                 }
 151         }
 152
 153         if ((adv->state & ADV_IN_TIMEOUT) != 0) {
 154                 struct adv_ccb_info *cinfo;
 155
 156                 cinfo = (struct adv_ccb_info *)ccb->ccb_h.ccb_cinfo_ptr;
 157                 if ((cinfo->state & ACCB_RECOVERY_CCB) != 0) {
 158                         struct ccb_hdr *ccb_h;
 159
 160                         /*
 161                          * We now traverse our list of pending CCBs
 162                          * and reinstate their timeouts.
 163                          */
 164                         ccb_h = LIST_FIRST(&adv->pending_ccbs);
 165                         while (ccb_h != NULL) {
 166                                 ccb_h->timeout_ch =
 167                                     timeout(adv_timeout, (caddr_t)ccb_h,
 168                                             (ccb_h->timeout * hz) / 1000);
 169                                 ccb_h = LIST_NEXT(ccb_h, sim_links.le);
 170                         }
 171                         adv->state &= ~ADV_IN_TIMEOUT;
 172                         printf("%s: No longer in timeout\n", adv_name(adv));
 173                 }
 174         }
 175         if (adv->state == 0)
 176                 ccb->ccb_h.status |= CAM_RELEASE_SIMQ;
 177 }
 178
 179 void
 180 adv_map(void *arg, bus_dma_segment_t *segs, int nseg, int error)
 181 {
 182         bus_addr_t* physaddr;
 183
 184         physaddr = (bus_addr_t*)arg;
 185         *physaddr = segs->ds_addr;
 186 }
 187
 188 char *
 189 adv_name(struct adv_softc *adv)
 190 {
 191         static char name[10];
 192
 193         snprintf(name, sizeof(name), "adv%d", adv->unit);
 194         return (name);
 195 }
 196
 197 static void
 198 adv_action(struct cam_sim *sim, union ccb *ccb)
 199 {
 200         struct adv_softc *adv;
 201
 202         CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("adv_action\n"));
 203
 204         adv = (struct adv_softc *)cam_sim_softc(sim);
 205
 206         switch (ccb->ccb_h.func_code) {
 207         /* Common cases first */
 208         case XPT_SCSI_IO:       /* Execute the requested I/O operation */
 209         {
 210                 struct  ccb_hdr *ccb_h;
 211                 struct  ccb_scsiio *csio;
 212                 struct  adv_ccb_info *cinfo;
 213
 214                 ccb_h = &ccb->ccb_h;
 215                 csio = &ccb->csio;
 216                 cinfo = adv_get_ccb_info(adv);
 217                 if (cinfo == NULL)
 218                         panic("XXX Handle CCB info error!!!");
 219
 220                 ccb_h->ccb_cinfo_ptr = cinfo;
 221                 cinfo->ccb = ccb;
 222
 223                 /* Only use S/G if there is a transfer */
 224                 if ((ccb_h->flags & CAM_DIR_MASK) != CAM_DIR_NONE) {
 225                         if ((ccb_h->flags & CAM_SCATTER_VALID) == 0) {
 226                                 /*
 227                                  * We've been given a pointer
 228                                  * to a single buffer
 229                                  */
 230                                 if ((ccb_h->flags & CAM_DATA_PHYS) == 0) {
 231                                         int s;
 232                                         int error;
 233
 234                                         s = splsoftvm();
 235                                         error =
 236                                             bus_dmamap_load(adv->buffer_dmat,
 237                                                             cinfo->dmamap,
 238                                                             csio->data_ptr,
 239                                                             csio->dxfer_len,
 240                                                             adv_execute_ccb,
 241                                                             csio, /*flags*/0);
 242                                         if (error == EINPROGRESS) {
 243                                                 /*
 244                                                  * So as to maintain ordering,
 245                                                  * freeze the controller queue
 246                                                  * until our mapping is
 247                                                  * returned.
 248                                                  */
 249                                                 adv_set_state(adv,
 250                                                               ADV_BUSDMA_BLOCK);
 251                                         }
 252                                         splx(s);
 253                                 } else {
 254                                         struct bus_dma_segment seg;
 255
 256                                         /* Pointer to physical buffer */
 257                                         seg.ds_addr =
 258                                              (bus_addr_t)csio->data_ptr;
 259                                         seg.ds_len = csio->dxfer_len;
 260                                         adv_execute_ccb(csio, &seg, 1, 0);
 261                                 }
 262                         } else {
 263                                 struct bus_dma_segment *segs;
 264                                 if ((ccb_h->flags & CAM_DATA_PHYS) != 0)
 265                                         panic("adv_setup_data - Physical "
 266                                               "segment pointers unsupported");
 267
 268                                 if ((ccb_h->flags & CAM_SG_LIST_PHYS) == 0)
 269                                         panic("adv_setup_data - Virtual "
 270                                               "segment addresses unsupported");
 271
 272                                 /* Just use the segments provided */
 273                                 segs = (struct bus_dma_segment *)csio->data_ptr;
 274                                 adv_execute_ccb(ccb, segs, csio->sglist_cnt, 0);
 275                         }
 276                 } else {
 277                         adv_execute_ccb(ccb, NULL, 0, 0);
 278                 }
 279                 break;
 280         }
 281         case XPT_RESET_DEV:     /* Bus Device Reset the specified SCSI device */
 282         case XPT_TARGET_IO:     /* Execute target I/O request */
 283         case XPT_ACCEPT_TARGET_IO:      /* Accept Host Target Mode CDB */
 284         case XPT_CONT_TARGET_IO:        /* Continue Host Target I/O Connection*/
 285         case XPT_EN_LUN:                /* Enable LUN as a target */
 286         case XPT_ABORT:                 /* Abort the specified CCB */
 287                 /* XXX Implement */
 288                 ccb->ccb_h.status = CAM_REQ_INVALID;
 289                 xpt_done(ccb);
 290                 break;
 291         case XPT_SET_TRAN_SETTINGS:
 292         {
 293                 struct   ccb_trans_settings *cts;
 294                 target_bit_vector targ_mask;
 295                 struct adv_transinfo *tconf;
 296                 u_int    update_type;
 297                 int      s;
 298
 299                 cts = &ccb->cts;
 300                 targ_mask = ADV_TID_TO_TARGET_MASK(cts->ccb_h.target_id);
 301                 update_type = 0;
 302
 303                 /*
 304                  * The user must specify which type of settings he wishes
 305                  * to change.
 306                  */
 307                 if (((cts->flags & CCB_TRANS_CURRENT_SETTINGS) != 0)
 308                  && ((cts->flags & CCB_TRANS_USER_SETTINGS) == 0)) {
 309                         tconf = &adv->tinfo[cts->ccb_h.target_id].current;
 310                         update_type |= ADV_TRANS_GOAL;
 311                 } else if (((cts->flags & CCB_TRANS_USER_SETTINGS) != 0)
 312                         && ((cts->flags & CCB_TRANS_CURRENT_SETTINGS) == 0)) {
 313                         tconf = &adv->tinfo[cts->ccb_h.target_id].user;
 314                         update_type |= ADV_TRANS_USER;
 315                 } else {
 316                         ccb->ccb_h.status = CAM_REQ_INVALID;
 317                         break;
 318                 }
 319
 320                 s = splcam();
 321
 322                 if ((update_type & ADV_TRANS_GOAL) != 0) {
 323                         if ((cts->valid & CCB_TRANS_DISC_VALID) != 0) {
 324                                 if ((cts->flags & CCB_TRANS_DISC_ENB) != 0)
 325                                         adv->disc_enable |= targ_mask;
 326                                 else
 327                                         adv->disc_enable &= ~targ_mask;
 328                                 adv_write_lram_8(adv, ADVV_DISC_ENABLE_B,
 329                                                  adv->disc_enable);
 330                         }
 331
 332                         if ((cts->valid & CCB_TRANS_TQ_VALID) != 0) {
 333                                 if ((cts->flags & CCB_TRANS_TAG_ENB) != 0)
 334                                         adv->cmd_qng_enabled |= targ_mask;
 335                                 else
 336                                         adv->cmd_qng_enabled &= ~targ_mask;
 337                         }
 338                 }
 339
 340                 if ((update_type & ADV_TRANS_USER) != 0) {
 341                         if ((cts->valid & CCB_TRANS_DISC_VALID) != 0) {
 342                                 if ((cts->flags & CCB_TRANS_DISC_ENB) != 0)
 343                                         adv->user_disc_enable |= targ_mask;
 344                                 else
 345                                         adv->user_disc_enable &= ~targ_mask;
 346                         }
 347
 348                         if ((cts->valid & CCB_TRANS_TQ_VALID) != 0) {
 349                                 if ((cts->flags & CCB_TRANS_TAG_ENB) != 0)
 350                                         adv->user_cmd_qng_enabled |= targ_mask;
 351                                 else
 352                                         adv->user_cmd_qng_enabled &= ~targ_mask;
 353                         }
 354                 }
 355
 356                 /*
 357                  * If the user specifies either the sync rate, or offset,
 358                  * but not both, the unspecified parameter defaults to its
 359                  * current value in transfer negotiations.
 360                  */
 361                 if (((cts->valid & CCB_TRANS_SYNC_RATE_VALID) != 0)
 362                  || ((cts->valid & CCB_TRANS_SYNC_OFFSET_VALID) != 0)) {
 363                         /*
 364                          * If the user provided a sync rate but no offset,
 365                          * use the current offset.
 366                          */
 367                         if ((cts->valid & CCB_TRANS_SYNC_OFFSET_VALID) == 0)
 368                                 cts->sync_offset = tconf->offset;
 369
 370                         /*
 371                          * If the user provided an offset but no sync rate,
 372                          * use the current sync rate.
 373                          */
 374                         if ((cts->valid & CCB_TRANS_SYNC_RATE_VALID) == 0)
 375                                 cts->sync_period = tconf->period;
 376
 377                         adv_period_offset_to_sdtr(adv, &cts->sync_period,
 378                                                   &cts->sync_offset,
 379                                                   cts->ccb_h.target_id);
 380
 381                         adv_set_syncrate(adv, /*struct cam_path */NULL,
 382                                          cts->ccb_h.target_id, cts->sync_period,
 383                                          cts->sync_offset, update_type);
 384                 }
 385
 386                 splx(s);
 387                 ccb->ccb_h.status = CAM_REQ_CMP;
 388                 xpt_done(ccb);
 389                 break;
 390         }
 391         case XPT_GET_TRAN_SETTINGS:
 392         /* Get default/user set transfer settings for the target */
 393         {
 394                 struct ccb_trans_settings *cts;
 395                 struct adv_transinfo *tconf;
 396                 target_bit_vector target_mask;
 397                 int s;
 398
 399                 cts = &ccb->cts;
 400                 target_mask = ADV_TID_TO_TARGET_MASK(cts->ccb_h.target_id);
 401
 402                 cts->flags &= ~(CCB_TRANS_DISC_ENB|CCB_TRANS_TAG_ENB);
 403
 404                 s = splcam();
 405                 if ((cts->flags & CCB_TRANS_CURRENT_SETTINGS) != 0) {
 406                         tconf = &adv->tinfo[cts->ccb_h.target_id].current;
 407                         if ((adv->disc_enable & target_mask) != 0)
 408                                 cts->flags |= CCB_TRANS_DISC_ENB;
 409                         if ((adv->cmd_qng_enabled & target_mask) != 0)
 410                                 cts->flags |= CCB_TRANS_TAG_ENB;
 411                 } else {
 412                         tconf = &adv->tinfo[cts->ccb_h.target_id].user;
 413                         if ((adv->user_disc_enable & target_mask) != 0)
 414                                 cts->flags |= CCB_TRANS_DISC_ENB;
 415                         if ((adv->user_cmd_qng_enabled & target_mask) != 0)
 416                                 cts->flags |= CCB_TRANS_TAG_ENB;
 417                 }
 418
 419                 cts->sync_period = tconf->period;
 420                 cts->sync_offset = tconf->offset;
 421                 splx(s);
 422
 423                 cts->bus_width = MSG_EXT_WDTR_BUS_8_BIT;
 424                 cts->valid = CCB_TRANS_SYNC_RATE_VALID
 425                            | CCB_TRANS_SYNC_OFFSET_VALID
 426                            | CCB_TRANS_BUS_WIDTH_VALID
 427                            | CCB_TRANS_DISC_VALID
 428                            | CCB_TRANS_TQ_VALID;
 429                 ccb->ccb_h.status = CAM_REQ_CMP;
 430                 xpt_done(ccb);
 431                 break;
 432         }
 433         case XPT_CALC_GEOMETRY:
 434         {
 435                 struct    ccb_calc_geometry *ccg;
 436                 u_int32_t size_mb;
 437                 u_int32_t secs_per_cylinder;
 438                 int       extended;
 439
 440                 ccg = &ccb->ccg;
 441                 size_mb = ccg->volume_size
 442                         / ((1024L * 1024L) / ccg->block_size);
 443                 extended = (adv->control & ADV_CNTL_BIOS_GT_1GB) != 0;
 444
 445                 if (size_mb > 1024 && extended) {
 446                         ccg->heads = 255;
 447                         ccg->secs_per_track = 63;
 448                 } else {
 449                         ccg->heads = 64;
 450                         ccg->secs_per_track = 32;
 451                 }
 452                 secs_per_cylinder = ccg->heads * ccg->secs_per_track;
 453                 ccg->cylinders = ccg->volume_size / secs_per_cylinder;
 454                 ccb->ccb_h.status = CAM_REQ_CMP;
 455                 xpt_done(ccb);
 456                 break;
 457         }
 458         case XPT_RESET_BUS:             /* Reset the specified SCSI bus */
 459         {
 460                 int s;
 461
 462                 s = splcam();
 463                 adv_stop_execution(adv);
 464                 adv_reset_bus(adv, /*initiate_reset*/TRUE);
 465                 adv_start_execution(adv);
 466                 splx(s);
 467
 468                 ccb->ccb_h.status = CAM_REQ_CMP;
 469                 xpt_done(ccb);
 470                 break;
 471         }
 472         case XPT_TERM_IO:               /* Terminate the I/O process */
 473                 /* XXX Implement */
 474                 ccb->ccb_h.status = CAM_REQ_INVALID;
 475                 xpt_done(ccb);
 476                 break;
 477         case XPT_PATH_INQ:              /* Path routing inquiry */
 478         {
 479                 struct ccb_pathinq *cpi = &ccb->cpi;
 480
 481                 cpi->version_num = 1; /* XXX??? */
 482                 cpi->hba_inquiry = PI_SDTR_ABLE|PI_TAG_ABLE;
 483                 cpi->target_sprt = 0;
 484                 cpi->hba_misc = 0;
 485                 cpi->hba_eng_cnt = 0;
 486                 cpi->max_target = 7;
 487                 cpi->max_lun = 7;
 488                 cpi->initiator_id = adv->scsi_id;
 489                 cpi->bus_id = cam_sim_bus(sim);
 490                 cpi->base_transfer_speed = 3300;
 491                 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN);
 492                 strncpy(cpi->hba_vid, "Advansys", HBA_IDLEN);
 493                 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN);
 494                 cpi->unit_number = cam_sim_unit(sim);
 495                 cpi->ccb_h.status = CAM_REQ_CMP;
 496                 xpt_done(ccb);
 497                 break;
 498         }
 499         default:
 500                 ccb->ccb_h.status = CAM_REQ_INVALID;
 501                 xpt_done(ccb);
 502                 break;
 503         }
 504 }
 505
 506 /*
 507  * Currently, the output of bus_dmammap_load suits our needs just
 508  * fine, but should it change, we'd need to do something here.
 509  */
 510 #define adv_fixup_dmasegs(adv, dm_segs) (struct adv_sg_entry *)(dm_segs)
 511
 512 static void
 513 adv_execute_ccb(void *arg, bus_dma_segment_t *dm_segs,
 514                 int nsegments, int error)
 515 {
 516         struct  ccb_scsiio *csio;
 517         struct  ccb_hdr *ccb_h;
 518         struct  cam_sim *sim;
 519         struct  adv_softc *adv;
 520         struct  adv_ccb_info *cinfo;
 521         struct  adv_scsi_q scsiq;
 522         struct  adv_sg_head sghead;
 523         int     s;
 524
 525         csio = (struct ccb_scsiio *)arg;
 526         ccb_h = &csio->ccb_h;
 527         sim = xpt_path_sim(ccb_h->path);
 528         adv = (struct adv_softc *)cam_sim_softc(sim);
 529         cinfo = (struct adv_ccb_info *)csio->ccb_h.ccb_cinfo_ptr;
 530
 531         /*
 532          * Setup our done routine to release the simq on
 533          * the next ccb that completes.
 534          */
 535         if ((adv->state & ADV_BUSDMA_BLOCK) != 0)
 536                 adv->state |= ADV_BUSDMA_BLOCK_CLEARED;
 537
 538         if ((ccb_h->flags & CAM_CDB_POINTER) != 0) {
 539                 if ((ccb_h->flags & CAM_CDB_PHYS) == 0) {
 540                         /* XXX Need phystovirt!!!! */
 541                         /* How about pmap_kenter??? */
 542                         scsiq.cdbptr = csio->cdb_io.cdb_ptr;
 543                 } else {
 544                         scsiq.cdbptr = csio->cdb_io.cdb_ptr;
 545                 }
 546         } else {
 547                 scsiq.cdbptr = csio->cdb_io.cdb_bytes;
 548         }
 549         /*
 550          * Build up the request
 551          */
 552         scsiq.q1.status = 0;
 553         scsiq.q1.q_no = 0;
 554         scsiq.q1.cntl = 0;
 555         scsiq.q1.sg_queue_cnt = 0;
 556         scsiq.q1.target_id = ADV_TID_TO_TARGET_MASK(ccb_h->target_id);
 557         scsiq.q1.target_lun = ccb_h->target_lun;
 558         scsiq.q1.sense_len = csio->sense_len;
 559         scsiq.q1.extra_bytes = 0;
 560         scsiq.q2.ccb_index = cinfo - adv->ccb_infos;
 561         scsiq.q2.target_ix = ADV_TIDLUN_TO_IX(ccb_h->target_id,
 562                                               ccb_h->target_lun);
 563         scsiq.q2.flag = 0;
 564         scsiq.q2.cdb_len = csio->cdb_len;
 565         if ((ccb_h->flags & CAM_TAG_ACTION_VALID) != 0)
 566                 scsiq.q2.tag_code = csio->tag_action;
 567         else
 568                 scsiq.q2.tag_code = 0;
 569         scsiq.q2.vm_id = 0;
 570
 571         if (nsegments != 0) {
 572                 bus_dmasync_op_t op;
 573
 574                 scsiq.q1.data_addr = dm_segs->ds_addr;
 575                 scsiq.q1.data_cnt = dm_segs->ds_len;
 576                 if (nsegments > 1) {
 577                         scsiq.q1.cntl |= QC_SG_HEAD;
 578                         sghead.entry_cnt
 579                             = sghead.entry_to_copy
 580                             = nsegments;
 581                         sghead.res = 0;
 582                         sghead.sg_list = adv_fixup_dmasegs(adv, dm_segs);
 583                         scsiq.sg_head = &sghead;
 584                 } else {
 585                         scsiq.sg_head = NULL;
 586                 }
 587                 if ((ccb_h->flags & CAM_DIR_MASK) == CAM_DIR_IN)
 588                         op = BUS_DMASYNC_PREREAD;
 589                 else
 590                         op = BUS_DMASYNC_PREWRITE;
 591                 bus_dmamap_sync(adv->buffer_dmat, cinfo->dmamap, op);
 592         } else {
 593                 scsiq.q1.data_addr = 0;
 594                 scsiq.q1.data_cnt = 0;
 595                 scsiq.sg_head = NULL;
 596         }
 597
 598         s = splcam();
 599
 600         /*
 601          * Last time we need to check if this SCB needs to
 602          * be aborted.
 603          */
 604         if (ccb_h->status != CAM_REQ_INPROG) {
 605                 if (nsegments != 0)
 606                         bus_dmamap_unload(adv->buffer_dmat, cinfo->dmamap);
 607                 adv_clear_state(adv, (union ccb *)csio);
 608                 adv_free_ccb_info(adv, cinfo);
 609                 xpt_done((union ccb *)csio);
 610                 splx(s);
 611                 return;
 612         }
 613
 614         if (adv_execute_scsi_queue(adv, &scsiq, csio->dxfer_len) != 0) {
 615                 /* Temporary resource shortage */
 616                 adv_set_state(adv, ADV_RESOURCE_SHORTAGE);
 617                 if (nsegments != 0)
 618                         bus_dmamap_unload(adv->buffer_dmat, cinfo->dmamap);
 619                 csio->ccb_h.status = CAM_REQUEUE_REQ;
 620                 adv_clear_state(adv, (union ccb *)csio);
 621                 adv_free_ccb_info(adv, cinfo);
 622                 xpt_done((union ccb *)csio);
 623                 splx(s);
 624                 return;
 625         }
 626         cinfo->state |= ACCB_ACTIVE;
 627         ccb_h->status |= CAM_SIM_QUEUED;
 628         LIST_INSERT_HEAD(&adv->pending_ccbs, ccb_h, sim_links.le);
 629         /* Schedule our timeout */
 630         ccb_h->timeout_ch =
 631             timeout(adv_timeout, csio, (ccb_h->timeout * hz)/1000);
 632         splx(s);
 633 }
 634
 635 static struct adv_ccb_info *
 636 adv_alloc_ccb_info(struct adv_softc *adv)
 637 {
 638         int error;
 639         struct adv_ccb_info *cinfo;
 640
 641         cinfo = &adv->ccb_infos[adv->ccb_infos_allocated];
 642         cinfo->state = ACCB_FREE;
 643         error = bus_dmamap_create(adv->buffer_dmat, /*flags*/0,
 644                                   &cinfo->dmamap);
 645         if (error != 0) {
 646                 printf("%s: Unable to allocate CCB info "
 647                        "dmamap - error %d\n", adv_name(adv), error);
 648                 return (NULL);
 649         }
 650         adv->ccb_infos_allocated++;
 651         return (cinfo);
 652 }
 653
 654 static void
 655 adv_destroy_ccb_info(struct adv_softc *adv, struct adv_ccb_info *cinfo)
 656 {
 657         bus_dmamap_destroy(adv->buffer_dmat, cinfo->dmamap);
 658 }
 659
 660 void
 661 adv_timeout(void *arg)
 662 {
 663         int s;
 664         union ccb *ccb;
 665         struct adv_softc *adv;
 666         struct adv_ccb_info *cinfo;
 667
 668         ccb = (union ccb *)arg;
 669         adv = (struct adv_softc *)xpt_path_sim(ccb->ccb_h.path)->softc;
 670         cinfo = (struct adv_ccb_info *)ccb->ccb_h.ccb_cinfo_ptr;
 671
 672         xpt_print_path(ccb->ccb_h.path);
 673         printf("Timed out\n");
 674
 675         s = splcam();
 676         /* Have we been taken care of already?? */
 677         if (cinfo == NULL || cinfo->state == ACCB_FREE) {
 678                 splx(s);
 679                 return;
 680         }
 681
 682         adv_stop_execution(adv);
 683
 684         if ((cinfo->state & ACCB_ABORT_QUEUED) == 0) {
 685                 struct ccb_hdr *ccb_h;
 686
 687                 /*
 688                  * In order to simplify the recovery process, we ask the XPT
 689                  * layer to halt the queue of new transactions and we traverse
 690                  * the list of pending CCBs and remove their timeouts. This
 691                  * means that the driver attempts to clear only one error
 692                  * condition at a time.  In general, timeouts that occur
 693                  * close together are related anyway, so there is no benefit
 694                  * in attempting to handle errors in parrallel.  Timeouts will
 695                  * be reinstated when the recovery process ends.
 696                  */
 697                 adv_set_state(adv, ADV_IN_TIMEOUT);
 698
 699                 /* This CCB is the CCB representing our recovery actions */
 700                 cinfo->state |= ACCB_RECOVERY_CCB|ACCB_ABORT_QUEUED;
 701
 702                 ccb_h = LIST_FIRST(&adv->pending_ccbs);
 703                 while (ccb_h != NULL) {
 704                         untimeout(adv_timeout, ccb_h, ccb_h->timeout_ch);
 705                         ccb_h = LIST_NEXT(ccb_h, sim_links.le);
 706                 }
 707
 708                 /* XXX Should send a BDR */
 709                 /* Attempt an abort as our first tact */
 710                 xpt_print_path(ccb->ccb_h.path);
 711                 printf("Attempting abort\n");
 712                 adv_abort_ccb(adv, ccb->ccb_h.target_id,
 713                               ccb->ccb_h.target_lun, ccb,
 714                               CAM_CMD_TIMEOUT, /*queued_only*/FALSE);
 715                 ccb->ccb_h.timeout_ch =
 716                     timeout(adv_timeout, ccb, 2 * hz);
 717         } else {
 718                 /* Our attempt to perform an abort failed, go for a reset */
 719                 xpt_print_path(ccb->ccb_h.path);
 720                 printf("Resetting bus\n");
 721                 ccb->ccb_h.status &= ~CAM_STATUS_MASK;
 722                 ccb->ccb_h.status |= CAM_CMD_TIMEOUT;
 723                 adv_reset_bus(adv, /*initiate_reset*/TRUE);
 724         }
 725         adv_start_execution(adv);
 726         splx(s);
 727 }
 728
 729 struct adv_softc *
 730 adv_alloc(device_t dev, bus_space_tag_t tag, bus_space_handle_t bsh)
 731 {
 732         struct adv_softc *adv = device_get_softc(dev);
 733
 734         /*
 735          * Allocate a storage area for us
 736          */
 737         LIST_INIT(&adv->pending_ccbs);
 738         SLIST_INIT(&adv->free_ccb_infos);
 739         adv->dev = dev;
 740         adv->unit = device_get_unit(dev);
 741         adv->tag = tag;
 742         adv->bsh = bsh;
 743
 744         return(adv);
 745 }
 746
 747 void
 748 adv_free(struct adv_softc *adv)
 749 {
 750         switch (adv->init_level) {
 751         case 6:
 752         {
 753                 struct adv_ccb_info *cinfo;
 754
 755                 while ((cinfo = SLIST_FIRST(&adv->free_ccb_infos)) != NULL) {
 756                         SLIST_REMOVE_HEAD(&adv->free_ccb_infos, links);
 757                         adv_destroy_ccb_info(adv, cinfo);
 758                 }
 759
 760                 bus_dmamap_unload(adv->sense_dmat, adv->sense_dmamap);
 761         }
 762         case 5:
 763                 bus_dmamem_free(adv->sense_dmat, adv->sense_buffers,
 764                                 adv->sense_dmamap);
 765         case 4:
 766                 bus_dma_tag_destroy(adv->sense_dmat);
 767         case 3:
 768                 bus_dma_tag_destroy(adv->buffer_dmat);
 769         case 2:
 770                 bus_dma_tag_destroy(adv->parent_dmat);
 771         case 1:
 772                 if (adv->ccb_infos != NULL)
 773                         free(adv->ccb_infos, M_DEVBUF);
 774         case 0:
 775                 break;
 776         }
 777 }
 778
 779 int
 780 adv_init(struct adv_softc *adv)
 781 {
 782         struct    adv_eeprom_config eeprom_config;
 783         int       checksum, i;
 784         int       max_sync;
 785         u_int16_t config_lsw;
 786         u_int16_t config_msw;
 787
 788         adv_lib_init(adv);
 789
 790         /*
 791          * Stop script execution.
 792          */
 793         adv_write_lram_16(adv, ADV_HALTCODE_W, 0x00FE);
 794         adv_stop_execution(adv);
 795         if (adv_stop_chip(adv) == 0 || adv_is_chip_halted(adv) == 0) {
 796                 printf("adv%d: Unable to halt adapter. Initialization"
 797                        "failed\n", adv->unit);
 798                 return (1);
 799         }
 800         ADV_OUTW(adv, ADV_REG_PROG_COUNTER, ADV_MCODE_START_ADDR);
 801         if (ADV_INW(adv, ADV_REG_PROG_COUNTER) != ADV_MCODE_START_ADDR) {
 802                 printf("adv%d: Unable to set program counter. Initialization"
 803                        "failed\n", adv->unit);
 804                 return (1);
 805         }
 806
 807         config_msw = ADV_INW(adv, ADV_CONFIG_MSW);
 808         config_lsw = ADV_INW(adv, ADV_CONFIG_LSW);
 809
 810         if ((config_msw & ADV_CFG_MSW_CLR_MASK) != 0) {
 811                 config_msw &= ~ADV_CFG_MSW_CLR_MASK;
 812                 /*
 813                  * XXX The Linux code flags this as an error,
 814                  * but what should we report to the user???
 815                  * It seems that clearing the config register
 816                  * makes this error recoverable.
 817                  */
 818                 ADV_OUTW(adv, ADV_CONFIG_MSW, config_msw);
 819         }
 820
 821         /* Suck in the configuration from the EEProm */
 822         checksum = adv_get_eeprom_config(adv, &eeprom_config);
 823
 824         if (ADV_INW(adv, ADV_CHIP_STATUS) & ADV_CSW_AUTO_CONFIG) {
 825                 /*
 826                  * XXX The Linux code sets a warning level for this
 827                  * condition, yet nothing of meaning is printed to
 828                  * the user.  What does this mean???
 829                  */
 830                 if (adv->chip_version == 3) {
 831                         if (eeprom_config.cfg_lsw != config_lsw)
 832                                 eeprom_config.cfg_lsw = config_lsw;
 833                         if (eeprom_config.cfg_msw != config_msw) {
 834                                 eeprom_config.cfg_msw = config_msw;
 835                         }
 836                 }
 837         }
 838         if (checksum == eeprom_config.chksum) {
 839
 840                 /* Range/Sanity checking */
 841                 if (eeprom_config.max_total_qng < ADV_MIN_TOTAL_QNG) {
 842                         eeprom_config.max_total_qng = ADV_MIN_TOTAL_QNG;
 843                 }
 844                 if (eeprom_config.max_total_qng > ADV_MAX_TOTAL_QNG) {
 845                         eeprom_config.max_total_qng = ADV_MAX_TOTAL_QNG;
 846                 }
 847                 if (eeprom_config.max_tag_qng > eeprom_config.max_total_qng) {
 848                         eeprom_config.max_tag_qng = eeprom_config.max_total_qng;
 849                 }
 850                 if (eeprom_config.max_tag_qng < ADV_MIN_TAG_Q_PER_DVC) {
 851                         eeprom_config.max_tag_qng = ADV_MIN_TAG_Q_PER_DVC;
 852                 }
 853                 adv->max_openings = eeprom_config.max_total_qng;
 854                 adv->user_disc_enable = eeprom_config.disc_enable;
 855                 adv->user_cmd_qng_enabled = eeprom_config.use_cmd_qng;
 856                 adv->isa_dma_speed = EEPROM_DMA_SPEED(eeprom_config);
 857                 adv->scsi_id = EEPROM_SCSIID(eeprom_config) & ADV_MAX_TID;
 858                 EEPROM_SET_SCSIID(eeprom_config, adv->scsi_id);
 859                 adv->control = eeprom_config.cntl;
 860                 for (i = 0; i <= ADV_MAX_TID; i++) {
 861                         u_int8_t sync_data;
 862
 863                         if ((eeprom_config.init_sdtr & (0x1 << i)) == 0)
 864                                 sync_data = 0;
 865                         else
 866                                 sync_data = eeprom_config.sdtr_data[i];
 867                         adv_sdtr_to_period_offset(adv,
 868                                                   sync_data,
 869                                                   &adv->tinfo[i].user.period,
 870                                                   &adv->tinfo[i].user.offset,
 871                                                   i);
 872                 }
 873                 config_lsw = eeprom_config.cfg_lsw;
 874                 eeprom_config.cfg_msw = config_msw;
 875         } else {
 876                 u_int8_t sync_data;
 877
 878                 printf("adv%d: Warning EEPROM Checksum mismatch. "
 879                        "Using default device parameters\n", adv->unit);
 880
 881                 /* Set reasonable defaults since we can't read the EEPROM */
 882                 adv->isa_dma_speed = /*ADV_DEF_ISA_DMA_SPEED*/1;
 883                 adv->max_openings = ADV_DEF_MAX_TOTAL_QNG;
 884                 adv->disc_enable = TARGET_BIT_VECTOR_SET;
 885                 adv->user_disc_enable = TARGET_BIT_VECTOR_SET;
 886                 adv->cmd_qng_enabled = TARGET_BIT_VECTOR_SET;
 887                 adv->user_cmd_qng_enabled = TARGET_BIT_VECTOR_SET;
 888                 adv->scsi_id = 7;
 889                 adv->control = 0xFFFF;
 890
 891                 if (adv->chip_version == ADV_CHIP_VER_PCI_ULTRA_3050)
 892                         /* Default to no Ultra to support the 3030 */
 893                         adv->control &= ~ADV_CNTL_SDTR_ENABLE_ULTRA;
 894                 sync_data = ADV_DEF_SDTR_OFFSET | (ADV_DEF_SDTR_INDEX << 4);
 895                 for (i = 0; i <= ADV_MAX_TID; i++) {
 896                         adv_sdtr_to_period_offset(adv, sync_data,
 897                                                   &adv->tinfo[i].user.period,
 898                                                   &adv->tinfo[i].user.offset,
 899                                                   i);
 900                 }
 901                 config_lsw |= ADV_CFG_LSW_SCSI_PARITY_ON;
 902         }
 903         config_msw &= ~ADV_CFG_MSW_CLR_MASK;
 904         config_lsw |= ADV_CFG_LSW_HOST_INT_ON;
 905         if ((adv->type & (ADV_PCI|ADV_ULTRA)) == (ADV_PCI|ADV_ULTRA)
 906          && (adv->control & ADV_CNTL_SDTR_ENABLE_ULTRA) == 0)
 907                 /* 25ns or 10MHz */
 908                 max_sync = 25;
 909         else
 910                 /* Unlimited */
 911                 max_sync = 0;
 912         for (i = 0; i <= ADV_MAX_TID; i++) {
 913                 if (adv->tinfo[i].user.period < max_sync)
 914                         adv->tinfo[i].user.period = max_sync;
 915         }
 916
 917         if (adv_test_external_lram(adv) == 0) {
 918                 if ((adv->type & (ADV_PCI|ADV_ULTRA)) == (ADV_PCI|ADV_ULTRA)) {
 919                         eeprom_config.max_total_qng =
 920                             ADV_MAX_PCI_ULTRA_INRAM_TOTAL_QNG;
 921                         eeprom_config.max_tag_qng =
 922                             ADV_MAX_PCI_ULTRA_INRAM_TAG_QNG;
 923                 } else {
 924                         eeprom_config.cfg_msw |= 0x0800;
 925                         config_msw |= 0x0800;
 926                         eeprom_config.max_total_qng =
 927                              ADV_MAX_PCI_INRAM_TOTAL_QNG;
 928                         eeprom_config.max_tag_qng = ADV_MAX_INRAM_TAG_QNG;
 929                 }
 930                 adv->max_openings = eeprom_config.max_total_qng;
 931         }
 932         ADV_OUTW(adv, ADV_CONFIG_MSW, config_msw);
 933         ADV_OUTW(adv, ADV_CONFIG_LSW, config_lsw);
 934 #if 0
 935         /*
 936          * Don't write the eeprom data back for now.
 937          * I'd rather not mess up the user's card.  We also don't
 938          * fully sanitize the eeprom settings above for the write-back
 939          * to be 100% correct.
 940          */
 941         if (adv_set_eeprom_config(adv, &eeprom_config) != 0)
 942                 printf("%s: WARNING! Failure writing to EEPROM.\n",
 943                        adv_name(adv));
 944 #endif
 945
 946         adv_set_chip_scsiid(adv, adv->scsi_id);
 947         if (adv_init_lram_and_mcode(adv))
 948                 return (1);
 949
 950         adv->disc_enable = adv->user_disc_enable;
 951
 952         adv_write_lram_8(adv, ADVV_DISC_ENABLE_B, adv->disc_enable);
 953         for (i = 0; i <= ADV_MAX_TID; i++) {
 954                 /*
 955                  * Start off in async mode.
 956                  */
 957                 adv_set_syncrate(adv, /*struct cam_path */NULL,
 958                                  i, /*period*/0, /*offset*/0,
 959                                  ADV_TRANS_CUR);
 960                 /*
 961                  * Enable the use of tagged commands on all targets.
 962                  * This allows the kernel driver to make up it's own mind
 963                  * as it sees fit to tag queue instead of having the
 964                  * firmware try and second guess the tag_code settins.
 965                  */
 966                 adv_write_lram_8(adv, ADVV_MAX_DVC_QNG_BEG + i,
 967                                  adv->max_openings);
 968         }
 969         adv_write_lram_8(adv, ADVV_USE_TAGGED_QNG_B, TARGET_BIT_VECTOR_SET);
 970         adv_write_lram_8(adv, ADVV_CAN_TAGGED_QNG_B, TARGET_BIT_VECTOR_SET);
 971         printf("adv%d: AdvanSys %s Host Adapter, SCSI ID %d, queue depth %d\n",
 972                adv->unit, (adv->type & ADV_ULTRA) && (max_sync == 0)
 973                           ? "Ultra SCSI" : "SCSI",
 974                adv->scsi_id, adv->max_openings);
 975         return (0);
 976 }
 977
 978 void
 979 adv_intr(void *arg)
 980 {
 981         struct    adv_softc *adv;
 982         u_int16_t chipstat;
 983         u_int16_t saved_ram_addr;
 984         u_int8_t  ctrl_reg;
 985         u_int8_t  saved_ctrl_reg;
 986         u_int8_t  host_flag;
 987
 988         adv = (struct adv_softc *)arg;
 989
 990         chipstat = ADV_INW(adv, ADV_CHIP_STATUS);
 991
 992         /* Is it for us? */
 993         if ((chipstat & (ADV_CSW_INT_PENDING|ADV_CSW_SCSI_RESET_LATCH)) == 0)
 994                 return;
 995
 996         ctrl_reg = ADV_INB(adv, ADV_CHIP_CTRL);
 997         saved_ctrl_reg = ctrl_reg & (~(ADV_CC_SCSI_RESET | ADV_CC_CHIP_RESET |
 998                                        ADV_CC_SINGLE_STEP | ADV_CC_DIAG |
 999                                        ADV_CC_TEST));
1000
1001         if ((chipstat & (ADV_CSW_SCSI_RESET_LATCH|ADV_CSW_SCSI_RESET_ACTIVE))) {
1002                 printf("Detected Bus Reset\n");
1003                 adv_reset_bus(adv, /*initiate_reset*/FALSE);
1004                 return;
1005         }
1006
1007         if ((chipstat & ADV_CSW_INT_PENDING) != 0) {
1008
1009                 saved_ram_addr = ADV_INW(adv, ADV_LRAM_ADDR);
1010                 host_flag = adv_read_lram_8(adv, ADVV_HOST_FLAG_B);
1011                 adv_write_lram_8(adv, ADVV_HOST_FLAG_B,
1012                                  host_flag | ADV_HOST_FLAG_IN_ISR);
1013
1014                 adv_ack_interrupt(adv);
1015
1016                 if ((chipstat & ADV_CSW_HALTED) != 0
1017                  && (ctrl_reg & ADV_CC_SINGLE_STEP) != 0) {
1018                         adv_isr_chip_halted(adv);
1019                         saved_ctrl_reg &= ~ADV_CC_HALT;
1020                 } else {
1021                         adv_run_doneq(adv);
1022                 }
1023                 ADV_OUTW(adv, ADV_LRAM_ADDR, saved_ram_addr);
1024 #ifdef DIAGNOSTIC
1025                 if (ADV_INW(adv, ADV_LRAM_ADDR) != saved_ram_addr)
1026                         panic("adv_intr: Unable to set LRAM addr");
1027 #endif
1028                 adv_write_lram_8(adv, ADVV_HOST_FLAG_B, host_flag);
1029         }
1030
1031         ADV_OUTB(adv, ADV_CHIP_CTRL, saved_ctrl_reg);
1032 }
1033
1034 void
1035 adv_run_doneq(struct adv_softc *adv)
1036 {
1037         struct adv_q_done_info scsiq;
1038         u_int             doneq_head;
1039         u_int             done_qno;
1040
1041         doneq_head = adv_read_lram_16(adv, ADVV_DONE_Q_TAIL_W) & 0xFF;
1042         done_qno = adv_read_lram_8(adv, ADV_QNO_TO_QADDR(doneq_head)
1043                                    + ADV_SCSIQ_B_FWD);
1044         while (done_qno != ADV_QLINK_END) {
1045                 union ccb* ccb;
1046                 struct adv_ccb_info *cinfo;
1047                 u_int done_qaddr;
1048                 u_int sg_queue_cnt;
1049                 int   aborted;
1050
1051                 done_qaddr = ADV_QNO_TO_QADDR(done_qno);
1052
1053                 /* Pull status from this request */
1054                 sg_queue_cnt = adv_copy_lram_doneq(adv, done_qaddr, &scsiq,
1055                                                    adv->max_dma_count);
1056
1057                 /* Mark it as free */
1058                 adv_write_lram_8(adv, done_qaddr + ADV_SCSIQ_B_STATUS,
1059                                  scsiq.q_status & ~(QS_READY|QS_ABORTED));
1060
1061                 /* Process request based on retrieved info */
1062                 if ((scsiq.cntl & QC_SG_HEAD) != 0) {
1063                         u_int i;
1064
1065                         /*
1066                          * S/G based request.  Free all of the queue
1067                          * structures that contained S/G information.
1068                          */
1069                         for (i = 0; i < sg_queue_cnt; i++) {
1070                                 done_qno = adv_read_lram_8(adv, done_qaddr
1071                                                            + ADV_SCSIQ_B_FWD);
1072
1073 #ifdef DIAGNOSTIC
1074                                 if (done_qno == ADV_QLINK_END) {
1075                                         panic("adv_qdone: Corrupted SG "
1076                                               "list encountered");
1077                                 }
1078 #endif
1079                                 done_qaddr = ADV_QNO_TO_QADDR(done_qno);
1080
1081                                 /* Mark SG queue as free */
1082                                 adv_write_lram_8(adv, done_qaddr
1083                                                  + ADV_SCSIQ_B_STATUS, QS_FREE);
1084                         }
1085                 } else
1086                         sg_queue_cnt = 0;
1087 #ifdef DIAGNOSTIC
1088                 if (adv->cur_active < (sg_queue_cnt + 1))
1089                         panic("adv_qdone: Attempting to free more "
1090                               "queues than are active");
1091 #endif
1092                 adv->cur_active -= sg_queue_cnt + 1;
1093
1094                 aborted = (scsiq.q_status & QS_ABORTED) != 0;
1095
1096                 if ((scsiq.q_status != QS_DONE)
1097                  && (scsiq.q_status & QS_ABORTED) == 0)
1098                         panic("adv_qdone: completed scsiq with unknown status");
1099
1100                 scsiq.remain_bytes += scsiq.extra_bytes;
1101
1102                 if ((scsiq.d3.done_stat == QD_WITH_ERROR) &&
1103                     (scsiq.d3.host_stat == QHSTA_M_DATA_OVER_RUN)) {
1104                         if ((scsiq.cntl & (QC_DATA_IN|QC_DATA_OUT)) == 0) {
1105                                 scsiq.d3.done_stat = QD_NO_ERROR;
1106                                 scsiq.d3.host_stat = QHSTA_NO_ERROR;
1107                         }
1108                 }
1109
1110                 cinfo = &adv->ccb_infos[scsiq.d2.ccb_index];
1111                 ccb = cinfo->ccb;
1112                 ccb->csio.resid = scsiq.remain_bytes;
1113                 adv_done(adv, ccb,
1114                          scsiq.d3.done_stat, scsiq.d3.host_stat,
1115                          scsiq.d3.scsi_stat, scsiq.q_no);
1116
1117                 doneq_head = done_qno;
1118                 done_qno = adv_read_lram_8(adv, done_qaddr + ADV_SCSIQ_B_FWD);
1119         }
1120         adv_write_lram_16(adv, ADVV_DONE_Q_TAIL_W, doneq_head);
1121 }
1122
1123
1124 void
1125 adv_done(struct adv_softc *adv, union ccb *ccb, u_int done_stat,
1126          u_int host_stat, u_int scsi_status, u_int q_no)
1127 {
1128         struct     adv_ccb_info *cinfo;
1129
1130         cinfo = (struct adv_ccb_info *)ccb->ccb_h.ccb_cinfo_ptr;
1131         LIST_REMOVE(&ccb->ccb_h, sim_links.le);
1132         untimeout(adv_timeout, ccb, ccb->ccb_h.timeout_ch);
1133         if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) {
1134                 bus_dmasync_op_t op;
1135
1136                 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN)
1137                         op = BUS_DMASYNC_POSTREAD;
1138                 else
1139                         op = BUS_DMASYNC_POSTWRITE;
1140                 bus_dmamap_sync(adv->buffer_dmat, cinfo->dmamap, op);
1141                 bus_dmamap_unload(adv->buffer_dmat, cinfo->dmamap);
1142         }
1143
1144         switch (done_stat) {
1145         case QD_NO_ERROR:
1146                 if (host_stat == QHSTA_NO_ERROR) {
1147                         ccb->ccb_h.status = CAM_REQ_CMP;
1148                         break;
1149                 }
1150                 xpt_print_path(ccb->ccb_h.path);
1151                 printf("adv_done - queue done without error, "
1152                        "but host status non-zero(%x)\n", host_stat);
1153                 /*FALLTHROUGH*/
1154         case QD_WITH_ERROR:
1155                 switch (host_stat) {
1156                 case QHSTA_M_TARGET_STATUS_BUSY:
1157                 case QHSTA_M_BAD_QUEUE_FULL_OR_BUSY:
1158                         /*
1159                          * Assume that if we were a tagged transaction
1160                          * the target reported queue full.  Otherwise,
1161                          * report busy.  The firmware really should just
1162                          * pass the original status back up to us even
1163                          * if it thinks the target was in error for
1164                          * returning this status as no other transactions
1165                          * from this initiator are in effect, but this
1166                          * ignores multi-initiator setups and there is
1167                          * evidence that the firmware gets its per-device
1168                          * transaction counts screwed up occassionally.
1169                          */
1170                         ccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR;
1171                         if ((ccb->ccb_h.flags & CAM_TAG_ACTION_VALID) != 0
1172                          && host_stat != QHSTA_M_TARGET_STATUS_BUSY)
1173                                 scsi_status = SCSI_STATUS_QUEUE_FULL;
1174                         else
1175                                 scsi_status = SCSI_STATUS_BUSY;
1176                         adv_abort_ccb(adv, ccb->ccb_h.target_id,
1177                                       ccb->ccb_h.target_lun,
1178                                       /*ccb*/NULL, CAM_REQUEUE_REQ,
1179                                       /*queued_only*/TRUE);
1180                         /*FALLTHROUGH*/
1181                 case QHSTA_M_NO_AUTO_REQ_SENSE:
1182                 case QHSTA_NO_ERROR:
1183                         ccb->csio.scsi_status = scsi_status;
1184                         switch (scsi_status) {
1185                         case SCSI_STATUS_CHECK_COND:
1186                         case SCSI_STATUS_CMD_TERMINATED:
1187                                 ccb->ccb_h.status |= CAM_AUTOSNS_VALID;
1188                                 /* Structure copy */
1189                                 ccb->csio.sense_data =
1190                                     adv->sense_buffers[q_no - 1];
1191                                 /* FALLTHROUGH */
1192                         case SCSI_STATUS_BUSY:
1193                         case SCSI_STATUS_RESERV_CONFLICT:
1194                         case SCSI_STATUS_QUEUE_FULL:
1195                         case SCSI_STATUS_COND_MET:
1196                         case SCSI_STATUS_INTERMED:
1197                         case SCSI_STATUS_INTERMED_COND_MET:
1198                                 ccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR;
1199                                 break;
1200                         case SCSI_STATUS_OK:
1201                                 ccb->ccb_h.status |= CAM_REQ_CMP;
1202                                 break;
1203                         }
1204                         break;
1205                 case QHSTA_M_SEL_TIMEOUT:
1206                         ccb->ccb_h.status = CAM_SEL_TIMEOUT;
1207                         break;
1208                 case QHSTA_M_DATA_OVER_RUN:
1209                         ccb->ccb_h.status = CAM_DATA_RUN_ERR;
1210                         break;
1211                 case QHSTA_M_UNEXPECTED_BUS_FREE:
1212                         ccb->ccb_h.status = CAM_UNEXP_BUSFREE;
1213                         break;
1214                 case QHSTA_M_BAD_BUS_PHASE_SEQ:
1215                         ccb->ccb_h.status = CAM_SEQUENCE_FAIL;
1216                         break;
1217                 case QHSTA_M_BAD_CMPL_STATUS_IN:
1218                         /* No command complete after a status message */
1219                         ccb->ccb_h.status = CAM_SEQUENCE_FAIL;
1220                         break;
1221                 case QHSTA_D_EXE_SCSI_Q_BUSY_TIMEOUT:
1222                 case QHSTA_M_WTM_TIMEOUT:
1223                 case QHSTA_M_HUNG_REQ_SCSI_BUS_RESET:
1224                         /* The SCSI bus hung in a phase */
1225                         ccb->ccb_h.status = CAM_SEQUENCE_FAIL;
1226                         adv_reset_bus(adv, /*initiate_reset*/TRUE);
1227                         break;
1228                 case QHSTA_M_AUTO_REQ_SENSE_FAIL:
1229                         ccb->ccb_h.status = CAM_AUTOSENSE_FAIL;
1230                         break;
1231                 case QHSTA_D_QDONE_SG_LIST_CORRUPTED:
1232                 case QHSTA_D_ASC_DVC_ERROR_CODE_SET:
1233                 case QHSTA_D_HOST_ABORT_FAILED:
1234                 case QHSTA_D_EXE_SCSI_Q_FAILED:
1235                 case QHSTA_D_ASPI_NO_BUF_POOL:
1236                 case QHSTA_M_BAD_TAG_CODE:
1237                 case QHSTA_D_LRAM_CMP_ERROR:
1238                 case QHSTA_M_MICRO_CODE_ERROR_HALT:
1239                 default:
1240                         panic("%s: Unhandled Host status error %x",
1241                               adv_name(adv), host_stat);
1242                         /* NOTREACHED */
1243                 }
1244                 break;
1245
1246         case QD_ABORTED_BY_HOST:
1247                 /* Don't clobber any, more explicit, error codes we've set */
1248                 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_INPROG)
1249                         ccb->ccb_h.status = CAM_REQ_ABORTED;
1250                 break;
1251
1252         default:
1253                 xpt_print_path(ccb->ccb_h.path);
1254                 printf("adv_done - queue done with unknown status %x:%x\n",
1255                        done_stat, host_stat);
1256                 ccb->ccb_h.status = CAM_REQ_CMP_ERR;
1257                 break;
1258         }
1259         adv_clear_state(adv, ccb);
1260         if ((ccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_CMP
1261          && (ccb->ccb_h.status & CAM_DEV_QFRZN) == 0) {
1262                 xpt_freeze_devq(ccb->ccb_h.path, /*count*/1);
1263                 ccb->ccb_h.status |= CAM_DEV_QFRZN;
1264         }
1265         adv_free_ccb_info(adv, cinfo);
1266         /*
1267          * Null this out so that we catch driver bugs that cause a
1268          * ccb to be completed twice.
1269          */
1270         ccb->ccb_h.ccb_cinfo_ptr = NULL;
1271         ccb->ccb_h.status &= ~CAM_SIM_QUEUED;
1272         xpt_done(ccb);
1273 }
1274
1275 /*
1276  * Function to poll for command completion when
1277  * interrupts are disabled (crash dumps)
1278  */
1279 static void
1280 adv_poll(struct cam_sim *sim)
1281 {
1282         adv_intr(cam_sim_softc(sim));
1283 }
1284
1285 /*
1286  * Attach all the sub-devices we can find
1287  */
1288 int
1289 adv_attach(adv)
1290         struct adv_softc *adv;
1291 {
1292         struct ccb_setasync csa;
1293         int max_sg;
1294
1295         /*
1296          * Allocate an array of ccb mapping structures.  We put the
1297          * index of the ccb_info structure into the queue representing
1298          * a transaction and use it for mapping the queue to the
1299          * upper level SCSI transaction it represents.
1300          */
1301         adv->ccb_infos = malloc(sizeof(*adv->ccb_infos) * adv->max_openings,
1302                                 M_DEVBUF, M_WAITOK);
1303         adv->init_level++;
1304
1305         /*
1306          * Create our DMA tags.  These tags define the kinds of device
1307          * accessible memory allocations and memory mappings we will
1308          * need to perform during normal operation.
1309          *
1310          * Unless we need to further restrict the allocation, we rely
1311          * on the restrictions of the parent dmat, hence the common
1312          * use of MAXADDR and MAXSIZE.
1313          *
1314          * The ASC boards use chains of "queues" (the transactional
1315          * resources on the board) to represent long S/G lists.
1316          * The first queue represents the command and holds a
1317          * single address and data pair.  The queues that follow
1318          * can each hold ADV_SG_LIST_PER_Q entries.  Given the
1319          * total number of queues, we can express the largest
1320          * transaction we can map.  We reserve a few queues for
1321          * error recovery.  Take those into account as well.
1322          *
1323          * There is a way to take an interrupt to download the
1324          * next batch of S/G entries if there are more than 255
1325          * of them (the counter in the queue structure is a u_int8_t).
1326          * We don't use this feature, so limit the S/G list size
1327          * accordingly.
1328          */
1329         max_sg = (adv->max_openings - ADV_MIN_FREE_Q - 1) * ADV_SG_LIST_PER_Q;
1330         if (max_sg > 255)
1331                 max_sg = 255;
1332
1333         /* DMA tag for mapping buffers into device visible space. */
1334         if (bus_dma_tag_create(adv->parent_dmat, /*alignment*/1, /*boundary*/0,
1335                                /*lowaddr*/BUS_SPACE_MAXADDR,
1336                                /*highaddr*/BUS_SPACE_MAXADDR,
1337                                /*filter*/NULL, /*filterarg*/NULL,
1338                                /*maxsize*/MAXPHYS,
1339                                /*nsegments*/max_sg,
1340                                /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
1341                                /*flags*/BUS_DMA_ALLOCNOW,
1342                                &adv->buffer_dmat) != 0) {
1343                 return (ENXIO);
1344         }
1345         adv->init_level++;
1346
1347         /* DMA tag for our sense buffers */
1348         if (bus_dma_tag_create(adv->parent_dmat, /*alignment*/1, /*boundary*/0,
1349                                /*lowaddr*/BUS_SPACE_MAXADDR,
1350                                /*highaddr*/BUS_SPACE_MAXADDR,
1351                                /*filter*/NULL, /*filterarg*/NULL,
1352                                sizeof(struct scsi_sense_data)*adv->max_openings,
1353                                /*nsegments*/1,
1354                                /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
1355                                /*flags*/0, &adv->sense_dmat) != 0) {
1356                 return (ENXIO);
1357         }
1358
1359         adv->init_level++;
1360
1361         /* Allocation for our sense buffers */
1362         if (bus_dmamem_alloc(adv->sense_dmat, (void **)&adv->sense_buffers,
1363                              BUS_DMA_NOWAIT, &adv->sense_dmamap) != 0) {
1364                 return (ENOMEM);
1365         }
1366
1367         adv->init_level++;
1368
1369         /* And permanently map them */
1370         bus_dmamap_load(adv->sense_dmat, adv->sense_dmamap,
1371                         adv->sense_buffers,
1372                         sizeof(struct scsi_sense_data)*adv->max_openings,
1373                         adv_map, &adv->sense_physbase, /*flags*/0);
1374
1375         adv->init_level++;
1376
1377         /*
1378          * Fire up the chip
1379          */
1380         if (adv_start_chip(adv) != 1) {
1381                 printf("adv%d: Unable to start on board processor. Aborting.\n",
1382                        adv->unit);
1383                 return (ENXIO);
1384         }
1385
1386         /*
1387          * Construct our SIM entry.
1388          */
1389         adv->sim = cam_sim_alloc(adv_action, adv_poll, "adv", adv, adv->unit,
1390                                  1, adv->max_openings, NULL);
1391         if (adv->sim == NULL)
1392                 return (ENOMEM);
1393
1394         /*
1395          * Register the bus.
1396          *
1397          * XXX Twin Channel EISA Cards???
1398          */
1399         if (xpt_bus_register(adv->sim, 0) != CAM_SUCCESS) {
1400                 cam_sim_free(adv->sim);
1401                 return (ENXIO);
1402         }
1403
1404         if (xpt_create_path(&adv->path, /*periph*/NULL, cam_sim_path(adv->sim),
1405                             CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD)
1406             != CAM_REQ_CMP) {
1407                 xpt_bus_deregister(cam_sim_path(adv->sim));
1408                 cam_sim_free(adv->sim);
1409                 return (ENXIO);
1410         }
1411
1412         xpt_setup_ccb(&csa.ccb_h, adv->path, /*priority*/5);
1413         csa.ccb_h.func_code = XPT_SASYNC_CB;
1414         csa.event_enable = AC_FOUND_DEVICE|AC_LOST_DEVICE;
1415         csa.callback = advasync;
1416         csa.callback_arg = adv;
1417         xpt_action((union ccb *)&csa);
1418         return (0);
1419 }