2 * Copyright (c) 1998,1999,2000,2001,2002 Søren Schmidt <sos@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * $FreeBSD: src/sys/dev/ata/ata-all.h,v 1.26.2.12 2003/01/30 07:19:59 sos Exp $
31 /* ATA register defines */
32 #define ATA_DATA 0x00 /* data register */
33 #define ATA_ERROR 0x01 /* (R) error register */
34 #define ATA_E_NM 0x02 /* no media */
35 #define ATA_E_ABORT 0x04 /* command aborted */
36 #define ATA_E_MCR 0x08 /* media change request */
37 #define ATA_E_IDNF 0x10 /* ID not found */
38 #define ATA_E_MC 0x20 /* media changed */
39 #define ATA_E_UNC 0x40 /* uncorrectable data */
40 #define ATA_E_ICRC 0x80 /* UDMA crc error */
42 #define ATA_FEATURE 0x01 /* (W) feature register */
43 #define ATA_F_DMA 0x01 /* enable DMA */
44 #define ATA_F_OVL 0x02 /* enable overlap */
46 #define ATA_COUNT 0x02 /* (W) sector count */
47 #define ATA_IREASON 0x02 /* (R) interrupt reason */
48 #define ATA_I_CMD 0x01 /* cmd (1) | data (0) */
49 #define ATA_I_IN 0x02 /* read (1) | write (0) */
50 #define ATA_I_RELEASE 0x04 /* released bus (1) */
51 #define ATA_I_TAGMASK 0xf8 /* tag mask */
53 #define ATA_SECTOR 0x03 /* sector # */
54 #define ATA_CYL_LSB 0x04 /* cylinder# LSB */
55 #define ATA_CYL_MSB 0x05 /* cylinder# MSB */
56 #define ATA_DRIVE 0x06 /* Sector/Drive/Head register */
57 #define ATA_D_LBA 0x40 /* use LBA addressing */
58 #define ATA_D_IBM 0xa0 /* 512 byte sectors, ECC */
60 #define ATA_CMD 0x07 /* command register */
61 #define ATA_C_NOP 0x00 /* NOP command */
62 #define ATA_C_F_FLUSHQUEUE 0x00 /* flush queued cmd's */
63 #define ATA_C_F_AUTOPOLL 0x01 /* start autopoll function */
64 #define ATA_C_ATAPI_RESET 0x08 /* reset ATAPI device */
65 #define ATA_C_READ 0x20 /* read command */
66 #define ATA_C_READ48 0x24 /* read command */
67 #define ATA_C_READ_DMA48 0x25 /* read w/DMA command */
68 #define ATA_C_READ_DMA_QUEUED48 0x26 /* read w/DMA QUEUED command */
69 #define ATA_C_READ_MUL48 0x29 /* read multi command */
70 #define ATA_C_WRITE 0x30 /* write command */
71 #define ATA_C_WRITE48 0x34 /* write command */
72 #define ATA_C_WRITE_DMA48 0x35 /* write w/DMA command */
73 #define ATA_C_WRITE_DMA_QUEUED48 0x36 /* write w/DMA QUEUED command */
74 #define ATA_C_WRITE_MUL48 0x39 /* write multi command */
75 #define ATA_C_PACKET_CMD 0xa0 /* packet command */
76 #define ATA_C_ATAPI_IDENTIFY 0xa1 /* get ATAPI params*/
77 #define ATA_C_SERVICE 0xa2 /* service command */
78 #define ATA_C_READ_MUL 0xc4 /* read multi command */
79 #define ATA_C_WRITE_MUL 0xc5 /* write multi command */
80 #define ATA_C_SET_MULTI 0xc6 /* set multi size command */
81 #define ATA_C_READ_DMA_QUEUED 0xc7 /* read w/DMA QUEUED command */
82 #define ATA_C_READ_DMA 0xc8 /* read w/DMA command */
83 #define ATA_C_WRITE_DMA 0xca /* write w/DMA command */
84 #define ATA_C_WRITE_DMA_QUEUED 0xcc /* write w/DMA QUEUED command */
85 #define ATA_C_SLEEP 0xe6 /* sleep command */
86 #define ATA_C_FLUSHCACHE 0xe7 /* flush cache to disk */
87 #define ATA_C_FLUSHCACHE48 0xea /* flush cache to disk */
88 #define ATA_C_ATA_IDENTIFY 0xec /* get ATA params */
89 #define ATA_C_SETFEATURES 0xef /* features command */
90 #define ATA_C_F_SETXFER 0x03 /* set transfer mode */
91 #define ATA_C_F_ENAB_WCACHE 0x02 /* enable write cache */
92 #define ATA_C_F_DIS_WCACHE 0x82 /* disable write cache */
93 #define ATA_C_F_ENAB_RCACHE 0xaa /* enable readahead cache */
94 #define ATA_C_F_DIS_RCACHE 0x55 /* disable readahead cache */
95 #define ATA_C_F_ENAB_RELIRQ 0x5d /* enable release interrupt */
96 #define ATA_C_F_DIS_RELIRQ 0xdd /* disable release interrupt */
97 #define ATA_C_F_ENAB_SRVIRQ 0x5e /* enable service interrupt */
98 #define ATA_C_F_DIS_SRVIRQ 0xde /* disable service interrupt */
100 #define ATA_STATUS 0x07 /* status register */
101 #define ATA_S_ERROR 0x01 /* error */
102 #define ATA_S_INDEX 0x02 /* index */
103 #define ATA_S_CORR 0x04 /* data corrected */
104 #define ATA_S_DRQ 0x08 /* data request */
105 #define ATA_S_DSC 0x10 /* drive seek completed */
106 #define ATA_S_SERVICE 0x10 /* drive needs service */
107 #define ATA_S_DWF 0x20 /* drive write fault */
108 #define ATA_S_DMA 0x20 /* DMA ready */
109 #define ATA_S_READY 0x40 /* drive ready */
110 #define ATA_S_BUSY 0x80 /* busy */
112 #define ATA_ALTSTAT 0x00 /* alternate status register */
113 #define ATA_ALTOFFSET 0x206 /* alternate registers offset */
114 #define ATA_PCCARD_ALTOFFSET 0x0e /* do for PCCARD devices */
115 #define ATA_A_IDS 0x02 /* disable interrupts */
116 #define ATA_A_RESET 0x04 /* RESET controller */
117 #define ATA_A_4BIT 0x08 /* 4 head bits */
120 #define ATA_PRIMARY 0x1f0
121 #define ATA_SECONDARY 0x170
122 #define ATA_IOSIZE 0x08
123 #define ATA_ALTIOSIZE 0x01
124 #define ATA_BMIOSIZE 0x08
125 #define ATA_OP_FINISHED 0x00
126 #define ATA_OP_CONTINUES 0x01
127 #define ATA_IOADDR_RID 0
128 #define ATA_ALTADDR_RID 1
129 #define ATA_BMADDR_RID 2
130 #define ATA_IRQ_RID 0
131 #define ATA_DEV(device) ((device == ATA_MASTER) ? 0 : 1)
133 /* busmaster DMA related defines */
134 #define ATA_DMA_ENTRIES 256
135 #define ATA_DMA_EOT 0x80000000
137 #define ATA_BMCMD_PORT 0x00
138 #define ATA_BMCMD_START_STOP 0x01
139 #define ATA_BMCMD_WRITE_READ 0x08
141 #define ATA_BMDEVSPEC_0 0x01
143 #define ATA_BMSTAT_PORT 0x02
144 #define ATA_BMSTAT_ACTIVE 0x01
145 #define ATA_BMSTAT_ERROR 0x02
146 #define ATA_BMSTAT_INTERRUPT 0x04
147 #define ATA_BMSTAT_MASK 0x07
148 #define ATA_BMSTAT_DMA_MASTER 0x20
149 #define ATA_BMSTAT_DMA_SLAVE 0x40
150 #define ATA_BMSTAT_DMA_SIMPLEX 0x80
152 #define ATA_BMDEVSPEC_1 0x03
153 #define ATA_BMDTP_PORT 0x04
155 /* structure for holding DMA address data */
156 struct ata_dmaentry {
161 /* structure describing an ATA/ATAPI device */
163 struct ata_channel *channel;
164 int unit; /* unit number */
165 #define ATA_MASTER 0x00
166 #define ATA_SLAVE 0x10
168 char *name; /* device name */
169 struct ata_params *param; /* ata param structure */
170 void *driver; /* ptr to driver for device */
172 #define ATA_D_USE_CHS 0x0001
173 #define ATA_D_DETACHING 0x0002
174 #define ATA_D_MEDIA_CHANGED 0x0004
175 #define ATA_D_ENC_PRESENT 0x0008
177 int mode; /* transfermode */
178 int cmd; /* last cmd executed */
179 void *result; /* misc data */
182 /* structure describing an ATA channel */
184 struct device *dev; /* device handle */
185 int unit; /* channel number */
186 struct resource *r_io; /* io addr resource handle */
187 struct resource *r_altio; /* altio addr resource handle */
188 struct resource *r_bmio; /* bmio addr resource handle */
189 struct resource *r_irq; /* interrupt of this channel */
190 void *ih; /* interrupt handle */
191 int (*intr_func)(struct ata_channel *); /* interrupt function */
192 u_int32_t chiptype; /* pciid of controller chip */
193 u_int32_t alignment; /* dma engine min alignment */
194 int flags; /* controller flags */
195 #define ATA_NO_SLAVE 0x01
196 #define ATA_USE_16BIT 0x02
197 #define ATA_ATAPI_DMA_RO 0x04
198 #define ATA_QUEUED 0x08
199 #define ATA_DMA_ACTIVE 0x10
201 struct ata_device device[2]; /* devices on this channel */
205 int devices; /* what is present */
206 #define ATA_ATA_MASTER 0x01
207 #define ATA_ATA_SLAVE 0x02
208 #define ATA_ATAPI_MASTER 0x04
209 #define ATA_ATAPI_SLAVE 0x08
211 u_int8_t status; /* last controller status */
212 u_int8_t error; /* last controller error */
213 int active; /* active processing request */
214 #define ATA_IDLE 0x0000
215 #define ATA_IMMEDIATE 0x0001
216 #define ATA_WAIT_INTR 0x0002
217 #define ATA_WAIT_READY 0x0004
218 #define ATA_WAIT_MASK 0x0007
219 #define ATA_ACTIVE 0x0010
220 #define ATA_ACTIVE_ATA 0x0020
221 #define ATA_ACTIVE_ATAPI 0x0040
222 #define ATA_CONTROL 0x0080
224 TAILQ_HEAD(, ad_request) ata_queue; /* head of ATA queue */
225 TAILQ_HEAD(, atapi_request) atapi_queue; /* head of ATAPI queue */
226 void *running; /* currently running request */
229 /* disk bay/enclosure related */
230 #define ATA_LED_OFF 0x00
231 #define ATA_LED_RED 0x01
232 #define ATA_LED_GREEN 0x02
233 #define ATA_LED_ORANGE 0x03
234 #define ATA_LED_MASK 0x03
237 extern devclass_t ata_devclass;
239 /* public prototypes */
240 int ata_probe(device_t);
241 int ata_attach(device_t);
242 int ata_detach(device_t);
243 int ata_resume(device_t);
245 void ata_start(struct ata_channel *);
246 void ata_reset(struct ata_channel *);
247 int ata_reinit(struct ata_channel *);
248 int ata_wait(struct ata_device *, u_int8_t);
249 int ata_command(struct ata_device *, u_int8_t, u_int64_t, u_int16_t, u_int8_t, int);
250 void ata_enclosure_leds(struct ata_device *, u_int8_t);
251 void ata_enclosure_print(struct ata_device *);
252 int ata_printf(struct ata_channel *, int, const char *, ...) __printflike(3, 4);
253 int ata_prtdev(struct ata_device *, const char *, ...) __printflike(2, 3);
254 void ata_set_name(struct ata_device *, char *, int);
255 void ata_free_name(struct ata_device *);
256 int ata_get_lun(u_int32_t *);
257 int ata_test_lun(u_int32_t *, int);
258 void ata_free_lun(u_int32_t *, int);
259 char *ata_mode2str(int);
260 int ata_pmode(struct ata_params *);
261 int ata_wmode(struct ata_params *);
262 int ata_umode(struct ata_params *);
263 int ata_find_dev(device_t, u_int32_t, u_int32_t);
265 void *ata_dmaalloc(struct ata_channel *, int);
266 void ata_dmainit(struct ata_channel *, int, int, int, int);
267 int ata_dmasetup(struct ata_channel *, int, struct ata_dmaentry *, caddr_t, int);
268 void ata_dmastart(struct ata_channel *, int, struct ata_dmaentry *, int);
269 int ata_dmastatus(struct ata_channel *);
270 int ata_dmadone(struct ata_channel *);
272 /* macros for locking a channel */
273 #define ATA_LOCK_CH(ch, value)\
274 (((ch)->active == ATA_IDLE) ? ((ch)->active = value) : 0)
276 #define ATA_SLEEPLOCK_CH(ch, value) {\
277 while ((ch)->active != ATA_IDLE)\
278 tsleep((caddr_t)&(ch), PRIBIO, "atalck", 1);\
279 (ch)->active = value; }
281 #define ATA_FORCELOCK_CH(ch, value) \
284 #define ATA_UNLOCK_CH(ch) \
285 (ch)->active = ATA_IDLE
287 /* macros to hide busspace uglyness */
288 #define ATA_INB(res, offset) \
289 bus_space_read_1(rman_get_bustag((res)), \
290 rman_get_bushandle((res)), (offset))
291 #define ATA_INW(res, offset) \
292 bus_space_read_2(rman_get_bustag((res)), \
293 rman_get_bushandle((res)), (offset))
294 #define ATA_INL(res, offset) \
295 bus_space_read_4(rman_get_bustag((res)), \
296 rman_get_bushandle((res)), (offset))
297 #define ATA_INSW(res, offset, addr, count) \
298 bus_space_read_multi_2(rman_get_bustag((res)), \
299 rman_get_bushandle((res)), \
300 (offset), (addr), (count))
301 #define ATA_INSL(res, offset, addr, count) \
302 bus_space_read_multi_4(rman_get_bustag((res)), \
303 rman_get_bushandle((res)), \
304 (offset), (addr), (count))
305 #define ATA_OUTB(res, offset, value) \
306 bus_space_write_1(rman_get_bustag((res)), \
307 rman_get_bushandle((res)), (offset), (value))
308 #define ATA_OUTW(res, offset, value) \
309 bus_space_write_2(rman_get_bustag((res)), \
310 rman_get_bushandle((res)), (offset), (value))
311 #define ATA_OUTL(res, offset, value) \
312 bus_space_write_4(rman_get_bustag((res)), \
313 rman_get_bushandle((res)), (offset), (value))
314 #define ATA_OUTSW(res, offset, addr, count) \
315 bus_space_write_multi_2(rman_get_bustag((res)), \
316 rman_get_bushandle((res)), \
317 (offset), (addr), (count))
318 #define ATA_OUTSL(res, offset, addr, count) \
319 bus_space_write_multi_4(rman_get_bustag((res)), \
320 rman_get_bushandle((res)), \
321 (offset), (addr), (count))