sys/net/i4b/layer1/isic/i4b_drn_ngo.c

   1 /*
   2  * Copyright (c) 1997, 2001 Hellmuth Michaelis. All rights reserved.
   3  *
   4  * Redistribution and use in source and binary forms, with or without
   5  * modification, are permitted provided that the following conditions
   6  * are met:
   7  * 1. Redistributions of source code must retain the above copyright
   8  *    notice, this list of conditions and the following disclaimer.
   9  * 2. Redistributions in binary form must reproduce the above copyright
  10  *    notice, this list of conditions and the following disclaimer in the
  11  *    documentation and/or other materials provided with the distribution.
  12  *
  13  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  14  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  15  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  16  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  17  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  18  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  19  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  21  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  23  * SUCH DAMAGE.
  24  *
  25  *---------------------------------------------------------------------------
  26  *
  27  *      i4b_drn_ngo.c - Dr. Neuhaus Niccy GO@ and SAGEM Cybermod
  28  *      --------------------------------------------------------
  29  *
  30  * $FreeBSD: src/sys/i4b/layer1/isic/i4b_drn_ngo.c,v 1.5.2.1 2001/08/10 14:08:38 obrien Exp $
  31  *
  32  *      last edit-date: [Wed Jan 24 09:07:44 2001]
  33  *
  34  *---------------------------------------------------------------------------*/
  35
  36 #include "isic.h"
  37 #include "opt_i4b.h"
  38
  39 #if (NISIC > 0) && defined(DRN_NGO)
  40
  41 #include <sys/param.h>
  42 #include <sys/systm.h>
  43 #include <sys/socket.h>
  44 #include <net/if.h>
  45
  46 #include <machine/i4b_ioctl.h>
  47
  48 #include <i4b/layer1/isic/i4b_isic.h>
  49 #include <i4b/layer1/isic/i4b_hscx.h>
  50
  51 /*---------------------------------------------------------------------------*
  52  *      Niccy GO@ definitions
  53  *
  54  *      the card uses 2 i/o addressranges each using 2 bytes
  55  *
  56  *      addressrange 0:
  57  *              offset 0 - ISAC dataregister
  58  *              offset 1 - HSCX dataregister
  59  *      addressrange 1:
  60  *              offset 0 - ISAC addressregister
  61  *              offset 1 - HSCX addressregister
  62  *
  63  *      to access an ISAC/HSCX register, you have to write the register
  64  *      number into the ISAC or HSCX addressregister and then read/write
  65  *      data for the ISAC/HSCX register into/from the corresponding
  66  *      dataregister.
  67  *
  68  *      Thanks to Klaus Muehle of Dr. Neuhaus Telekommunikation for giving
  69  *      out this information!
  70  *
  71  *---------------------------------------------------------------------------*/
  72 #define NICCY_PORT_MIN  0x200
  73 #define NICCY_PORT_MAX  0x3e0
  74
  75 #define HSCX_ABIT       0x1000          /* flag, HSCX A is meant */
  76 #define HSCX_BBIT       0x2000          /* flag, HSCX B is meant */
  77
  78 #define HSCX_BOFF       0x40
  79
  80 #define ADDR_OFF        2               /* address register range offset */
  81
  82 #define ISAC_DATA       0
  83 #define HSCX_DATA       1
  84
  85 #define ISAC_ADDR       0
  86 #define HSCX_ADDR       1
  87
  88 /*---------------------------------------------------------------------------*
  89  *      Dr. Neuhaus Niccy GO@ read fifo routine
  90  *---------------------------------------------------------------------------*/
  91 static void
  92 drnngo_read_fifo(struct l1_softc *sc, int what, void *buf, size_t size)
  93 {
  94         bus_space_tag_t tdata, tadr;
  95         bus_space_handle_t hdata, hadr;
  96
  97         tdata = rman_get_bustag(sc->sc_resources.io_base[0]);
  98         hdata = rman_get_bushandle(sc->sc_resources.io_base[0]);
  99         tadr = rman_get_bustag(sc->sc_resources.io_base[1]);
 100         hadr = rman_get_bushandle(sc->sc_resources.io_base[1]);
 101
 102         switch(what)
 103         {
 104                 case ISIC_WHAT_ISAC:
 105                         bus_space_write_1     (tadr ,hadr, ISAC_ADDR,0x0);
 106                         bus_space_read_multi_1(tdata,hdata,ISAC_DATA,buf,size);
 107                         break;
 108                 case ISIC_WHAT_HSCXA:
 109                         bus_space_write_1     (tadr ,hadr ,HSCX_ADDR,0x0);
 110                         bus_space_read_multi_1(tdata,hdata,HSCX_DATA,buf,size);
 111                         break;
 112                 case ISIC_WHAT_HSCXB:
 113                         bus_space_write_1     (tadr ,hadr ,HSCX_ADDR,HSCX_BOFF);
 114                         bus_space_read_multi_1(tdata,hdata,HSCX_DATA,buf,size);
 115                         break;
 116         }
 117 }
 118
 119 /*---------------------------------------------------------------------------*
 120  *      Dr. Neuhaus Niccy GO@ write fifo routine
 121  *---------------------------------------------------------------------------*/
 122 static void
 123 drnngo_write_fifo(struct l1_softc *sc, int what, void *buf, size_t size)
 124 {
 125         bus_space_tag_t tdata, tadr;
 126         bus_space_handle_t hdata, hadr;
 127
 128         tdata = rman_get_bustag(sc->sc_resources.io_base[0]);
 129         hdata = rman_get_bushandle(sc->sc_resources.io_base[0]);
 130         tadr = rman_get_bustag(sc->sc_resources.io_base[1]);
 131         hadr = rman_get_bushandle(sc->sc_resources.io_base[1]);
 132
 133         switch(what)
 134         {
 135                 case ISIC_WHAT_ISAC:
 136                         bus_space_write_1      (tadr ,hadr, ISAC_ADDR,0x0);
 137                         bus_space_write_multi_1(tdata,hdata,ISAC_DATA,buf,size);
 138                         break;
 139                 case ISIC_WHAT_HSCXA:
 140                         bus_space_write_1      (tadr ,hadr ,HSCX_ADDR,0x0);
 141                         bus_space_write_multi_1(tdata,hdata,HSCX_DATA,buf,size);
 142                         break;
 143                 case ISIC_WHAT_HSCXB:
 144                         bus_space_write_1      (tadr ,hadr ,HSCX_ADDR,HSCX_BOFF);
 145                         bus_space_write_multi_1(tdata,hdata,HSCX_DATA,buf,size);
 146                         break;
 147         }
 148 }
 149
 150 /*---------------------------------------------------------------------------*
 151  *      Dr. Neuhaus Niccy GO@ write register routine
 152  *---------------------------------------------------------------------------*/
 153 static void
 154 drnngo_write_reg(struct l1_softc *sc, int what, bus_size_t reg, u_int8_t data)
 155 {
 156         bus_space_tag_t tdata, tadr;
 157         bus_space_handle_t hdata, hadr;
 158
 159         tdata = rman_get_bustag(sc->sc_resources.io_base[0]);
 160         hdata = rman_get_bushandle(sc->sc_resources.io_base[0]);
 161         tadr = rman_get_bustag(sc->sc_resources.io_base[1]);
 162         hadr = rman_get_bushandle(sc->sc_resources.io_base[1]);
 163
 164         switch(what)
 165         {
 166                 case ISIC_WHAT_ISAC:
 167                         bus_space_write_1(tadr ,hadr, ISAC_ADDR,reg);
 168                         bus_space_write_1(tdata,hdata,ISAC_DATA,data);
 169                         break;
 170                 case ISIC_WHAT_HSCXA:
 171                         bus_space_write_1(tadr ,hadr ,HSCX_ADDR,reg);
 172                         bus_space_write_1(tdata,hdata,HSCX_DATA,data);
 173                         break;
 174                 case ISIC_WHAT_HSCXB:
 175                         bus_space_write_1(tadr ,hadr ,HSCX_ADDR,reg+HSCX_BOFF);
 176                         bus_space_write_1(tdata,hdata,HSCX_DATA,data);
 177                         break;
 178         }
 179 }
 180
 181 /*---------------------------------------------------------------------------*
 182  *      Dr. Neuhaus Niccy GO@ read register routine
 183  *---------------------------------------------------------------------------*/
 184 static u_int8_t
 185 drnngo_read_reg(struct l1_softc *sc, int what, bus_size_t reg)
 186 {
 187         bus_space_tag_t tdata, tadr;
 188         bus_space_handle_t hdata, hadr;
 189
 190         tdata = rman_get_bustag(sc->sc_resources.io_base[0]);
 191         hdata = rman_get_bushandle(sc->sc_resources.io_base[0]);
 192         tadr = rman_get_bustag(sc->sc_resources.io_base[1]);
 193         hadr = rman_get_bushandle(sc->sc_resources.io_base[1]);
 194
 195         switch(what)
 196         {
 197                 case ISIC_WHAT_ISAC:
 198                         bus_space_write_1(tadr ,hadr, ISAC_ADDR,reg);
 199                         return bus_space_read_1(tdata,hdata,ISAC_DATA);
 200                 case ISIC_WHAT_HSCXA:
 201                         bus_space_write_1(tadr ,hadr ,HSCX_ADDR,reg);
 202                         return bus_space_read_1(tdata,hdata,HSCX_DATA);
 203                 case ISIC_WHAT_HSCXB:
 204                         bus_space_write_1(tadr ,hadr ,HSCX_ADDR,reg+HSCX_BOFF);
 205                         return bus_space_read_1(tdata,hdata,HSCX_DATA);
 206                 default:
 207                         return 0;
 208         }
 209 }
 210
 211 /*---------------------------------------------------------------------------*
 212  *      probe for ISA PnP cards
 213  *---------------------------------------------------------------------------*/
 214 int
 215 isic_attach_drnngo(device_t dev)
 216 {
 217         int unit = device_get_unit(dev);
 218         struct l1_softc *sc = &l1_sc[unit];
 219
 220         sc->sc_resources.io_rid[1] = 1;
 221
 222         /*
 223          * this card needs a second io_base,
 224          * free resources if we don't get it
 225          */
 226
 227         if(!(sc->sc_resources.io_base[1] =
 228                         bus_alloc_resource(dev, SYS_RES_IOPORT,
 229                                         &sc->sc_resources.io_rid[1],
 230                                         0UL, ~0UL, 1, RF_ACTIVE)))
 231         {
 232                 printf("isic%d: Failed to get second io base.\n", unit);
 233                 isic_detach_common(dev);
 234                 return ENXIO;
 235         }
 236
 237         /* setup ISAC access routines */
 238
 239         sc->clearirq = NULL;
 240         sc->readreg = drnngo_read_reg;
 241         sc->writereg = drnngo_write_reg;
 242
 243         sc->readfifo = drnngo_read_fifo;
 244         sc->writefifo = drnngo_write_fifo;
 245
 246         /* setup card type */
 247
 248         sc->sc_cardtyp = CARD_TYPEP_DRNNGO;
 249
 250         /* setup IOM bus type */
 251
 252         sc->sc_bustyp = BUS_TYPE_IOM2;
 253
 254         sc->sc_ipac = 0;
 255         sc->sc_bfifolen = HSCX_FIFO_LEN;
 256
 257         return (0);
 258 }
 259
 260 #endif /* (NISIC > 0) && defined(DRN_NGO) */