1 /*#######################################################################*/
4 /* REMARKS: This file contains all defines used by DDK functions. It*/
5 /* should be included by all applications and should be*/
6 /* referenced by programmers to make their code easy to read*/
10 /* 7/10/95 --- added #def DRAM_HOLES*/
11 /*#######################################################################*/
14 /*#######################################################################*/
16 /* Macros for use in loading Synth Addr Regs*/
18 /*#######################################################################*/
19 #define ADDR_HIGH(x) (short)(x>>7)
20 #define ADDR_LOW(x) (short)(x<<9)
21 /*#######################################################################*/
23 /* Defines for DMA Controllers*/
25 /*#######################################################################*/
26 /* DMA Controler #1 (8-bit controller) */
27 #define DMA1_STAT 0x08 /* read status register */
28 #define DMA1_WCMD 0x08 /* write command register */
29 #define DMA1_WREQ 0x09 /* write request register */
30 #define DMA1_SNGL 0x0A /* write single bit register */
31 #define DMA1_MODE 0x0B /* write mode register */
32 #define DMA1_CLRFF 0x0C /* clear byte ptr flip/flop */
33 #define DMA1_MCLR 0x0D /* master clear register */
34 #define DMA1_CLRM 0x0E /* clear mask register */
35 #define DMA1_WRTALL 0x0F /* write all mask register */
37 /* DMA Controler #2 (16-bit controller) */
38 #define DMA2_STAT 0xD0 /* read status register */
39 #define DMA2_WCMD 0xD0 /* write command register */
40 #define DMA2_WREQ 0xD2 /* write request register */
41 #define DMA2_SNGL 0xD4 /* write single bit register */
42 #define DMA2_MODE 0xD6 /* write mode register */
43 #define DMA2_CLRFF 0xD8 /* clear byte ptr flip/flop */
44 #define DMA2_MCLR 0xDA /* master clear register */
45 #define DMA2_CLRM 0xDC /* clear mask register */
46 #define DMA2_WRTALL 0xDE /* write all mask register */
48 #define DMA0_ADDR 0x00 /* chan 0 base adddress */
49 #define DMA0_CNT 0x01 /* chan 0 base count */
50 #define DMA1_ADDR 0x02 /* chan 1 base adddress */
51 #define DMA1_CNT 0x03 /* chan 1 base count */
52 #define DMA2_ADDR 0x04 /* chan 2 base adddress */
53 #define DMA2_CNT 0x05 /* chan 2 base count */
54 #define DMA3_ADDR 0x06 /* chan 3 base adddress */
55 #define DMA3_CNT 0x07 /* chan 3 base count */
56 #define DMA4_ADDR 0xC0 /* chan 4 base adddress */
57 #define DMA4_CNT 0xC2 /* chan 4 base count */
58 #define DMA5_ADDR 0xC4 /* chan 5 base adddress */
59 #define DMA5_CNT 0xC6 /* chan 5 base count */
60 #define DMA6_ADDR 0xC8 /* chan 6 base adddress */
61 #define DMA6_CNT 0xCA /* chan 6 base count */
62 #define DMA7_ADDR 0xCC /* chan 7 base adddress */
63 #define DMA7_CNT 0xCE /* chan 7 base count */
65 #define DMA0_PAGE 0x87 /* chan 0 page register (refresh)*/
66 #define DMA1_PAGE 0x83 /* chan 1 page register */
67 #define DMA2_PAGE 0x81 /* chan 2 page register */
68 #define DMA3_PAGE 0x82 /* chan 3 page register */
69 #define DMA4_PAGE 0x8F /* chan 4 page register (unusable)*/
70 #define DMA5_PAGE 0x8B /* chan 5 page register */
71 #define DMA6_PAGE 0x89 /* chan 6 page register */
72 #define DMA7_PAGE 0x8A /* chan 7 page register */
73 /*#######################################################################*/
75 /* Defines for register UISR (Interrupt Status)*/
77 /*#######################################################################*/
78 #define MIDI_TX_IRQ 0x01
79 #define MIDI_RX_IRQ 0x02
80 #define ALIB_TIMER1_IRQ 0x04
81 #define ALIB_TIMER2_IRQ 0x08
82 #define _UASBCI 0x45 /* UASBCI index */
83 #define SAMPLE_CONTROL 0x49 /* Not used by IW */
84 #define SET_VOICES 0x0E
85 #define WAVETABLE_IRQ 0x20
86 #define ENVELOPE_IRQ 0x40
87 #define DMA_TC_IRQ 0x80
88 /*#######################################################################*/
90 /* Synthesizer-related defines*/
92 /*#######################################################################*/
93 #define GEN_INDEX 0x03 /* IGIDX offset into p3xr */
94 #define VOICE_SELECT 0x02 /* SVSR offset into p3xr */
95 #define VOICE_IRQS 0x8F /* SVII index (read) */
96 #define _URSTI 0x4C /* URSTI index */
97 #define GF1_SET 0x01 /* URSTI[0] */
98 #define GF1_OUT_ENABLE 0x02 /* URSTI[1] */
99 #define GF1_IRQ_ENABLE 0x04 /* URSTI[2] */
100 #define GF1_RESET 0xFE /* URSTI[0]=0 */
101 #define VOICE_VOLUME_IRQ 0x04 /* SVII[2] */
102 #define VOICE_WAVE_IRQ 0x08 /* SVII[3] */
103 #define VC_IRQ_ENABLE 0x20 /* SACI[5] or SVCI[5]*/
104 #define VOICE_NUMBER 0x1F /* Mask for SVII[4:0] */
105 #define VC_IRQ_PENDING 0x80 /* SACI[7] or SVCI[7] */
106 #define VC_DIRECT 0x40 /* SACI[6] or SVCI[6]*/
107 #define VC_DATA_WIDTH 0x04 /* SACI[2] */
108 #define VOICE_STOP 0x02 /* SACI[1] */
109 #define VOICE_STOPPED 0x01 /* SACI[0] */
110 #define VOLUME_STOP 0x02 /* SVCI[1] */
111 #define VOLUME_STOPPED 0x01 /* SVCI[0] */
112 #define VC_ROLLOVER 0x04 /* SVCI[2] */
113 #define VC_LOOP_ENABLE 0x08 /* SVCI[3] or SACI[3]*/
114 #define VC_BI_LOOP 0x10 /* SVCI[4] or SACI[4]*/
115 #define VOICE_OFFSET 0x20 /* SMSI[5] */
116 #define VOLUME_RATE0 0x00 /* SVRI[7:6]=(0,0) */
117 #define VOLUME_RATE1 0x40 /* SVRI[7:6]=(0,1) */
118 #define VOLUME_RATE2 0x80 /* SVRI[7:6]=(1,0) */
119 #define VOLUME_RATE3 0xC0 /* SVRI[7:6]=(1,1) */
120 /*#######################################################################*/
122 /* Power-Mode Control Defines*/
124 /*#######################################################################*/
125 #define SHUT_DOWN 0x7E /* shuts InterWave down */
126 #define POWER_UP 0xFE /* enables all modules */
127 #define CODEC_PWR_UP 0x81 /* enables Codec Analog Ckts */
128 #define CODEC_PWR_DOWN 0x01 /* disables Codec Analog Ckts */
129 #define CODEC_REC_UP 0x82 /* Enables Record Path */
130 #define CODEC_REC_DOWN 0x02 /* Disables Record Path */
131 #define CODEC_PLAY_UP 0x84 /* Enables Playback Path */
132 #define CODEC_PLAY_DOWN 0x04 /* Disables Playback Path */
133 #define CODEC_IRQ_ENABLE 0x02 /* CEXTI[2] */
134 #define CODEC_TIMER_IRQ 0x40 /* CSR3I[6] */
135 #define CODEC_REC_IRQ 0x20 /* CSR3I[5] */
136 #define CODEC_PLAY_IRQ 0x10 /* CSR3I[4] */
137 #define CODEC_INT 0x01 /* CSR1R[0] */
138 #define MONO_INPUT 0x80 /* CMONOI[7] */
139 #define MONO_OUTPUT 0x40 /* CMONOI[6] */
140 #define MIDI_UP 0x88 /* Enables MIDI ports */
141 #define MIDI_DOWN 0x08 /* Disables MIDI ports */
142 #define SYNTH_UP 0x90 /* Enables Synthesizer */
143 #define SYNTH_DOWN 0x10 /* Disables Synthesizer */
144 #define LMC_UP 0xA0 /* Enables LM Module */
145 #define LMC_DOWN 0x20 /* Disbales LM Module */
146 #define XTAL24_UP 0xC0 /* Enables 24MHz Osc */
147 #define XTAL24_DOWN 0x40 /* Disables 24MHz Osc */
148 #define _PPWRI 0xF2 /* PPWRI index */
151 #define LEFT_AUX1_INPUT 0x02
152 #define RIGHT_AUX1_INPUT 0x03
153 #define LEFT_AUX2_INPUT 0x04
154 #define RIGHT_AUX2_INPUT 0x05
155 #define LEFT_LINE_IN 0x12
156 #define RIGHT_LINE_IN 0x13
157 #define LEFT_LINE_OUT 0x19
158 #define RIGHT_LINE_OUT 0x1B
159 #define LEFT_SOURCE 0x00
160 #define RIGHT_SOURCE 0x01
165 #define LEFT_DAC 0x06
166 #define RIGHT_DAC 0x07
167 #define LEFT_MIC_IN 0x16
168 #define RIGHT_MIC_IN 0x17
186 /*#######################################################################*/
188 /* Defines for DMA transfer related operations*/
190 /*#######################################################################*/
192 #define DMA_DECREMENT 0x20
193 #define AUTO_INIT 0x10
194 #define DMA_READ 0x01
195 #define DMA_WRITE 0x02
196 #define AUTO_READ 0x03
197 #define AUTO_WRITE 0x04
198 #define IDMA_INV 0x0400
199 #define IDMA_WIDTH_16 0x0100
200 /*#######################################################################*/
202 /* Bits for dma flags within a DMA structure.*/
204 /*#######################################################################*/
205 #define DMA_USED 0x0001
207 #define DMA_SPLIT 0x0004 /* DMA Controller Page Crossover*/
208 #define CODEC_DMA 0x0008 /* Indicates a Codec DMA*/
209 #define DMA_WAIT 0x0020 /* Wait for DMA xfer to complete*/
210 #define DMA_DOWN 0x0040 /* DMA xfer from PC to InterWave*/
211 #define DRAM_HOLES 0x8000 /* Indicates Non-contiguous RAM configuration*/
212 #define DMA_UP 0xFFBF /* DMA xfer from InterWave to PC */
213 /*#######################################################################*/
215 /* Bits for DMA Control Register (LDMACI)*/
217 /*#######################################################################*/
218 #define _LDMACI 0x41 /* Index */
220 #define DMA_IRQ_ENABLE 0x20
221 #define DMA_IRQ_PENDING 0x40 /* on reads of LDMACI[6] */
222 #define DMA_DATA_16 0x40 /* on writes to LDMACI[6] */
223 #define DMA_WIDTH_16 0x04 /* 1=16-bit, 0=8-bit (DMA channel) */
224 #define DMA_RATE 0x18 /* 00=fastest,...,11=slowest */
225 #define DMA_UPLOAD 0x02 /* From LM to PC */
226 #define DMA_ENABLE 0x01
227 /*#######################################################################*/
229 /* DMA Transfer Rates*/
231 /*#######################################################################*/
232 #define DMA_R0 0xE7 /* Fastest (use ANDing to set) */
235 #define DMA_R3 0x18 /* Slowest */
236 /*#######################################################################*/
238 /* Interrupt Controller Defines*/
240 /*#######################################################################*/
241 #define IW_HANDLERS_ON 0x80 /* Flag for when IVT is modified */
243 #define OCR1 0x20 /* 8259-1 Operation Control Reg. */
244 #define IMR1 0x21 /* 8259-1 Interrupt Mask Reg. */
245 #define OCR2 0xA0 /* 8259-2 Operation Control Reg. */
246 #define IMR2 0xA1 /* 8259-2 Interrupt Mask Reg. */
247 #define IRQ0_UNMASK 0xFE /* Mask to clear bit 0 in IMR */
248 #define IRQ1_UNMASK 0xFD
249 #define IRQ2_UNMASK 0xFB
250 #define IRQ3_UNMASK 0xF7
251 #define IRQ4_UNMASK 0xEF
252 #define IRQ5_UNMASK 0xDF
253 #define IRQ6_UNMASK 0xBF
254 #define IRQ7_UNMASK 0x7F
255 #define IRQ8_UNMASK 0xFE /* Mask to clear bit 0 in IMR */
256 #define IRQ9_UNMASK 0xFD
257 #define IRQ10_UNMASK 0xFB
258 #define IRQ11_UNMASK 0xF7
259 #define IRQ12_UNMASK 0xEF
260 #define IRQ13_UNMASK 0xDF
261 #define IRQ14_UNMASK 0xBF
262 #define IRQ15_UNMASK 0x7F
263 #define IRQ0_EOI 0x60 /* Spec EOI for IRQ0 */
264 #define IRQ1_EOI 0x61
265 #define IRQ2_EOI 0x62
266 #define IRQ3_EOI 0x63
267 #define IRQ4_EOI 0x64
268 #define IRQ5_EOI 0x65
269 #define IRQ6_EOI 0x66
270 #define IRQ7_EOI 0x67
271 #define IRQ8_EOI 0x60 /* Spec EOI for IRQ8 */
272 #define IRQ9_EOI 0x61
273 #define IRQ10_EOI 0x62
274 #define IRQ11_EOI 0x63
275 #define IRQ12_EOI 0x64
276 #define IRQ13_EOI 0x65
277 #define IRQ14_EOI 0x66
278 #define IRQ15_EOI 0x67
279 /*#######################################################################*/
283 /*#######################################################################*/
285 #define MEMBANK0 0L /* Addr of Memory Bank 0*/
286 #define MEMBANK1 4194304L /* Addr of Memory Bank 1*/
287 #define MEMBANK2 8388608L /* Addr of Memory Bank 2*/
288 #define MEMBANK3 12582912L /* Addr of Memory Bank 3*/
289 #define IRQ_UNAVAIL 0x0000
290 #define IRQ_AVAIL 0x0001
291 #define IRQ_USED 0x0002
293 #define NEXT_OFFSET 0L
294 #define PREV_OFFSET 4L
295 #define SIZE_OFFSET 8L
296 #define MEM_HEADER_SIZE 12L
297 #define GF1_POOL (usigned long)(256L*1024L)
298 #define GUS_MODE 0x00 /* SGMI[0]=0*/
299 #define ENH_MODE 0x01 /* SGMI[0]=1*/
300 #define ENABLE_LFOS 0x02 /* SGMI[1]*/
301 #define NO_WAVETABLE 0x04 /* SGMI[2]*/
302 #define RAM_TEST 0x08 /* SGMI[3]*/
313 #define ALLOC_FAILURE 0xFFFFFFFFL
314 #define MEM_EXHAUSTED 0xFFFFFFFFL
315 #define RAM_MAX 16777216L
316 #define RAM_STEP 65536L
317 #define BANK_MAX 4194304L
318 #define ILLEGAL_SIZE -1
320 #define NO_NEXT 0xFFFFFFFFL
321 #define NO_PREV NO_NEXT
322 #define DMA_BAD_ADDR -1
325 #define MIDI_TX_IRQ 0x01
326 #define MIDI_RX_IRQ 0x02
327 #define ALIB_TIMER1_IRQ 0x04
328 #define ALIB_TIMER2_IRQ 0x08
329 #define WAVETABLE_IRQ 0x20
330 #define ENVELOPE_IRQ 0x40
331 #define DMA_TC_IRQ 0x80
332 #define DMA_SET_MASK 0x04
333 #define PNP_DATA_RDY 1 /* PRESSI[0] */
334 #define IWAVE_ABSENT 2
337 #define BAD_VOICES -1
338 #define PNP_ABSENT 0xFF /* No PNP cards in system */
339 #define DPMI_INT 0x31
343 #define _PNPWRP 0xA79
353 #define _SVCI_RD 0x8D
354 #define _SVCI_WR 0x0D
355 #define _SACI_RD 0x80
356 #define _SACI_WR 0x00
357 #define _SALI_RD 0x8B
358 #define _SALI_WR 0x0B
359 #define _SAHI_RD 0x8A
360 #define _SAHI_WR 0x0A
361 #define _SASHI_RD 0x82
362 #define _SASHI_WR 0x02
363 #define _SASLI_RD 0x83
364 #define _SASLI_WR 0x03
365 #define _SAEHI_RD 0x84
366 #define _SAEHI_WR 0x04
367 #define _SAELI_RD 0x85
368 #define _SAELI_WR 0x05
369 #define _SVRI_RD 0x86
370 #define _SVRI_WR 0x06
371 #define _SVSI_RD 0x87
372 #define _SVSI_WR 0x07
373 #define _SVEI_RD 0x88
374 #define _SVEI_WR 0x08
375 #define _SVLI_RD 0x89
376 #define _SVLI_WR 0x09
377 #define _SROI_RD 0x8C
378 #define _SROI_WR 0x0C
379 #define _SLOI_RD 0x93
380 #define _SLOI_WR 0x13
381 #define _SMSI_RD 0x95
382 #define _SMSI_WR 0x15
383 #define _SGMI_RD 0x99
384 #define _SGMI_WR 0x19
385 #define _SFCI_RD 0x81
386 #define _SFCI_WR 0x01
387 #define _SUAI_RD 0x90
388 #define _SUAI_WR 0x10
390 #define _CMODEI 0x0C /* index for CMODEI */
395 #define _CSR3I 0x18 /* Index to CSR3I (Interrupt Status) */
396 #define _CEXTI 0x0A /* Index to External Control Register */
397 #define _CFIG1I 0x09 /* Index to Codec Conf Reg 1 */
398 #define _CSR2I 0x0B /* Index to Codec Stat Reg 2 */
399 #define _CPDFI 0x08 /* Index to Play Data Format Reg */
400 #define _CRDFI 0x1C /* Index to Rec Data Format Reg */
401 #define _CLMICI 0x16 /* Index to Left Mic Input Ctrl Register */
402 #define _CRMICI 0x17 /* Index to Right Mic Input Ctrl Register */
403 #define _CLCI 0x0D /* Index to Loopback Ctrl Register */
404 #define _IVERI 0x5B /* Index to register IVERI */
405 #define CODEC_MODE1 0x00
406 #define CODEC_MODE2 0x40
407 #define CODEC_MODE3 0x6C /* Enhanced Mode */
408 #define CODEC_STATUS1 0x01
409 #define CODEC_STATUS2 0x0B /* Index to CSR2I */
410 #define CODEC_STATUS3 0x18 /* Index to CSR3I */
411 #define PLAYBACK 0x01 /* Enable playback path CFIG1I[0]=1*/
412 #define RECORD 0x02 /* Enable Record path CFIG1I[1]=1*/
413 #define TIMER_ENABLE 0x40 /* CFIG2I[6] */
414 #define CODEC_MCE 0x40 /* CIDXR[6] */
415 #define CALIB_IN_PROGRESS 0x20 /* CSR2I[5] */
416 #define CODEC_INIT 0x80 /* CIDXR[7] */
417 #define BIT16_BIG 0xC0 /* 16-bit signed, big endian */
418 #define IMA_ADPCM 0xA0 /* IMA-compliant ADPCM */
419 #define BIT8_ALAW 0x60 /* 8-bit A-law */
420 #define BIT16_LITTLE 0x40 /* 16-bit signed, lillte endian */
421 #define BIT8_ULAW 0x20 /* 8-bit u-law */
422 #define BIT8_LINEAR 0x00 /* 8-bit unsigned */
423 #define REC_DFORMAT 0x1C
424 #define PLAY_DFORMAT 0x08
425 #define DMA_ACCESS 0x00
426 #define PIO_ACCESS 0xC0
427 #define DMA_SIMPLEX 0x04
428 #define STEREO 0x10 /* CxDFI[4] */
429 #define XTAL1 0x00 /* CxDFI[4]=0 selects 24.5Mhz XTAL */
430 #define XTAL2 0x01 /* CxDFI[4]=1 selects 16.9Mhz XTAL */
431 #define AUTOCALIB 0x08 /* CFIG1I[3] */
432 #define ROM_IO 0x02 /* ROM I/O cycles - LMCI[1]=1 */
433 #define DRAM_IO 0x4D /* DRAM I/O cycles - LMCI[1]=0 */
434 #define AUTOI 0x01 /* LMCI[0]=1 */
436 #define ACTIVATE_DEV 0x30
437 #define _PWAKEI 0x03 /* Index for PWAKEI */
438 #define _PISOCI 0x01 /* Index for PISOCI */
439 #define _PSECI 0xF1 /* Index for PSECI */
440 #define RANGE_IOCHK 0x31 /* PURCI or PRRCI Index */
441 #define MIDI_RESET 0x03
442 #define IO_OK 5 /* No IO conflict flag */
443 #define IO_CONFLICT 6 /* IO Conflict detected */
446 /*#######################################################################*/
448 /* Defines for Sound Handlers in "iw".*/
450 /*#######################################################################*/
451 #define PLAY_DMA_HANDLER 0x01
452 #define REC_DMA_HANDLER 0x02
453 #define MIDI_TX_HANDLER 0x03
454 #define MIDI_RX_HANDLER 0x04
455 #define TIMER1_HANDLER 0x05
456 #define TIMER2_HANDLER 0x06
457 #define WAVE_HANDLER 0x07
458 #define VOLUME_HANDLER 0x08
459 #define CODEC_TIMER_HANDLER 0x09
460 #define CODEC_PLAY_HANDLER 0x0A
461 #define CODEC_REC_HANDLER 0x0B
462 #define AUX_HANDLER 0x0C
463 /*#######################################################################*/
465 /* Mapping for System Control Regs.*/
467 /*#######################################################################*/
468 #define UMCR 0x00010000 /* Mix Control Reg.*/
469 #define UISR 0x00020006 /* IRQ Stat Reg. (read) */
470 #define U2X6R 0x00030006 /* SB 2X6 reg */
471 #define UACWR 0x00040008 /* AdLib Command Write Reg */
472 #define UASRR 0x00050008 /* AdLib Stat Read Reg */
473 #define UADR 0x00060009 /* AdLib Data Register */
474 #define UACRR 0x0007000A /* AdLib Cmd Read Reg */
475 #define UASWR 0x0008000A /* AdLib Stat Write Reg */
476 #define UHRDP 0x0009000B /* Hidden Reg Data Port */
477 #define UI2XCR 0x000A000C /* SB IRQ 2xC Reg */
478 #define U2XCR 0x000B000D /* SB 2xC Reg. (No IRQ) */
479 #define U2XER 0x000C000E /* SB 2xE Reg. */
480 #define URCR 0x000D000F /* Reg Control Register */
481 #define USRR 0x000E000F /* Status Read Register */
482 #define UDCI 0x000F000B /* DMA Channel Control Reg */
483 #define UICI 0x0010000B /* Interrupt Ctrl Reg */
484 #define UGP1I 0x0011010B /* GP Reg 1 (Back Door) */
485 #define UGP2I 0x0012020B /* GP Reg 2 (Back Door) */
486 #define UGPA1I 0x0013030B /* GP reg 1 Address */
487 #define UGPA2I 0x0014040B /* GP reg 2 Address */
488 #define UCLRII 0x0015050B /* Clear Interrupt Reg */
489 #define UJMPI 0x0016060B /* Jumper Register */
490 #define UGP1II 0x0017000B /* Gen. Purp Reg 1(Emulation) */
491 #define UGP2II 0x0018000B /* Gen. Purp Reg 2(Emulation) */
492 #define GGCR 0x00190201 /* Game Control Register */
493 #define GMCR 0x001A0000 /* MIDI Control Register */
494 #define GMSR 0x001B0000 /* MIDI Status Reg. */
495 #define GMTDR 0x001C0001 /* MIDI xmit data reg */
496 #define GMRDR 0x001D0001 /* MIDI rcv data reg */
497 #define SVSR 0x001E0002 /* Synth Voice Select Reg */
498 #define IGIDXR 0x001F0003 /* General Index Register */
499 #define I16DP 0x00200004 /* General 16-bit Data Port */
500 #define I8DP 0x00210005 /* General 8-bit Data Port */
501 /*#######################################################################*/
505 /*#######################################################################*/
506 #define SACI 0x00220005 /* Synth Addr Control */
507 #define SFCI 0x00230104 /* Synth Freq Control */
508 #define SASHI 0x00240204 /* Synth Addr Start High */
509 #define SASLI 0x00250304 /* Synth Addr Start Low */
510 #define SAEHI 0x00260404 /* Synth Addr End High */
511 #define SAELI 0x00270504 /* Synth Addr End Low */
512 #define SVRI 0x00280605 /* Synth Volume Rate */
513 #define SVSI 0x00290705 /* Synth Volume Start */
514 #define SVEI 0x002A0805 /* Synth Volume End */
515 #define SVLI 0x002B0904 /* Synth Volume Level */
516 #define SAHI 0x002C0A04 /* Synth Address High */
517 #define SALI 0x002D0B04 /* Synth Address Low */
518 #define SROI 0x002E0C04 /* Synth Right Offset */
519 #define SVCI 0x002F0D05 /* Synth Volume Control */
520 #define SAVI 0x00300E05 /* Synth Active Voices */
521 #define SVII 0x00318F05 /* Synth Voice IRQ */
522 #define SUAI 0x00321005 /* Synth Upper Addr */
523 #define SEAHI 0x00331104 /* Synth Effect Addr High */
524 #define SEALI 0x00341204 /* Synth Effect Addr Low */
525 #define SLOI 0x00351304 /* Synth Left Offset */
526 #define SEASI 0x00361405 /* Synth Effects Accum Sel */
527 #define SMSI 0x00371505 /* Synth Mode Select */
528 #define SEVI 0x00381604 /* Synth Effect Volume */
529 #define SFLFOI 0x00391705 /* Synth Freq LFO */
530 #define SVLFOI 0x003A1805 /* Synth Vol LFO */
531 #define SGMI 0x003B1905 /* Synth Global Mode */
532 #define SLFOBI 0x003C1A04 /* Synth LFO Base Address */
533 #define SROFI 0x003D1B04
534 #define SLOFI 0x003E1C04
535 #define SEVFI 0x003F1D04
536 #define SVIRI 0x00409F05 /* Synth Voice Read IRQ */
537 #define LDMACI 0x00414105 /* DMA Control Reg. */
538 #define LDSALI 0x00424204 /* LMC DMA Start Addr. Low Reg. */
539 #define LMALI 0x00434304 /* LMC Addr Low (I/O) */
540 #define LMAHI 0x00444405 /* LMC Addr High (I/O) */
541 #define UASBCI 0x00454505 /* Adlib-SB Control */
542 #define UAT1I 0x00464605 /* AdLib Timer 1 Count */
543 #define UAT2I 0x00474705 /* AdLib Timer 2 Count */
544 #define USCI 0x00484905 /* Sample Control Reg */
545 #define GJTDI 0x00494B05
546 #define URSTI 0x004A4C05
547 #define LDSAHI 0x004B5005
548 #define LMSBAI 0x004C5104
549 #define LMCFI 0x004D5204
550 #define LMCI 0x004E5305
551 #define LMRFAI 0x004F5404
552 #define LMPFAI 0x00505504
553 #define LMSFI 0x00515604
554 #define LDICI 0x00525704
555 #define LDIBI 0x00535804
556 #define ICMPTI 0x00545905
557 #define IDECI 0x00555A05
558 #define IVERI 0x00565B05
559 #define IEMUAI 0x00575C05
560 #define IEMUBI 0x00585D05
561 #define GMRFAI 0x00595E05
562 #define ITCI 0x005A5F05
563 #define IEIRQI 0x005B6005
564 #define LMBDR 0x005C0007
565 /*##########################################################*/
566 /* Mnemonics for Codec Registers*/
567 /*##########################################################*/
568 #define CIDXR 0x005D0000
569 #define CDATAP 0x005E0001
570 #define CSR1R 0x005F0002
571 #define CPDR 0x00600003
572 #define CRDR 0x00610003
573 #define CLICI 0x00620001
574 #define CRICI 0x00630101
575 #define CLAX1I 0x00640201
576 #define CRAX1I 0x00650301
577 #define CLAX2I 0x00660401
578 #define CRAX2I 0x00670501
579 #define CLDACI 0x00680601
580 #define CRDACI 0x00690701
581 #define CPDFI 0x006A0801
582 #define CFIG1I 0x006B0901
583 #define CEXTI 0x006C0A01
584 #define CSR2I 0x006D0B01
585 #define CMODEI 0x006E0C01
586 #define CLCI 0x006F0D01
587 #define CUPCTI 0x00700E01
588 #define CLPCTI 0x00710F01
589 #define CFIG2I 0x00721001
590 #define CFIG3I 0x00731101
591 #define CLLICI 0x00741201
592 #define CRLICI 0x00751301
593 #define CLTIMI 0x00761401
594 #define CUTIMI 0x00771501
595 #define CLMICI 0x00781601
596 #define CRMICI 0x00791701
597 #define CSR3I 0x007A1801
598 #define CLOAI 0x007B1901
599 #define CMONOI 0x007C1A01
600 #define CROAI 0x007D1B01
601 #define CRDFI 0x007E1C01
602 #define CPVFI 0x007F1D01
603 #define CURCTI 0x00801E01
604 #define CLRCTI 0x00811F01
605 /*##########################################################*/
606 /* Mnemonics for PnP Registers*/
607 /*##########################################################*/
608 #define PCSNBR 0x00820201
609 #define PIDXR 0x00830279
610 #define PNPWRP 0x00840A79
611 #define PNPRDP 0x00850000
612 #define PSRPAI 0x00860000
613 #define PISOCI 0x00870100
614 #define PCCCI 0x00880200
615 #define PWAKEI 0x00890300
616 #define PRESDI 0x008A0400
617 #define PRESSI 0x008B0500
618 #define PCSNI 0x008C0600
619 #define PLDNI 0x008D0700
620 #define PUACTI 0x008E3000
621 #define PURCI 0x008F3100
622 #define P2X0HI 0x00906000
623 #define P2X0LI 0x00916100
624 #define P3X0HI 0x00926200
625 #define P3X0LI 0x00936300
626 #define PHCAI 0x00946400
627 #define PLCAI 0x00956500
628 #define PUI1SI 0x00967000
629 #define PUI1TI 0x00977100
630 #define PUI2SI 0x00987200
631 #define PUI2TI 0x00997300
632 #define PUD1SI 0x009A7400
633 #define PUD2SI 0x009B7500
634 #define PSEENI 0x009CF000
635 #define PSECI 0x009DF100
636 #define PPWRI 0x009EF200
637 #define PRACTI 0x009F3001
638 #define PRRCI 0x00A03101
639 #define PRAHI 0x00A16001
640 #define PRALI 0x00A26101
641 #define PATAHI 0x00A36201
642 #define PATALI 0x00A46301
643 #define PRISI 0x00A57001
644 #define PRITI 0x00A67101
645 #define PRDSI 0x00A77401
646 #define PGACTI 0x00A83002
647 #define PGRCI 0x00A93102
648 #define P201HI 0x00AA6002
649 #define P201LI 0x00AB6102
650 #define PSACTI 0x00AC3003
651 #define PSRCI 0x00AD3103
652 #define P388HI 0x00AE6003
653 #define P388LI 0x00AF6103
654 #define PSBISI 0x00B07003
655 #define PSBITI 0x00B17103
656 #define PMACTI 0x00B23004
657 #define PMRCI 0x00B33104
658 #define P401HI 0x00B46004
659 #define P401LI 0x00B56104
660 #define PMISI 0x00B67004
661 #define PMITI 0x00B77104
663 typedef unsigned char BYTE;
664 typedef unsigned short WORD;
665 typedef unsigned short PORT;
666 typedef unsigned long DWORD;
667 typedef unsigned long ADDRESS;
673 short flags; /* InterWave stat flags */
674 PORT pcodar; /* Base Port for Codec */
675 PORT pcdrar; /* Base Port for Ext Device */
676 PORT p2xr; /* Compatibility Base Port */
677 PORT p3xr; /* MIDI and Synth Base Port */
678 PORT p401ar; /* Gen Purpose Reg. 1 address */
679 PORT p201ar; /* Game Ctrl normally at 0x201 */
680 PORT pataar; /* Base Address for ATAPI I/O Space */
681 PORT p388ar; /* Base Port for AdLib. It should be 388h */
682 PORT pnprdp; /* PNP read data port */
683 PORT igidxr; /* Gen Index Reg at P3XR+0x03 */
684 PORT i16dp; /* 16-bit data port at P3XR+0x04 */
685 PORT i8dp; /* 8-bit data port at P3XR+0x05 */
686 PORT svsr; /* Synth Voice Select at P3XR+0x02 */
687 PORT cdatap; /* Codec Indexed Data Port at PCODAR+0x01 */
688 PORT csr1r; /* Codec Stat Reg 1 at PCODAR+0x02 */
689 PORT cxdr; /* Play or Record Data Reg at PCODAR+0x03 */
690 PORT gmxr; /* GMCR or GMSR at P3XR+0x00 */
691 PORT gmxdr; /* GMTDR or GMRDR at P3XR+0x01 */
692 PORT lmbdr; /* LMBDR at P3XR+0x07 */
693 BYTE csn; /* Card Select Number */
694 BYTE cmode; /* Codec Operation Mode */
695 int dma1_chan; /* DMA channel 1 (local DMA & codec rec) */
696 int dma2_chan; /* DMA channel 2 (codec play) */
697 int ext_chan; /* Ext Dev DMA channel */
698 BYTE voices; /* Number of active voices */
699 DWORD vendor; /* Vendor ID and Product Identifier */
700 int synth_irq; /* Synth IRQ number */
701 int midi_irq; /* MIDI IRQ number */
702 int ext_irq; /* Ext Dev IRQ */
703 int mpu_irq; /* MPU401 Dev IRQ */
704 int emul_irq; /* Sound Blaster/AdLib Dev IRQ */
705 ADDRESS free_mem; /* Address of First Free LM Block */
706 DWORD reserved_mem; /* Amount of LM reserved by app. */
707 BYTE smode; /* Synth Mode */
708 WORD size_mem; /* Total LM in Kbytes */
projects / dragonfly.git / blob