2 * Copyright (c) 1997, by Steve Passe, All rights reserved.
3 * Copyright (c) 2003, by Matthew Dillon, All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/isa/apic_ipl.s,v 1.27.2.2 2000/09/30 02:49:35 ps Exp $
26 * $DragonFly: src/sys/platform/pc32/apic/apic_ipl.s,v 1.7 2003/07/06 21:23:49 dillon Exp $
33 * Interrupt mask for APIC interrupts, defaults to all hardware
34 * interrupts turned off.
37 .p2align 2 /* MUST be 32bit aligned */
47 * Functions to enable and disable a hardware interrupt. Generally
48 * called with only one bit set in the mask but can handle multiple
49 * bits to present the same API as the ICU.
53 IMASK_LOCK /* enter critical reg */
61 movl CNAME(int_to_apicintpin) + 8(%ecx), %edx
62 movl CNAME(int_to_apicintpin) + 12(%ecx), %ecx
65 movl %ecx, (%edx) /* target register index */
66 orl $IOART_INTMASK,16(%edx) /* set intmask in target apic reg */
69 IMASK_UNLOCK /* exit critical reg */
73 IMASK_LOCK /* enter critical reg */
74 movl 4(%esp), %eax /* mask into %eax */
76 bsfl %eax, %ecx /* get pin index */
79 btrl %ecx, apic_imen /* update apic_imen */
81 movl CNAME(int_to_apicintpin) + 8(%ecx), %edx
82 movl CNAME(int_to_apicintpin) + 12(%ecx), %ecx
85 movl %ecx, (%edx) /* write the target register index */
86 andl $~IOART_INTMASK, 16(%edx) /* clear mask bit */
89 IMASK_UNLOCK /* exit critical reg */
92 /******************************************************************************
97 * u_int io_apic_write(int apic, int select);
100 movl 4(%esp), %ecx /* APIC # */
102 movl (%eax,%ecx,4), %edx /* APIC base register address */
103 movl 8(%esp), %eax /* target register index */
104 movl %eax, (%edx) /* write the target register index */
105 movl 16(%edx), %eax /* read the APIC register data */
106 ret /* %eax = register value */
109 * void io_apic_write(int apic, int select, int value);
112 movl 4(%esp), %ecx /* APIC # */
114 movl (%eax,%ecx,4), %edx /* APIC base register address */
115 movl 8(%esp), %eax /* target register index */
116 movl %eax, (%edx) /* write the target register index */
117 movl 12(%esp), %eax /* target register value */
118 movl %eax, 16(%edx) /* write the APIC register data */
119 ret /* %eax = void */
122 * Send an EOI to the local APIC.